ETC NT7701H

NT7701
160 Output LCD Segment/Common Driver
Features
! Available in a single mode (160-bits shift register) or in a
dual mode (80-bits shift register x 2)
1. Y1 → Y160
Single mode
2. Y160 → Y1
Single mode
3. Y1 → Y80, Y81 → Y160
Dual mode
4. Y160 → Y81, Y80 → Y1
Dual mode
The above 4 shift directions are pin-selectable
(Segment mode)
! Shift Clock frequency :
14 MHz (Max.) (VDD = 5V ± 10%)
8 MHz (Max.) (VDD = 2.5V - 4.5V)
! Adopts a data bus system
! 4-bit/8-bit parallel input modes are selectable with a
mode (MD) pin
! Automatic transfer function with an enable signal
! Automatic counting function when in the chip select
mode, causes the internal clock to be stopped by
automatically counting 160 bits of input data
(Both segment mode and common mode)
! Supply voltage for LCD drive: 15.0 to 30.0V
! Number of LCD driver outputs: 160
! Low output impedance
! Low power consumption
! Supply voltage for the logic system: +2.5 to +5.5V
! COMS process
! Package : 190pin TCP (Tape Carrier Package)
! Not designed or rated as radiation hardened
(Common mode)
! Shift clock frequency:
4.0MHz (Max.)
! Built-in 160-bits bidirectional shift register (divisible into
80-bits x 2)
General Description
The NT7701 is a 160-bit output segment/common driver LSI
suitable for driving the large scale dot matrix LCD panels
used by PDA's, personal computers and work stations for
example. Through the use of SST (Super Slim TCP)
technology, it is ideal for substantially decreasing the size of
the frame section of the LCD module. The NT7701 is good
as both a segment driver and a common driver, and a low
power consuming, high-precision LCD panel display can be
assembled using the NT7701. In the segment mode, the
data input is selected 4bit parallel input mode or as 8bit
parallel input mode by a mode (MD) pin. In common mode,
the data input/output pins are bi-directional and the four data
shift directions are pin-selectable.
Pin Configuration
D
U
M
M
Y
D
U
M
M
Y
Y
1
6
0
Y
1
5
9
Y
1
5
8
Y
1
5
7
Y
1
5
6
Y
1
5
5
190 189 188 187 186 185
Y
8
3
Y
8
2
Y
8
1
Y
8
0
Y
7
9
Y
7
8
113 112 111 110 109 108
Y
6
Y
5
Y
4
Y
3
Y
2
D D
U U
M M
Y M M
1 Y Y
36 35 34 33 32 31
NT7701
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
D V V V V V L V S E D D D D D D D D X D L E F M T T V V V V V D
U 0 1 4 5 S / D / I 0 1 2 3 4 5 6 7 C I P I R D E E S 5 4 1 O U
M L 2 3 L S R D C O
K S
O
S S S R 3 2 R M
M
M
P
L L
2
1
T T
R R
Y
Y
O
1 2
F
F
1
V2.0
NT7701
Pad Configuration
199
54
200
53
NT7701
216
37
1
36
Block Diagram
V0R
V12R V43R
V5R
Y1
Y2
Y159 Y160
V5L
FR
160 Bits 4 Level Driver
Level
Shifter
V43L
V12L
DISPOFF
/160
V0L
160 Bits Level Shifter
EIO1
V5R
/160
Active
Control
160 Bits Line Latch/Shift Register
EIO2
/16
LP
/16
/16
/16
/16
/16
/16
/16
/16
/16
8Bits x 2
Data
Latch
Control
Logic
XCK
Data Latch Control
L/R
/8
MD
SP Conversion & Data Control
(4 to 8 or 8 to 8)
S/C
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
2
VDD
VSS
VSS
NT7701
Pin Description
Pin No.
Designation
I/O
Description
1
V0L
P
Power supply for LCD driver
2
V12L
P
Power supply for LCD driver
3
V43L
P
Power supply for LCD driver
4
V5L
P
Power supply for LCD driver
5
VSS
P
Ground (0V), these two pads must be connected to each other
6
L/R
I
Display data shift direction selection
7
VDD
P
Power supply for the logic system (+2.5 to +5.5V)
8
S/C
I
Segment mode / common mode selection
9
EIO2
I/O
10 - 16
D0 - D6
I
Display data input for segment mode
17
D7
I
Display data input for Segment mode / Dual mode data input
18
XCK
I
Display data shift clock input for segment mode
19
DISPOFF
I
Control input for deselect output level
20
LP
I
Latch pulse input/shift clock input for the shift register
21
EIO1
I/O
22
FR
I
AC-converting signal input for LCD driver waveform
23
MD
I
Mode selection input
24
TEST1
I
Test pin, no connection for user
25
TEST2
I
Test pin, no connection for user
26
VSS
P
Ground (0V), these two pads must be connected to each other
27
V5R
P
Power supply for LCD driver
28
V43R
P
Power supply for LCD driver
29
V12R
P
Power supply for LCD driver
30
V0R
P
Power supply for LCD driver
31 - 190
Y1 - Y160
O
LCD driver output
Input / output for chip select or data of shift register
Input / output for chip select or data of the shift register
3
NT7701
Pad Description
Pad No.
Designation
I/O
Description
1, 2
L/R
I
Display data shift direction selection
3, 4
VDD
P
Power supply for the logic system (+2.5 to + 5.5V)
5, 6
S/C
I
Segment mode/common mode selection
7, 8
EIO2
I/O
9,10 - 21, 22
D0 - D6
I
Display data input for segment mode
23, 24
D7
I
Display data input for Segment mode / Dual mode data input
25, 26
XCK
I
Display data shift clock input for segment mode
27, 28
DISPOFF
I
Control input for deselect output level
29, 30
LP
I
Latch pulse input / shift clock input for the shift register
31, 32
EIO1
I/O
Input/output for chip select or data of the shift register
33, 34
FR
I
AC-converting signal input for LCD driver waveform
35, 36
MD
I
Mode selection input
37, 38,
VSS
P
Ground (0V), these two pads must be connected to each other
39, 40
V5R
P
Power supply for LCD driver
41, 42
V43R
P
Power supply for LCD driver
43, 44
V12R
P
Power supply for LCD driver
45, 46
V0R
P
Power supply for LCD driver
47 - 206
Y1 - Y160
O
LCD driver output
207, 208
V0L
P
Power supply for LCD driver
209, 210
V12L
P
Power supply for LCD driver
211, 212
V43L
P
Power supply for LCD driver
213, 214
V5L
P
Power supply for LCD driver
215, 216
VSS
P
Ground (0V), these two pads must be connected to each other
Input/output for chip select or data of shift register
4
NT7701
Input / Output Circuits
VDD
I
Input Signal
Applicable Pins
L/R, S/C, D0 - D6,
DISPOFF , LP, FR, MD
VSS
Input Circuit (1)
VDD
I
Input Signal
Control Signal
VSS
VSS
Input Circuit (2)
5
Applicable Pins
D7, XCK
NT7701
VDD
Input Signal
Control Signal
VSS VDD
VSS
Output Signal
I/O
Control Signal
Applicable Pins
EIO1, EIO2
VSS
Input / Output Circuit
V0
V12
Control Signal 1
Control Signal 2
Control Signal 3
Control Signal 4
O
Applicable Pins
Y1 to Y160
V43
VSS
LCD Driver Output circuit
6
V5
NT7701
Pad Description
Segment mode
Symbol
Function
VDD
Logic system power supply pin connects to +2.5 to +5.5V
VSS
Ground pin connects to 0V
VOR, VOL
V12R, V12L
V43R, V43L
V5R, V5L
D0 - D7
XCK
Power supply pin for LCD driver voltage bias
# Normally, the bias voltage used is set by a resistor divider
# Ensure that the voltages are set such that VSS ≤ V5 < V43 < V12 < V0
# To further reduce the differences between the output waveforms of the LCD driver output pins Y1 and Y160,
externally connect ViR and ViL (I = 0, 12, 43)
Input pin for display data
# In 4-bit parallel input mode, input data into the 4 pins D0 - D3. Connect D4 - D7 to VSS or VDD
# In 8-bit parallel input mode, input data into the 8 pins D0 - D7
Clock input pin for taking display data
# Data is read on the falling edge of the clock pulse
LP
Latch pulse input pin for display data
# Data is latched on the falling edge of the clock pulse
L/R
Direction selection pin for reading display data
# When set to VSS level "L", data is read sequentially from Y160 to Y1
# When set to VDD level "H", data is read sequentially from Y1 to Y160
Control input pin for output deselect level
# The input signal is level-shifted from logic voltage level to LCD driver voltage level, and controls LCD
driver circuit
# When set to VSS level “L”, the LCD driver output pins (Y1 - Yl60) are set to level V5
DISPOFF
# While DISPOFF is set to “L”, the contents of the line latch are reset, but the display data in the data latch
are read regardless of the condition of DISPOFF . When the DISPOFF function is canceled, the driver
outputs deselect level (V12 or V43), then outputs the contents of the date latch onto the next falling edge
of the LP.
That time, if DISPOFF removal time can not keep regulation what is shown AC characteristics, can not
output the reading data correctly
FR
AC signal input for LCD driving waveform
# The input signal is level-shifted from the logic voltage level to the driver voltage level, and controls LCD
driver circuit
# Normally inputs a frame inversion signal
The LCD driver output pin’s output voltage level can be set to the line latch output signal and the FR signal
MD
Mode selection pin
# When set to VSS level “L”, 4-bit parallel input mode is set
# When set to VDD level “H", 8-bit parallel input mode is set
7
NT7701
Segment mode continued
Symbol
S/C
Function
Segment mode/common mode selection pin
# When set to VDD level "H", segment mode is set.
# When set to VSS level "L", common mode is set.
EIO1, EIO2
Input/output pin for chip selection
# When L/R input is at VSS level “L”, EIO1 is set for output, and EIO2 is set for input.
# When L/R input is at VDD level “H”, EIO1 is set for input, and EIO2 is set for output.
# During output, it is set to “H” while LP* XCK is “H” and after 160-bits of data have been read, it is set to
“L” for one cycle (from falling edge to falling edge of XCK), after which it returns to “H”
# During input, after the LP signal is input, the chip is selected while EI is set to “L”. After 160-bits of
data have been read, the chip is deselected
Y1 - Y160
LCD driver output pins
These corresponding directly to each bit of the data latch, one level (V0, V12, V43, or V5) is selected and
output
Common mode
Symbol
Function
VDD
Logic system power supply pin connects to +2.5 to +5.5V
VSS
Ground pin connects to 0V
V0R, V0L
V12R, V12L
V43R, V43L
V5R, V5L
Power supply pin for LCD driver voltage bias.
# Normally, the bias voltage used is set by a resistor divider
# Ensure that the voltages are set such that VSS ≤ V5 <V43 < V12 < V0
# To further reduce the differences between the output waveforms of the LCD driver output pins Y1 and
Y160, externally connect ViR and ViL (I = 0, 12, 43)
EIO1
Bi-directional shift register shift data input/output pin
# Is an Output pin when L/R is at VSS level “L” and an input pin when L/R is at VDD level “H”
# When EIO1 is used as an input pin, it will be pulled-down
# When EIO1 is used as an output pin, it won’t be pulled-down
EIO2
Bi-directional shift register shift data input/output pin
# Is an Input pin when L/R is at VSS level “L” and an output pin when L/R is at VDD level “H”
# When EIO2 is used as an input pin, it will be pulled-down
# When EIO2 is used as an output pin, it won’t be pulled-down
LP
Bi-directional shift register shift clock pulse input pin
# Data is shifted on the falling edge of the clock pulse
L/R
Bi-directional shift register shift direction selection pin
# Data is shifted from Y160 to Y1 when it is set to VSS level “L”, and data is shifted from Y1 to Y160 when it is
set to VDD level “H”
8
NT7701
Common mode continued
Symbol
Function
Control input pin for output deselect level
# The input signal is level-shifted from the logic voltage level to the LCD driver voltage level and it controls
the LCD driver circuit
# When set to VSS level “L”, the LCD driver output pins (Y1 - Y160) are set to level V5
DISPOFF
# While set to “L”, the contents of the shift resister are reset and not reading data. When the DISPOFF
function is canceled, the driver outputs deselect level (V12 or V34), and the shift data is read on the falling
edge of the LP. That time, if DISPOFF removal time can not keep regulation what is shown AC
characteristics, the shift data is not reading correctly
FR
AC signal input for LCD driving waveform
# The input signal is level-shifted from the logic voltage level to the LCD driver voltage level, and controls the
LCD driver circuit
# Normally, inputs a frame inversion signal
The LCD driver output pin’s output voltage level can be set using the shift register output signal and the FR
signal
MD
Mode selection pin
# When set to VSS level “L”, Single Mode operation is selected. When set to VDD level “H”, Dual Mode
operation is selected
D7
Dual Mode data input pin
# According to the data shift direction of the data shift register, data can be input starting from the 81st bit
When the chip is used as Dual Mode, D7 will be pulled-down
When the chip is used as Single Mode, D7 won’t be pulled-down
S/C
Segment mode/common mode selection pin
# When set to VSS level “L”, common mode is set
D0 - D6
Not used
# Connect D0-D6 to VSS or VDD. Avoiding floating
XCK
Y1 - Y160
Not used
# XCK is pulled-down in common mode, so connect to VSS or open
LCD driver output pins
# These corresponding directly Corresponding directly to each bit of the shift register, one level (V0, V12, V43,
or V5) is selected and output
9
NT7701
Functional Description
1. Block description
1.1. Active Control
In the case of segment mode, controls the selection or
deselection of the chip. Following a LP signal input, and after
the select signal is input, a select signal is generated
internally until 160 bits of data have been read in. Once data
input has been completed, a select signal for cascade
connection is output, and the ship is deselected.
1.5. Line Latch / Shift Register
In the case of the segment mode, all 160 bits which have
been read into the data latch, are simultaneously latched on
to the falling edge of the LP signal, and output to the level
shift block.
In the case of the common mode, shifts data from the data
input pin on to the falling edge of the LP signal.
In the case of common mode, controls the input/output data
of bidirectional pins.
1.2. SP Conversion & Data Control
In the case of segment mode, keep input data which are 2
clocks of XCK at 4-bit parallel mode into latch circuit, or keep
input data which are 1 clock of XCK at 8-bit parallel mode
into latch circuit, after that they are put on the internal data
bus 8 bits at a time.
1.3. Data Latch Control
In the case of the segment mode, it selects the state of the
data latch, which reads in the data bus signals. The shift
direction is controlled by the control logic and for every 16
bits of data read in, the selection signal shifts one bit, based
on the state of the control circuit.
1.4. Data Latch
In the case of the segment mode, it latches the data on the
data bus. The latched state of each LCD driver output pin is
controlled by the control logic and the data latch control 160
bits of data are read in 20 sets of 8 bits.
1.6. Level Shifter
The logic voltage signal is level-shifted to the LCD driver
voltage level, and output to the driver block.
1.7. 4-Level Driver
It drives the LCD driver output pins from the line latch/shift
register data, selecting one of 4 levels (V0, V12, V43, VSS)
based on the S/C, FR and DISPOFF signals.
1.8. Control Logic
It controls the operation of each block. In the case of the
segment mode, when an LP signal has been input, all blocks
are reset and the control logic waits for the selection signal
output from the active control block. Once the selection
signal has been output, operation of the data latch and data
transmission are controlled, 160 bits of data are read in, and
the chip is deselected.
In the case of the common mode, it controls the direction of
the data shift.
10
NT7701
2. LCD Driver Output Voltage Level
The relationship amongst the data bus signal, AC converted signal FR and LCD driver output voltage is as shown in the table
below:
2.1. Segment Mode
FR
Latch Data
DISPOFF
Driver Output Voltage Level (Y1 - Y160)
L
L
H
V43
L
H
H
V5
H
L
H
V12
H
H
H
V0
X
X
L
V5
Here, VSS ≤ V5 < V43 < V12 <V0, H: VDD (+2.5 to +5.5V), L: VSS (0V), X: Don't care
2.2. Common Mode
FR
Latch Data
DISPOFF
Driver Output Voltage Level (Y1 - Y160)
L
L
H
V43
L
H
H
V0
H
L
H
V12
H
H
H
V5
X
X
L
V5
Here, VSS ≤ V5 < V43 < V12 < V0, H: VDD (+2.5 to +5.5V), L: VSS (0V), X: Don't care
Note: There are two kinds of power supply (logic level voltage, LCD driver voltage) for the LCD driver. Please supply regular
voltage, which assigned by specification for each power pin.
That time "Don't care" should be fixed to "H" or "L", avoiding floating.
11
NT7701
3. Relationship between the Display Data and Driver Output Pins
3.1. Segment Mode:
(a) 4-bit Parallel Mode
MD
L/R
L
L
L
H
EIO1
EIO2
Output Input
Input Output
Data
Input
D0
D1
D2
D3
D0
D1
D2
D3
40clock
Y1
Y2
Y3
Y4
Y160
Y159
Y158
Y157
39clock
Y5
Y6
Y7
Y8
Y156
Y155
Y154
Y153
Number of Clock
38clcok
~
3clock
~
Y9
Y149
~
Y10
Y150
~
Y11
Y151
~
Y12
Y152
~
Y152
Y12
~
Y151
Y11
~
Y150
Y10
~
Y149
Y9
2clock
Y153
Y154
Y155
Y156
Y8
Y7
Y6
Y5
1clock
Y157
Y158
Y159
Y160
Y4
Y3
Y2
Y1
19clock
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y152
Y151
Y150
Y149
Y148
Y147
Y146
Y145
Number of Clock
18clcok
~
3clock
Y17
~
Y137
Y18
~
Y138
Y19
~
Y139
Y20
~
Y140
Y21
~
Y141
Y22
~
Y142
Y23
~
Y143
Y24
~
Y144
Y144
~
Y24
Y143
~
Y23
Y142
~
Y22
Y141
~
Y21
Y140
~
Y20
Y139
~
Y19
Y138
~
Y18
Y137
~
Y17
2clock
Y145
Y146
Y147
Y148
Y149
Y150
Y151
Y152
Y16
Y15
Y14
Y13
Y12
Y11
Y10
Y9
1clock
Y153
Y154
Y155
Y156
Y157
Y158
Y159
Y160
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
(b) 8-bit Parallel Mode
MD
L/R
H
L
H
H
EIO1
EIO2
Output Input
Input Output
Data
Input
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
20clock
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y160
Y159
Y158
Y157
Y156
Y155
Y154
Y153
12
NT7701
3.2. Common Mode
MD
L/R
Data Transfer Direction
EIO1
EIO2
D7
L
(Single)
L (shift to left)
Y160 to Y1
Output
Input
X
H (shift to right)
Y1 to Y160
Input
Output
X
Output
Input
Input
Input
Output
Input
Y160 to Y81
L (shift to left)
Y80 to Y1
H
(Dual)
Y1 to Y80
H (shift to right)
Y81 to Y160
Here, L: VSS (0V), H: VDD (+2.5V to +5.5V), X: Don't care
Note: "Don't care" should be fixed to "H" or "L", avoiding floating.
13
NT7701
4. Connection Examples of Segment Drivers
4.1. Case of L/R = “L”
last data
first data
(data taking flow)
Y160 ---------------------->Y1
Y160 ---------------------->Y1
Y160 ---------------------->Y1
EIO2
EIO2
EIO2
EIO1
EIO1
DI0~DI7
FR
MD
L/R
LP
DI0~DI7
FR
MD
LP
L/R
XCK
DI0~DI7
FR
MD
LP
XCK
L/R
XCK
EIO1
XCK
LP
MD
FR
D0 - D7
/8
VSS
4.2 Case of L/R = “H”
VDD
D0 - D7
/8
FR
MD
LP
L/R
VSS
L/R
EIO1
EIO2
Y1 ---------------------->Y160
XCK
LP
MD
FR
DI0 - DI7
XCK
LP
MD
FR
DI0 - DI7
XCK
LP
MD
FR
DI0 - DI7
XCK
L/R
EIO1
EIO2
Y1 ---------------------->Y160
EIO1
EIO2
Y1 ---------------------->Y160
(data taking flow)
first data
last data
14
NT7701
5. Timing Waveform of 4-Device Cascade Connection of Segment Drivers.
FR
LP
XCK
First data
D0 - D7
n 1 2
Last data
n 1 2
device A
n 1 2
device B
n 1 2
device C
EI
(device A)
n 1 2
device D
H
L
EO
(device A)
EO
(device B)
EO
(device C)
n: 4-bit parallel mode 40
8-bit parallel mode 20
15
NT7701
6. Connection Examples for Common Drivers
First
FR
DISPOFF
LP
D7
LP
L/R
EIO1
MD
EIO2
D7
EIO1
FR
EIO2
DISPOFF
EIO1
L/R
EIO2
MD
Y1
FR
Y160
DISPOFF
Y1
L/R
Y160
MD
Y1
D7
Y160
LP
D
Last
LP
VSS(VDD)
VSS
VSS
DISPOFF
FR
Single Mode (Shifting towards the left)
FR
CS
DISPOFF
VDD
VSS
VSS(VDD)
EIO1
Y1
EIO2
Y160
EIO1
EIO2
Y1
Y160
First
EIO1
Y1
EIO2
Y160
Last
Single Mode (Sifting towards the right)
16
LP
DI7
MD
L/R
DISPOFF
CS
FR
LP
DI7
MD
L/R
DISPOFF
CS
FR
LP
DI7
MD
L/R
DISPOFF
DI
CS
FR
LP
NT7701
Last2
Y80
EIO1
D7
FR
FR
EIO2
DISPOFF
EIO1
L/R
Y1
MD
Y160
LP
Y1
DISPOFF
MD
Y81
D7
LP
EIO2
FR
EIO1
DISPOFF
EIO2
L/R
Y160
MD
Y1
D7
Y160
LP
D1
Last1 First2
L/R
First1
LP
D2
VSS (VDD)
VDD
VSS
DISPOFF
FR
Dual mode (Shifting towards the left)
FR
DISPOFF
VDD
VDD
VSS (VDD)
D2
D1
EIO1
EIO2
EIO1
Y1
Y160
Y1
First1
EIO2
Y80
Y81
Y160
Last1 First2
Dual mode (Shifting towards the right)
17
LP
D7
MD
L/R
DISPOFF
FR
LP
D7
MD
L/R
DISPOFF
FR
LP
D7
MD
L/R
DISPOFF
FR
LP
EIO1
EIO2
Y1
Y160
Last2
NT7701
7. Precaution
Be careful when connecting or disconnecting the power
This LSI has a high-voltage LCD driver, so it may be permanently damaged by a high current, which may occur, if a voltage is
supplied to the LCD driver power supply while the logic system power supply is floating.
The details are as follows:
!
!
When connecting the power supply, connect the LCD driver power after connecting the logic system power. Furthermore,
when disconnecting the power, disconnect the logic system power after disconnecting the LCD driver power.
We recommend that you connect a serial resistor (50-100Ω) or fuse to the LCD driver power V0 of the system as a current
limiting device. Also, set a suitable value for the resistor in consideration of the LCD display grade.
In addition, when connecting the logic power supply, the logic condition of the LSI inside is insecure. Therefore connect the LCD
driver power supply after resetting logic condition of this LSI inside on DISPOFF function. After that, the DISPOFF cancel the
function after the LCD driver power supply has become stable. Furthermore, when disconnecting the power, set the LCD driver
output pins to level VSS on the DISPOFF function. After that, disconnect the logic system power after disconnecting the LCD
driver power.
When connecting the power supply, follow the recommended sequence shown.
VDD
VDD
VSS
VDD
DISPOFF
VSS
V0
V0
VSS
18
NT7701
Absolute Maximum Rating*
*Comments
DC Supply Voltage VDD . . . . . . . . . . . . -0.3V to +7.0V
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device under these or any other conditions above those
indicated in the operational sections of this specification is
not implied or intended. Exposure to the absolute maximum
rating conditions for extended periods may affect device
reliability.
DC Supply Voltage V0 . . . . . . . . . . . . . -0.3V to +30V
Input Voltage . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V
Operating Ambient Temperature . . . . -30°C to +85°C
Storage Temperature . . . . . . . . . . . . .-45°C to +125°C
Electrical Characteristics
DC Characteristics
Segment Mode (VSS = V5 = 0V, VDD = 2.5 - 5.5V, V0 = 15 to 30 V, and TA = -30 to +85°C, unless otherwise noted)
Parameter
Symbol
Min.
Typ.
Max.
Unit
VDD
2.5
-
5.5
V
Operating Voltage
V0
15
-
30
V
Input high voltage
VIH
0.8 VDD
-
-
V
D0 - 7, XCK, LP, L/R, FR, MD, S/C, EIO1,
Input low voltage
VIL
-
-
0.2 VDD
V
EIO2 and DISPOFF pins
Output high voltage
VOH
VDD - 0.4
-
-
V
EIO1, EIO2 pins, IOH = -0.4mA
Output low voltage
VOL
-
-
+0.4
V
EIO1, EIO2 pins, IOL = +0.4mA
Input leakage current 1
IIH
-
-
+1
µA
D0 - 7, XCK, LP, L/R, FR, MD, S/C, EIO1,
EIO2 and DISPOFF pins, VI = VDD
Input leakage current 2
IIL
-
-
-1
µA
D0 - 7, XCK, LP, L/R, FR, MD, S/C, EIO1,
EIO2 and DISPOFF pins, VI = VSS
-
1.0
1.5
-
1.5
2.0
Operating Voltage
Condition
V0 = +30.0V
Output resistance
RON
Stand-by current
ISB
-
-
5
µA
VSS pin, Note 1
Consumed current (1)
(Deselection)
IDD1
-
-
2.0
mA
VDD pin, Note 2
Consumed current (2)
(Selection)
IDD2
-
-
8.0
mA
VDD pin, Note 3
I0
-
-
1.0
mA
V0 pin, Note 4
Consumed current
kΩ
V0 = +20.0V
Note:
1. VDD = +5.0V, V0 = +30V, VI = VSS
2. VDD = +5.0V, V0 = +30V, fXCK = 14MHz, No-load, EI = VDD
The input data is turned over by the data taking clock (4-bit parallel input mode)
3. VDD = +5.0V, V0 = +30V, fXCK = 14MHz, No-load. EI = VSS
The input data is turned over by the data taking clock (4-bit parallel input mode)
4. VDD = +5.0V, V0 = +30V, fXCK = 14MHz, fLP = 41.6kHz. fFR = 80 Hz, No-load
The input data is turned over by the data taking clock (4-bit parallel-input mode)
19
Y1 - Y160 pins,
∆V O N = 0.5V
NT7701
Common Mode (VSS = V5 = 0V, VDD = 2.5 - 5.5V, V0 = 15 to 30V, and TA = -30 to +85°C, unless otherwise noted)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Condition
Operating Voltage
VDD
2.5
-
5.5
V
Operating Voltage
V0
15
-
30
V
Input high voltage
VIH
0.8 VDD
-
-
V
D0 - 7, XCK, LP, L/R, FR, MD, S/C, EIO1,
Input low voltage
VIL
-
-
0.2 VDD
V
EIO2 and DISPOFF pins
Output high voltage
VOH
VDD - 0.4
-
-
V
EIO1, EIO2 pins, IOH = -0.4mA
Output low voltage
VOL
-
-
+0.4
V
EIO1, EIO2 pins, IOL = +0.4mA
Input leakage current 1
IIH
-
-
+10.0
µA
Input leakage current 2
IIL
-
-
-10.0
µA
-
1.0
1.5
-
1.5
2.0
D0 - 6, LP, L/R, FR, MD, S/C and
DISPOFF pins, VI = VDD
D0 - 7, XCK, LP, L/R, FR, MD, S/C, EIO1,
EIO2 and DISPOFF pins, VI = VSS
V0 = +30.0V
Output resistance
RON
Stand-by current
ISB
-
-
50
µA
VSS pin, Note 1
Consumed current (1)
IDD
-
-
80
µA
VDD pin, Note 2
Consumed current (2)
I0
-
-
160
µA
V0 pin, Note 2
kΩ
V0 = +20.0V
Note:
1. VDD = +5.0V, V0 = +30V, fLP = 0 - 41.6kHz
2. VDD = +5.0V, V0 = +30V, fLP = 41.6KHz, fFR = 80Hz, case of 1/480 duty operation, No-load
20
Y1 - Y160 pins,
∆V O N = 0.5V
NT7701
AC Characteristics
Segment Mode 1 (VSS = V5 = 0V, VDD = 4.5 - 5.5V, V0 = 15 to 30, and TA = -30 to +85°C, unless otherwise noted)
Parameter
Symbol
Min.
Typ.
Shift clock period
tWCK
71
-
ns
Shift clock "H" pulse width
tWCKH
23
-
ns
Shift clock "L" pulse width
tWCKL
23
-
ns
Data setup time
tDS
10
-
ns
Data hole time
tDH
20
-
ns
tWLPH
23
-
ns
Shift clock rise to Latch pulse rise time
tLD
0
-
ns
Shift clock fall to Latch pulse fall time
tSL
25
-
ns
Latch pulse rise to Shift clock rise time
tLS
25
-
ns
Latch pulse fall to Shift clock rise time
tLH
25
-
ns
Latch pulse "H" pulse width
Max.
Unit
Condition
tr, tf ≦ 10ns, Note 1
Input signal rise time
tr
-
50
ns
Note 2
Input signal fall time
tf
-
50
ns
Note 2
Enable setup time
tS
21
-
ns
DISPOFF Removal time
tSD
100
-
ns
tWDL
1.2
-
µs
DISPOFF enable pulse width
Output delay time (1)
tD
-
40
ns
CL = 15pF
Output delay time (2)
tpd1, tpd2
-
1.2
µs
CL = 15pF
Output delay time (3)
tpd3
-
1.2
µs
CL = 15pF
Note
1. Take the cascade connection into consideration.
2. (Tck - tWCKII - twckl)/2 is the maximum in the case of high speed operation.
21
NT7701
Segment Mode 2 (VSS = V5 = 0V, VDD = 2.5 - 4.5V, V0 = 15 to 30, and TA = -30 to +85°C, unless otherwise noted)
Parameter
Symbol
Min.
Typ.
Shift clock period
tWCK
125
-
ns
Shift clock "H" pulse width
tWCKH
51
-
ns
Shift clock "L" pulse width
tWCKL
51
-
ns
Data setup time
tDS
30
-
ns
Data hole time
tDH
40
-
ns
tWLPH
51
-
ns
Shift clock rise to Latch pulse rise time
tLD
0
-
ns
Shift clock fall to Latch pulse fall time
tSL
51
-
ns
Latch pulse rise to Shift clock rise time
tLS
51
-
ns
Latch pulse fall to Shift clock fall time
tLH
51
-
ns
Latch pulse "H" pulse width
Max.
Unit
Condition
tr, tf ≦ 11ns, Note 1
Input signal rise time
tr
-
50
ns
Note 2
Input signal fall time
tf
-
50
ns
Note 2
Enable setup time
tS
36
-
ns
DISPOFF Removal time
tSD
100
-
ns
tWDL
1.2
-
µs
DISPOFF enable pulse width
Output delay time (1)
tD
-
78
ns
CL = 15pF
Output delay time (2)
tpd1, tpd2
-
1.2
µs
CL = 15pF
Output delay time (3)
tpd3
-
1.2
µs
CL = 15pF
Note
1. Take the cascade connection into consideration.
2. (tCK - tWCKII - tWCKL)/2 is the maximum in the case of high speed operation.
22
NT7701
Timing waveform of the Segment Mode
tWLPH
LP
tLD
tSL
tLH
tLS
tWCKH
tWCKL
XCK
D0 - D7
tr
tr
tWCK
tDS
LAST DATA
tDH
TOP DATA
tWDL
tSD
DISPOFF
LP
1
XCK
2
n
tS
EI
tD
EO
n: 4-bit parallel mode 40
8-bit parallel mode 20
FR
tpd1
LP
tpd2
DISPOFF
tpd3
Y1 - Y160
23
NT7701
Common Mode (VSS = V5 = 0V, VDD = 2.5 - 5.5V, V0 = 15 to 30V and TA = -30 to +85°C, unless otherwise noted)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Condition
Shift clock period
tWLP
250
-
-
ns
tr, tf ≦ 20ns
Shift clock "H" pulse width
tWLPH
15
-
-
ns
VDD = +5.0V ± 10%
30
-
-
ns
VDD = +2.5 - +4.5V
Data setup time
tSU
30
-
-
ns
Data hole time
tH
50
-
-
ns
Input signal rise time
tr
-
50
ns
Input signal fall time
tf
-
50
ns
tSD
100
-
-
ns
tWDL
1.2
-
-
µs
Output delay time (1)
tDL
-
-
200
ns
CL = 15pF
Output delay time (2)
tpd1, tpd2
-
-
1.2
µs
CL = 15pF
Output delay time (3)
tpd3
-
-
1.2
µs
CL = 15pF
DISPOFF Removal time
DISPOFF enable pulse width
24
NT7701
Timing Characteristics of Common Mode
tWLP
LP
tr
tWLPH
tSU
tf
tH
EIO2
(D7)
tDL
EIO1
tWDL
tSD
DISPOFF
FR
tpd1
LP
tpd2
DISPOFF
tpd3
Y1 - Y160
L/R = "L"
25
NT7701
Application Circuit (for reference only)
EIO1
Y1~Y160
MD
FR
S/C
LP
L/R
DISPOFF
XCK
EIO2
EIO1
Y1~Y160
MD
FR
S/C
L/R
LP
DISPOFF
640*480 DOT MATRIX
LCD PANEL
D0~D7
D0~D7
NT7701*4
SEG640
SEG639
EIO2
XCK
EIO1
Y1~Y160
MD
FR
S/C
LP
L/R
DISPOFF
XCK
D0~D7
EIO2
EIO1
Y1~Y160
MD
SEG3
SEG2
FR
S/C
SEG1
C
O
M
4
7
9
L/R
DISPOFF
XCK
D0~D7
EIO2
XCK
EIO2
LP
DISPOFF
D0~D7
L/R
Y1~Y160
FR
S/C
MD
EIO1
XCK
EIO2
DISPOFF
LP
L/R
D0~D7
S/C
EIO1
FR
XCK
EIO2
LP
DISPOFF
L/R
D0~D7
FR
S/C
MD
NT7701*3
EIO1
LP
C
O
M
4
8
0
/8
Y1~Y160
C
O
M
3
Y1~Y160
C
O
M
2
MD
C
O
M
1
/5
/5
VEE
V0
R
V1
(n-4)R
V2
R
V3
R
V4
V5
VDD
VSS
26
LCD controller
XD0~XD7
XCK
LP
DISPOFF
FR
YD
(case of 1/n bias)
50~100Ω
/8
R
NT7701
Bonding Diagram
7664um
199
54
200
53
Y
NT7701
986um
X
(0,0)
ALK_L
ALK_R
216
37
1
36
Pad Location
Pad No.
Designation
X
Y
Pad No.
Designation
X
Y
1
LR
-3600
-440
31
EIO1
2160
-440
2
LR
-3440
-440
32
EIO1
2320
-440
3
VDD
-3280
-440
33
FR
2480
-440
4
VDD
-3120
-440
34
FR
2640
-440
5
SC
-2000
-440
35
MD
2800
-440
6
SC
-1840
-440
36
MD
2960
-440
7
EIO2
-1680
-440
37
GND
3779
-410
8
EIO2
-1520
-440
38
GND
3779
-350
9
D0
-1360
-440
39
V5R
3779
-300
10
D0
-1200
-440
40
V5R
3779
-250
11
D1
-1040
-440
41
V43R
3779
-200
12
D1
-880
-440
42
V43R
3779
-150
13
D2
-720
-440
43
V12R
3779
-100
14
D2
-560
-440
44
V12R
3779
-50
15
D3
-400
-440
45
V0R
3779
0
16
D3
-240
-440
46
V0R
3779
50
17
D4
-80
-440
47
Y1
3779
100
18
D4
80
-440
48
Y2
3779
150
19
D5
240
-440
49
Y3
3779
200
20
D5
400
-440
50
Y4
3779
250
21
D6
560
-440
51
Y5
3779
300
22
D6
720
-440
52
Y6
3779
350
23
D7
880
-440
53
Y7
3779
410
24
D7
1040
-440
54
Y8
3635
440
25
XCK
1200
-440
55
Y9
3575
440
26
XCK
1360
-440
56
Y10
3525
440
27
DISPOFF
1520
-440
57
Y11
3475
440
28
DISPOFF
1680
-440
58
Y12
3425
440
29
LP
1840
-440
59
Y13
3375
440
30
LP
2000
-440
60
Y14
3325
440
27
NT7701
Pad Location (continued)
Pad No.
Designation
X
Y
Pad No.
Designation
X
Y
61
Y15
3275
440
101
Y55
1275
440
62
Y16
3225
440
102
Y56
1225
440
63
Y17
3175
440
103
Y57
1175
440
64
Y18
3125
440
104
Y58
1125
440
65
Y19
3075
440
105
Y59
1075
440
66
Y20
3025
440
106
Y60
1025
440
67
Y21
2975
440
107
Y61
975
440
68
Y22
2925
440
108
Y62
925
440
69
Y23
2875
440
109
Y63
875
440
70
Y24
2825
440
110
Y64
825
440
71
Y25
2775
440
111
Y65
775
440
72
Y26
2725
440
112
Y66
725
440
73
Y27
2675
440
113
Y67
675
440
74
Y28
2625
440
114
Y68
625
440
75
Y29
2575
440
115
Y69
575
440
76
Y30
2525
440
116
Y70
525
440
77
Y31
2475
440
117
Y71
475
440
78
Y32
2425
440
118
Y72
425
440
79
Y33
2375
440
119
Y73
375
440
80
Y34
2325
440
120
Y74
325
440
81
Y35
2275
440
121
Y75
275
440
82
Y36
2225
440
122
Y76
225
440
83
Y37
2175
440
123
Y77
175
440
84
Y38
2125
440
124
Y78
125
440
85
Y39
2075
440
125
Y79
75
440
86
Y40
2025
440
126
Y80
25
440
87
Y41
1975
440
127
Y81
-25
440
88
Y42
1925
440
128
Y82
-75
440
89
Y43
1875
440
129
Y83
-125
440
90
Y44
1825
440
130
Y84
-175
440
91
Y45
1775
440
131
Y85
-225
440
92
Y46
1725
440
132
Y86
-275
440
93
Y47
1675
440
133
Y87
-325
440
94
Y48
1625
440
134
Y88
-375
440
95
Y49
1575
440
135
Y89
-425
440
96
Y50
1525
440
136
Y90
-475
440
97
Y51
1475
440
137
Y91
-525
440
98
Y52
1425
440
139
Y92
-575
440
99
Y53
1375
440
139
Y93
-625
440
100
Y54
1325
440
140
Y94
-675
440
28
NT7701
Pad Location (continued)
Pad No.
Designation
X
Y
Pad No.
Designation
X
Y
141
Y95
-725
440
181
Y135
-2725
440
142
Y96
-775
440
182
Y136
-2775
440
143
Y97
-825
440
183
Y137
-2825
440
144
Y98
-875
440
184
Y138
-2875
440
145
Y99
-925
440
185
Y139
-2925
440
146
Y100
-975
440
186
Y140
-2975
440
147
Y101
-1025
440
187
Y141
-3025
440
148
Y102
-1075
440
188
Y142
-3075
440
149
Y103
-1125
440
189
Y143
-3125
440
150
Y104
-1175
440
190
Y144
-3175
440
151
Y105
-1225
440
191
Y145
-3225
440
152
Y106
-1275
440
192
Y146
-3275
440
153
Y107
-1325
440
193
Y147
-3325
440
154
Y108
-1375
440
194
Y148
-3375
440
155
Y109
-1425
440
195
Y149
-3425
440
156
Y110
-1475
440
196
Y150
-3475
440
157
Y111
-1525
440
197
Y151
-3525
440
158
Y112
-1575
440
198
Y152
-3575
440
159
Y113
-1625
440
199
Y153
-3635
440
160
Y114
-1675
440
200
Y154
-3779
410
161
Y115
-1725
440
201
Y155
-3779
350
162
Y116
-1775
440
202
Y156
-3779
300
163
Y117
-1825
440
203
Y157
-3779
250
164
Y118
-1875
440
204
Y158
-3779
200
165
Y119
-1925
440
205
Y159
-3779
150
166
Y120
-1975
440
206
Y160
-3779
100
167
Y121
-2025
440
207
V0L
-3779
50
168
Y122
-2075
440
208
V0L
-3779
0
169
Y123
-2125
440
209
V12L
-3779
-50
170
Y124
-2175
440
210
V12L
-3779
-100
171
Y125
-2225
440
211
V43L
-3779
-150
172
Y126
-2275
440
212
V43L
-3779
-200
173
Y127
-2325
440
213
V5L
-3779
-250
174
Y128
-2375
440
214
V5L
-3779
-300
175
Y129
-2425
440
215
GND
-3779
-350
176
Y130
-2475
440
216
GND
-3779
-410
177
Y131
-2525
440
ALK_L
-3438
-323
ALK_R
3438
-323
178
Y132
-2575
440
179
Y133
-2625
440
180
Y134
-2675
440
29
NT7701
Dummy Pad Location (Total: 10 pin)
NO
X
Y
NO
X
Y
NO
X
Y
NO
X
Y
0
-2960
-440
3
-2480
-440
6
3120
-440
9
3600
-440
1
-2800
-440
4
-2320
-440
7
3280
-440
2
-2640
-440
5
-2160
-440
8
3440
-440
30
NT7701
Package Information
A1
D3
D3
C1
n3
n3
m3
m2
m2
NT7701
m2
n2
15× n2×
J
m3
n2A
n2A n2B
D1
A2
n3
C2
n2
m3
D3
A1
D1
144× m2×
A2
n3
C1
m3
D3
n2B n2A
n2B
m2
D1
m2
m2
n2
r
f e f
15× n2×
J
f
e
f
H
D3
H
m1
m3
C1
D3
m3
n1
n3
n3
C2
D2
B
37× m1×
Chip Outline Dimensions
B
unit: µm
Symbol
Dimensions in µm
Symbol
Dimensions in µm
A1
197
n1
56
A2
53
n2
67
B
232
n2A
35
C1
83
n2B
32
C2
53
n3
60
D1
50
r
35
D2
160
e
24
D3
60
f
23
m1
54
H
120
m2
32
J
202
m3
52
31
C1
NT7701
TCP Pin Layout
DUMMY
DUMMY
Y1
31
Y2
32
Y3
33
Y5
34
Y4
35
Y6
36
Y78
108
Y79
109
Y80
110
Y81
111
Y82
112
Y83
113
NT7701
DUMMY
30
V0R
29
V12R
28
V43R
27
V5R
26
VSS
25
TEST2
24
TEST1
23
MD
22
FR
21
EIO1
20
LP
19
DISPOFF
18
XCK
17
D7
16
D6
15
D5
14
D4
13
D3
12
D2
11
D1
10
D0
9
EIO2
8
S/C
7
VDD
6
L/R
5
VSS
4
V5L
3
V43L
2
V12L
1
V0L
DUMMY
Y155
185
Y156
186
Y157
187
Y158
188
Y159
189
Y160
190
DUMMY
DUMMY
(COPPER SIDE VIEW)
32
NT7701
External view of TCP pins
33
NT7701
Cautions concerning storage:
1. When storing the product, it is recommended that it be left in its shipping package.
After the seal of the packing bag has been broken, store the products in a nitrogen atmosphere.
2. Storage conditions :
Storage state
Storage conditions
Temperature: 5 to 30℃; humidity: 80%RH or less
unopened (less than 90 days)
3.
4.
5.
6.
After seal of broken (less than 30 days) Room temperature, dry nitrogen atmosphere
Don't store in a location exposed to corrosive gas or excessive dust.
Don't store in a location exposed to direct sunlight of subject to sharp changes in temperature.
Don't store the product such that it is subjected to an excessive load weight, such as by stacking.
Deterioration of the plating may occur after long-term storage, so special care is required.
It is recommended that the products be inspected before use.
34
NT7701
Tray Information
f
Y
e
7*33
X
X
W1
W2
T2 T1
SECTION Y-Y
c
d
Y
g
h
W1
W2
a
b
e
g
f
h
T2
T1
SECTION X-X
Symbol
Dimensions in mm
Symbol
Dimensions in mm
a
1.46
g
0.84
b
2.04
h
4.20
c
8.16
W1
76.0
d
9.50
W2
68.0
e
1.60
T1
71.0
f
1.40
T2
68.3
35
NT7701
Ordering Information
Part No.
NT7701H-BDT
NT7701H-TABF3
Package
Au bump on chip tray
TCP Form
36
NT7701
Product Spec. Change Notice
NT7701 Specification Revision History
Version
Content
Date
2.0
˙Chip size modified ( Due to scribe-line modified, change
7720μm x 1030μm to 7664μm x 986μm , Page 27 )
˙Gold bump size modified ( Page 31 )
Jul. 2002
1.0
Formal version release
Oct. 2000
37