OKI MSC23441D

This version: Mar. 6. 2000
Previous version: Mar. 8. 1999
Semiconductor
MSC23441D-xxBS10/DS10
4,194,304-word x 40-bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE
DESCRIPTION
The MSC23441D-xxBS10/DS10 is a 4,194,304-word x 40-bit CMOS dynamic random access memory module
which is composed of ten 16Mb DRAMs (4Mx4) in SOJ packages mounted with ten decoupling capacitors. This is a
72-pin single in-line memory module. This module supports any application where high density and large capacity of
storage memory are required.
FEATURES
• 4,194,304-word x 40-bit organization
• 72-pin Single In-Line Memory Module
MSC23441D-xxBS10 : Gold tab
MSC23441D-xxDS10 : Solder tab
• Single 5V power supply, ±10% tolerance
• Input
: TTL compatible
• Output : TTL compatible, 3-state
• Refresh : 4096cycles/64ms
• Fast page mode, read modify write capability
• /CAS before /RAS refresh, hidden refresh, /RAS only refresh capability
• Multi-bit test mode capability
PRODUCT FAMILY
Access Time (Max.)
Power Dissipation (Max.)
tRAC
tAA
tCAC
tOEA
Cycle Time
(Min.)
MSC23441D-60BS10/DS10
60ns
30ns
15ns
15ns
110ns
3850mW
MSC23441D-70BS10/DS10
70ns
35ns
20ns
20ns
130ns
3575mW
Family
Operating
Standby
55mW
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Semiconductor
MSC23441D
MODULE OUTLINE
(Unit : mm)
MSC23441D-xxBS10/DS10
5.28Max.
107.95±0.2*1
101.19Typ.
3.38Typ.
2.03Typ.
1
72
1.27±0.1
R1.57
6.35Typ.
6.35
95.25
1.04Typ.
3.5Min.
6.35Typ.
25.4±0.2
10.16Typ.
φ3.18
+0.1
1.27
−0.08
Note:
1. Tolerance over 12.5mm from board edge is ±0.5.
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Semiconductor
MSC23441D
PIN CONFIGURATION
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
1
VSS
19
/OE
37
DQ19
55
DQ28
2
DQ0
20
DQ8
38
DQ20
56
DQ29
3
DQ1
21
DQ9
39
VSS
57
DQ30
4
DQ2
22
DQ10
40
/CAS0
58
DQ31
5
DQ3
23
DQ11
41
A10
59
VCC
6
DQ4
24
DQ12
42
A11
60
DQ32
7
DQ5
25
DQ13
43
NC
61
DQ33
8
DQ6
26
DQ14
44
/RAS0
62
DQ34
9
DQ7
27
DQ15
45
NC
63
DQ35
10
VCC
28
A7
46
DQ21
64
DQ36
11
PD5
29
DQ16
47
/WE
65
DQ37
12
A0
30
VCC
48
VSS
66
DQ38
13
A1
31
A8
49
DQ22
67
PD1
14
A2
32
A9
50
DQ23
68
PD2
15
A3
33
NC
51
DQ24
69
PD3
16
A4
34
NC
52
DQ25
70
PD4
17
A5
35
DQ17
53
DQ26
71
DQ39
18
A6
36
DQ18
54
DQ27
72
VSS
Presence Detect Pins
Pin No.
Pin Name
-60
-70
67
PD1
VSS
VSS
68
PD2
NC
NC
69
PD3
NC
VSS
70
PD4
NC
NC
11
PD5
VSS
VSS
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Semiconductor
MSC23441D
BLOCK DIAGRAM
A0-A11
/RAS0
/CAS0
/WE
/OE
A0-A11 DQ
/RAS
DQ
/CAS
DQ
/WE
DQ
/OE
D0
VCC
VSS
DQ0
DQ1
DQ2
DQ3
A0-A11 DQ
/RAS
DQ
/CAS
DQ
/WE
DQ
/OE
D5
VCC
VSS
DQ20
DQ21
DQ22
DQ23
A0-A11 DQ
/RAS
DQ
/CAS
DQ
/WE
DQ
/OE
D1
VCC
VSS
DQ4
DQ5
DQ6
DQ7
A0-A11 DQ
/RAS
DQ
/CAS
DQ
/WE
DQ
/OE
D6
VCC
VSS
DQ24
DQ25
DQ26
DQ27
A0-A11 DQ
/RAS
DQ
/CAS
DQ
/WE
DQ
/OE D2
VCC
VSS
DQ8
DQ9
DQ10
DQ11
A0-A11 DQ
/RAS
DQ
/CAS
DQ
/WE
DQ
/OE D7
VCC
VSS
DQ28
DQ29
DQ30
DQ31
A0-A11 DQ
/RAS
DQ
/CAS
DQ
/WE
DQ
/OE
D3
VCC
VSS
DQ12
DQ13
DQ14
DQ15
A0-A11 DQ
/RAS
DQ
/CAS
DQ
/WE
DQ
/OE
D8
VCC
VSS
DQ32
DQ33
DQ34
DQ35
A0-A11 DQ
/RAS
DQ
/CAS
DQ
/WE
DQ
/OE D4
VCC
VSS
DQ16
DQ17
DQ18
DQ19
A0-A11 DQ
/RAS
DQ
/CAS
DQ
/WE
DQ
/OE D9
VCC
VSS
DQ36
DQ37
DQ38
DQ39
VCC
VSS
C0-C9
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Semiconductor
MSC23441D
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Voltage on Any Pin Relative to VSS
VT
−0.5 to 7.0
V
Short Circuit Output Current
IOS
50
mA
Power Dissipation
PD *
10
W
Operating Temperature
TOPR
0 to 70
°C
Storage Temperature
TSTG
−40 to 125
°C
*: Ta = 25°C
Recommended Operating Conditions
(Ta = 0°C to 70°C)
Parameter
Symbol
Min.
Typ.
Max.
Unit
VCC
4.5
5.0
5.5
V
VSS
0
0
0
V
Input High Voltage
VIH
2.4

VCC + 0.5
V
Input Low Voltage
VIL
−0.5

0.8
V
Power Supply Voltage
Capacitance
(VCC = 5V ±10%, Ta = 25°C, f = 1 MHz)
Parameter
Symbol
Typ.
Max.
Unit
Input Capacitance (A0 - A11)
CIN1

70
pF
Input Capacitance (/RAS0, /CAS0, /WE, /OE)
CIN2

80
pF
I/O Capacitance (DQ0 - DQ39)
CI/O

16
pF
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Semiconductor
MSC23441D
DC Characteristics
(VCC = 5V ±10%, Ta = 0°C to 70°C)
Parameter
Symbol
Condition
-60
-70
Unit
Min.
Max.
Min.
Max.
2.4
VCC
2.4
VCC
V
0
0.4
0
0.4
V
Note
Output High Voltage
VOH
IOH = −5.0mA
Output Low Voltage
VOL
IOL = 4.2mA
Input Leakage Current
ILI
0V ≤ VIN ≤ 6.5V;
All other pins not
under test = 0V
−100
100
−100
100
µA
Output Leakage Current
ILO
DQ disable
0V ≤ VOUT ≤ VCC
−10
10
−10
10
µA
Average Power
Supply Current
(Operating)
ICC1
/RAS, /CAS cycling,
tRC = Min.

700

650
mA
1, 2
/RAS, /CAS = VIH

20

20
/RAS, /CAS
≥ VCC − 0.2V

10

10
mA
1
Power supply current
(Standby)
ICC2
Average Power
Supply Current
(/RAS only refresh)
ICC3
/RAS cycling,
/CAS = VIH,
tRC = Min.

700

650
mA
1, 2
Average Power
Supply Current
(/CAS before /RAS refresh)
ICC6
/RAS cycling,
/CAS before /RAS

700

650
mA
1, 2
Average Power
Supply Current
(Fast Page Mode)
ICC7
/RAS = VIL,
/CAS cycling,
tPC = Min.

650

600
mA
1, 3
Notes: 1. ICC Max. is specified as ICC for output open condition.
2. The address can be changed once or less while /RAS = VIL.
3. The address can be changed once or less while /CAS = VIH.
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Semiconductor
MSC23441D
AC Characteristics (1/2)
(VCC = 5V ±10%, Ta = 0°C to 70°C) Note: 1, 2, 3, 11, 12
Parameter
Symbol
-60
-70
Min.
Max.
Min.
Max.
Unit
Note
Random Read or Write Cycle Time
tRC
110

130

ns
Read Modify Write Cycle Time
tRWC
155

185

ns
Fast Page Mode Cycle Time
tPC
40

45

ns
Fast Page Mode Read Modify Write Cycle Time
tPRWC
85

100

ns
Access Time from /RAS
tRAC

60

70
ns
4, 5, 6
Access Time from /CAS
tCAC

15

20
ns
4, 5
Access Time from Column Address
tAA

30

35
ns
4, 6
Access Time from /CAS Precharge
tCPA

35

40
ns
4
Access Time from /OE
tOEA

15

20
ns
4
Output Low Impedance Time from /CAS
tCLZ
0

0

ns
4
/CAS to Data Output Buffer Turn-off Delay Time
tOFF
0
15
0
20
ns
7
/OE to Data Output Buffer Turn-off Delay Time
tOEZ
0
15
0
20
ns
7
Transition Time
tT
3
50
3
50
ns
3
Refresh Period
tREF

64

64
ms
/RAS Precharge Time
tRP
40

50

ns
/RAS Pulse Width
tRAS
60
10K
70
10K
ns
/RAS Pulse Width (Fast Page Mode)
tRASP
60
100K
70
100K
ns
/RAS Hold Time
tRSH
15

20

ns
/RAS Hold Time referenced to /OE
tROH
15

20

ns
/CAS Precharge Time (Fast Page Mode)
tCP
10

10

ns
/CAS Pulse Width
tCAS
15
10K
20
10K
ns
/CAS Hold Time
tCSH
60

70

ns
/CAS to /RAS Precharge Time
tCRP
5

5

ns
/RAS Hold Time from /CAS Precharge
tRHCP
35

40

ns
/RAS to /CAS Delay Time
tRCD
20
45
20
50
ns
5
/RAS to Column Address Delay Time
tRAD
15
30
15
35
ns
6
Row Address Set-up Time
tASR
0

0

ns
Row Address Hold Time
tRAH
10

10

ns
Column Address Set-up Time
tASC
0

0

ns
Column Address Hold Time
tCAH
15

15

ns
Column Address to /RAS Lead Time
tRAL
30

35

ns
Read Command Set-up Time
tRCS
0

0

ns
Read Command Hold Time
tRCH
0

0

ns
8
Read Command Hold Time referenced to /RAS
tRRH
0

0

ns
8
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Semiconductor
MSC23441D
AC Characteristics (2/2)
(VCC = 5V ±10%, Ta = 0°C to 70°C) Note: 1, 2, 3, 11, 12
Parameter
Symbol
-60
-70
Min.
Max.
Min.
Max.
Unit
Note
Write Command Set-up Time
tWCS
0

0

ns
Write Command Hold Time
tWCH
10

15

ns
Write Command Pulse Width
tWP
10

10

ns
/OE Command Hold Time
tOEH
15

20

ns
Write Command to /RAS Lead Time
tRWL
15

20

ns
Write Command to /CAS Lead Time
tCWL
15

20

ns
Data-in Set-up Time
tDS
0

0

ns
10
Data-in Hold Time
tDH
10

15

ns
10
/OE to Data-in Delay Time
tOED
15

20

ns
/CAS to /WE Delay Time
tCWD
40

50

ns
9
Column Address to /WE Delay Time
tAWD
55

65

ns
9
/RAS to /WE Delay Time
tRWD
85

100

ns
9
/CAS Precharge /WE Delay Time
tCPWD
60

70

ns
9
/CAS Active Delay Time from /RAS Precharge
tRPC
5

5

ns
/RAS to /CAS Set-up Time (/CAS before /RAS)
tCSR
10

10

ns
/RAS to /CAS Hold Time (/CAS before /RAS)
tCHR
10

10

ns
/WE to /RAS Precharge Time (/CAS before /RAS)
tWRP
10

10

ns
/WE Hold Time from /RAS (/CAS before /RAS)
tWRH
10

10

ns
/RAS to /WE Set-up Time (Test Mode)
tWTS
10

10

ns
/RAS to /WE Hold Time (Test Mode)
tWTH
10

10

ns
9
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Semiconductor
MSC23441D
Notes: 1. A start-up delay of 200µs is required after power-up, followed by a minimum of eight initialization cycles
(/RAS only refresh or /CAS before /RAS refresh) before proper device operation is achieved.
2. The AC characteristics assumes tT = 5ns.
3. VIH(Min.) and VIL(Max.) are reference levels for measuring input timing signals. Transition times (tT) are
measured between VIH and VIL.
4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100pF.
5. Operation within the tRCD(Max.) limit ensures that tRAC(Max.) can be met.
tRCD(Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD(Max.) limit, then
the access time is controlled by tCAC.
6. Operation within the tRAD(Max.) limit ensures that tRAC(Max.) can be met.
tRAD(Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD(Max.) limit, then
the access time is controlled by tAA.
7. tOFF(Max.) and tOEZ(Max.) define the time at which the output achieves the open circuit condition and are
not referenced to output voltage levels.
8. tRCH or tRRH must be satisfied for a read cycle.
9. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictve operating parameters. They are included in the data
sheet as electrical characteristics only. If tWCS ≥ tWCS(Min.), then the cycle is an early write cycle and the
data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD ≥ tCWD(Min.), tRWD
≥ tRWD(Min.), tAWD ≥ tAWD(Min.) and tCPWD ≥ tCPWD(Min.), then the cycle is a read modify write cycle and
data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied,
then the condition of the data out (at access time) is indeterminate.
10. These parameters are referenced to the /CAS leading edge in an early write cycle, and to the /WE
leading edge in an /OE control write cycle, or a read modify write cycle.
11. The test mode is initiated by performing a /WE and /CAS before /RAS refresh cycle. This mode is
latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet
is a 4-bit parallel test function. CA0 and CA1 are not used. In a read cycle, if all internal bits are equal,
the DQ pin will indicate a high level. If any internal bits are not equal, the DQ pin will indicate a low level.
The test mode is cleared and the memory device returned to its normal operating state by a /RAS only
refresh or /CAS before /RAS refresh cycle.
12. In a test mode read cycle, the value of access time parameters is delayed for 5ns for the specified value.
These parameters should be specified in test mode cycle by adding the above value to the specified
value in this data sheet.
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