Pr E2G0127-17-61 el im y 2,097,152-Word ¥ 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE DESCRIPTION The MSM51V17800D/DSL is a 2,097,152-word ¥ 8-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM51V17800D/DSL achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/ double-layer metal CMOS process. The MSM51V17800D/DSL is available in a 28-pin plastic SOJ or 28-pin plastic TSOP. The MSM51V17800DSL (the self-refresh version) is specially designed for lower-power applications. FEATURES • 2,097,152-word ¥ 8-bit configuration • Single 3.3 V power supply, ±0.3 V tolerance • Input : LVTTL compatible, low input capacitance • Output : LVTTL compatible, 3-state • Refresh : 2048 cycles/32 ms, 2048 cycles/128 ms (SL version) • Fast page mode, read modify write capability • CAS before RAS refresh, hidden refresh, RAS-only refresh capability • CAS before RAS self-refresh capability (SL version) • Multi-bit test mode capability • Package options: 28-pin 400 mil plastic SOJ (SOJ28-P-400-1.27) (Product : MSM51V17800D/DSL-xxJS) 28-pin 400 mil plastic TSOP (TSOPII28-P-400-1.27-K) (Product : MSM51V17800D/DSL-xxTS-K) xx indicates speed rank. PRODUCT FAMILY Family Access Time (Max.) tRAC tAA tCAC tOEA ar This version: Mar. 1998 MSM51V17800D/DSL in ¡ Semiconductor MSM51V17800D/DSL ¡ Semiconductor Cycle Time Power Dissipation (Min.) Operating (Max.) Standby (Max.) MSM51V17800D/DSL-50 50 ns 25 ns 13 ns 13 ns 90 ns 360 mW MSM51V17800D/DSL-60 60 ns 30 ns 15 ns 15 ns 110 ns 324 mW MSM51V17800D/DSL-70 70 ns 35 ns 20 ns 20 ns 130 ns 288 mW 1.8 mW/ 0.72 mW (SL version) 1/17 ¡ Semiconductor MSM51V17800D/DSL PIN CONFIGURATION (TOP VIEW) VCC 1 28 VSS VCC 1 28 VSS DQ1 2 27 DQ8 DQ1 2 27 DQ8 DQ2 3 26 DQ7 DQ2 3 26 DQ7 DQ3 4 25 DQ6 DQ3 4 25 DQ6 DQ4 5 24 DQ5 DQ4 5 24 DQ5 WE 6 23 CAS WE 6 23 CAS RAS 7 22 OE RAS 7 22 OE NC 8 21 A9 NC 8 21 A9 A10R 9 20 A8 A10R 9 20 A8 A0 10 19 A7 A0 10 19 A7 A1 11 18 A6 A1 11 18 A6 A2 12 17 A5 A2 12 17 A5 A3 13 16 A4 A3 13 16 A4 VCC 14 15 VSS VCC 14 15 VSS 28-Pin Plastic SOJ Pin Name A0 - A9, A10R RAS Note : 28-Pin Plastic TSOP (K Type) Function Address Input Row Address Strobe CAS Column Address Strobe DQ1 - DQ8 Data Input/Data Output OE Output Enable WE Write Enable VCC Power Supply (3.3 V) VSS Ground (0 V) NC No Connection The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin. 2/17 ¡ Semiconductor MSM51V17800D/DSL BLOCK DIAGRAM WE RAS OE Timing Generator I/O Controller CAS 8 Output Buffers 8 Input Buffers 8 DQ1 - DQ8 10 Internal Address Counter A0 - A9 10 A10R Column Address Buffers 1 10 Refresh Control Clock Row Row Address 11 DecoBuffers ders Word Drivers Column Decoders Sense Amplifiers 8 I/O Selector 8 8 Memory Cells VCC On Chip VBB Generator VSS 3/17 ¡ Semiconductor MSM51V17800D/DSL ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Symbol Rating Unit VT –0.5 to 4.6 V Short Circuit Output Current IOS 50 mA Power Dissipation PD* 1 W Operating Temperature Topr 0 to 70 °C Storage Temperature Tstg –55 to 150 °C Voltage on Any Pin Relative to VSS *: Ta = 25°C Recommended Operating Conditions Parameter Power Supply Voltage (Ta = 0°C to 70°C) Symbol Min. Typ. Max. Unit VCC 3.0 3.3 3.6 V VSS 0 0 0 V Input High Voltage VIH 2.0 — VCC + 0.3 V Input Low Voltage VIL –0.3 — 0.8 V Capacitance (VCC = 3.3 V ±0.3 V, Ta = 25°C, f = 1 MHz) Symbol Typ. Max. Unit Input Capacitance (A0 - A9, A10R) CIN1 — 5 pF Input Capacitance (RAS, CAS, WE, OE) CIN2 — 7 pF Output Capacitance (DQ1 - DQ8) CI/O — 7 pF Parameter 4/17 ¡ Semiconductor MSM51V17800D/DSL DC Characteristics Parameter (VCC = 3.3 V ±0.3 V, Ta = 0°C to 70°C) Symbol Condition MSM51V17800 MSM51V17800 MSM51V17800 D/DSL-50 D/DSL-60 D/DSL-70 Unit Note Min. Max. Min. Max. Min. Max. Output High Voltage VOH IOH = –2.0 mA 2.4 VCC 2.4 VCC 2.4 VCC V Output Low Voltage VOL IOL = 2.0 mA 0 0.4 0 0.4 0 0.4 V Input Leakage Current ILI –10 10 –10 10 –10 10 mA –10 10 –10 10 –10 10 mA — 100 — 90 — 80 mA 1, 2 — 2 — 2 — 2 — 0.5 — 0.5 — 0.5 mA 1 — 200 — 200 — 200 mA 1, 5 — 100 — 90 — 80 mA 1, 2 — 5 — 5 — 5 mA 1 — 100 — 90 — 80 mA 1, 2 — 75 — 70 — 65 mA 1, 3 — 300 — 300 — 300 mA — 300 — 300 — 300 mA 0 V £ VI £ VCC + 0.3 V; All other pins not under test = 0 V Output Leakage Current ILO Average Power Supply Current ICC1 (Operating) DQ disable 0 V £ VO £ VCC RAS, CAS cycling, tRC = Min. RAS, CAS = VIH Power Supply Current (Standby) ICC2 RAS, CAS ≥ VCC –0.2 V RAS cycling, Average Power ICC3 CAS = VIH, Supply Current (RAS-only Refresh) tRC = Min. RAS = VIH, Power Supply Current (Standby) ICC5 CAS = VIL, DQ = enable Average Power ICC6 Supply Current (CAS before RAS Refresh) RAS cycling, CAS before RAS RAS = VIL, Average Power ICC7 CAS cycling, Supply Current (Fast Page Mode) tPC = Min. Average Power tRC = 62.5 ms, ICC10 CAS before RAS, Supply Current tRAS £ 1 ms (Battery Backup) 1, 4, 5 Average Power Supply Current (CAS before RAS ICCS RAS £ 0.2 V, CAS £ 0.2 V 1, 5 Self-Refresh) Notes : 1. 2. 3. 4. 5. ICC Max. is specified as ICC for output open condition. The address can be changed once or less while RAS = VIL. The address can be changed once or less while CAS = VIH. VCC – 0.2 V £ VIH £ VCC + 0.3 V, –0.3 V £ VIL £ 0.2 V. SL version. 5/17 ¡ Semiconductor MSM51V17800D/DSL AC Characteristics (1/2) (VCC = 3.3 V ±0.3 V, Ta = 0°C to 70°C) Note 1, 2, 3, 11, 12 Parameter MSM51V17800 MSM51V17800 MSM51V17800 D/DSL-60 D/DSL-70 Unit Note Symbol D/DSL-50 Min. Max. Min. Max. Min. Max. — — — 110 — — 130 — — ns ns tPC 90 131 35 — ns tPRWC 76 — Access Time from RAS tRAC — Access Time from CAS tCAC — Access Time from Column Address Access Time from CAS Precharge tAA tCPA Access Time from OE Output Low Impedance Time from CAS Random Read or Write Cycle Time Read Modify Write Cycle Time tRC tRWC — 185 45 85 — 100 — ns 50 — 60 — 70 ns 4, 5, 6 13 — 15 — 20 ns 4, 5 — — 25 30 — — 30 35 — — 35 40 ns ns 4, 6 4 tOEA tCLZ — 0 13 — — 0 15 — — 0 20 — ns ns 4 4 CAS to Data Output Buffer Turn-off Delay Time tOFF tOEZ tT tREF 0 0 3 — 13 OE to Data Output Buffer Turn-off Delay Time Transition Time Refresh Period 13 50 32 0 0 3 — 15 15 50 32 0 0 3 — 20 20 50 32 ns ns ns ms 7 7 3 Refresh Period (SL version) tREF — 128 — 128 — 128 ms 13 RAS Precharge Time tRP 30 — 40 — 50 — ns RAS Pulse Width tRAS 50 10,000 60 10,000 70 10,000 ns RAS Pulse Width (Fast Page Mode) tRASP 50 100,000 60 100,000 70 100,000 ns RAS Hold Time tRSH 13 tROH 13 15 15 — — 20 20 — — ns RAS Hold Time referenced to OE — — CAS Precharge Time (Fast Page Mode) tCP 7 — 10 — 10 — ns CAS Pulse Width tCAS 13 10,000 15 10,000 20 10,000 ns CAS Hold Time tCSH CAS to RAS Precharge Time tCRP 50 5 — — 60 5 — — 70 5 — — ns ns RAS Hold Time from CAS Precharge tRHCP RAS to CAS Delay Time tRCD RAS to Column Address Delay Time tRAD 30 17 12 — 37 25 35 20 15 — 45 30 40 20 15 — 50 35 ns ns ns Row Address Set-up Time tASR 0 — 0 — 0 — ns Row Address Hold Time tRAH 7 — 10 — 10 — ns Column Address Set-up Time tASC 0 — 0 — 0 — ns Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time 155 40 ns 5 6 Column Address Hold Time tCAH 7 — 10 — 15 — ns Column Address to RAS Lead Time tRAL 25 — 30 — 35 — ns Read Command Set-up Time tRCS 0 — 0 — 0 — ns Read Command Hold Time tRCH 0 — 0 — 0 — ns 8 Read Command Hold Time referenced to RAS tRRH 0 — 0 — 0 — ns 8 6/17 ¡ Semiconductor MSM51V17800D/DSL AC Characteristics (2/2) (VCC = 3.3 V ±0.3 V, Ta = 0°C to 70°C) Note 1, 2, 3, 11, 12 Parameter Symbol MSM51V17800MSM51V17800 MSM51V17800 D/DSL-50 D/DSL-60 D/DSL-70 Unit Note Min. Max. Min. Max. Min. Max. Write Command Set-up Time tWCS 0 — 0 — 0 — ns Write Command Hold Time tWCH 7 — 10 — 15 — ns Write Command Pulse Width OE Command Hold Time Write Command to RAS Lead Time Write Command to CAS Lead Time tWP tOEH tRWL tCWL 7 13 — — 10 15 — — 10 20 — — ns ns 13 13 — — 15 15 — — 20 20 — — ns ns Data-in Set-up Time Data-in Hold Time OE to Data-in Delay Time tDS tDH tOED tCWD tAWD tRWD — — — — — — 0 10 15 40 55 85 — — — — — — 0 15 20 50 65 100 — — — — — — ns ns ns ns ns ns 10 10 CAS to WE Delay Time Column Address to WE Delay Time RAS to WE Delay Time 0 7 13 36 48 73 CAS Precharge WE Delay Time tCPWD 53 — 60 — 70 — ns 9 9 9 9 9 CAS Active Delay Time from RAS Precharge tRPC 5 — 5 — 5 — ns RAS to CAS Set-up Time (CAS before RAS) RAS to CAS Hold Time (CAS before RAS) tCSR tCHR 10 10 — — 10 10 — — 10 10 — — ns ns WE to RAS Precharge Time (CAS before RAS) WE Hold Time from RAS (CAS before RAS) RAS to WE Set-up Time (Test Mode) RAS to WE Hold Time (Test Mode) tWRP tWRH tWTS tWTH 10 10 10 10 — — — — 10 10 10 10 — — — — 10 10 10 10 — — — — ns ns ns ns tRASS 100 — 100 — 100 — ms 13 tRPS 90 — 110 — 130 — ns 13 tCHS –50 — –50 — –50 — ns 13 RAS Pulse Width (CAS before RAS Self-Refresh) RAS Precharge Time (CAS before RAS Self-Refresh) CAS Hold Time (CAS before RAS Self-Refresh) 7/17 ¡ Semiconductor Notes: MSM51V17800D/DSL 1. A start-up delay of 200 µs is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 5 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 1 TTL load and 100 pF. The output timing reference levels are VOH = 2.0 V and VOL = 0.8 V. 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. 7. tOFF (Max.) and tOEZ (Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. tRCH or tRRH must be satisfied for a read cycle. 9. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD ≥ tCWD (Min.) , tRWD ≥ tRWD (Min.), tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 10. These parameters are referenced to the CAS leading edge in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle. 11. The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet is a 2-bit parallel test function. CA9 is not used. In a read cycle, if all internal bits are equal, the DQ pin will indicate a high level. If any internal bits are not equal, the DQ pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operating state by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle. 12. In a test mode read cycle, the value of access time parameters is delayed for 5 ns for the specified value. These parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet. 13. Only SL version. 8/17 E2G0101-17-41N ¡ Semiconductor MSM51V17800D/DSL ,,, , ,,,, TIMING WAVEFORM Read Cycle tRC tRP tRAS RAS VIH – VIL – tCRP tCSH tCRP CAS tRCD VIH – VIL – tRAD tASR Address VIH – VIL – tRSH tCAS tRAH tASC tRAL tCAH Column Row tRCS WE OE VIH – VIL – tAA tROH tOEA VIH – VIL – tCAC tRAC DQ tRCH tRRH VOH – tOEZ Open VOL – tOFF Valid Data-out tCLZ "H" or "L" Write Cycle (Early Write) tRC tRP tRAS RAS VIH – VIL – tCRP tCRP CAS VIH – VIL – WE OE VIH – VIL – tASC Row tCAS tCAH tRAL Column tWCS VIH – tWCH tCWL tWP VIL – tRWL VIH – VIL – tDS DQ tRSH tRAD tRAH tASR Address tCSH tRCD VIH – VIL – tDH Valid Data-in Open "H" or "L" 9/17 ,,, ¡ Semiconductor MSM51V17800D/DSL Read Modify Write Cycle tRWC tRAS RAS VIH – VIL – tRP tCRP tCSH tCRP tRCD tRSH tCAS VIH – CAS VIL – tASR VIH – Address VIL – WE VIH – VIL – OE VIH – VIL – tRAH tASC tCAH Column Row tRAD tRWD tAA tAWD tRCS tOEA tOED tCAC tRAC DQ VI/OH– VI/OL– tCWL tRWL tWP tCWD tCLZ tOEZ Valid Data-out tOEH tDS tDH Valid Data-in "H" or "L" 10/17 ,, , , ,, , ¡ Semiconductor MSM51V17800D/DSL Fast Page Mode Read Cycle tRASP VIH – RAS V – IL VIH – CAS VIL – Address WE VIH – VIL – tRP tRHCP tCRP tPC tRCD tCP tASR tCP tCAS tCAS tRAD tRAH tASC tCSH tCAH tASC Column Row VIH – VIL – tCAC VOH – DQ VOL – Column tRCS tRCH tRRH tCPA tOEA tOFF tOEZ tRCH tAA tAA tCAC tOEA tOFF tCAC tOEZ tCLZ Valid Data-out tCLZ tRCS tCPA tOEA tRAC tRAL tCAH tASC Column tAA VIH – OE VIL – tCAS tCAH tRCH tRCS tCRP tRSH tCLZ tOFF tOEZ Valid Data-out Valid Data-out "H" or "L" Fast Page Mode Write Cycle (Early Write) tRASP VIH – RAS V – IL tCRP VIH – CAS VIL – Address VIH – VIL – tCAS tASR tRAH tASC Row tRAD VIH – VIL – tDS VIH – DQ VIL – tRHCP tRSH tRCD tWCS WE tRP tPC tCSH tCAH Column tCWL tWCH tWP tDH Valid Data-in tCP tCRP tCP tCAS tASC tCAH tASC Column tCWL tWCS tWCH tWP tDS tDH Valid Data-in tCAS tCAH tRAL Column tRWL tCWL tWCS tWCH tWP tDS tDH Valid Data-in Note: OE = "H" or "L" "H" or "L" 11/17 ¡ Semiconductor MSM51V17800D/DSL ,,, , , , , Fast Page Mode Read Modify Write Cycle tRASP VIH – RAS VIL – tRP tCSH tPRWC tRCD VIH – CAS VIL – tASC tCAH tRAH VIH – VIL – tCRP tCAS tASC tCAH tCAH Column Column tASC Column Row tRCS tCPWD tCWD tRWD tCWD tRCS V WE IH – VIL – tCWL tAWD tCWL tWP tDH VI/OH– VI/OL – Out tCLZ tOEA tOED tOEZ tCAC In tDH tDS tOEA tOEZ tCAC tWP tCPA tAA tOED VIH – OE V – IL tCWL tROH tWP tDH tDS tOEA tRWL tAWD tCPA tAA tAA tRAL tRCS tCPWD tCWD tAWD tDS tRAC DQ tCP tCAS tRAD tASR Address tCP tCAS tRSH Out tOED In tCLZ tOEZ tCAC Out In tCLZ "H" or "L" RAS-Only Refresh Cycle tRC RAS VIL – CAS Address VIH – VIL – VIH – VIL – tRP tRAS VIH – tCRP tASR tRPC tRAH Row tOFF DQ VOH – VOL – Open Note: WE, OE = "H" or "L" "H" or "L" 12/17 M L K ^ ] \ S R Q P ¡ Semiconductor MSM51V17800D/DSL CAS before RAS Refresh Cycle tRC tRP RAS tRP tRAS VIH – VIL – tRPC tRPC tCP CAS tCSR tCHR tWRP tWRH VIH – VIL – tWRP , ,, , WE VIH – VIL – DQ VOH – VOL – tOFF Open Note: OE, Address = "H" or "L" "H" or "L" Hidden Refresh Read Cycle tRC tRAS RAS tRP VIL – VIH – VIL – VIH – VIL – tRSH tRCD tRAD tASC tRAH tASR Address tRAS tRP VIH – tCRP CAS tRC Row tCHR tCAH Column tRCS tRAL VIH – WE V IL – tRRH tAA tROH tOEA VIH – OE V IL – tRAC DQ VOH – VOL – tCAC tCLZ tOFF tOEZ Valid Data-out "H" or "L" 13/17 ¡ Semiconductor MSM51V17800D/DSL Hidden Refresh Write Cycle tRC tRAS VIH – VIL – RAS Address VIH – VIL – tCRP tRCD tRSH tRAD tASC tASR tCAH tRAH Row WE VIH – VIL – OE VIH – VIL – tCHR tRAL Column tWCS tDS DQ tRP , ,,,, , VIH – VIL – CAS tRC tRAS tRP VIH – VIL – tWCH tWP tWRP tWRH tDH Valid Data-in "H" or "L" CAS before RAS Self-Refresh Cycle tRASS tRP VIH – RAS VIL – tRPS tRPC tCP tRPC tCSR tCHS VIH – CAS VIL – tOFF DQ VOH – VOL – Open Note: WE, OE, Address = "H" or "L" Only SL version "H" or "L" 14/17 , ¡ Semiconductor MSM51V17800D/DSL Test Mode Initiate Cycle tRC tRP RAS VIH – VIL – tRPC tCP CAS tRAS tCSR VIH – VIL – tWTS WE tCHR tWTH VIH – VIL – tOFF DQ VOH – VOL – Open Note: OE, Address = "H" or "L" "H" or "L" 15/17 ¡ Semiconductor MSM51V17800D/DSL PACKAGE DIMENSIONS (Unit : mm) SOJ28-P-400-1.27 Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.30 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 16/17 ¡ Semiconductor MSM51V17800D/DSL (Unit : mm) TSOPII28-P-400-1.27-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.51 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 17/17