E2L0047-28-Z2 This version: Dec. 1998 MSM5416258A Previous version: Jan. 1998 ¡ Semiconductor MSM5416258A ¡ Semiconductor 262,144-Word ¥ 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO DESCRIPTION The MSM5416258A is a 262,144-word ¥ 16-bit dynamic RAM fabricated in Oki's CMOS silicon gate technology. The MSM5416258A achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/double-layer metal CMOS process. The MSM5416258A is available in a 44/40-pin plastic TSOP. FEATURES • 262,144-word ¥ 16-bit configuration • Single 5.0 V power supply, ±0.5 V tolerance • Input: TTL compatible • Output: TTL compatible, 3-state • Refresh: 512 cycles/8 ms • Fast page mode with EDO, read modify write capability • Byte wide control: 2 CAS control • CAS before RAS refresh, hidden refresh, RAS only refresh capability • Package : 44/40-pin 400 mil plastic TSOP (Type II) (TSOPII44/40-P-400-0.80-K) (Product : MSM5416258A-xxTS-K) xx indicates speed rank. PRODUCT FAMILY Family Access Time (Max.) Cycle Time (Min.) Power Dissipation tRC tHPC (Max.) MSM5416258A-40 40 ns 22 ns 10 ns 10 ns 80 ns 15 ns 825 mW MSM5416258A-45 45 ns 24 ns 12 ns 12 ns 90 ns 20 ns 770 mW tRAC tAA tCAC tOEA 1/21 ¡ Semiconductor MSM5416258A PIN CONFIGURATION (TOP VIEW) VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 1 2 3 4 5 6 7 8 9 10 44 43 42 41 40 39 38 37 36 35 VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 VSS* NC WE RAS NC A0 A1 A2 A3 VCC 13 14 15 16 17 18 19 20 21 22 32 31 30 29 28 27 26 25 24 23 VSS* LCAS UCAS OE A8 A7 A6 A5 A4 VSS 44/40-Pin Plastic TSOP (II) (K Type) Pin Name A0 - A8 RAS Function Address Input Row Address Strobe LCAS, UCAS Column Address Strobe DQ0 - DQ15 Data - Input / Data - Output WE Write Enable OE Output Enable VCC Power Supply (5.0 V) VSS Ground (0 V) NC No Connection VSS* Ground (0 V)* Note: The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin. *: For improved signal integrity, it is recommended to connect the VSS* pins, pin 13 and pin 32, to GND: the pins are electrically connected to internal GND. 2/21 ¡ Semiconductor MSM5416258A BLOCK DIAGRAM OE RAS WE Timing Generator I/O Controller LCAS UCAS I/O Controller 8 Output Buffers 8 Input Buffers 8 8 Input Buffers 8 8 Output Buffers 8 DQ0 - DQ7 Column Address Buffers 9 9 Internal Address Counter A0 - A8 Row Address Buffers 9 Refresh Control Clock Row Decoders 9 Column Decoders Sense Amplifiers Word Drivers 16 I/O Selector 16 DQ8 - DQ15 Memory Cells 8 VCC On-chip VBB Generator VSS FUNCTION TABLE Input Pin RAS LCAS DQ Pin UCAS WE OE DQ0 - DQ7 DQ8 - DQ15 Function Mode H * * * * High-Z High-Z Standby L H H * * High-Z High-Z Refresh L L H H L Lower Byte Read H L H L DOUT High-Z High-Z L DOUT Upper Byte Read L L L H L DOUT DOUT Word Read L L H L H DIN Don't Care Lower Byte Write L H L L H Don't Care DIN Upper Byte Write L L L L H DIN DIN Word Write L L L H H High-Z High-Z — * : "H" or "L" 3/21 ¡ Semiconductor MSM5416258A ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Symbol Condition Rating Unit Voltage on Any Pin Relative to VSS VT Ta = 25°C –1.0 to 7.0 V Short Circuit Output Current IOS Ta = 25°C 50 mA Power Dissipation PD Ta = 25°C 1 W Operating Temperature Topr — 0 to 70 °C Storage Temperature Tstg — –55 to 150 °C Recommended Operating Conditions Parameter Power Supply Voltage (Ta = 0°C to 70°C) Symbol Min. Typ. Max. Unit VCC 4.5 5.0 5.5 V VSS 0 0 0 V Input High Voltage VIH 2.4 — VCC + 1.0 V Input Low Voltage VIL –1.0 — 0.8 V Capacitance Parameter (VCC = 5.0 V ±0.5 V, Ta = 25°C, f = 1 MHz) Symbol Typ. Max. Unit Input Capacitance (A0 - A8) CIN1 — 5 pF Input Capacitance (RAS, LCAS, UCAS, WE, OE) CIN2 — 7 pF Input / Output Capacitance (DQ0 - DQ15) CI/O — 7 pF 4/21 ¡ Semiconductor MSM5416258A DC Characteristics (VCC = 5.0 V ±0.5 V, Ta = 0°C to 70°C) Parameter Symbol Condition MSM5416258A -40 MSM5416258A -45 Unit Note Min. Max. Min. Max. Output High Voltage VOH IOH = –2.5 mA 2.4 VCC 2.4 VCC V Output Low Voltage VOL IOL = 2.0 mA 0 0.4 0 0.4 V Input Leakage Current ILI 0 V £ VI £ VCC –10 10 –10 10 mA Output Leakage Current ILO DQi Disable 0 V £ VO £ 5.5 V –10 10 –10 10 mA Average Power Supply Current (Operating) ICC1 RAS, CAS Cycling, tRC = Min. — 150 — 140 mA 1, 2 Power Supply Current (Standby) ICC2 RAS, CAS = VIH — 3 — 3 Average Power Supply Current (RAS Only Refresh) ICC3 RAS = Cycling, CAS = VIH, tRC = Min. — 150 — 140 mA 1, 2 Average Power Supply Current (Fast Page Mode) ICC4 RAS = VIL, CAS Cycling, tHPC = Min. — 130 — 115 mA 1, 3 Average Power Supply Current (CAS before RAS Refresh) ICC5 RAS = Cycling, CAS before RAS — 150 — 140 mA 1, 2 mA 1 Notes : 1. ICC Max. is specified as ICC for output open condition. 2. The address can be changed once or less while RAS = VIL. 3. The address can be changed once or less while CAS = VIH. 5/21 ¡ Semiconductor MSM5416258A AC Characteristics (1/2) (VCC = 5.0 V ±0.5 V, Ta = 0°C to 70°C) MSM5416258A -40 MSM5416258A -45 Min. Max. Min. Max. tRC 80 — 90 — ns Read Modify Write Cycle Time tRWC 115 — 130 — ns Fast Page Mode Cycle Time tHPC 15 — 20 — ns Parameter Random Read or Write Cycle Time Symbol Unit Note tPRWC 55 — 60 — ns Access Time from RAS tRAC — 40 — 45 ns 7, 12, 13 Access Time from CAS tCAC — 10 — 12 ns 7, 12 Access Time from Column Address tAA — 22 — 24 ns 7, 13 Access Time from OE tOEA — 10 — 12 ns Access Time from CAS Precharge tCPA — 22 — 24 ns Fast Page Mode Read Modify Write Cycle Time 7, 12 Output Low Impedance Time from CAS tCLZ 0 — 0 — ns Data Hold After CAS Low tCOH 3 — 3 — ns 17 Output Buffer Turn-off Delay Time tOFF 3 8 3 8 ns 8 Output Buffer Turn-off Delay Time from OE tOEZ 3 8 3 8 ns 8 Output Buffer Turn-off Delay Time from RAS tREZ 1.5 8 1.5 8 ns 8 Output Buffer Turn-off Delay Time from WE tWEZ 3 8 3 8 ns 8 Transition Time tT 2 35 2 35 ns Refresh Period tREF — 8 — 8 ms RAS Precharge Time tRP 30 — 35 — ns RAS Pulse Width tRAS 40 10,000 45 10,000 ns RAS Pulse Width (Fast Page Mode) tRASP 40 100,000 45 100,000 ns RAS Hold Time tRSH 8 — 10 — ns RAS Hold Time Reference to OE tROH 8 — 8 — ns CAS Precharge Time tCP 5 — 6 — ns CAS Pulse Width tCAS 6 10,000 7 10,000 ns CAS Hold Time tCSH 35 — 35 — ns CAS to RAS Precharge Time tCRP 5 — 5 — ns RAS Hold Time from CAS Precharge tRHCP 22 — 24 — ns RAS to CAS Delay Time tRCD 18 30 18 30 ns 12 RAS to Column Address Delay Time tRAD 13 18 13 18 ns 13 Row Address Set-up Time tASR 0 — 0 — ns Row Address Hold Time tRAH 8 — 8 — ns Column Address Set-up Time tASC 0 — 0 — ns Column Address Hold Time tCAH 6 — 6 — ns Column Address Hold Time from RAS tAR 30 — 30 — ns Column Address to RAS Lead Time tRAL 22 — 24 — ns 6/21 ¡ Semiconductor MSM5416258A AC Characteristics (2/2) Parameter (VCC = 5.0 V ±0.5 V, Ta = 0°C to 70°C) Symbol MSM5416258A -40 MSM5416258A -45 Min. Max. Min. Max. Unit Note Read Command Set-up Time tRCS 0 — 0 — ns Read Command Hold Time tRCH 0 — 0 — ns 9 Read Command Hold Time Reference to RAS tRRH 0 — 0 — ns 9 WE Pulse Width (DQ Disable) tWEP 10 — 10 — ns Write Command Set-up Time tWCS 0 — 0 — ns Write Command Hold Time tWCH 6 — 6 — ns 11 tWP 6 — 6 — ns tWCR 30 — 30 — ns OE Command Hold Time tOEH 6 — 7 — ns Write Command to CAS Lead Time tCWL 6 — 7 — ns Write Command to RAS Lead Time tRWL 8 — 9 — ns Data to CAS Delay Time tDZC 0 — 0 — ns Data to OE Delay Time tDZO 0 — 0 — ns Data-in Set-up Time tDS 0 — 0 — ns 10 Data-in Hold Time tDH 6 — 7 — ns 10 Data-in Hold Time referenced to RAS tDHR 30 — 30 — ns OE to Data-in Delay Time tOED 8 — 8 — ns OE "L" to CAS "H" Lead Time tOCH 10 — 10 — ns CAS "H" to OE "L" Lead Time tCHO 10 — 10 — ns Write Command Pulse Width Write Command Hold Time from RAS Hi-Z Command Pulse Width tOEP 10 — 10 — ns CAS to WE Delay Time tCWD 22 — 22 — ns 11 Column Address to WE Delay Time tAWD 32 — 32 — ns 11 11 RAS to WE Delay Time tRWD 50 — 55 — ns CAS Active Delay Time from RAS Precharge tRPC 0 — 0 — ns RAS to CAS Set-up Time (CAS before RAS) tCSR 10 — 10 — ns RAS to CAS Hold Time (CAS before RAS) tCHR 10 — 10 — ns 7/21 ¡ Semiconductor Notes: MSM5416258A 1. All voltages are referenced to VSS. 2. This parameter is dependent upon the cycle rate. 3. This parameter is dependent upon the output loading. Specified values are obtained with the output open. 4. An initial pause of 200 ms is required after power-up, followed by any 8 RAS cycles. (Example : RAS-only-refresh) before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS before RAS cycles instead of 8 RAS cycles are required. 5. The AC characteristics assume tT = 5 ns. 6. VIH (Min.) and VIL (Max.) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. 7. Data outputs are measured with a load of 50 pF. DOUT reference levels: VOH/VOL = 2.0 V/1.4 V. Note that VOL is defined as 1.4 V when VSS* pins, pin 13 and pin 32, were open. The data output measurements under VOH/VOL = 2.0 V/0.8 V are guaranteed when VSS* pins, pin 13 and pin 32, were connected to GND. 8. tREZ (Max.), tOFF (Max.), tWEZ (Max.) and tOEZ (Max.) define the time at which the outputs achieve the open circuit condition and are not referenced to output voltage levels. This parameter is sampled and not 100% tested. 9. Either tRCH or tRRH must be satisfied for a read cycle. 10. These parameters are referenced to CAS leading edge of early write cycles and to WE leading edge in OE-controlled write cycles and read-modify-write cycles. 11. tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), the cycle is an early write cycle and the data out pins will remain open circuit throughout the entire cycle. If tRWD ≥ tRWD (Min.), tCWD ≥ tCWD (Min.) and tAWD ≥ tAWD (Min.), the cycle is a read-modify-write cycle and the data out will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of the data out is indeterminate. 12. Operation within the tRCD (Max.) limit insures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then access time is controlled by tCAC. 13. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only: If tRAD is greater than the specified tRAD (Max.) limit, then access time is controlled by tAA. 14. Input levels at the AC testing are 3.0 V/0 V. 15. Addresses (A0 - A8) may be changed two times or less while RAS = VIL. 16. Addresses (A0 - A8) may be changed once or less while CAS = VIH and RAS = VIL. 17. This is guaranteed by design. (tCOH = tCAC - output transition time). This parameter is not 100% tested. 18. This parameter is dependent upon the number of address transitions. Specified values are measured with a maximum of two transitions per address cycle in Fast Page Mode. 8/21 ¡ Semiconductor MSM5416258A , ,, TIMING WAVEFORM Read Cycle (RAS Output Control) tRC tRP tRAS RAS tCSH tCRP tRCD tRSH tCAS UCAS LCAS tAR tRAD tASR A0 - A8 tRAL tRAH tASC Row tCAH Column tRCH tRCS WE tRRH tROH tOEZ tOEA OE tCAC tOFF tAA DQ0 - 7 High-Z Valid Data tRAC DQ8 - 15 High-Z tOFF Valid Data "H" or "L" 9/21 ¡ Semiconductor MSM5416258A , ,, Read Cycle (CAS Output Control) tRC tRP tRAS RAS tCSH tCRP tRCD UCAS LCAS tRSH tCAS tAR tRAD tASR A0 - A8 tRAL tRAH tASC Row tCAH Column tRCS tRRH WE tROH tOEZ tOEA OE tCAC tOFF tAA DQ0 - 7 High-Z Valid Data tRAC DQ8 - 15 High-Z Valid Data "H" or "L" 10/21 ¡ Semiconductor MSM5416258A , ,, , ,, Early Write Cycle (LCAS and UCAS Active) tRC tRP tRAS RAS tCSH tCRP tRCD UCAS LCAS tRSH tCAS tAR tRAD tASR A0 - A8 tRAH tRAL tASC Row tCAH Column tCWL tRWL tWP WE tWCR tWCS tWCH OE tDHR tDS DQ0 - 7 Valid Data tDS DQ8 - 15 tDH tDH Valid Data "H" or "L" 11/21 ¡ Semiconductor MSM5416258A , ,, ,, ,, Late Write Cycle (LCAS and UCAS Active) tRC tRP tRAS RAS tCSH tCRP tRCD UCAS LCAS tRSH tCAS tAR tRAD tASR A0 - A8 tRAH Row tRAL tASC tCAH Column tCWL tRWL tRCS tWP WE tWCR tOEH OE tDS DQ0 - 7 Valid Data tDS DQ8 - 15 tDH tDH Valid Data "H" or "L" 12/21 ¡ Semiconductor MSM5416258A , ,, , ,, Read Modify Write Cycle (LCAS and UCAS Active) tRWC tRP tRAS RAS tCSH tCRP tRCD UCAS LCAS tRSH tCAS tAR tRAD tASR A0 - A8 tRAH tRAL tASC Row tCAH Column tAWD tCWL tRWL tWP tRCS WE tRWD tDZO tCWD tOEA tOEZ OE tOEH tOED tCAC tDZC tDS Out DQ0 - 7 tDH In tRAC tDS DQ8 - 15 Out tDH In "H" or "L" 13/21 ¡ Semiconductor MSM5416258A Fast Page Mode Read Cycle tRASP tAR tRHCP tRP RAS tPC tCRP tRSH , , , tCRP tRCD tCAS tCAS tRAD tASR A0 - A8 tCP tCAS UCAS LCAS tCP tRAH tASC Row tCSH tCAH tASC Column tRCS WE Column tRCH tAA tRCS tRAL tCAH tASC tCAH Column tRCH tAA tAA tCPA tOEA tOEA tRCH tRCS tRRH tCPA tOEA OE tCAC tRAC DQ0 - 7 tOFF tOEZ tCLZ DQ8 - 15 High-Z tOFF tOEZ Valid Data High-Z tCAC Valid Data tOFF tOEZ Valid Data tCLZ tCAC Valid Data tCLZ Valid Data Valid Data "H" or "L" 14/21 tAR RAS tCSH tCRP tHPC tRCD tRSH tCP UCAS LCAS tCAS tCP tCP tCAS tCRP tCAS tCAS tRAL tRAD ¡ Semiconductor tRP Fast Page Mode Read High-Z Operation tRC tRASP , tASR tRAH A0 - A8 tASC Row tCAH tASC tCAH tASC tCAH tASC tCAH Column Column Column Column tRRH tRCS tRCH tRCS tRCH WE tRAC tCHO tOEA tCAC tOEP tAA OE tCAC tDOH tWEP tOEP tCAC tCPA tAA tOCH tAA tOEZ tOEA tCAC tOEZ tOEA tWEZ tAA tREZ High-Z Valid Data Valid Data Valid Data Valid Data Valid Data DQ8 - 15 High-Z Valid Data Valid Data Valid Data Valid Data Valid Data 15/21 "H" or "L" MSM5416258A DQ0 - 7 ,,,, , , ,, ¡ Semiconductor MSM5416258A Fast Page Mode Early Write Cycle tRC tRASP tRP RAS tCRP tPC tAR tRAD tASR tRAH tCAS tCAS tCAH tASC tASC Row tRAL Column tWCS tWP tWCH tCAH Column tCWL WE tRSH tCP tCP tCAS UCAS LCAS A0 - A8 tCSH tRCD tASC Column tCWL tWCS tWP tWCH tCAH tCWL tWCS tWP tWCH OE tDS DQ0 - 7 Input Data tDS DQ8 - 15 tDH tDH Input Data tDS tDH Input Data tDS tDH Input Data tDS tDH Input Data tDS tDH Input Data "H" or "L" 16/21 ¡ Semiconductor MSM5416258A Fast Page Mode Read Modify Write Cycle , , , tRC tRP tRASP RAS tCSH tCRP tRCD UCAS LCAS tCAS tRSH tCAS tCP tAR tRAL tRAD tASR tRAH A0 - A8 tPRWC tCAS tCP tCAH tASC Row tCAH tASC Column Column tCWL tAWD WE tAWD tCWL tAWD tCWD tWP tOEA Column tCWL tCWD tRCS tCAH tASC tCWD tWP tOEZ tOEA tWP tOEZ tOEA tOEZ OE tCAC tCAC tAA tDH tCAC tDH tAA tDS DQ0 - 7 Out tCAC tAA DQ8 - 15 tDS In tDH tDS Out In Out Out tDS In tDH tCAC tDS tAA In tDH tAA Out In tDH tCAC tDS tAA Out In "H" or "L" 17/21 , ,,, , ¡ Semiconductor MSM5416258A CAS before RAS Refresh Cycle tRC tRP tRAS tRP RAS tRPC UCAS LCAS tCSR tRPC tCHR Inhibit Falling Transition A0 - A8 WE OE tOFF High-Z DQ0 - 7 tOFF DQ8 - 15 High-Z "H" or "L" 18/21 ¡ Semiconductor MSM5416258A , ,, Hidden Refresh Cycle tRC tRAS tRP tRAS RAS tCRP tRCD tRSH tCHR UCAS LCAS tAR tRAD tASR A0 - A8 tRAH tRAL tASC Row tCAH Column tRRH tRCS WE tROH tOEZ tOEA OE tRAC tOFF tCAC tAA DQ0 - 7 Valid Data High-Z tRAC tCAC tAA DQ8 - 15 High-Z tOFF Valid Data "H" or "L" 19/21 , ,,, , ¡ Semiconductor MSM5416258A RAS Only Refresh Cycle tRC tRAS tRP RAS tRPC tCRP UCAS LCAS A0 - A8 tASR tRAH Row WE OE DQ0 - 7 High-Z DQ8 - 15 High-Z "H" or "L" 20/21 ¡ Semiconductor MSM5416258A PACKAGE DIMENSIONS (Unit : mm) TSOPII44/40-P-400-0.80-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.49 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 21/21 E2Y0002-28-41 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents cotained herein may be reprinted or reproduced without our prior permission. 9. MS-DOS is a registered trademark of Microsoft Corporation. Copyright 1998 Oki Electric Industry Co., Ltd. Printed in Japan