Pr E2G0130-17-61 el im y 1,048,576-Word ¥ 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE DESCRIPTION The MSM51V16160D/DSL is a 1,048,576-word ¥ 16-bit dynamic RAM fabricated in Oki's silicongate CMOS technology. The MSM51V16160D/DSL achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/ double-layer metal CMOS process. The MSM51V16160D/DSL is available in a 42-pin plastic SOJ or 50/44-pin plastic TSOP. The MSM51V16160DSL (the self-refresh version) is specially designed for lower-power applications. FEATURES • 1,048,576-word ¥ 16-bit configuration • Single 3.3 V power supply, ±0.3 V tolerance • Input : LVTTL compatible, low input capacitance • Output : LVTTL compatible, 3-state • Refresh : 4096 cycles/64 ms, 4096 cycles/128 ms (SL version) • Fast page mode, read modify write capability • CAS before RAS refresh, hidden refresh, RAS-only refresh capability • CAS before RAS self-refresh capability (SL version) • Package options: 42-pin 400 mil plastic SOJ (SOJ42-P-400-1.27) (Product : MSM51V16160D/DSL-xxJS) 50/44-pin 400 mil plastic TSOP (TSOPII50/44-P-400-0.80-K) (Product : MSM51V16160D/DSL-xxTS-K) xx indicates speed rank. PRODUCT FAMILY Family Access Time (Max.) tRAC tAA tCAC tOEA ar This version: Mar. 1998 MSM51V16160D/DSL in ¡ Semiconductor MSM51V16160D/DSL ¡ Semiconductor Cycle Time Power Dissipation (Min.) Operating (Max.) Standby (Max.) MSM51V16160D/DSL-50 50 ns 25 ns 13 ns 13 ns 90 ns 270 mW MSM51V16160D/DSL-60 60 ns 30 ns 15 ns 15 ns 110 ns 234 mW MSM51V16160D/DSL-70 70 ns 35 ns 20 ns 20 ns 130 ns 216 mW 1.8 mW/ 0.72 mW (SL version) 1/16 ¡ Semiconductor MSM51V16160D/DSL PIN CONFIGURATION (TOP VIEW) VCC 1 DQ1 2 DQ2 3 DQ3 4 DQ4 5 VCC 6 DQ5 7 DQ6 8 DQ7 9 DQ8 10 NC 11 NC 12 WE 13 42 VSS VCC 1 50 VSS 41 DQ16 DQ1 2 49 DQ16 40 DQ15 DQ2 3 48 DQ15 39 DQ14 DQ3 4 47 DQ14 38 DQ13 DQ4 5 46 DQ13 37 VSS VCC 6 45 VSS 36 DQ12 DQ5 7 44 DQ12 35 DQ11 DQ6 8 43 DQ11 34 DQ10 DQ7 9 42 DQ10 33 DQ9 DQ8 10 41 DQ9 32 NC NC 11 40 NC NC 15 36 NC 31 LCAS 30 UCAS RAS 14 29 OE A11R 15 28 A9R A10R 16 27 A8R NC 16 35 LCAS A0 17 26 A7 WE 17 34 UCAS A1 18 25 A6 RAS 18 33 OE A2 19 24 A5 A11R 19 32 A9R A3 20 23 A4 A10R 20 31 A8R VCC 21 22 VSS 42-Pin Plastic SOJ A0 21 30 A7 A1 22 29 A6 A2 23 28 A5 A3 24 27 A4 VCC 25 26 VSS 50/44-Pin Plastic TSOP (K Type) Pin Name A0 - A7, A8R - A11R Address Input RAS Row Address Strobe LCAS Lower Byte Column Address Strobe UCAS DQ1 - DQ16 Note : Function Upper Byte Column Address Strobe Data Input/Data Output OE Output Enable WE Write Enable VCC Power Supply (3.3 V) VSS Ground (0 V) NC No Connection The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin. 2/16 ¡ Semiconductor MSM51V16160D/DSL BLOCK DIAGRAM WE OE Timing Generator RAS I/O Controller LCAS UCAS 8 I/O Controller 8 Column Address Buffers Internal Address Counter A0 - A7 8 A8R - A11R 4 Refresh Control Clock Row Row Address 12 DecoBuffers ders 8 DQ1 - DQ8 Column Decoders 8 Output Buffers Sense Amplifiers I/O Selector 16 8 Input Buffers 8 8 Input Buffers 8 16 Memory Cells Word Drivers DQ9 - DQ16 8 Output Buffers 8 VCC On Chip VBB Generator VSS FUNCTION TABLE Input Pin DQ Pin Function Mode RAS LCAS UCAS WE OE DQ1 - DQ8 DQ9 - DQ16 H * H * H * * High-Z High-Z Standby Refresh L H * L High-Z L * H High-Z DOUT High-Z Lower Byte Read L H L H L High-Z DOUT Upper Byte Read L L L H L DOUT DOUT Word Read L L L H L H DIN L H L L H Don't Care Don't Care DIN Lower Byte Write DIN Word Write High-Z — L L L L H DIN L L L H H High-Z Upper Byte Write *: "H" or "L" 3/16 ¡ Semiconductor MSM51V16160D/DSL ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Symbol Rating Unit VT –0.5 to 4.6 V Short Circuit Output Current IOS 50 mA Power Dissipation PD* 1 W Operating Temperature Topr 0 to 70 °C Storage Temperature Tstg –55 to 150 °C Voltage on Any Pin Relative to VSS *: Ta = 25°C Recommended Operating Conditions Parameter Power Supply Voltage (Ta = 0°C to 70°C) Symbol Min. Typ. Max. Unit VCC 3.0 3.3 3.6 V VSS 0 0 0 V Input High Voltage VIH 2.0 — VCC + 0.3 V Input Low Voltage VIL –0.3 — 0.8 V Capacitance Parameter Input Capacitance (A0 - A7, A8R - A11R) Input Capacitance (RAS, LCAS, UCAS, WE, OE) Output Capacitance (DQ1 - DQ16) (VCC = 3.3 V ±0.3 V, Ta = 25°C, f = 1 MHz) Symbol Typ. Max. Unit CIN1 — 5 pF CIN2 — 7 pF CI/O — 7 pF 4/16 ¡ Semiconductor MSM51V16160D/DSL DC Characteristics Parameter (VCC = 3.3 V ±0.3 V, Ta = 0°C to 70°C) Symbol Condition MSM51V16160 MSM51V16160 MSM51V16160 D/DSL-50 D/DSL-60 D/DSL-70 Unit Note Min. Max. Min. Max. Min. Max. Output High Voltage VOH IOH = –2.0 mA 2.4 VCC 2.4 VCC 2.4 VCC V Output Low Voltage VOL IOL = 2.0 mA 0 0.4 0 0.4 0 0.4 V Input Leakage Current ILI –10 10 –10 10 –10 10 mA –10 10 –10 10 –10 10 mA — 75 — 65 — 60 mA 1, 2 — 2 — 2 — 2 — 0.5 — 0.5 — 0.5 mA 1 — 200 — 200 — 200 mA 1, 5 — 75 — 65 — 60 mA 1, 2 — 5 — 5 — 5 mA 1 — 75 — 65 — 60 mA 1, 2 — 70 — 65 — 60 mA 1, 3 — 400 — 400 — 400 mA — 300 — 300 — 300 mA 0 V £ VI £ VCC + 0.3 V; All other pins not under test = 0 V Output Leakage Current ILO Average Power Supply Current ICC1 (Operating) DQ disable 0 V £ VO £ VCC RAS, CAS cycling, tRC = Min. RAS, CAS = VIH Power Supply Current (Standby) ICC2 RAS, CAS ≥ VCC –0.2 V RAS cycling, Average Power Supply Current ICC3 CAS = VIH, (RAS-only Refresh) tRC = Min. RAS = VIH, Power Supply Current (Standby) ICC5 CAS = VIL, DQ = enable Average Power Supply Current ICC6 (CAS before RAS Refresh) CAS before RAS RAS = VIL, Average Power Supply Current RAS cycling, ICC7 CAS cycling, (Fast Page Mode) tPC = Min. Average Power tRC = 31.3 ms, Supply Current ICC10 CAS before RAS, tRAS £ 1 ms (Battery Backup) 1, 4, 5 Average Power Supply Current (CAS before RAS ICCS RAS £ 0.2 V, CAS £ 0.2 V 1, 5 Self-Refresh) Notes : 1. 2. 3. 4. 5. ICC Max. is specified as ICC for output open condition. The address can be changed once or less while RAS = VIL. The address can be changed once or less while CAS = VIH. VCC – 0.2 V £ VIH £ VCC + 0.3 V, –0.3 V £ VIL £ 0.2 V. SL version. 5/16 ¡ Semiconductor MSM51V16160D/DSL AC Characteristics (1/2) (VCC = 3.3 V ±0.3 V, Ta = 0°C to 70°C) Note 1, 2, 3 Parameter Symbol MSM51V16160 MSM51V16160 MSM51V16160 D/DSL-50 D/DSL-60 D/DSL-70 Unit Note Min. Max. Min. Max. Min. Max. tRC 90 — 130 185 — 131 110 155 — tRWC — — — ns ns tPC 35 — 40 — 45 — ns tPRWC 76 — 85 — 100 — ns Access Time from RAS tRAC — 50 — 60 — 70 ns 4, 5, 6 Access Time from CAS tCAC — 13 — 15 — 20 ns 4, 5 Access Time from Column Address Access Time from CAS Precharge tAA tCPA — — 25 30 — — 30 35 — — 35 40 ns ns 4, 6 4, 12 Access Time from OE Output Low Impedance Time from CAS tOEA tCLZ — 0 13 — — 0 15 — — 0 20 — ns ns 4 4 CAS to Data Output Buffer Turn-off Delay Time tOFF OE to Data Output Buffer Turn-off Delay Time Transition Time Refresh Period tOEZ tT tREF 0 0 3 — 13 13 50 64 0 0 3 — 15 15 50 64 0 0 3 — 20 20 50 64 ns ns ns ms 7 7 3 Refresh Period (SL version) tREF — 128 — 128 — 128 ms 15 RAS Precharge Time tRP 30 — 40 — 50 — ns RAS Pulse Width tRAS 50 10,000 60 10,000 70 10,000 ns RAS Pulse Width (Fast Page Mode) tRASP 50 100,000 60 100,000 70 100,000 ns RAS Hold Time tRSH RAS Hold Time referenced to OE tROH 13 13 — — 15 15 — — 20 20 — — ns ns CAS Precharge Time (Fast Page Mode) tCP 7 — 10 — 10 — ns CAS Pulse Width tCAS 13 10,000 15 10,000 20 10,000 ns CAS Hold Time tCSH 50 5 — — ns — 70 5 — — 60 5 — ns 12 — 37 25 35 20 15 — 45 30 40 20 15 — 50 35 ns ns ns 12 Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time 14 CAS to RAS Precharge Time tCRP RAS Hold Time from CAS Precharge tRHCP RAS to CAS Delay Time tRCD RAS to Column Address Delay Time tRAD 30 17 12 Row Address Set-up Time tASR 0 — 0 — 0 — ns Row Address Hold Time tRAH 7 — 10 — 10 — ns Column Address Set-up Time tASC 0 — 0 — 0 — ns 11 Column Address Hold Time tCAH 7 — 10 — 15 — ns 11 Column Address to RAS Lead Time tRAL 25 — 30 — 35 — ns Read Command Set-up Time tRCS 0 — 0 — 0 — ns 11 Read Command Hold Time tRCH 0 — 0 — 0 — ns 8, 11 Read Command Hold Time referenced to RAS tRRH 0 — 0 — 0 — ns 8 5 6 6/16 ¡ Semiconductor MSM51V16160D/DSL AC Characteristics (2/2) (VCC = 3.3 V ±0.3 V, Ta = 0°C to 70°C) Note 1, 2, 3 Parameter Symbol MSM51V16160MSM51V16160 MSM51V16160 D/DSL-50 D/DSL-60 D/DSL-70 Unit Note Min. Max. Min. Max. Min. Max. Write Command Set-up Time tWCS 0 — 0 — 0 — ns 9, 11 Write Command Hold Time tWCH 7 — 10 — 15 — ns 11 Write Command Pulse Width OE Command Hold Time Write Command to RAS Lead Time Write Command to CAS Lead Time tWP tOEH tRWL tCWL 7 13 — — 10 15 — — 10 20 — — ns ns 13 13 — — 15 15 — — 20 20 — — ns ns 13 Data-in Set-up Time Data-in Hold Time OE to Data-in Delay Time CAS to WE Delay Time Column Address to WE Delay Time RAS to WE Delay Time tDS tDH tOED tCWD tAWD tRWD 0 7 13 36 48 73 — — — — — — 0 10 15 40 55 85 — — — — — — 0 15 20 50 65 100 — — — — — — ns ns ns ns ns ns 10, 11 10, 11 CAS Precharge WE Delay Time tCPWD 53 — 60 — 70 — ns 9 9 9 9 CAS Active Delay Time from RAS Precharge tRPC 5 — 5 — 5 — ns 11 RAS to CAS Set-up Time (CAS before RAS) RAS to CAS Hold Time (CAS before RAS) tCSR tCHR 10 10 — — 10 10 — — 10 10 — — ns ns 11 12 tRASS 100 — 100 — 100 — ms 15 tRPS 90 — 110 — 130 — ns 15 tCHS –50 — –50 — –50 — ns 15 RAS Pulse Width (CAS before RAS Self-Refresh) RAS Precharge Time (CAS before RAS Self-Refresh) CAS Hold Time (CAS before RAS Self-Refresh) 7/16 ¡ Semiconductor Notes: MSM51V16160D/DSL 1. A start-up delay of 200 µs is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 5 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 1 TTL load and 100 pF. The output timing reference levels are VOH = 2.0 V and VOL = 0.8 V. 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. 7. tOFF (Max.) and tOEZ (Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. tRCH or tRRH must be satisfied for a read cycle. 9. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD ≥ tCWD (Min.) , tRWD ≥ tRWD (Min.), tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 10. These parameters are referenced to the UCAS and LCAS, leading edges in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle. 11. These parameters are determined by the falling edge of either UCAS or LCAS, whichever is earlier. 12. These parameters are determined by the rising edge of either UCAS or LCAS, whichever is later. 13. tCWL should be satisfied by both UCAS and LCAS. 14. tCP is determined by the time both UCAS and LCAS and high. 15. Only SL version. 8/16 E2G0103-17-41P ,, , , ,,,, ¡ Semiconductor MSM51V16160D/DSL TIMING WAVEFORM Read Cycle tRC tRP tRAS RAS VIH – VIL – tCRP tCSH tCRP tRCD VIH – CAS VIL – tRAD tASR Address VIH – VIL – tRSH tCAS tRAH tASC tRAL tCAH Column Row tRCS WE OE VIH – VIL – tAA tROH tOEA VIH – VIL – tCAC tRAC DQ tRCH tRRH VOH – tOEZ Open VOL – tOFF Valid Data-out tCLZ "H" or "L" Write Cycle (Early Write) tRC tRP tRAS RAS VIH – VIL – tCRP tCRP VIH – CAS VIL – WE OE VIH – VIL – tASC Row tCAS tCAH tRAL Column tWCS VIH – tWCH tCWL tWP VIL – tRWL VIH – VIL – tDS DQ tRSH tRAD tRAH tASR Address tCSH tRCD VIH – VIL – tDH Valid Data-in Open "H" or "L" 9/16 ,,, ¡ Semiconductor MSM51V16160D/DSL Read Modify Write Cycle tRWC tRAS VIH – RAS VIL – tRCD tRSH tCAS VIH – VIL – tASR VIH – Address VIL – WE VIH – VIL – OE VIH – VIL – tRAH tASC tCAH Column Row tRAD tRWD tAA tOEA tOED tCAC VI/OH– VI/OL– tCWL tRWL tWP tCWD tAWD tRCS tRAC DQ tCRP tCSH tCRP CAS tRP tCLZ tOEZ Valid Data-out tOEH tDS tDH Valid Data-in "H" or "L" 10/16 ,, , , ,, , ¡ Semiconductor MSM51V16160D/DSL Fast Page Mode Read Cycle tRASP VIH – RAS V – IL VIH – CAS VIL – Address WE VIH – VIL – tRP tRHCP tCRP tPC tRCD tCP tASR tCP tCAS tCAS tRAD tRAH tASC tCSH tCAH tASC Column Row VIH – VIL – tCAC VOH – DQ VOL – Column tRCS tRCH tRRH tCPA tOEA tOFF tOEZ tRCH tAA tAA tCAC tOEA tOFF tCAC tOEZ tCLZ Valid Data-out tCLZ tRCS tCPA tOEA tRAC tRAL tCAH tASC Column tAA VIH – OE VIL – tCAS tCAH tRCH tRCS tCRP tRSH tCLZ tOFF tOEZ Valid Data-out Valid Data-out "H" or "L" Fast Page Mode Write Cycle (Early Write) tRASP tPC VIH – RAS V – IL tCRP VIH – CAS VIL – Address VIH – VIL – tCAS tASR tRAH tASC Row tRAD VIH – VIL – tDS DQ VIH – VIL – tRHCP tRSH tRCD tWCS WE tRP tCSH tCAH Column tCWL tWCH tWP tDH Valid Data-in tCP tCRP tCP tCAS tASC tCAH tASC Column tCWL tWCS tWCH tWP tDS tDH Valid Data-in tCAS tCAH tRAL Column tRWL tCWL tWCS tWCH tWP tDS tDH Valid Data-in Note: OE = "H" or "L" "H" or "L" 11/16 ¡ Semiconductor MSM51V16160D/DSL ,, , , , , , Fast Page Mode Read Modify Write Cycle tRASP VIH – RAS VIL – tRP tCSH tPRWC tRCD VIH – CAS VIL – tASC tCAH tRAH VIH – VIL – tCRP tCAS tASC tCAH tCAH Column Column tASC Column Row tRCS tCPWD tCWD tRWD tCWD tRCS V WE IH – VIL – tCWL tAWD tCWL tWP tDH VI/OH– VI/OL – Out tCLZ tOEA tOED tOEZ tCAC In tDH tDS tOEA tOEZ tCAC tWP tCPA tAA tOED VIH – OE V – IL tCWL tROH tWP tDH tDS tOEA tRWL tAWD tCPA tAA tAA tRAL tRCS tCPWD tCWD tAWD tDS tRAC DQ tCP tCAS tRAD tASR Address tCP tCAS tRSH Out tOED In tCLZ tOEZ tCAC Out In tCLZ "H" or "L" RAS-Only Refresh Cycle tRC RAS CAS Address VIL – VIH – VIL – VIH – VIL – tRP tRAS VIH – tCRP tASR tRPC tRAH Row tOFF DQ VOH – VOL – Open Note: WE, OE = "H" or "L" "H" or "L" 12/16 M L K ^ ] \ S R Q P ¡ Semiconductor MSM51V16160D/DSL CAS before RAS Refresh Cycle tRC tRP RAS tRP tRAS VIH – VIL – tRPC tRPC tCP CAS tCSR tCHR tWRP tWRH VIH – VIL – tWRP ,,, , WE VIH – VIL – DQ VOH – VOL – tOFF Open Note: OE, Address = "H" or "L" "H" or "L" Hidden Refresh Read Cycle tRC tRAS RAS tRP VIL – VIH – VIL – VIH – VIL – tRSH tRCD tRAD tASC tRAH tASR Address tRAS tRP VIH – tCRP CAS tRC Row tCHR tCAH Column tRCS tRAL VIH – WE V IL – tRRH tAA tROH tOEA VIH – OE V IL – tRAC DQ VOH – VOL – tCAC tCLZ tOFF tOEZ Valid Data-out "H" or "L" 13/16 ¡ Semiconductor MSM51V16160D/DSL Hidden Refresh Write Cycle tRC tRAS VIH – VIL – RAS VIH – VIL – Address tCRP tRCD tRSH tRAD tASC tASR tCAH tRAH Row WE VIH – VIL – OE VIH – VIL – tCHR tRAL Column tWCS tDS VIH – VIL – DQ tRP , ,,,, , VIH – VIL – CAS tRC tRAS tRP tWCH tWP tWRP tWRH tDH Valid Data-in "H" or "L" CAS before RAS Self-Refresh Cycle tRASS tRP VIH – RAS VIL – tRPC tCP CAS tRPS tRPC tCHS tCSR VIH – VIL – tOFF DQ VOH – VOL – Open Note: WE, OE, Address = "H" or "L" Only SL version "H" or "L" 14/16 ¡ Semiconductor MSM51V16160D/DSL PACKAGE DIMENSIONS (Unit : mm) SOJ42-P-400-1.27 Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.86 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 15/16 ¡ Semiconductor MSM51V16160D/DSL (Unit : mm) TSOPII50/44-P-400-0.80-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.60 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 16/16