OKI MSM548332

E2L0036-17-Y1
¡ Semiconductor
MSM548332
¡ Semiconductor
This version:
Jan. 1998
MSM548332
Previous version: Dec. 1996
278,400-Word ¥ 12-Bit Field Memory
DESCRIPTION
The MSM548332 is a 3.3-Mbit, 960 bits ¥ 290 lines, Field Memory. Access is done line by line. The line
address must be set each time a line is changed.
More than two MSM548332s can be cascaded directly without any delay devices between them.
Cascading MSM548332s provides larger capacity and longer delay.
X serial address input enables random initial address setting of serial access in a page. Other than the
random address setting, MSM548332 has several types of address set modes such as line hold,
address jump to initial address and line increment.
Self refresh function releases the MSM548332 from being applied external refresh control clocks even
though it contains dynamic type memory cells. MSM548332 has write mask function or input enable
function (IE), and read-data skipping function or output enable function (OE).
The MSM548332 is especially designed for digital TVs and VTRs for consumer use and video
cameras.
The MSM548332 is not designed for high end use in such applications as medical systems,
professional graphics systems which require long term picture storage, data storage systems and
others.
FEATURES
• 960 ¥ 290 ¥ 12-bit configuration
• Line by line access
• X serial address inputs for random serial initial bit address
• Asynchronous operation
• Serial read and write cycle times
Read cycle: 30 ns/50 ns
Write cycle: 30 ns/50 ns
• Low operating supply voltage: 3.3 V ±0.3 V
• Self-refresh
• Various address reset mode for picture processing
• Write mask function (Input enable control)
• Data skipping function (Output enable control)
• Package:
44-pin 400 mil plastic TSOP (Type II) (TSOPII44-P-400-0.80-K) (Product : MSM548332-xxTS-K)
xx indicates speed rank.
1/23
¡ Semiconductor
MSM548332
PIN CONFIGURATION (TOP VIEW)
VSS
DIN5
DIN4
DIN3
DIN2
DIN1
DIN0
RCLK
RXAD
RADE/RX
RR
RXINC
RE
OE
DO0
DO1
VCC
DO2
DO3
VSS
DO4
DO5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
DIN6
DIN7
DIN8
DIN9
DIN10
DIN11
WCLK
WXAD
WADE/RX
WR/TR
WE
WXINC
IE
DO11
DO10
VCC
DO9
DO8
VSS
DO7
DO6
VCC
44-Pin Plastic TSOP (II)
(K Type)
2/23
¡ Semiconductor
Pin Name
RCLK
MSM548332
Function
Address Setting Cycle
Read Port, X Serial Address Strobes
Serial Read/Write Cycle
Read Port, Serial Read Clock
RE
—
Read Port, Read Enable
DO0 - 11
—
Read Port, Data Output
RR
Read Port, Address Reset Mode Enable
—
RXINC
Read Port, X Address Increment
—
RADE/RX
RXAD
OE
WCLK
WE
DIN0 - 11
Read Port, X Address Input Enable
Read Port, X Serial Address Data
—
—
Output Enable
Write Port, X Serial Address Strobes
Write Port, Write Enable
—
Write Port, Input Data
Write Port, Address Reset Mode Enable
WXINC
Write Port, X Address Increment
WXAD
IE
Write Port, Serial Write Clock
—
WR/TR
WADE/RX
—
Read Port, X Address Reset
Write Port, Write Data Transfer
—
Write Port, X Address Input Enable
—
Write Port, X Address Reset
Write Port, X Serial Address Data
—
—
Input Enable
VCC
Power Supply Voltage (3.3 V)
VSS
Ground (0 V)
Note: Same power supply voltage level must be provided to every VCC pin.
Same ground voltage level must be provided to every VSS pin.
3/23
WR/TR
DIN0 to DIN11
¡ Semiconductor
WXAD
Write Buffer
Write
Address Control
WADE/RX
IE
12
Refresh
Counter
WCLK
WCLK
BLOCK DIAGRAM
WE
Write Register
WXINC
RXAD
RR
X-Address
Decoder
Memory
Controller
RADE/RX
960 ¥ 290 ¥ 12 bits
Read
Address Control
RCLK
Memory Cell Array
Read Register
RXINC
12
DOUT Buffer
RCLK
RE
DO0 to DO11
OE
4/23
MSM548332
VBB
Generator
¡ Semiconductor
MSM548332
PIN FUNCTION
READ RELATED
RCLK : Read Clock
RCLK is the read control clock input. Synchronized with RCLK's rising edge, serial read access from
read ports is executed when both RE and OE are high.
The internal counter for the serial read address is incremented automatically on the rising edge of
RCLK. In a read address set cycle, all the read address bits which were input from RXAD pin are
stored into internal address registers synchronized with RCLK. In this address set cycle, RADE/RX
must be held high and RR must be held low.
In the read address reset cycle, various read address reset modes can be set synchronously with
RCLK. These reset cycles work to replace complicated serial address control which requires many
RCLK clocks with a simple reset cycle control requiring only a single RCLK cycle. It greatly facilitates
memory access.
RE : Read Enable
RE is a read enable clock input. RE enables or disables both internal read address pointers and dataout buffers. When RE is high, the internal read address pointer is incremented synchronously with
RCLK. When RE is low, even if the RCLK is input, the internal read address pointer is not
incremented.
OE : Output Enable
OE is an output enable clock input. OE enables or disables data-outs. OE high level enables the
outputs. The internal read address pointer is always incremented by cycling RCLK regardless of OE
level.
DO0-11 : Data-Outs
DO0-11 are serial data-outs. Data is output synchronously with RCLK when OE is high. The output
enable/disable operation through OE input is performed synchronously with OE and asynchronously
with RCLK.
RR : Read Reset
RR is a read reset control input. Read address reset modes are defined when RR level is high
according to the "FUNCTION TABLE for read".
RXINC : Read X Address Increment
RXINC is a read X address (or line address) increment control input. In the read address reset cycle,
defined by RR high, the X address (or line address) is incremented by 1 when RXINC is pulled high
with RADE/RX low.
RADE/RX : Read Address Enable/Read X Address Reset Logic Function
RADE/RX is a dual function control input. RADE, one of the two functions of RADE/RX, is a read
address enable input. In the read address set cycle, defined by RR high, X address (or line address)
input from the RXAD pin are latched into internal read X address register synchronously with RCLK.
RX, the second function of RADE/RX, works as an element to set read X address (or line address)
reset mode. In an address reset mode cycle, defined by RR high, read X address is reset to 0 when
RADE/RX is pulled high with RXINC low.
RXAD : Read X Address
RXAD is a read X address (or line address) input. RXAD specifies the line address. 9 bits of read X
address data are input serially from RXAD.
5/23
¡ Semiconductor
MSM548332
WRITE RELATED
WCLK : Write Clock
WCLK is a write control clock input. Synchronized with WCLK's rising edge, serial write access into
write ports is executed when WE is high and IE is high.
According to WCLK clocks, the internal counter for the serial address is incremented automatically.
In a write address set cycle, all the write addresses which were input from WXAD are stored into
internal address registers synchronously with WCLK. In this address set cycle, WADE/RX must be
held high and WR/TR must be held low.
In the write address reset cycle, various write address reset modes can be set synchronously with
WCLK. These reset cycles replace complicated serial address control with simple reset cycle control
which requires only one WCLK cycle. It greatly facilitates memory access.
WE : Write Enable
WE is a write enable clock input. WE enables or disables both internal write address pointers and
data-in buffers. When WE is high, the internal write address pointer is incremented synchronously
with WCLK. When WE is low, even if WCLK is input, the internal write address pointer is not
incremented.
DIN0-11 : Data-Ins
DIN0-11 are serial data-ins. Corresponding data-in-buffers are masked by IE.
WR/TR : Write Reset/Write Transfer
WR/TR is a write reset control input. Write address reset modes are defined when WR/TR level is
high according to the "FUNCTION TABLE for write".
When the write operation on a line is terminated, be sure to perform a write transfer operation by
WR/TR in order to store the written data in the write register to corresponding memory cells.
WXINC : Write X Address Increment
WXINC is a write X address (or line address) increment control input. In the write address reset cycle,
defined by WR/TR high, the write X address (or line address) is incremented when WXINC and
WADE/RX are high.
WADE/RX : Write Address Enable/Write X Address Reset Logic Function
WADE/RX is a dual functional control input. WADE, one of the two functions of WADE/RX, is a
write address enable input. In the write address reset cycle, defined by WR/TR high, X address (or
line address) input from WXAD is latched into internal write X address register synchronously with
WCLK.
WXAD : Write X Address
WXAD is a write X address (or line address) input. WXAD specifies line address. 9 bits of write X
address data are input serially from WXAD.
IE : Input Enable
IE is an input enable which controls the write operation. When IE is high, the input operation is
enabled. When IE is low, the write operation is masked. When WE signal is high, and IE low, the
internal serial write address pointer is incremented on the rising edge of WCLK without actual write
operations. This function facilitates picture in picture function in a TV system.
6/23
¡ Semiconductor
MSM548332
OPERATION MODE
Write
1. Write operation
Before the write operation begins, X address (or line address) must be input to set the initial
bit address for the following serial write access. When WE and IE are high, a set of serial 12bit -width write data on DIN0-11 is written into write registers attached to the DRAM memory
arrays temporarily on the rising edge of WCLK.
Following 12-bit-width serial input data is written into the memory locations in the write
register designated by an internal write address pointer which is advanced by WCLK. This
enables continuous serial write on a line. When write clock WCLK and read clock RCLK are
tied together and are controlled by a common clock or CLK, more than two MSM548332s can
be cascaded directly without any delay devices between the MSM548332s because the read
timing is delayed by one CLK cycle to the write timing. When the write operation on a line is
terminated, be sure to perform a write transfer operation by WR/TR in order to store the
written data in the write registers to the corresponding memory cells in the DRAM memory
arrays.
2. Write address pointer increment operation
The write address pointer is incremented synchronously with WCLK when WE is high.
Relationship between the WE and IE input levels,
Write Address pointer, and data input status
WCLK Rise
WE
IE
H
H
H
L
L
—
Internal Write
Address Pointer
Incremented
Stopped
Data Input
Inputted
Not Inputted
When WE and IE are high, the write operation is enabled.
If IE level goes low while WCLK is active, the write operation is halted but the write address
pointer will continue to advance. That is, IE enables a write mask function. When WE goes
low, the write address pointer stops without WCLK.
Read
1. Read operation
Before the read operation begins, the X address (or line address) must be input for setting
initial bit address for the following serial read access.
When both RE and OE are high, a set of serial 12-bit-width read data on DO0-11 pins is read
from read registers attached to DRAM memory arrays on the rising edge of RCLK.
Each access time is specified by the rising edges of RCLK.
7/23
¡ Semiconductor
MSM548332
2. Read address pointer increment operation
The read address pointer is incremented synchronized with RCLK when OE level is high.
Relationship between the RE and OE input levels,
Read Address pointer, and data output status
RCLK Rise
RE
OE
H
H
H
L
L
H
L
L
Internal Read
Address Pointer
Incremented
Stopped
Data Output
Outputted
Hi-Z
Outputted
Hi-Z
When each read address pointer reaches the last address of a line, it stops at the last address
and no address increment occurs.
Initial Address Setting (Write/Read Independent)
Any read operations are prohibited in the read initial address set period. Similarly, any write
operations are prohibited in the write initial address set period. Note that read initial address set and
write initial address set can occur independently. Similarly, read access can be achieved independently
from write initial address set period and write access can be achieved independently from read initial
address set cycles.
1. Write address setting
WADE/RX enables initial read address inputs. When WADE/RX is high, 9 bits of serial X
address (or line address) are input from WXAD.
The operations above enable selection of specific lines randomly and enables the start of serial
write access synchronized with write clock WCLK. Address for each line must be input
between each line access. In other words, MSM548332's write is achieved in a "line by line"
manner. Any write operations are prohibited in the initial write address set periods.
Serial write input enable time tSWE must be kept for starting a serial write just after the initial
write address set period.
2. Read address setting
RADE/RX enables initial read address inputs.
When RADE/RX is high, 9 bits of serial X address (or line address) are input from RXAD.
The operations above enable selection of specific lines randomly and enables the start of serial
read access synchronized with read clocks, RCLK. Address for each line must be input
between each line access. In other words, MSM548332's read operation is achieved in "line by
line" manner.
Any read operations are prohibited in the initial read address set periods. Serial read
operations are prohibited while RADE/RX is high. Serial read port enable time tSRE must be
kept for starting a serial read just after the initial read address set period.
Initial Address Reset Modes (Write/Read Independent)
The initial address reset modes replace complicated read or write initial address settings with simple
reset cycles. Initial address reset modes are selected by RR high during read and WR/TR high during
write. As in normal read or write address settings, any read operations are prohibited in the read
address reset cycles. Similarly, any write operations are prohibited in the initial write address reset
cycles. Note that read initial address reset and write initial address reset can occur independently.
Similarly, read access can be achieved independently from write initial address reset cycles and write
8/23
¡ Semiconductor
MSM548332
access can be achieved independently from read initial address reset cycles.
Input addresses are stored into address registers which are connected with address counter which
controls address pointer operation. In the serial access operation, the input address into the address
registers are kept.
Serial write data input enable time tSWE and serial read port read enable time tSRE must be kept for
starting serial read or write just after the initial read or write address reset cycles.
Refer to the "FUNCTION TABLE" shown later.
1. Line hold operation (read only)
By the "Line hold operation" logic which is composed by a combination of control inputs' level,
access is executed starting from the first word on the current line.
2. Original address reset operation
By the "Original address reset" logic, the address counter is reset to (0,0). After the reset mode,
serial access starts from the address (0,0) .
The address counter is reset by this reset mode but the address register, which stored input
address in the previous address reset cycle or address set cycle, is not reset. The non-initialized
address can be used as a preset address in "address jump reset" mode.
3. Line increment operation
By the "Line increment operation" logic, the X address counter is incremented by one from the
current X address. That is, serial access from the Y = (0) on the next line is enabled.
4. Address jump operation
By the "Address jump operation" logic, a jump may be caused to the initialized line address.
Note : During one reset setting cycle, a plurality of resets cannot be set.
Power ON
Power must be applied to RCLK, RE, OE, WCLK, WE and IE input signals to pull them "Low" before
or when the VCC supply is turned on.
After power-up, the device is designed to begin proper operation in at least 200 ms after VCC has
reached the specified voltage. After 200 ms, a minimum of one line dummy write operation and read
operation is required according to the address setting mode, because the read and write address
pointers are not valid after power-up.
New Data Read Access
In order to read out "new data', the delay between the beginning of a write address setting cycle and
read address setting cycle must be at least two lines.
Old Data Read Access
In order to read out "old data", the delay between the beginning of a write address setting cycle and
read address setting cycle must be more than 0 but less than a half line.
9/23
¡ Semiconductor
MSM548332
FUNCTION TABLE
1. Write
Mode
No.
Description of
Operation
WR/TR
WXINC WADE/RX Internal Address Pointer
1
Write Transfer
H
L
L
2
Reset
H
L
H
X address cleared to (0, 0)
3
Line Increment
H
H
L
X address increment to (Xn +
1, 0)
4
Address Jump
H
H
H
X address jump to (Xi, 0)
—
First Address Setting
L
L
H
X address set
Address Reset
Mode
Address Setting
Mode
Note : For write, Line hold is not provided.
2. Read
Mode
Address Reset
Mode
Address Setting
Mode
No.
Description of
Operation
RR
RXINC RADE/RX Internal Address Pointer
1
Line Hold
H
L
L
X address holde to (Xn, 0)
2
Reset
H
L
H
X address cleared to (0, 0)
3
Line Increment
H
H
L
X address increment to (Xn +
1, 0)
4
Adress Jump
H
H
H
X address jump to (Xi, 0)
—
First Address Setting
L
L
H
X address set
10/23
¡ Semiconductor
MSM548332
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Symbol
Condition
Rating
Pin Voltage
Parameter
VT
Ta = 25°C, with respect to VSS
–0.5 to 4.6 V
Short Circuit Output Current
IOS
Ta = 25°C
50 mA
Power Dissipation
PD
Ta = 25°C
1W
Operating Temperature
Topr
—
0 to 70°C
Storage Temperature
Tstg
—
–55 to 150°C
Recommended Operating Conditions
(Ta = 0 to 70°C)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Power Supply Voltage
VCC
3.0
3.3
3.6
V
Power Supply Voltage
VSS
0
0
0
V
"H" Input Voltage
VIH
2.1
VCC
VCC + 0.3
V
"L" Input Voltage
VIL
–0.5
0
0.8
V
DC Characteristics
Parameter
(VCC = 3.0 to 3.6 V, Ta = 0 to 70°C)
Min.
Max.
Unit
"H" Output Voltage
VOH
IOH = –0.1 mA
2.2
—
V
"L" Output Voltage
VOL
IOL = 0.1 mA
—
0.6
V
Input Leakage Current
ILI
–10
10
mA
Output Leakage Current
ILO
–10
10
mA
—
75
—
50
—
10
Power Supply Current
(During Operation)
Power Supply Voltage
(During Standby)
Symbol
Condition
0 < VI < VCC
Other input voltage 0 V
0 < VO < VCC
ICC1
min. cycle
ICC2
Input pin = VIL/VIH
-30
-50
mA
mA
Capacitance
(Ta = 25°C, f = 1 MHz)
Parameter
Symbol
Max.
Unit
Input Capacitance
CI
7
pF
Output Capacitance
CO
7
pF
11/23
¡ Semiconductor
MSM548332
AC Characteristics (1/2)
Measurement Conditions: (VCC = 3.3 V ±0.3 V, Ta = 0 to 70°C)
Parameter
Symbol
MSM548332-30 MSM548332-50
Unit
Min.
Max.
Min.
Max.
tWCLK
30
—
50
—
ns
WCLK "H" Pulse Width
tWWCLH
13
—
23
—
ns
WCLK "L" Pulse Width
tWWCLL
13
—
23
—
ns
tWAS
5
—
5
—
ns
Serial Write Address Input Active Hold Time
tWAH
7
—
7
—
ns
Serial Write Address Input Inactive Hold Time
tWADH
7
—
7
—
ns
Serial Write Address Input Inactive Setup Time
tWADS
7
—
7
—
ns
Write Transfer Instruction Setup Time
tWTRS
5
—
5
—
ns
Write Transfer Instruction Hold Time
tWTRH
7
—
7
—
ns
Write Transfer Instruction Inactive Hold Time
tWTDH
7
—
7
—
ns
Write Transfer Instruction Inactive Setup Time
tWTDS
7
—
7
—
ns
Serial Write X Address Setup Time
tWXAS
5
—
5
—
ns
Serial Write X Address Hold Time
tWXAH
7
—
7
—
ns
Serial Write Data Input Enable Time
tSWE
3000
—
3000
—
ns
Write Instruction Setup Time
tWES
5
—
5
—
ns
Write Instruction Hold Time
tWEH
7
—
7
—
ns
Write Instruction Inactive Hold Time
tWEDH
7
—
7
—
ns
Write Instruction Inactive Setup Time
tWEDS
7
—
7
—
ns
tDS
5
—
5
—
ns
WCLK Cycle Time
Serial Write Address Input Active Setup Time
Input Data Setup Time
tDH
12
—
12
—
ns
tWRS
5
—
5
—
ns
WR/TR-WCLK Active Hold Time
tWRH
7
—
7
—
ns
WR/TR-WCLK Inactive Hold Time
tWRDH
7
—
7
—
ns
WR/TR-WCLK Inactive Setup Time
tWRDS
7
—
7
—
ns
WXINC-WCLK Active Setup Time
tWINS
5
—
5
—
ns
WXINC-WCLK Active Hold Time
tWINH
7
—
7
—
ns
WXINC-WCLK Inactive Hold Time
tWINDH
7
—
7
—
ns
WXINC-WCLK Inactive Setup Time
tWINDS
7
—
7
—
ns
WADE/RX-WCLK Active Setup Time
tWRXS
5
—
5
—
ns
WADE/RX-WCLK Active Hold Time
tWRXH
7
—
7
—
ns
WADE/RX-WCLK Inactive Hold Time
tWRXDH
7
—
7
—
ns
WADE/RX-WCLK Inactive Setup Time
tWRXDS
7
—
7
—
ns
IE Enable Setup Time
tIES
5
—
5
—
ns
IE Enable Hold Time
tIEH
7
—
7
—
ns
IE Disable Setup Time
tIEDS
7
—
7
—
ns
IE Disable Hold Time
tIEDH
7
—
7
—
ns
Input Data Hold Time
WR/TR-WCLK Active Setup Time
12/23
¡ Semiconductor
MSM548332
AC Characteristics (2/2)
Measurement Conditions: (VCC = 3.3 V ±0.3 V, Ta = 0 to 70°C)
Parameter
Symbol
MSM548332-30 MSM548332-50
Unit
Min.
Max.
Min.
Max.
tRCLK
30
—
50
—
ns
RCLK "H" Pulse Width
tWRCLH
13
—
23
—
ns
RCLK "L" Pulse Width
tWRCLL
13
—
23
—
ns
tRAS
5
—
5
—
ns
Serial Read Address Input Active Hold Time
tRAH
7
—
7
—
ns
Serial Read Address Input Inactive Hold Time
tRADH
7
—
7
—
ns
Serial Read Address Input Inactive Setup Time
tRADS
7
—
7
—
ns
Serial Read X Address Setup Time
tRXAS
5
—
5
—
ns
Serial Read X Address Hold Time
tRXAH
7
—
7
—
ns
RE Enable Setup Time
tRES
5
—
5
—
ns
RE Enable Hold Time
tREH
7
—
7
—
ns
RE Disable Hold Time
tREDH
7
—
7
—
ns
RE Disable Setup Time
tREDS
7
—
7
—
ns
Read Port Read Enable Time
tSRE
3000
—
3000
—
ns
Read Port Read Data Hold Time
tOH
12
—
12
—
ns
30
—
40
ns
RCLK Cycle Time
Serial Read Address Input Active Setup Time
tAC
—
Read Data Hold Time from OE
tDDOE
2
—
2
—
ns
Access Time from OE
tDEOE
—
20
—
30
ns
RR-RCLK Active Setup Time
tRRS
5
—
5
—
ns
RR-RCLK Active Hold Time
tRRH
7
—
7
—
ns
RR-RCLK Inactive Hold Time
tRRDH
7
—
7
—
ns
RR-RCLK Inactive Setup Time
tRRDS
7
—
7
—
ns
RXINC-RCLK Active Setup Time
tRINS
5
—
5
—
ns
RXINC-RCLK Active Hold Time
tRINH
7
—
7
—
ns
RXINC-RCLK Inactive Hold Time
tRINDH
7
—
7
—
ns
RXINC-RCLK Inactive Setup Time
tRINDS
7
—
7
—
ns
RADE/RX-RCLK Active Setup Time
tRRXS
5
—
5
—
ns
RADE/RX-RCLK Active Hold Time
tRRXH
7
—
7
—
ns
RADE/RX-RCLK Inactive Setup Time
tRRXDS
7
—
7
—
ns
RADE/RX-RCLK Inactive Hold Time
tRRXDH
7
—
7
—
ns
tT
2
30
2
30
ns
Access Time from RCLK
Transition Time (Rise and Fall)
Note :
Measurement conditions
Input pulse level
Input timing reference level
Output timing reference level
Input rise/fall time
Load condition
: VIH = 2.1 V, VIL = 0.8 V
: VIH = 2.1 V, VIL = 0.8 V
: VOH = 2.2 V, VOL = 0.6 V
: 2 ns
: CL = 30 pF (Oscilloscope and tool capacity included)
13/23
\
WADE/RX
\
tWWCLH
tWADH
\
tWXAS
\
WXAD
\
tWAH tWADS
tWAS
tWXAH
Valid
A8
tWXAS
tWXAH
Valid
A7
tWXAS
tWXAH
Valid
A1
tWXAS
tWXAH
Valid
A0
tSWE
WE
tWEDH
tWES
¡ Semiconductor
\
WCLK
TIMING WAVEFORM
Write Cycle (Address Setting Cycle)
tWCLK
tWWCLL
\
\
\
tIEDH
tIES
IE
\
WR/TR
\
Low
\
\
WXINC
\
\
\
Valid
tDH
tDS
Valid
tDH
14/23
MSM548332
DIN0 - 11
Low
tDS
¡ Semiconductor
MSM548332
Write Cycle (WE Control)
(N-2)CYCLE (N-1)CYCLE
tWCLK
N CYCLE
(N+1) CYCLE (N+2) CYCLE
\
WCLK
\
\
WADE/RX
Low
\
\
IE
High
\
\
WR/TR
Low
\
\
WXINC
Low
\
tWEH tWEDS tWEDH tWES
\
WE
\
DIN0 - 11
\
\
Valid
D(N-3)
Valid
D(N-2)
Valid
D(N-1)
Valid
D(N)
Valid
D(N+1)
Valid
D(N+2)
Note : In the WE =" L" cycle, the write address pointer is not incremented and no DIN data is written.
Write Cycle (IE Control)
(N-2)CYCLE (N-1)CYCLE
tWCLK
N CYCLE
(N+2) CYCLE (N+3) CYCLE
\
WCLK
\
\
WADE/RX
Low
\
\
WE
High
\
\
WR/TR
Low
\
\
WXINC
Low
\
tIEH
tIEDS
tIEDH
tIES
\
IE
\
DIN0 - 11
\
\
Valid
D(N-3)
Valid
D(N-2)
Valid
D(N-1)
Valid
D(N)
Valid
D(N+2)
Valid
D(N+3)
Note : In the IE = "L" cycle, the write address pointer is incremented, though no DIN data is written
and the memory data is held.
15/23
¡ Semiconductor
MSM548332
Write Cycle (Write Transfer)
(N-2)CYCLE (N-1)CYCLE
tWCLK
N CYCLE
\
WCLK
\
\
WADE/RX
Low
\
tWTRS
tWTDH
\
tWTRH
tWTDS
WR/TR
\
\
WXINC
Low
\
tWEH tWEDS
\
WE
\
\
DIN0 - 11
\
Valid
D(N-3)
Valid
D(N-2)
Valid
D(N-1)
Valid
D(N)
Note : When finishing the write operation on a line, be sure to perform a write transfer operation
because the write data on the line is stored in the memory cell.
16/23
RCLK
\
\
RADE/RX
\
tWRCLH
tRAH tRADS
tRAS
tRADH
\
tRXAS
tRXAS
tRXAS
,
,
,
tRXAS
\
RXAD
\
tRXAH
Valid
B8
tRXAH
Valid
B7
tRXAH
Valid
B1
tRXAH
Valid
B0
tSRE
RE
tREDH
¡ Semiconductor
Read Cycle (Address Setting Cycle)
tRCLK
tWRCLL
tRES
\
\
RR
\
Low
\
\
RXINC
Low
\
tAC
\
DO0 - 11
High-Z
tOH
Valid
Valid
\
MSM548332
17/23
¡ Semiconductor
MSM548332
Read Cycle (RE Control)
(N-2)CYCLE (N-1)CYCLE
tRCLK
N CYCLE
(N+1) CYCLE (N+2) CYCLE
\
RCLK
\
\
RADE/RX
Low
\
\
RR
Low
\
\
RXINC
Low
\
tREH tREDS tREDH tRES
\
RE
\
DO0 - 11
\
\
tOH
Valid
D(N-3)
tAC
Valid
D(N-2)
Valid
D(N-1)
Valid
D(N)
Valid
D(N+1)
Valid
D(N+2)
\
OE
High
\
Note : In the cycle of RE = "L", the read address pointer is not incremented and the data at the address
is output continuously.
Read Cycle (OE Control)
(N-2)CYCLE (N-1)CYCLE
tRCLK
N CYCLE
(N+2) CYCLE (N+3) CYCLE
\
RCLK
\
\
RADE/RX
\
\
RR
\
\
RXINC
\
\
OE
\
DO0 - 11
\
\
\
RE
\
tDDOE
tOH
Valid
D(N-3)
Valid
D(N-2)
Valid
D(N-1)
Valid
D(N)
tDEOE
High-Z
Low
Low
Low
tAC
Valid
D(N+2)
Valid
D(N+3)
High
Note : In the cycle of OE = "L", the read address pointer is incremented and the output enters the high
impedance state.
18/23
¡ Semiconductor
MSM548332
Write Reset Mode
tWCLK
tWWCLL
\
WCLK
\
\
tWWCLH
tWRXDH tWRXS tWRXH tWRXDS
WADE/RX
\
\
tWRDH tWRS tWRH tWRDS
WR/TR
\
\
WXINC
Low
\
\
tSWE
WE
tWEDH
tWES
tDS
\
tDS
tDH
tDH
\
DIN0 - 11
Valid
\
Valid
Note : Both the line address and word address are reset to 0.
Write Line Increment Mode
tWCLK
tWWCLL
\
WCLK
\
tWWCLH
\
WADE/RX
\
\
WR/TR
\
\
WXINC
tWRDH tWRS
tWRH t
WRDS
tWINDH tWINS tWINH tWINDS
\
\
WE
\
tSWE
tWEDH
tWES
tDS
tDH
tDS
tDH
\
DIN0 - 11
\
Valid
Valid
Note : The line address is incremented by 1 and the word address is reset to 0.
19/23
¡ Semiconductor
MSM548332
Write Address Jump Mode
tWCLK
tWWCLL
\
WCLK
\
\
tWWCLH
tWRXDH tWRXS tWRXH tWRXDS
WADE/RX
\
\
tWRDH tWRS
tWRH t
WRDS
WR/TR
\
tWINDH tWINS tWINH tWINDS
\
WXINC
\
\
WE
\
tSWE
tWEDH
tWES
tDS
tDH
tDS
tDH
\
DIN0 - 11
\
Valid
Valid
Note : The line address is reset to the initialized addresses and the word address is reset to 0.
20/23
¡ Semiconductor
MSM548332
Read Line Hold Mode
tRCLK
tWRCLL
\
RCLK
\
tWRCLH
\
RADE/RX
Low
\
\
tRRDH
tRRS
tRRH t
RRDS
RR
\
\
RXINC
Low
\
\
tSRE
RE
tREDH
tRES
\
tAC
tOH
\
DO0 - 11
Valid
\
Valid
\
OE
High
\
Note : The line address is held and the word address is reset to 0.
Read Reset Mode
tRCLK
tWRCLL
\
RCLK
\
\
RADE/RX
\
\
RR
tWRCLH
tRRXDH tRRXS tRRXH tRRXDS
tRRDH tRRS
tRRH t
RRDS
\
\
RXINC
\
\
RE
tSRE
tREDH
\
Low
tRES
tAC
tOH
\
DO0 - 11
\
Valid
Valid
\
High
OE
\
Note : Both the line address and word address are reset to 0.
21/23
¡ Semiconductor
MSM548332
Read Line Increment Mode
tRCLK
tWRCLL
\
RCLK
\
tWRCLH
\
RADE/RX
Low
\
\
tRRDH
tRRS
tRRH t
RRDS
RR
\
\
tRINDH tRINS tRINH tRINDS
RXINC
\
\
tSRE
RE
tREDH
\
tRES
tAC
tOH
\
DO0 - 11
Valid
\
Valid
\
OE
High
\
Note : The line address is incremented by 1 and the word address is reset to 0.
Read Address Jump Mode
tRCLK
tWRCLL
\
RCLK
\
\
RADE/RX
\
\
RR
\
\
RXINC
tWRCLH
tRRXDH tRRXS tRRXH tRRXDS
tRRDH tRRS
tRRH t
RRDS
tRINDH tRINS tRINH tRINDS
\
\
RE
\
tSRE
tREDH
tRES
tAC
tOH
\
DO0 - 11
\
Valid
Valid
\
High
OE
\
Note : The line address is reset to the initialized addresses and the word address is reset to 0.
22/23
¡ Semiconductor
MSM548332
PACKAGE DIMENSIONS
(Unit : mm)
TSOPII44-P-400-0.80-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.54 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
23/23