OKI MSM548333

E2L0035-17-Y1
¡ Semiconductor
MSM548333
¡ Semiconductor
This version:
Jan. 1998
MSM548333
Previous version: Dec. 1996
240,384-Word ¥ 8-bit + 240,384-Word ¥ 4-bit Triple Port type Field Memory
DESCRIPTION
The MSM548333 is a high performance double triple-port type 2.88-Mbit, 768 bits ¥ 313 lines ¥ (8 +
4), Field Memory for Y-C separation signal control. The MSM548333 has two memory plain blocks:
Y area has 8 plains and C area has 4 plains. Each plain contains 768 ¥ 313 bits. Each plain has one input
port and two output ports. Access is done line by line. The line address must be set each time a line
is changed.
The MSM548333 is especially designed for high performance digital cameras, TVs, VTRs and Multimedia applications which require special operations such as time-base correction, noise reduction
and other digital techniques.
The MSM548333 is not designed for high end use in such applications as medical systems,
professional graphics systems which require long term picture storage, data storage systems and
others.
More than two MSM548333s can be cascaded directly without any delay devices between them.
Cascading MSM548333s provides larger capacity and longer delay.
X and Y serial address input enables random initial address setting of serial access in a page. Other
than the random address setting, MSM548333 has several types of address set modes such as line
hold, address jump to initial address and line increment. For example, address jump to initial X
address and line increment enable block access.
Self refresh function releases the MSM548333 from being applied external refresh control clocks even
though it contains dynamic type memory cells. Input enable control or IE pin enables write mask
function.
FEATURES
• Configuration
6-port configuration
Y area: 768 ¥ 313 ¥ 8-bit configuration ¥ 1 (serial write port)
768 ¥ 313 ¥ 8-bit configuration ¥ 2 (serial read port)
C area: 768 ¥ 313 ¥ 4-bit configuration ¥ 1 (serial write port)
768 ¥ 313 ¥ 4-bit configuration ¥ 2 (serial read port)
• Line by line access.
• X and Y serial address inputs for random serial initial bit address
• Asynchronous operation
• Serial read and write cycle times
Read cycle: 30 ns min.
Write cycle: 50 ns min.
• Low operating supply voltage: 3.3 V ±0.3 V
• Self-refresh.
• Various address reset mode for picture processing
• Write mask by IE.
• Package:
100-pin plastic TQFP (TQFP100-P-1414-0.50-K)
(Product : MSM548333TS-K)
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¡ Semiconductor
MSM548333
76 NC
77 DINY/1
78 DINY/0
79 WADE/RX
80 WXINC
81 WR/TR
82 NC
83 WE/WY
84 IE
85 WCLK
86 WYAD
87 VCC
88 VCC
89 NC
90 WXAD
91 RYADC2
92 RYADY2
93 RXAD2
94 NC
95 RYAD1
96 RXAD1
97 TEST
98 RADE2/RX
99 RXINC2
100 NC
PIN CONFIGURATION (TOP VIEW)
RR2/TR 1
75 DINY/2
REC2/RY 2
74 DINY/3
RCLKC2 3
73 DINY/4
72 NC
NC 4
REY2/RY 5
71 DINY/5
RCLKY2 6
70 DINY/6
RADE1/RX 7
69 DINY/7
RXINC1 8
68 DINC/0
67 NC
NC 9
RR1/TR 10
66 DINC/1
RE1/RY 11
65 DINC/2
64 NC
NC 12
63 DINC/3
RCLK 13
NC 14
62 VCC
VSS 15
61 VSS
VSS 16
60 NC
VSS 17
59 VSS
DOY1/0 18
58 DOC2/0
DOY1/1 19
57 DOC2/1
DOY1/2 20
56 DOC2/2
DOY1/3 21
55 NC
NC 22
54 DOC2/3
VCC 23
53 VCC
NC 50
DOC1/2 49
DOC1/3 48
VSS 47
VSS 46
DOY2/7 45
DOY2/6 44
DOY2/5 43
NC 42
DOY2/4 41
VCC 40
NC 39
VCC 38
VCC 37
VCC 36
DOY2/3 35
NC 34
DOY2/2 33
DOY2/1 32
DOY2/0 31
VSS 30
VSS 29
DOY1/7 28
51 DOC1/1
NC 26
52 DOC1/0
DOY1/5 25
DOY1/6 27
DOY1/4 24
100-Pin Plastic TQFP
2/42
¡ Semiconductor
MSM548333
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
1
RR2/TR
26
NC
51
DOC1/1
76
NC
2
REC2/RY
27
DOY1/6
52
DOC1/0
77
DINY/1
3
RCLKC2
28
DOY1/7
53
VCC
78
DINY/0
4
NC
29
VSS
54
DOC2/3
79
WADE/RX
5
REY2/RY
30
VSS
55
NC
80
WXINC
6
RCLKY2
31
DOY2/0
56
DOC2/2
81
WR/TR
7
RADE1/RX
32
DOY2/1
57
DOC2/1
82
NC
8
RXINC1
33
DOY2/2
58
DOC2/0
83
WE/WY
9
NC
34
NC
59
VSS
84
IE
10
RR1/TR
35
DOY2/3
60
NC
85
WCLK
11
RE1/RY
36
VCC
61
VSS
86
WYAD
12
NC
37
VCC
62
VCC
87
VCC
13
RCLK
38
VCC
63
DINC/3
88
VCC
14
NC
39
NC
64
NC
89
NC
15
VSS
40
VCC
65
DINC/2
90
WXAD
16
VSS
41
DOY2/4
66
DINC/1
91
RYADC2
17
VSS
42
NC
67
NC
92
RYADY2
18
DOY1/0
43
DOY2/5
68
DINC/0
93
RXAD2
19
DOY1/1
44
DOY2/6
69
DINY/7
94
NC
20
DOY1/2
45
DOY2/7
70
DINY/6
95
RYAD1
21
DOY1/3
46
VSS
71
DINY/5
96
RXAD1
22
NC
47
VSS
72
NC
97
TEST
23
VCC
48
DOC1/3
73
DINY/4
98
RADE2/RX
24
DOY1/4
49
DOC1/2
74
DINY/3
99
RXINC2
25
DOY1/5
50
NC
75
DINY/2
100
NC
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¡ Semiconductor
Pin Name
MSM548333
Function
Address Setting Cycle
Serial Read/Write Cycle
Y1, C1, Y2 and C2 Read Ports
RCLK
Y1 and C1 Read Ports, Serial Read Clock
X and Y Serial Address Strobes
RE1/RY
Y1 and C1 Read Ports, Y Address Reset
Y1 and C1 Read Ports, Read Enable
DOY1/0 - 7
—
Y1 Read Port, Data Output
DOC1/0 - 3
—
C1 Read Port, Data Output
RR1/TR
Y1 and C1 Read Ports, Address Reset Mode Enable
—
RXINC1
Y1 and C1 Read Ports, X Address Increment
—
RADE1/RX
Y1 and C1 Read Ports, X and Y Address Input Enable
—
Y1 and C1 Read Ports, X Address Reset
RXAD1
Y1 and C1 Read Ports, X Serial Address Data
—
RYAD1
Y1 and C1 Read Ports, Y Serial Address Data
—
RR2/TR
Y2 and C2 Read Ports, Address Reset Mode Enable
—
RXINC2
Y2 and C2 Read Ports, X Address Increment
—
RADE2/RX
Y2 and C2 Read Ports, X and Y Address Input Enable
RXAD2
Y2 and C2 Read Ports, X Serial Address Data
RYADY2
Y2 Read Port, Y Serial Address Data
RCLKY2
—
—
—
REY2/RY
DOY2/0 - 7
RYADC2
—
Y2 and C2 Read Ports, X Address Reset
Y2 Read Port, Serial Read Clock
Y2 Read Port, Y Address Reset
Y2 Read Port, Read Enable
—
Y2 Read Port, Data Output
C2 Read Port, Y Serial Address Data
RCLKC2
—
—
REC2/RY
DOC2/0 - 3
C2 Read Port, Serial Read Clock
C2 Read Port, Y Address Reset
C2 Read Port, Read Enable
—
C2 Read Port, Data Output
WCLK
Y and C Write Ports, X and Y Serial Address Strobes
Y and C Write Ports, Serial Write Clock
WE/WY
Y and C Write Ports, Y Address Reset
Y and C Write Ports, Write Enable
DINY/0 - 7
DINC/0 - 3
Y Write Port, Input Data
—
C Write Port, Input Data
WR/TR
Y and C Write Ports, Address Reset Mode Enable
WXINC
Y and C Write Ports, X Address Increment
WADE/RX
Y and C Write Ports, Write Data Transfer
—
Y and C Write Ports, X and Y Address Input Enable
—
Y and C Write Ports, X Address Reset
WXAD
Y and C Write Ports, X Serial Address Data
—
WYAD
Y and C Write Ports, Y Serial Address Data
—
IE
VCC
VSS
TEST
Notes:
—
Input Enable
Power Supply Voltage (3.3 V)
Ground (0 V)
Connect to Power Supply Voltage (3.3 V)
1. Same power supply voltage level must be provided to every VCC pin.
Same ground voltage level must be provided to every VSS pin.
2. Connect the TEST pin to the power supply.
3. NC must be opened. Don't connect to anything electrically.
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IE
12
DINY/0 to DINY/7
DINC/0 to DINC/3
Write Buffer
WXINC
WADE/RX
WCLK
WE/WY
WYAD
RADE1/RX
RCLK
RE1/RY
RYAD1
RADE2/RX
RCLK
REY2/RY
RYADY2
RCLK
REC2/RY
RYADC2
WR/TR
WXAD
Write Register
iY j
Refresh Controller
Write Register
iC j
¡ Semiconductor
BLOCK DIAGRAM
WCLK
WE/WY
Write Address Control
RXINC1
RR1/TR
RXAD1
Read Address Control
iY1/C1 j
Memory Cell Array
Memory Controller
RXINC2
RR2/TR
RXAD2
Read Address Control
iY2 j
Y-Region
768 ¥ 313 ¥ 8 bits
C-Region
768 ¥ 313 ¥ 4 bits
Read
Register
iY2 j
Read
Register
iY1 j
Read
Register
iC1 j
DOUT
Buffer-1
8 bits
DOUT
Buffer-1
4 bits
Read
Register
iC2 j
Read Address Control
iC2 j
8
DOY1/0 to DOY1/7
8
DOUT
Buffer-2
8 bits
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RCLKY2
RE1/RY
REY2/RY
DOC1/0 to DOC1/3
DOUT
Buffer-2
4 bits
4
RCLKC2
RCLK
REC2/RY
DOC2/0 to DOC2/3
MSM548333
DOY2/0 to DOY2/7
4
¡ Semiconductor
MSM548333
PIN FUNCTION (Note : Y1 = "port-1 of Y area", Y2 = "port-2 of Y area", C1 = "port-1 of C area",
C2 = "port-2 of C area "
READ RELATED
RCLK : Read Clock for Y1 and C1, Common Read Address Strobe Clock
RCLK is the read control clock input for Y1 and C 1. Synchronized with RCLK's rising edge, serial
read access from Y1 and C1 is executed when RE1/RY is high. (Note that the write port has one port,
Y and C, but the read port has dual ports, Y1 and C1 plus Y2 and C2. Y1 and C1 are controlled by the
common read clock RCLK. But Y2 and C2 are controlled by separated read clocks, RCLKY2 and
RCLKC2, asynchronously.)
The internal counter for the serial read address is incremented automatically on the rising edge of
RCLK. In a read address set cycle, all the read address bits which were input from each RXAD1, RYAD1,
RXAD2, RYADY2, and RYADC2 pins are stored into internal address registers synchronized
with RCLK. In this address set cycle, RADE1/RX and RADE2/RX must be held high and the RR1/
TR and RR2/TR must be held low.
In the read address reset cycle, various read address reset modes can be set synchronously with
RCLK. These reset cycles work to replace complicated serial address control which requires many
RCLK clocks with a simple reset cycle control requiring only a single RCLK cycle. It greatly facilitates
memory access.
RE1/RY : Read Enable for Y1 and C1/Read Y Address Reset Logic Function
RE1/RY is a dual function control input. RE1, one of the two functions of RE1/RY, is read enable.
RE1 enables or disables both internal read address pointers and data-out buffers of Y1 and C1. When
RE1/RY is high, the internal read address pointer for Y1 and C1 is incremented synchronously with
RCLK. When RE1/RY is low, even if the RCLK is input, the internal read address pointer is not
incremented.
RY, the second function of RE1/RY, performs a function for setting the read Y address (or bit address
in a certain line) reset mode in Y1 and C1. In a read address reset mode cycle, as defined by RR1/TR
being high, RY works as one of inputs which form several read reset logic as shown in the
"FUNCTION TABLE for read". In the address reset cycle, when RE1/RY level is low, each Y1and C1
internal read Y address is reset to 0. When RE1/RY is high, each Y1 and C1 internal read Y address
is reset to the respective address which was set in the previous read address set cycle.
DOY1/0-7 : Data-Outs for Y1
DOY1/0-7 are serial data-outs for Y1. Each corresponding data out buffer' impedance is controlled
by RE1/RY.
DOC1/0-3 : Data-Outs for C1
DOC1/0-3 are serial data-outs for C1. Each corresponding data out buffer' impedance is controlled
by RE1/RY.
RR1/TR : Read Reset for Y1 and C1
RR1/TR is a read reset control input for Y1 and C1. Read address reset modes are defined when RR1/
TR level is high according to the "FUNCTION TABLE for read".
RXINC1 : Read X Address Increment for Y1 and C1
RXINC1 is a read X address (or line address) increment control input for Y1 and C1. In the read
address reset cycle, defined by RR1/TR high, the common X address (or line address) for Y1 and C1
is incremented by RXINC1.
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¡ Semiconductor
MSM548333
RADE1/RX : Read Address Enable for Y1 and C1/Read X Address Reset Logic Function
RADE1/RX is a dual function control input. RADE1, one of the two functions of RADE1/RX, is a read
address enable input for Y1 and C1. In the read address set cycle, defined by RR1/TR low, X address
(or line address) and Y address (or bit address in a certain line) input from the RXAD1 pin and RYAD1
pin are latched into internal read X address register and Y address register, respectively synchronously
with RCLK.
RX, the second function of RADE1/RX, works as an element to set read X address (or line address)
reset mode. In an address reset mode cycle, defined by RR1/TR level high, RX works as one of inputs
which form several read reset logic as shown in the "FUNCTION TABLE for read".
RXAD1 : Read X Address for Y1 and C1
RXAD1 is a read X address (or line address) input for Y1 and C1. RXAD1 specifies the line address.
9 bits of read X address data are input serially from RXAD1.
RYAD1 : Read Y Address for Y1 and C1
RYAD1 is a read Y address (or bit address in a certain line) input for Y1 and C1. RYAD1 specifies the
first bit address of consecutive serial read data in the line whose line address is defined by the X read
address from RXAD1. 10 bits of Y address data are input serially from RYAD1.
RR2/TR : Read Reset for Y2 and C2
RR2/TR is a read reset control input for Y2 and C2. Read address reset modes for Y2 and C2 are
defined when RR2/TR level is high based on the "FUNCTION TABLE for read".
RXINC2 : Read X Address Increment for Y2 and C2
RXINC2 is a read X address (or line address) increment control input for Y2 and C2. In the read
address reset cycle, defined by RR2/TR high, the common read X address (or line address) for Y2
and C2 is incremented by RXINC2.
RADE2/RX : Read Address Enable for Y2 and C2/Read X Address Reset Logic Function
RADE2/RX is a dual function control input. RADE2, one of the two functions of RADE2/RX, is a read
address enable input for Y2 and C2. In the read address set cycle, defined by RR2/TR high, the read
X address (or line address) and the read Y address (or bit address in a certain line), which are input
from the RXAD2, RYADY2 and RYADC2 pins, are latched into internal read X address register and
read Y address register, respectively, synchronously with RCLK.
RX, the second function of RADE2/RX, performs a function for setting the read X address (or line
address) reset mode. In a read address reset mode cycle, defined by RR2/TR level high, RX works
as one of inputs which form several read reset logic as shown in the "FUNCTION TABLE for read".
RXAD2 : Read X Address for Y2 and C2
RXAD2 is a read X address (or line address) input for Y2 and C2. RXAD2 specifies the line address.
9 bits of X address data is input serially from RXAD2.
RYADY2 : Read Y Address for Y2
RYADY2 is a read Y address (or bit address in a certain line) input for Y2. RYADY2 specifies the first
bit address of serial read data in the line whose line address is specified by the X address RXAD2.
10 bits of Y address data are input serially from RYADY2.
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¡ Semiconductor
MSM548333
RCLKY2 : Read Clock for Y2
RCLKY2 is a read control clock input for Y2. (Note that there is RCLKC2 for C2.) Synchronized
with RCLKY2's rising edge, the serial read access from Y2 is executed when REY2/RY is high.
REY2/RY : Read Enable for Y2/Read Y Address Reset Logic Function for Y2
REY2/RY is a dual function control input. REY2, one of the two functions of REY2/RY, enables or
disables both internal read address pointers and data-out buffers of Y2. When REY2/RY is high, the
internal read address pointer for Y2 is incremented synchronously with RCLKY2. When REY2/RY
is low, even if RCLKY2 is input, the internal read address pointer is not incremented.
RY, the second function of REY2/RY, works as an element to set read Y address (or bit address in
a certain line) reset mode. In a read address reset mode cycle, defined by RR2/TR high, RY works
as one of inputs which form several read reset logic as shown in the "FUNCTION TABLE for read".
In the read address reset cycle, when REY2/RY is low, the internal read Y address for Y2 is reset to
0. When REY2/RY is high, the internal read Y address for Y2 is reset to the address which was set
in the previous address set cycle.
DOY2/0-7 : Data-Outs for Y2
DOY2/0-7 are serial data-outs for Y2. Each corresponding data-out-buffer' impedance is controlled
by REY2/RY.
RYADC2 : Read Y Address for C2
RYADC2 is a read Y address (or bit address in a certain line) input only for C2. RYADC2 specifies
the first bit address of serial read data in the line whose line address is specified by RXAD2. 10 bits
of Y address data are input serially from RYADC2.
RCLKC2 : Read Clock for C2
RCLKC2 is a read control clock input for only C2. (Note that there is RCLKY2 for Y2.) Synchronized
with RCLKC2, serial read access from C2 is executed when REC2/RY is high.
REC2/RY : Read Enable for C2/Read Y Address Reset Logic Function for C2
REC2/RY is a dual function control input. REC2, one of the two functions of REC2/RY, enables or
disables both internal read address pointers and data-out buffers for C2. When REC2/RY is high, the
internal read address pointer for C2 is incremented synchronously with RCLKC2. When REC2/RY
is low, even if RCLKC2 is input, the internal read address pointer is not incremented.
RY, the second function of REC2/RY, performs a function for setting the read Y address (or bit
address in a certain line) reset mode. In an address reset mode cycle, defined by RR2/TR high, RY
works as one of inputs which form several read reset logic as shown in the "FUNCTION TABLE for
read". In the read address reset cycle, when REC2/RY is low, the internal read Y address for C2 is
reset to 0. When REC2/RY is high, the internal read Y address for C2 is reset to the address which
was set in the previous read address set cycle.
DOC2/0-3 : Data-Outs for C2
DOC2/0-3 are serial data-outs for C2. Each corresponding data out buffer' impedance is controlled
by REC2/RY.
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¡ Semiconductor
MSM548333
WRITE RELATED
WCLK : Write Clock for Y and C
WCLK is a write control clock input for Y and C ports. Synchronized with WCLK's rising edge, serial
write access into Y and C ports is executed when WE/WY is high and IE is high. (Note that the read
port is dual port, Y1 and C1 + Y2 and C2, but write port has only one port, Y + C. X8 of Y and X4 of
C inputs are controlled by a common WCLK, that is, in the write port, the MSM548333 is controlled
as a X12 FRAM.)
According to WCLK clocks, the internal counter for the serial address is incremented automatically.
In a write address set cycle, all the write addresses which were input from WXAD and WYAD are
stored into internal address registers synchronously with WCLK. In this address set cycle, WADE/
RX must be held high and WR/TR must be held low.
In the write address reset cycle, various write address reset modes can be set synchronously with
WCLK. These reset cycles replace complicated serial address control with simple reset cycle control
which requires only one WCLK cycle. It greatly facilitates memory access.
WE/WY : Write Enable for Y and C/Write Y Address Reset Logic Function
WE/WY is a dual function control input. WE, one of the two functions of WE/WY, is write enable.
WE enables or disables both internal write address pointers and data-in buffers of Y and C. When
WE/WY is high, the internal write address pointer for Y and C is incremented synchronously with
WCLK. When WE/WY is low, even if WCLK is input, the internal write address pointer is not
incremented.
WY, the second function of WE/WY, performs a function for setting the write Y address (or bit
address in a certain line) reset mode in Y and C. In a write address reset mode cycle, defined by WR/
TR high, WY works as one of inputs which form several write reset logic as shown in the "FUNCTION
TABLE for write". In the address reset cycle, when WE/WY level is low, each Y and C internal write
Y address is reset to 0. When WE/WY is high, each Y and C internal write Y address is reset to the
respective address which was set in the previous write address set cycle.
DINY/0-7 : Data-Ins for Y
DINY/0-7 are serial data-ins for Y. Each corresponding data-in-buffer is masked by IE.
DINC/0-3 : Data-Ins for C
DINC/0-3 are serial data-ins for C. Each corresponding data-in-buffer is masked by IE.
WR/TR : Write Reset for Y and C
WR/TR is a write reset control input for Y and C. Write address reset modes are defined when WR/
TR level is high according to the "FUNCTION TABLE for write".
WXINC : Write X Address Increment for Y and C
WXINC is a write X address (or line address) increment control input for Y and C. In the write address
reset cycle, defined by WR/TR high, the common write X address (or line address) for Y and C is
incremented by WXINC.
WADE/RX : Write Address Enable for Y and C/Write X Address Reset Logic Function
WADE/RX is a dual functional control input. WADE, one of the two functions of WADE/RX, is a
write address enable input for Y and C. In the write address reset cycle, defined by WR/TR high, X
address (or line address) and Y address (or bit address in a certain line) input from WXAD and
WYAD are latched into internal write X address register and Y address register.
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¡ Semiconductor
MSM548333
WXAD : Write X Address for Y and C
WXAD is a write X address (or line address) input for Y and C. WXAD specifies line address. 9 bits
of write X address data are input serially from WXAD.
WYAD : Write Y Address for Y and C
WYAD is a read Y address (or bit address in a certain line) input for Y and C. WYAD specifies the
first bit address of consecutive serial write data in the line whose line address is defined by X write
address from WXAD. 10 bits of write Y address data are input serially from WYAD.
IE : Input Enable for Y and C
IE is an input enable which controls the write operation. When IE is high, the input operation is
enabled. When IE is low, the write operation is masked. When WE/WY signal is high, and IE low,
the internal serial write address pointer is incremented on the rising edge of WCLK without actual
write operations. This function facilitates picture in picture function in a TV system.
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¡ Semiconductor
MSM548333
OPERATION MODE
Write
1. Write operation
Before the write operation begins, X address (or line address) and Y address (or bit address
in the line specified by the X address) must be input to set the initial bit address for the
following serial write access. When WE/WY and IE are high, a set of serial 12-bit -width write
data on DINY/0-7 and DINC/0-3 is written into write registers attached to the DRAM
memory arrays temporarily on the rising edge of WCLK.
Following 12-bit-width serial input data is written into the memory locations in the write
register designated by an internal write address pointer which is advanced by WCLK. This
enables continuous serial write on a line. When write clock WCLK and read clock RCLK are
tied together and are controlled by a common clock or CLK, more than two MSM548333s can
be cascaded directly without any delay devices between the MSM548333s because the read
timing is delayed by one CLK cycle to the write timing. When the write operation on a line is
terminated, be sure to perform a write transfer operation by WR/TR in order to store the
written data in the write registers to the corresponding memory cells in the DRAM memory
arrays.
2. Write address pointer increment operation
The write address pointer is incremented synchronously with WCLK when WE/WY is high.
When the write address pointer reaches the last address of a line, it stops at the last address
and no address increment occurs.
Relationship between the WE/WY and IE input levels,
Write Address pointer, and data input status
WCLK Rise
WE/WY
IE
H
H
H
L
L
—
Internal Write
Address Pointer
Incremented
Stopped
Data Input
Inputted
Not Inputted
When WE/WY and IE are high, the write operation is enabled.
If IE level goes low while WCLK is active, the write operation is halted but the write address
pointer will continue to advance. That is, IE enables a write mask function. When WE/WY
goes low, the write address pointer stops without WCLK.
Read (Here, "port-1 of Y area" is Y1, "port-2 of Y area" is Y2, "port-1 of C area" is C1, "port-2 of C area"
is C2.)
1. Read operation
MSM548333 has dual read ports, port-1 for Y and C memory areas and port-2 for Y and C
memory areas. Note that the read of Y1 and C1 are controlled by a common control clock at
the same time. But the read of Y2 and C2 are controlled by separate sets of control clocks,
independently.
Before the read operation begins, the X address (or line address) and Y address (or bit address
in the line specified by the X address) must be input for setting initial bit address for the
following serial read access.
When RE1/RY is high, a set of serial 12-bit-width read data on DOY1/0-7 pins and DOC1/
0-3 pins is read from read registers attached to DRAM memory arrays on the rising edge of
RCLK.
When REY2/RY is high, a set of serial 8-bit-width read data on DOY2/0-7 pins is read from
read registers attached to DRAM memory arrays on the rising edge of RCLKY2.
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¡ Semiconductor
MSM548333
When REC2/RY is high, a set of 4-bit-width serial read data on DOC2/0-3 is read from the
read registers attached to DRAM memory arrays on the rising edge of RCLKC2.
Each access time is specified by the rising edges of RCLK, RCLKY2 and RCLKC2.
2. Read address pointer increment operation
There are three separate pointers for dual port serial read operation. The first one is the read
pointer for Y1 and C1 which is incremented by RCLK when RE1/RY is high. The second one
is the read pointer for Y2 which is incremented by RCLKY2 when REY2/RY is high. The third
one is the read pointer for C2 which incremented by RCLKC2 when REC2/RY is high. When
each read address pointer reaches the last address of a line, it stops at the last address and no
address increment occurs.
Initial Address Setting (Write/Read Independent)
Any read operations are prohibited in the read initial address set period. Similarly, any write
operations are prohibited in the write initial address set period. Note that read initial address set and
write initial address set can occur independently. Similarly, read access can be achieved independently
from write initial address set period and write access can be achieved independently from read initial
address set cycles.
1. Write address setting
During a write, MSM548333 has one write address enable input, WADE/RX. Note that there
are two read address enable inputs for read. WADE/RX enables Y and C initial read address
inputs. When WADE/RX is high, 9 bits of serial X address (or line address) for Y and C and
10 bits of serial Y address (or bit address in the line specified by the X address) for Y and C are
input in parallel from WXAD and WYAD respectively.
The operations above enable selection of specific lines randomly and enables the start of serial
write access synchronized with write clock WCLK. Address for each line must be input
between each line access. In other words, MSM548333's write is achieved in a "line by line"
manner. Any write operations are prohibited in the initial write address set periods.
Y and C Serial write input enable time tSWE must be kept for starting a serial write just after
the initial write address set period.
2. Read address setting
During a read, MSM548333 has two read address enable inputs, RADE1/RX and RADE2/RX.
RADE1/RX enables Y1 and C1 initial read address inputs. Similarly, RADE2/RX enables Y2
and C2 initial read address inputs.
When RADE1/RX is high, 9 bits of serial X address (or line address) for Y1 and C1 and 10 bits
of serial Y address (or bit address in the line specified by the X address) for Y1 and C1 are input
in parallel from RXAD1 and RYAD1, respectively. Note that the X and Y address inputs when
RADE1/RX is high are for Y1 and C1.
When RADE2/RX is high, 9 bits of serial X address (or line address) for Y2 and C2 is input from
RXAD2. In the same period, 10 bits of serial Y address (or bit address in the line specified by
the X address) for Y2 is input from RYADY2 pin and another 10 bits of serial Y address (or bit
address in the line specified by the same X address input from RXAD2) for C2 is input from
RYADC2 pin. Note that the X address input here is for both Y2 and C2 and the two sets of Y
address inputs from RYADY2 and RYADC2 are for Y2 and C2, respectively. That is,
MSM548333 can't set separate line addresses in Y2 and C2 but can set separate initial bit
address in Y2 and C2 on the specified lines by the common line address.
The operations above enable selection of specific lines randomly and enables the start of serial
read access synchronized with read clocks, RCLK for Y1 and C1, RCLKY2 for Y2 and RCLKC2
for C2. Address for each line must be input between each line access. In other words,
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¡ Semiconductor
MSM548333
MSM548333's read operation is achieved in "line by line" manner.
Any read operations are prohibited in the initial read address set periods. Serial read
operations for Y1 and C1, and also Y2 and C2, are prohibited while RADE1/RX is high.
Similarly, serial read operations for Y1 and C1, and also Y2 and C2, are prohibited while
RADE2/RX level is high. Y1 and C1 Serial read port enable time tSRE1, Y2 serial read port
enable time tSREY2 and C2 serial read port enable time tSREC2 must be kept for starting a serial
read just after the initial read address set period.
Initial Address Reset Modes (Write/Read Independent)
The initial address reset modes replace complicated read or write initial address settings with simple
reset cycles. Initial address reset modes are selected by RR/TR high during read and WR/TR high
during write. As in normal read or write address settings, any read operations are prohibited in the
read address reset cycles. Similarly, any write operations are prohibited in the initial write address
reset cycles. Note that read initial address reset and write initial address reset can occur independently.
Similarly, read access can be achieved independently from write initial address reset cycles and write
access can be achieved independently from read initial address reset cycles.
Input addresses are stored into address registers which are connected with address counter which
controls address pointer operation. In the serial access operation, the input address into the address
registers are kept.
Serial write data input enable time tSWE, Y1 and C1 read port read enable time tSRE1, Y2 serial read
port read enable time tSREY2, C2 serial read port read enable time tSREC2 must be kept for starting
serial read or write just after the initial read or write address reset cycles. Note that all the read ports'
initial address reset must occur with the same timing.
1. Original address reset No.1 - "X, Y address counter reset" By the "Original address reset No.1" logic which is composed by a combination of control
input' levels, the address counter is reset to (0,0), and then, the address pointer is initialized
to (0,0). Reference the "FUNCTION TABLE" for read and write shown later. After the reset
mode, serial access starts from the address (0,0) : the line address is "0" and the initial bit
address on the line is (0,0).
The address counter is reset by this reset mode but the address register, which stored input
address in the previous address reset cycle or address set cycle, is not reset. The non-initialized
address can be used as a preset address in "address jump reset" mode. When the address
register must be reset, choose "address register reset" mode.
2. Original address reset No.2 - "X,Y address register reset" By the "Original address reset No.2" logic, the address register is reset, and then, the address
counter and address pointer are initialized to address (0,0) automatically. After the reset
mode, serial access starts from the address (0,0) : the line address is "0" and the initial bit
address on the line is (0,0)
Both address register and address counter are reset to (0,0) and the stored initial address in the
previous address reset cycle or address set cycle is cleared by this "address register reset". Once
the reset mode is selected, the reset address (0,0) is stored in the address register as a preset
address until next initial address set or reset operation. The address can be used as a preset
address in the "address jump reset" mode.
Note that REY2/RY and REC2/C2 must be both "L" at the same time when the "address
register reset" is selected. REY2/RY = "L" and REC2/RY = "H" or REY2/RY = "H" and REC2/
RY = "L" are prohibited.
3. Original address reset No.3 - Y address counter reset" By the "Original address reset No.3" logic, the Y address register is reset, and then, address
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¡ Semiconductor
MSM548333
pointer for the line access is initialized to Y address (0). The X address Xi which specifies a
certain line address is one which was stored in the X address register in the previous address
reset or address set cycle. After the reset mode, serial access starts from the address (Xi,0) : line
address is "Xi" and initial bit address on the line is (0).
The Y address counter is reset by this reset mode but the Y address register, which stored the
input initial Y address in the previous address reset cycle or address set cycle, is not reset. The
non-initialized Y address can be used as a preset Y address in the "address jump reset" mode.
4. Line increment reset No.1 - "X address counter increment and Y address counter reset" By the "Line increment reset No.1" logic, the X address counter is incremented by one from
the current X address and Y address is reset to address (0). That is, by the reset mode, serial
access from the Y = (0) on the next line is enabled.
5. Line increment reset No.2 - "X address counter increment reset and Y address counter
initialize" By the "Line increment reset No.2" logic, the X address counter is incremented by one from
the current X address and Y address is initialized to the Y address set in the previous address
set cycle. This enables block access on the screen.
6. Line hold reset No. 1 (1) operation
When a predetermined input level is set during the reset setting cycle, access is executed
starting from the first word on the current line.
7. Line hold (2) operation
When a predetermined input level is set during the reset setting cycle, access is executed
starting from the word address on the current line which is initialized.
8. Address jump operation
When a predetermined input level is set during the reset setting cycle, a jump may be caused
to the initialized line or word address.
In the case of a read, set the same level in the Y2 and C2 regions for this operation.
Note : During one reset setting cycle, a plurality of resets cannot be set.
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¡ Semiconductor
MSM548333
Power ON
Power must be applied to RCLK, RCLKY2, RCLKC2, RE1/RY, REY2/RY, REC2/RY and WE/WY
input signals to pull them "Low" before or when the VCC supply is turned on.
After power-up, the device is designed to begin proper operation in at least 200 ms after VCC has
reached the specified voltage. After 200 ms, a minimum of one line dummy write operation and read
operation is required according to the address setting mode, because the read and write address
pointers are not valid after power-up.
New Data Read Access
In order to read out "new data', the delay between the beginning of a write address setting cycle and
read address setting cycle must be at least two lines.
Old Data Read Access
In order to read out "old data", the delay between the beginning of a write address setting cycle and
read address setting cycle must be more than 0 but less than a half line.
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¡ Semiconductor
MSM548333
FUNCTION TABLE
1. Write
Mode
Address Reset
Mode
Address Setting
Mode
No.
Description of
Operation
WR/TR
WXINC
WE/WY
WADE/ Internal Address
RX
Pointer
1
Write Transfer
H
L
L
L
2
Reset (1)
H
L
L
H
X and Y cleared
to (0, 0)
3
Reset (2)
H
H
L
H
X and Y cleared
to (0, 0)
4
Line Increment (1)
H
H
L
L
X set and Y cleared
to (Xn + 1, 0)
5
Line Increment (2)
H
H
H
L
X and Y set
to (Xn +1, Yi)
6
Reset (3)
H
L
H
H
X cleared and Y
set to (0, Yi)
7
Line Hold (2)
H
L
H
L
X and Y set
to (Xn, Yi)
8
Address Jump
H
H
H
H
X and Y set
to (Xi, Yi)
—
First Address Setting
L
L
L
H
X and Y set
(Note)
Note : When Address reset mode No. 3 is executed, the address X and Y which are set previously will
be cleared. For write, Line hold (1) is not provided.
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¡ Semiconductor
MSM548333
2. Read
Mode
Address Reset
Mode
Address Setting
Mode
No.
Description of
Operation
RR*/TR
RXINC*
RE*/RY
RADE* Internal Address
/RX
Pointer
1
Line Hold (1)
H
L
L
L
X set and Y cleared
to (Xn, 0)
2
Reset (1)
H
L
L
H
X and Y cleared
to (0, 0)
3
Reset (2)
H
H
L
H
X and Y cleared
to (0, 0)
4
Line Increment (1)
H
H
L
L
X set and Y cleared
to (Xn + 1, 0)
5
Line Increment (2)
H
H
H
L
X and Y set
to (Xn + 1, Yi)
6
Reset (3)
H
L
H
H
X cleared and Y set
to (0, Yi)
7
Line Hold (2)
H
L
H
L
X and Y set
to (Xn, Yi)
8
Address Jump
H
H
H
H
X and Y set
to (Xi, Yi)
—
First Address Setting
L
L
L
H
X and Y set
(Note)
RR*/TR : RR1/TR, RR2/TR
RE*/RY : RE1/RY, REY2/RY, REC2/RY
RXINC*
RADE*/RX
*
*
: RXINC1, RXINC2
: RADE1/RX, RADE2/RX
* Set the same level in the Y2 and C2 regions.
Note : When address reset mode No. 3 is executed, the addresses X and Y which are set previously
will be cleared.
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¡ Semiconductor
MSM548333
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Symbol
Condition
Rating
Pin Voltage
VT
Ta = 25°C, with respect to VSS
–0.5 to 4.6 V
Short Circuit Output Current
IOS
Ta = 25°C
50 mA
Power Dissipation
PD
Ta = 25°C
1W
Operating Temperature
Topr
—
0 to 70°C
Storage Temperature
Tstg
—
–55 to 150°C
Recommended Operating Conditions
(Ta = 0 to 70°C)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Power Supply Voltage
VCC
3.0
3.3
3.6
V
Power Supply Voltage
VSS
0
0
0
V
"H" Input Voltage
VIH
2.1
VCC
VCC + 0.3
V
"L" Input Voltage
VIL
–0.5
0
0.8
V
DC Characteristics
(VCC = 3.0 to 3.6 V, Ta = 0 to 70°C)
Min.
Max.
Unit
"H" Output Voltage
Parameter
Symbol
VOH
IOH = –0.1 mA
Condition
2.2
—
V
"L" Output Voltage
VOL
IOL = 0.1 mA
—
0.7
V
–10
10
mA
0 < VI < VCC + 1
Input Leakage Current
ILI
Output Leakage Current
ILO
0 < VO < 3.6
–10
10
mA
ICC1
min. cycle
—
50
mA
ICC2
Input pin = VIL/VIH
—
10
mA
Power Supply Current
(During Operation)
Power Supply Voltage
(During Standby)
Other input voltage 0 V
Capacitance
(Ta = 25°C, f = 1 MHz)
Symbol
Max.
Unit
Input Capacitance
Parameter
CI
7
pF
Output Capacitance
CO
7
pF
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¡ Semiconductor
MSM548333
AC Characteristics (1/4)
Measurement Conditions: (VCC = 3.3 V ±0.3 V, Ta = 0 to 70°C)
Parameter
WCLK Cycle Time
Symbol
Min.
Max.
Unit
tWCLK
50
—
ns
WCLK "H" Pulse Width
tWWCLH
15
—
ns
WCLK "L" Pulse Width
tWWCLL
15
—
ns
Serial Write Address Input Active Setup Time
tWAS
5
—
ns
Serial Write Address Input Active Hold Time
tWAH
7
—
ns
Serial Write Address Input Inactive Hold Time
tWADH
7
—
ns
Serial Write Address Input Inactive Setup Time
tWADS
7
—
ns
Write Transfer Instruction Setup Time
tWTRS
5
—
ns
Write Transfer Instruction Hold Time
tWTRH
7
—
ns
Write Transfer Instruction Inactive Hold Time
tWTDH
7
—
ns
Write Transfer Instruction Inactive Setup Time
tWTDS
7
—
ns
Serial Write X Address Setup Time
tWXAS
5
—
ns
Serial Write X Address Hold Time
tWXAH
7
—
ns
Serial Write Y Address Setup Time
tWYAS
5
—
ns
Serial Write Y Address Hold Time
tWYAH
7
—
ns
Serial Write Data Input Enable Time
tSWE
5000
—
ns
Write Instruction Setup Time
tWES
5
—
ns
Write Instruction Hold Time
tWEH
7
—
ns
Write Instruction Inactive Hold Time
tWEDH
7
—
ns
Write Instruction Inactive Setup Time
tWEDS
7
—
ns
IE Enable Setup Time
tIES
5
—
ns
IE Enable Hold Time
tIEH
7
—
ns
IE Disable Hold Time
tIEDS
7
—
ns
IE Disable Setup Time
tIEDH
7
—
ns
Input Data Setup Time
tDS
5
—
ns
Input Data Hold Time
tDH
15
—
ns
tWRS
5
—
ns
WR/TR-WCLK Active Hold Time
tWRH
7
—
ns
WR/TR-WCLK Inactive Hold Time
tWRDH
7
—
ns
WR/TR-WCLK Inactive Setup Time
tWRDS
7
—
ns
WXINC-WCLK Active Setup Time
tWINS
5
—
ns
WXINC-WCLK Active Hold Time
tWINH
7
—
ns
WXINC-WCLK Inactive Hold Time
tWINDH
7
—
ns
WXINC-WCLK Inactive Setup Time
tWINDS
7
—
ns
WADE/RX-WCLK Active Setup Time
tWRXS
5
—
ns
WADE/RX-WCLK Active Hold Time
tWRXH
7
—
ns
WADE/RX-WCLK Inactive Hold Time
tWRXDH
7
—
ns
WADE/RX-WCLK Inactive Setup Time
tWRXDS
7
—
ns
WE/WY-WCLK Active Setup Time
tWRYS
5
—
ns
WR/TR-WCLK Active Setup Time
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¡ Semiconductor
MSM548333
AC Characteristics (2/4)
Measurement Conditions: (VCC = 3.3 V ±0.3 V, Ta = 0 to 70°C)
Parameter
Symbol
Min.
Max.
Unit
WE/WY-WCLK Active Hold Time
tWRYH
7
—
ns
WE/WY-WCLK Inactive Hold Time
tWRYDH
7
—
ns
WE/WY-WCLK Inactive Setup Time
tWRYDS
7
—
ns
tRCLK
30
—
ns
RCLK "H" Pulse Width
tWRCLH
12
—
ns
RCLK "L" Pulse Width
tWRCLL
12
—
ns
RR1/TR-RCLK Active Setup Time
tRRS1
5
—
ns
RCLK Cycle Time
RR1/TR-RCLK Active Hold Time
tRRH1
7
—
ns
RR1/TR-RCLK Inactive Hold Time
tRRDH1
7
—
ns
RR1/TR-RCLK Inactive Setup Time
tRRDS1
7
—
ns
RXINC1-RCLK Active Setup Time
tRINS1
5
—
ns
RXINC1-RCLK Active Hold Time
tRINH1
7
—
ns
RXINC1-RCLK Inactive Hold Time
tRINDH1
7
—
ns
RXINC1-RCLK Inactive Setup Time
tRINDS1
7
—
ns
RADE1/RX-RCLK Active Setup Time
tRRXS1
5
—
ns
RADE1/RX-RCLK Active Hold Time
tRRXH1
7
—
ns
RADE1/RX-RCLK Inactive Hold Time
tRRXDH1
7
—
ns
RADE1/RX-RCLK Inactive Setup Time
tRRXDS1
7
—
ns
RE1/RY-RCLK Active Setup Time
tRRYS1
5
—
ns
RE1/RY-RCLK Active Hold Time
tRRYH1
7
—
ns
RE1/RY-RCLK Inactive Hold Time
tRRYDH1
7
—
ns
RE1/RY-RCLK Inactive Setup Time
tRRYDS1
7
—
ns
Y1 and C1 Read Port Output Instruction Setup Time
tRES1
5
—
ns
Y1 and C1 Read Port Output Instruction Hold Time
tREH1
tAC1
—
ns
Y1 and C1 Read Port Output Instruction Inactive Hold Time
tREDH1
7
—
ns
Y1 and C1 Read Port Output Instruction Inactive Setup Time
tREDS1
7
—
ns
Y1 and C1 Read Port Read EnableTime
tSRE1
5000
—
ns
Y1 and C1 Read Port Read Data Hold Time
tOH1
15
—
ns
Y1 and C1 Output Access Time
tAC1
30
ns
\
Y1 and C1 Data Output Turn Off Delay Time
tOHZ1
20
—
ns
RR2/TR-RCLK Active Setup Time
tRRS2
5
—
ns
RR2/TR-RCLK Active Hold Time
tRRH2
7
—
ns
RR2/TR-RCLK Inactive Hold Time
tRRDH2
7
—
ns
RR2/TR-RCLK Inactive Setup Time
tRRDS2
7
—
ns
RXINC2-RCLK Active Setup Time
tRINS2
5
—
ns
RXINC2-RCLK Active Hold Time
tRINH2
7
—
ns
RXINC2-RCLK Inactive Hold Time
tRINDH2
7
—
ns
RXINC2-RCLK Inactive Setup Time
tRINDS2
7
—
ns
RADE2/RX-RCLK Active Setup Time
tRRXS2
5
—
ns
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¡ Semiconductor
MSM548333
AC Characteristics (3/4)
Measurement Conditions: (VCC = 3.3 V ±0.3 V, Ta = 0 to 70°C)
Parameter
Symbol
Min.
Max.
Unit
RADE2/RX-RCLK Active Hold Time
tRRXH2
7
—
ns
RADE2/RX-RCLK Inactive Hold Time
tRRXDH2
7
—
ns
RADE2/RX-RCLK Inactive Setup Time
tRRXDS2
7
—
ns
RCLKY2 Cycle Time
tRCLKY
30
—
ns
RCLKY2 "H" Pulse Width
tWRCLHY
12
—
ns
RCLKY2 "L" Pulse Width
tWRCLLY
12
—
ns
REY2/RY-RCLK Active Setup Time
tRRYSY2
5
—
ns
REY2/RY-RCLK Active Hold Time
tRRYHY2
7
—
ns
REY2/RY-RCLK Inactive Hold Time
tRRYDHY2
7
—
ns
REY2/RY-RCLK Inactive Setup Time
tRRYDSY2
7
—
ns
tRESY2
5
—
ns
Y2 Read Port Output Instruction Hold Time
tREHY2
tACY2
—
ns
Y2 Read Port Output Instruction Inactive Hold Time
tREDHY2
7
—
ns
Y2 Read Port Output Instruction Inactive Setup Time
tREDSY2
7
—
ns
Y2 Read Port Enable Time
tSREY2
5000
—
ns
Y2 Read Port Read Data Hold Time
tOHY2
15
—
ns
Y2 Output Access Time
tACY2
—
30
ns
Y2 Data Output Turn Off Delay Time
tOHZY2
20
—
ns
Y2 Read Port Output Instruction Setup Time
tRCLKC
30
—
ns
RCLKC2 "H" Pulse Width
tWRCLHC
12
—
ns
RCLKC2 "L" Pulse Width
tWRCLLC
12
—
ns
REC2/RY-RCLK Active Setup Time
tRRYSC2
5
—
ns
REC2/RY-RCLK Active Hold Time
tRRYHC2
7
—
ns
REC2/RY-RCLK Inactive Hold Time
tRRYDHC2
7
—
ns
REC2/RY-RCLK Inactive Setup Time
tRRYDSC2
7
—
ns
tRESC2
5
—
ns
C2 Read Port Output Instruction Hold Time
tREHC2
tACC2
—
ns
C2 Read Port Output Instruction Inactive Hold Time
tREDHC2
7
—
ns
C2 Read Port Output Instruction Inactive Setup Time
tREDSC2
7
—
ns
C2 Read Port Enable Time
tSREC2
5000
—
ns
C2 Read Port Read Data Hold Time
tOHC2
15
—
ns
C2 Output Access Time
tACC2
—
30
ns
C2 Data Output Turn Off Delay Time
tOHZC2
20
—
ns
Y1 and C1 Serial Read Address Input Active Setup Time
tRAS1
5
—
ns
Y1 and C1 Serial Read Address Input Active Hold Time
tRAH1
7
—
ns
Y1 and C1 Serial Read Address Input Inactive Hold Time
tRADH1
7
—
ns
Y1 and C1 Serial Read Address Input Inactive Setup Time
tRADS1
7
—
ns
Y1 and C1 Serial Read X Address Setup Time
tRXAS1
5
—
ns
Y1 and C1 Serial Read X Address Hold Time
tRXAH1
7
—
ns
RCLKC2 Cycle Time
C2 Read Port Output Instruction Setup Time
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¡ Semiconductor
MSM548333
AC Characteristics (4/4)
Measurement Conditions: (VCC = 3.3 V ±0.3 V, Ta = 0 to 70°C)
Parameter
Symbol
Min.
Max.
Unit
Y1 and C1 Serial Read Y Address Setup Time
tRYAS1
5
—
ns
Y1 and C1 Serial Read Y Address Hold Time
tRYAH1
7
—
ns
Y2 and C2 Serial Read Address Input Active Setup Time
tRAS2
5
—
ns
Y2 and C2 Serial Read Address Input Active Hold Time
tRAH2
7
—
ns
Y2 and C2 Serial Read Address Input Inactive Hold Time
tRADH2
7
—
ns
Y2 and C2 Serial Read Address Input Inactive Setup Time
tRADS2
7
—
ns
Y2 and C2 Serial Read X Address Setup Time
tRXAS2
5
—
ns
Y2 and C2 Serial Read X Address Hold Time
tRXAH2
7
—
ns
Y2 Serial Read Y Address Setup Time
tRYASY2
5
—
ns
Y2 Serial Read Y Address Hold Time
tRYAHY2
7
—
ns
C2 Serial Read Y Address Setup Time
tRYASC2
5
—
ns
C2 Serial Read Y Address Hold Time
tRYAHC2
7
—
ns
tT
3
30
ns
Transition Time (Rise and Fall)
Note :
Measurement conditions
Input pulse level
Input timing reference level
Output timing reference level
Input rise/fall time
Load condition
: VIH = VCC – 0.3 V, VIL = 0.5 V
: VIH = VCC – 0.3 V, VIL = 0.5 V
: VOH = 2.2 V, VOL = 0.7 V
: 3 ns
: CL = 30 pF (Oscilloscope and tool capacity included)
22/42
tWWCLH
WADE/RX
tWAS
tWAH tWADS
tWADH
¡ Semiconductor
WCLK
TIMING WAVEFORM
Write Cycle (Address Setting Cycle)
tWCLK
tWWCLL
, , , tWXAS tWXAH
WXAD
Valid
A8
Valid
A1
Valid
A0
Valid
B8
Valid
B1
Valid
B0
tWYAS tWYAH
WYAD
Valid
B9
tSWE
tWEDH
tWES
WE/WY
tIEDH
IE
tIES
Low
WXINC
Low
23/42
DINY/0 - 7
DINC/0 - 3
tDS tDH
tDS tDH
Valid
Valid
MSM548333
WR/TR
¡ Semiconductor
MSM548333
Write Cycle (WE Control)
(N-2)CYCLE (N-1)CYCLE
tWCLK
N CYCLE
(N+1) CYCLE (N+2) CYCLE
\
WCLK
\
\
WADE/RX
Low
\
High
\
IE
\
\
WR/TR
Low
\
\
WXINC
Low
\
tWEH
tWEDS tWEDH tWES
\
WE/WY
\
DINY/0 - 7
\
DINC/0 - 3
\
Valid
D(N-3)
Valid
D(N-2)
Valid
D(N-1)
Valid
D(N)
Valid
D(N+1)
Valid
D(N+2)
Note : In the WE/WY = "L" cycle, the write address pointer is not incremented and no DIN data is
written.
Write Cycle (IE Control)
(N-2)CYCLE (N-1)CYCLE
tWCLK
N CYCLE
(N+2) CYCLE (N+3) CYCLE
\
WCLK
\
\
WADE/RX
Low
\
High
\
WE/WY
\
\
WR/TR
Low
\
\
WXINC
Low
\
tIEH
tIEDS tIEDH
tIES
\
IE
\
DINY/0 - 7
\
DINC/0 - 3
\
Valid
D(N-3)
Valid
D(N-2)
Valid
D(N-1)
Valid
D(N)
Valid
D(N+2)
Valid
D(N+3)
Note : In the IE = "L" cycle, the write address pointer is incremented, though no DIN data is written
and the memory data is held.
24/42
¡ Semiconductor
MSM548333
Write Cycle (Write Transfer)
(N-2)CYCLE (N-1)CYCLE
tWCLK
N CYCLE
\
WCLK
\
\
WADE/RX
Low
\
\
WR/TR
\
\
WXINC
\
\
WE/WY
\
DINY/0 - 7
\
DINC/0 - 3
\
tWTRS tWTRH
tWTDH
tWTDS
Low
tWEH
Valid
D(N-3)
Valid
D(N-2)
Valid
D(N-1)
tWEDS
Valid
D(N)
Note : When finishing the write operation on a line, be sure to perform a write transfer operation
because the write data on the line is stored in the memory cell.
25/42
¡ Semiconductor
Read Cycle (Y1, C1) (Address Setting Cycle)
,
,
,
tRCLK
tWRCLL
RCLK
tWRCLH
RADE1/RX
tRAS1
tRAH1 tRADS1
tRADH1
tRXAS1 tRXAH1
RXAD1
Valid
C8
Valid
C1
Valid
C0
Valid
D8
Valid
D1
Valid
D0
tRYAS1 tRYAH1
RYAD1
Valid
D9
tSRE1
tREDH1
tRES1
RE1/RY
RR1/TR
Low
RXINC1
Low
DOY1/0 - 7
DOC1/0 - 3
tOH1
Valid
Valid
26/42
MSM548333
tAC1
High-Z
RCLK
tWRCLH
RADE2/RX
tRAS2
tRAH2 tRADS2
tRADH2
¡ Semiconductor
Read Cycle (Y2) (Address Setting Cycle)
tRCLK
tWRCLL
,
,
,
tRXAS2 tRXAH2
RXAD2
Valid
E8
Valid
E1
Valid
E0
Valid
F8
Valid
F1
Valid
F0
tRYASY2 tRYAHY2
Valid
F9
RYADY2
RR2/TR
Low
RXINC2
Low
tRCLKY
tWRCLLY
tSREY2
RCLKY2
tREDHY2
tWRCLHY
tRESY2
tACY2
27/42
DOY2/0 - 7
High-Z
tOHY2
Valid
Valid
MSM548333
REY2/RY
¡ Semiconductor
Read Cycle (C2) (Address Setting Cycle)
,
,
,
tRCLK
tWRCLL
RCLK
tWRCLH
RADE2/RX
tRAS2
tRAH2 tRADS2
tRADH2
tRXAS2 tRXAH2
RXAD2
Valid
E8
Valid
E1
Valid
E0
Valid
F8
Valid
F1
Valid
F0
tRYASC2 tRYAHC2
Valid
F9
RYADC2
RR2/TR
Low
RXINC2
Low
tRCLKC
tWRCLLC
tSREC2
RCLKC2
tREDHC2
tWRCLHC
tRESC2
tACC2
28/42
DOC2/0 - 3
High-Z
tOHC2
Valid
Valid
MSM548333
REC2/RY
¡ Semiconductor
MSM548333
Read Cycle (RE Control)
(L-2)CYCLE
(L-1)CYCLE
tRCLK
L CYCLE
(L+1) CYCLE (L+2) CYCLE
\
RCLK
\
\
RADE1/RX
Low
\
\
RR1/TR
Low
\
\
RXINC1
Low
\
tREH1 tREDS1 tREDH1 tRES1
\
RE1/RY
\
DOY1/0 - 7
\
DOC1/0 - 3
\
tOH1
Valid
D(L-3)
tOHZ1
Valid
D(L-2)
Valid
D(L-1)
Valid
D(L)
tAC1
Valid
D(L+1)
High-Z
Valid
D(L+2)
\
RADE2/RX
Low
\
\
RR2/TR
Low
\
\
RXINC2
Low
\
(M-2)CYCLE (M-1)CYCLE
tRCLKY
M CYCLE
(M+1) CYCLE (M+2) CYCLE
\
RCLKY2
\
tREHY2 tREDSY2 tREDHY2 tRESY2
\
REY2/RY
\
\
DOY2/0 - 7
\
tOHY2
Valid
D(M-3)
tOHZY2
Valid
D(M-2)
Valid
D(M-1)
(N-2)CYCLE (N-1)CYCLE
Valid
D(M)
tACY2
tRCLKC
N CYCLE
Valid
D(M+1)
High-Z
Valid
D(M+2)
(N+1) CYCLE (N+2) CYCLE
\
RCLKC2
\
tREHC2 tREDSC2 tREDHC2 tRESC2
\
REC2/RY
\
\
DOC2/0 - 3
\
tOHC2
Valid
D(N-3)
tOHZC2
Valid
D(N-2)
Valid
D(N-1)
Valid
D(N)
tACC2
High-Z
Valid
D(N+1)
Valid
D(N+2)
Note : In the cycle in which RE1/RY = "L", REY2/RY = "L", or REC2/RY = "L", the read address
pointer is not incremented and the output enters the high impedance state.
The signals RE1/RY, REY2/RY, and REC2/RY can be operated independently.
29/42
¡ Semiconductor
MSM548333
Write Reset (1) Mode
,,,
,
tWCLK
tWWCLL
\
WCLK
\
\
WADE/RX
tWWCLH
tWRXDH tWRXS tWRXH tWRXDS
\
tSWE
\
WE/WY
\
\
WR/TR
tWRDH tWRS
tWRH t
WRDS
\
\
WXINC
\
DINY/0 - 7
\
DINC/0 - 3
\
tDS tDH
Valid
Low
tDS tDH
Valid
Note : Both the line address and word address are reset to 0.
Write Reset (2) Mode
tWCLK
tWWCLL
\
WCLK
\
\
tWWCLH
tWRXDH tWRXS tWRXH tWRXDS
WADE/RX
\
tSWE
\
WE/WY
\
\
tWRDH tWRS
tWRH t
WRDS
tWINDH tWINS
tWINH t
WR/TR
\
\
WINDS
WXINC
\
DINY/0 - 7
\
DINC/0 - 3
\
tDS tDH
Valid
Low
tDS tDH
Valid
Note : Both the line address and word address are reset to 0. However, since the internal address
register is also reset to 0, the initialized address data is cleared.
30/42
¡ Semiconductor
MSM548333
Write Line Increment (1) Mode
tWCLK
tWWCLL
\
WCLK
\
tWWCLH
\
WADE/RX
\
tSWE
\
WE/WY
\
\
tWRDH tWRS
tWRH t
WRDS
tWINDH tWINS
tWINH t
WR/TR
\
\
WINDS
WXINC
\
Low
tDS tDH
DINY/0 - 7
\
DINC/0 - 3
\
tDS tDH
Valid
Valid
Note : The line address is incremented by 1 and the word address is reset to 0.
Write Line Increment (2) Mode
tWCLK
tWWCLL
\
WCLK
\
tWWCLH
tSWE
\
WADE/RX
\
\
WE/WY
\
\
WR/TR
\
\
tWRYDH tWRYS tWRYH tWRYDS
tWRDH tWRS
tWRH t
WRDS
tWINDH tWINS
tWINH t
WINDS
WXINC
\
DINY/0 - 7
\
DINC/0 - 3
\
tDS tDH
Valid
Low
tDS tDH
Valid
Note : The line address is incremented by 1 and the word address is reset to the initialized address.
31/42
¡ Semiconductor
MSM548333
Write Reset (3) Mode
tWCLK
tWWCLL
\
WCLK
\
\
tWWCLH
tWRXDH tWRXS tWRXH tWRXDS
WADE/RX
\
\
tWRYDH tWRYS tWRYH tWRYDS
WE/WY
\
\
tWRDH tWRS
tWRH t
WRDS
WR/TR
Low
\
tSWE
\
WXINC
\
DINY/0 - 7
\
DINC/0 - 3
\
tDS tDH
tDS tDH
Valid
Valid
Note : The line address is reset to 0 and the word address is reset to the initialized address.
Write Line Hold (2) Mode
tWCLK
tWWCLL
\
WCLK
\
tWWCLH
tSWE
\
WADE/RX
\
\
WE/WY
\
\
WR/TR
tWRYDH tWRYS tWRYH tWRYDS
tWRDH tWRS
tWRH t
WRDS
\
\
WXINC
\
DINY/0 - 7
\
DINC/0 - 3
\
tDS tDH
Valid
Low
tDS tDH
Valid
Note : The line address is held and the word address is reset to the initialized address.
32/42
¡ Semiconductor
MSM548333
Write Address Jump Mode
tWCLK
tWWCLL
\
WCLK
\
\
tWWCLH
tWRXDH tWRXS tWRXH tWRXDS
WADE/RX
\
\
tWRYDH tWRYS tWRYH tWRYDS
WE/WY
\
\
tWRDH tWRS
tWRH t
WRDS
tWINDH tWINS
tWINH t
WR/TR
\
\
WINDS
WXINC
\
Low
tDS tDH
DINY/0 - 7
\
DINC/0 - 3
\
tSWE
tDS tDH
Valid
Valid
Note : Both the line address and word address are reset to the initialized addresses.
33/42
¡ Semiconductor
MSM548333
Read Line Hold (1) Mode
tRCLK
tWRCLL
\
RCLK
\
tWRCLH
\
RADE1/RX
Low
\
\
tSRE1
RE1/RY
\
\
tREDH1
tRES1
tRRDH1 tRRS1 tRRH1 tRRDS1
RR1/TR
\
\
RXINC1
\
,,
DOY1/0 - 7
\
DOC1/0 - 3
\
Low
tAC1
High-Z
tOH1
Valid
Valid
\
RADE2/RX
\
\
RR2/TR
tRRDH2
tRRS2
Low
tRRH2 t
RRDS2
\
\
RXINC2
Low
\
tRCLKY
tWRCLLY
\
RCLKY2
\
\
REY2/RY
tSREY2
tREDHY2
\
\
DOY2/0 - 7
tRESY2
tWRCLHY
tACY2
tOHY2
High-Z
Valid
\
\
RCLKC2
\
\
REC2/RY
tSREC2
tREDHC2
\
\
DOC2/0 - 3
High-Z
Valid
tRCLKC
tWRCLLC
tRESC2
tWRCLHC
tACC2
tOHC2
Valid
Valid
\
Note : The line address is held and the word address is reset to 0.
34/42
¡ Semiconductor
MSM548333
Read Reset (1) Mode
tRCLK
tWRCLL
\
RCLK
\
\
tWRCLH
tRRXDH1 tRRXS1 tRRXH1 tRRXDS1
RADE1/RX
\
\
tSRE1
RE1/RY
\
\
tREDH1
tRES1
tRRDH1 tRRS1 tRRH1 tRRDS1
RR1/TR
\
\
RXINC1
\
,,
DOY1/0 - 7
\
DOC1/0 - 3
\
\
RADE2/RX
\
\
RR2/TR
Low
tAC1
High-Z
tRRXDH2
tOH1
Valid
Valid
tRRXS2 tRRXH2 t
tRRDH2 tRRS2
RRXDS2
tRRH2 t
RRDS2
\
\
RXINC2
Low
\
tRCLKY
tWRCLLY
\
RCLKY2
\
\
REY2/RY
tSREY2
tREDHY2
\
\
DOY2/0 - 7
tRESY2
tWRCLHY
tACY2
tOHY2
High-Z
Valid
\
\
RCLKC2
\
\
REC2/RY
tSREC2
tREDHC2
\
\
DOC2/0 - 3
High-Z
Valid
tRCLKC
tWRCLLC
tRESC2
tWRCLHC
tACC2
tOHC2
Valid
Valid
\
Note : Both the line address and word address are reset to 0.
35/42
¡ Semiconductor
MSM548333
Read Reset (2) Mode
tRCLK
tWRCLL
\
RCLK
\
\
tWRCLH
tRRXDH1 tRRXS1 tRRXH1 tRRXDS1
RADE1/RX
\
\
tSRE1
RE1/RY
\
\
tREDH1
tRES1
tRRDH1 tRRS1 tRRH1 tRRDS1
RR1/TR
\
\
tRINDH1 tRINS1 tRINH1 tRINDS1
RXINC1
\
,,
DOY1/0 - 7
\
DOC1/0 - 3
\
\
RADE2/RX
\
\
RR2/TR
\
\
RXINC2
tAC1
High-Z
tRRXDH2
tOH1
Valid
tRRDH2 tRRS2
RRXDS2
tRRH2 t
RRDS2
tRINDH2 tRINS2 tRINH2 tRINDS2
\
tRCLKY
tWRCLLY
\
RCLKY2
\
\
REY2/RY
tSREY2
tREDHY2
\
\
DOY2/0 - 7
tRESY2
tWRCLHY
tACY2
tOHY2
High-Z
Valid
\
\
RCLKC2
\
\
REC2/RY
tSREC2
\
\
DOC2/0 - 3
Valid
tRRXS2 tRRXH2 t
High-Z
tREDHC2
Valid
tRCLKC
tWRCLLC
tRESC2
tWRCLHC
tACC2
tOHC2
Valid
Valid
\
Note : Both the line address and word address are reset to 0. However, since the internal address
register is also reset to 0, the initialized address data is cleared.
36/42
¡ Semiconductor
MSM548333
Read Line Increment (1) Mode
tRCLK
tWRCLL
\
RCLK
\
tWRCLH
\
RADE1/RX
Low
\
tSRE1
\
RE1/RY
\
\
tREDH1
tRES1
tRRDH1 tRRS1 tRRH1 tRRDS1
RR1/TR
\
\
tRINDH1 tRINS1 tRINH1 tRINDS1
RXINC1
\
,,
DOY1/0 - 7
\
DOC1/0 - 3
\
tAC1
High-Z
tOH1
Valid
Valid
\
RADE2/RX
\
\
RR2/TR
\
\
RXINC2
tRRDH2
tRRS2
Low
tRRH2 t
RRDS2
tRINDH2 tRINS2 tRINH2 tRINDS2
\
tRCLKY
tWRCLLY
\
RCLKY2
\
\
REY2/RY
tSREY2
tREDHY2
\
\
DOY2/0 - 7
tRESY2
tWRCLHY
tACY2
tOHY2
High-Z
Valid
\
\
RCLKC2
\
\
REC2/RY
tSREC2
\
\
DOC2/0 - 3
High-Z
tREDHC2
Valid
tRCLKC
tWRCLLC
tRESC2
tWRCLHC
tACC2
tOHC2
Valid
Valid
\
Note : The line address is incremented by 1 and the word address is reset to 0.
37/42
¡ Semiconductor
MSM548333
Read Line Increment (2) Mode
tRCLK
tWRCLL
\
RCLK
\
tWRCLH
tSRE1
\
RADE1/RX
Low
\
\
tRRYDH1
tRRYS1 tRRYH1 t
tREDH1
RRYDS1
tRES1
RE1/RY
\
\
tRRDH1 tRRS1 tRRH1 tRRDS1
RR1/TR
\
\
tRINDH1 tRINS1 tRINH1 tRINDS1
RXINC1
\
,,
DOY1/0 - 7
\
DOC1/0 - 3
\
tAC1
High-Z
tOH1
Valid
Valid
\
RADE2/RX
\
\
RR2/TR
\
\
RXINC2
tRRDH2
tRRS2
Low
tRRH2 t
RRDS2
tRINDH2 tRINS2 tRINH2 tRINDS2
\
tRCLKY
tWRCLLY
\
RCLKY2
\
\
REY2/RY
\
tSREY2
High-Z
\
DOY2/0 - 7
tREDHY2
tRRYDHY2 tRRYSY2 tRRYHY2 tRRYDSY2
tRESY2
tWRCLHY
tACY2
tOHY2
Valid
\
\
RCLKC2
\
\
REC2/RY
\
\
DOC2/0 - 3
tREDHC2
tRRYDHC2 tRRYSC2 tRRYHC2tRRYDSC2
tSREC2
High-Z
Valid
tRCLKC
tWRCLLC
tRESC2
tWRCLHC
tACC2
tOHC2
Valid
Valid
\
Note : The line address is incremented by 1 and the word address is reset to the initialized address.
38/42
¡ Semiconductor
MSM548333
Read Reset (3) Mode
tRCLK
tWRCLL
\
RCLK
\
\
tWRCLH
tRRXDH1 tRRXS1 tRRXH1 tRRXDS1
RADE1/RX
\
\
Low
tRRYDH1 tRRYS1 tRRYH1 tRRYDS1
tREDH1
tRES1
RE1/RY
\
\
tRRDH1 tRRS1 tRRH1 tRRDS1
RR1/TR
\
\
RXINC1
\
,,
DOY1/0 - 7
\
DOC1/0 - 3
\
\
RADE2/RX
tSRE1
High-Z
tRRXDH2
tRRXS2 tRRXH2 t
tRRDH2
tRRS2
\
\
RR2/TR
tAC1
tOH1
Valid
Valid
RRXDS2
Low
tRRH2 t
RRDS2
\
\
RXINC2
\
tRCLKY
tWRCLLY
\
RCLKY2
\
\
REY2/RY
\
tSREY2
High-Z
\
DOY2/0 - 7
tREDHY2
tRRYDHY2 tRRYSY2 tRRYHY2 tRRYDSY2
tRESY2
tWRCLHY
tACY2
tOHY2
Valid
\
\
RCLKC2
\
\
REC2/RY
\
\
DOC2/0 - 3
tREDHC2
tRRYDHC2 tRRYSC2 tRRYHC2tRRYDSC2
tSREC2
High-Z
Valid
tRCLKC
tWRCLLC
tRESC2
tWRCLHC
tACC2
tOHC2
Valid
Valid
\
Note : The line address is reset to 0 and the word address is reset to the initialized address.
39/42
¡ Semiconductor
MSM548333
Read Line Hold (2) Mode
tRCLK
tWRCLL
\
RCLK
\
tWRCLH
tSRE1
\
RADE1/RX
Low
\
\
tRRYDH1
tRRYS1 tRRYH1 t
tREDH1
RRYDS1
tRES1
RE1/RY
\
\
tRRDH1 tRRS1 tRRH1 tRRDS1
RR1/TR
\
\
RXINC1
\
,,
DOY1/0 - 7
\
DOC1/0 - 3
\
tAC1
High-Z
tOH1
Valid
Valid
\
RADE2/RX
\
\
RR2/TR
tRRDH2
tRRS2
Low
tRRH2 t
RRDS2
\
\
RXINC2
\
tRCLKY
tWRCLLY
\
RCLKY2
\
\
REY2/RY
\
tSREY2
High-Z
\
DOY2/0 - 7
tREDHY2
tRRYDHY2 tRRYSY2 tRRYHY2 tRRYDSY2
tRESY2
tWRCLHY
tACY2
tOHY2
Valid
\
\
RCLKC2
\
\
REC2/RY
\
\
DOC2/0 - 3
tREDHC2
tRRYDHC2 tRRYSC2 tRRYHC2tRRYDSC2
tSREC2
High-Z
Valid
tRCLKC
tWRCLLC
tRESC2
tWRCLHC
tACC2
tOHC2
Valid
Valid
\
Note : The line address is held and the word address is reset to the initialized address.
40/42
¡ Semiconductor
MSM548333
Read Address Jump Mode
tRCLK
tWRCLL
\
RCLK
\
\
tWRCLH
tRRXDH1 tRRXS1 tRRXH1 tRRXDS1
RADE1/RX
Low
\
\
tRRYDH1
tRRYS1 tRRYH1 t
tREDH1
RRYDS1
tRES1
RE1/RY
\
\
tRRDH1 tRRS1 tRRH1 tRRDS1
RR1/TR
,,
\
\
tRINDH1 tRINS1 tRINH1 tRINDS1
RXINC1
\
DOY1/0 - 7
\
DOC1/0 - 3
\
\
tSRE1
High-Z
tRRXDH2
tRRXS2 tRRXH2 t
tRRDH2
tRRS2
tAC1
tOH1
Valid
Valid
RRXDS2
RADE2/RX
\
\
Low
tRRH2 t
RRDS2
RR2/TR
\
\
tRINDH2 tRINS2 tRINH2 tRINDS2
RXINC2
\
tRCLKY
tWRCLLY
\
RCLKY2
\
\
tRRYDHY2 tRRYSY2 tRRYHY2 tRRYDSY2
tREDHY2
tRESY2
tWRCLHY
tACY2
tOHY2
REY2/RY
\
tSREY2
High-Z
\
DOY2/0 - 7
Valid
\
\
Valid
tRCLKC
tWRCLLC
RCLKC2
\
\
tRRYDHC2 tRRYSC2 tRRYHC2tRRYDSC2
tREDHC2
tRESC2
tWRCLHC
tACC2
tOHC2
REC2/RY
\
\
DOC2/0 - 3
tSREC2
High-Z
Valid
Valid
\
Note : Both the line address and word address are reset to the initialized addresses.
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¡ Semiconductor
MSM548333
PACKAGE DIMENSIONS
(Unit : mm)
TQFP100-P-1414-0.50-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.55 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
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