OKI MSM5424331TS-AK

FEDS5424331-01
1Semiconductor
MSM5424331
This version: Sep. 2000
222,720-Word × 24-Bit Field Memory
GENERAL DESCRIPTION
The MSM5424331 is an image data processing field memory organized as 222,720 (768 pixels by 290 lines) by 24
bits that can switch between the FIFO mode where the MSM5424331 is used as an ordinary field memory and a
block access mode where the MSM5424331 can easily exchange data with personal computer and the like.
Serial writing in and serial reading from the MSM5424331 are performed line by line. In the FIFO mode, any line
can be selected by specifying their addresses by the Serial Address input. In the Block Access mode, any line or
word address (10 bits) can be set by entering the address through the address multiplexer.
As the MSM5424331 in the Block Access mode can be controlled by RAS and CAS signals, it can easily interface
to the MPU.
The MSM5424331 contains dynamic memory cells. In the FIFO mode, the memory cells are automatically
refreshed by the self refresh control circuit, but in the Block Access mode, the memory cells must be refreshed by
the CAS before RAS Refresh function.
The MSM5424331 is not designed for high end use in such applications as medical systems, professional graphics
systems which require long term picture storage, data storage systems and others.
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MSM5424331
FEATURES
• Switching between FIFO and Block Access modes by the D/F pin
FIFO mode:
Serial write/read operation by line-by-line accessing
Block Access mode: Fast write/read operation on an 8-word basis by the RAS and CAS control
• Organization of 768 × 290 × 24 bits
FIFO mode: Input × 12 or × 24 controlled by L/UWE
Output × 24
Block Access mode: Input × 12 (Two 768 × 290 × 12-bit banks are controlled by L/UWE.)
Output × 12 (Two 768 × 290 × 12-bit banks are controlled by A9.)
• Asynchronous operation
Input and output asynchronous operation enabled only in the FIFO mode Single write or read operation in the
Block Access mode
• Serial Read and Write Cycle times (in both the FIFO mode and the Block Access mode)
Cycle time: 60 ns
Access time: 50 ns
• Operating supply voltage: 2.8 to 3.3 V
• Refresh
FIFO mode:
Self refresh
Block Access mode: by the CAS before RAS refresh function (290 cycles/8 ms)
• Address input
FIFO mode:
Setting random line address by the serial address input
Block Access mode: Setting random address in the address multiplexer by the RAS and CAS control
• Selectable serial address input setting or various address resetting in the FIFO mode
• Package:
70-pin 400 mil plastic TSOP (Type 2) (TSOP(2)70-P-400-0.50-K) (Product: MSM5424331TS-AK)
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MSM5424331
PIN CONFIGURATION (TOP VIEW)
RADE/RX 1
RCLK 2
RE
DO0[DQ0]
DO1[DQ1]
DO2[DQ2]
DO3[DQ3]
DO4[DQ4]
DO5[DQ5]
VSS
DO6[DQ6]
DO7[DQ7]
DO8[DQ8]
DO9[DQ9]
DO10[DQ10]
DO11[DQ11]
VCC
VCC
DO12
DO13
DO14
DO15
DO16
DO17
VCC
DO18
DO19
DO20
DO21
DO22
DO23
WXINC
WR/TR
WADE/RX
WXAD
70 RXAD
69 RR
68 RXINC
67 VSS
66 D/F
65 DIN0[RAS]
64 DIN1[CAS]
63 DIN2[A0]
62 DIN3[A1]
61 DIN4[A2]
60 DIN5[A3]
59 DIN6[A4]
58 DIN7[A5]
57 DIN8[A6]
56 DIN9[A7]
55 DIN10[A8]
54 DIN11[A9]
53 WAIT
52 VSS
51 DIN12
50 DIN13
49 DIN14
48 DIN15
47 DIN16
46 DIN17
45 DIN18
44 DIN19
43 DIN20
42 DIN21
41 DIN22
40 DIN23
39 WCLK
38 LWE
37 UWE
36 IE
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
70-Pin Plastic TSOP (2)
(K Type)
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MSM5424331
Pin Name
FIFO Mode Block Mode
RCLK
FIFO Mode
Address Setting Cycle
Read X Serial Address Strobe
RE
RE
DO0 - 11
DQ0 - 11
DO12 - 23
—
Serial Read/Write Cycle
Serial Read Clock
Block Mode
—
Read Enable
Read Enable
—
Data Output
Data Input/Output
—
Data Output
—
RR
Read Address Reset Mode Enable
—
—
RXINC
Read X Address Increment
—
—
—
—
—
—
Read X Address Input Enable
RADE/RX
Read X Address Reset
RXAD
Read X Serial Address Data
WCLK
Write X Serial Address Strobe
Serial Write Clock
—
LWE
LWE
—
Write Enable
Write Enable
UWE
UWE
—
Write Enable
Write Enable
—
Input Enable
DIN0
RAS
—
Data Input
X Address Strobe
DIN1
CAS
—
Data Input
Y Address Strobe
DIN2 - 11
A0 - A9
—
Data Input
Address Input
—
Data Input
—
Write Data Transfer
—
IE
DIN12 - 23
—
WR/TR
Write Address Reset Mode Enable
WXINC
Write X Address Increment
—
—
WADE/RX
Write X Address Input Enable
Write X Address Reset
—
—
WXAD
Write X Serial Address Data
—
WAIT
D/F
D/F
—
—
Mode Change (D/F = L)
VCC
Power Supply Voltage (3.0 V)
VSS
Ground (0 V)
Note:
—
External Synchronous
Signal
Mode Change (D/F = H)
Same power supply voltage level must be provided to every VCC pin.
Same ground voltage level must be provided to every VSS pin.
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MSM5424331
Memory Cell Array
(760 × 290 × 12)
X-Decoder
X-Decoder
Memory Controller
Mode
Control
WAIT
CAS
RAS
A0-A9
UWE
Control
LWE
Refresh
Control
CAS
BLOCK Mode
Control
RAS
FIFO Mode
WCLK
WR/TR
WADE/RX
WXAD
WXINC
RCLK
RR
RADE/RX
RXAD
RXINC
D/F
RE
DOUT0-11
12
12
L-Bank
Read Register
(760 × 290 × 12)
DOUT Buffer
VBB
Generator
Memory Cell Array
Write Buffer
Write Register
U-Bank
IE
LWE
DIN0-11
DQ0-11
12
Write Buffer
Write Register
DOUT Buffer
Read Register
DIN12-23
12
UWE
IE
12
RE
DOUT12-23
12
DQ0-11
BLOCK DIAGRAM
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MSM5424331
PIN FUNCTION
Read Related
D/F
This signal switches between the FIFO mode and the Block Access mode. The FIFO mode is selected when this
signal is low “L” and the Block Access mode is selected when this signal is high “H”.
RCLK: Read Clock
RCLK is the read control clock input in the FIFO mode. Synchronized with RCLK’s rising edge, serial read access
from read ports is executed when RE is low.
The internal counter for the serial read address is incremented automatically on the rising edge of RCLK. In a read
address set cycle, all the read address bits which were input from RXAD pin are stored into internal address
registers synchronized with RCLK. In this address set cycle, RADE/RX must be held high and RR must be held
low.
In the read address reset cycle, various read address reset modes can be set synchronously with RCLK. These reset
cycles work to replace complicated serial address control which requires many RCLK clocks with a simple reset
cycle control requiring only a single RCLK cycle. It greatly facilitates memory access.
In the Block Access mode, the RCLK signal is ignored.
RE: Read Enable
RE is a read enable clock input in the FIFO mode. RE enables or disables both internal read address pointers and
data-out buffers. When RE is low, the internal read address pointer is incremented synchronously with RCLK.
When RE is high, even if the RCLK is input, the internal read address pointer is not incremented.
The output pins are enabled in the read cycle of the Block Access mode when this pin (RE) is low “L”.
RR: Read Reset
RR is a read reset control input in the FIFO mode. Read address reset modes are defined when RR level is high
according to the “FUNCTION TABLE for read”.
In the Block Access mode, the RR signal is ignored.
RXINC: Read X Address Increment
RXINC is a read X address (or line address) increment control input in the FIFO mode. In the read address reset
cycle, defined by RR high, the X address (or line address) is incremented by 1 when RXINC is pulled high with
RADE/RX low.
In the Block Access mode, the RXINC signal is ignored.
RADE/RX: Read Address Enable/Read X Address Reset Logic Function
RADE/RX is a dual function control input in the FIFO mode. RADE, one of the two functions of RADE/RX, is a
read address enable input. In the read address set cycle, X address (or line address) input from the RXAD pin is
latched into internal read X address register synchronously with RCLK.
RX, the second function of RADE/RX, works as an element to set read X address (or line address) reset mode. In
an address reset mode cycle, defined by RR high, read X address is set to 0 when RADE/RX is pulled high with
RXINC low.
In the Block Access mode, the RADE/RX signal is ignored.
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MSM5424331
RXAD: Read X Address
RXAD is a read X address (or line address) input in the FIFO mode. RXAD specifies the line address. 10 bits of
read X address data are input serially from RXAD.
The bits of an address are fetched starting from the higher order bits. The most significant bit (A9) is ignored.
In the Block Access mode, the RXAD signal is ignored.
DO0-11 (DQ0-11), DO12-23: Data-Outs
In the FIFO mode, these pins are used as serial outputs.
In the Block Access mode, pins DO0 to DO11 (DQ0 to DQ11) are used as input and output pins.
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MSM5424331
Write Related
WCLK: Write Clock
WCLK is a write control clock input in the FIFO mode. Synchronized with WCLK’s rising edge, serial write
access into write ports is executed when LWE or UWE is low.
According to WCLK clocks, the internal counter for the serial address is incremented automatically.
In a write address set cycle, all the write addresses which were input from WXAD are stored into internal address
registers synchronously with WCLK. In this address set cycle, WADE/RX must be held high and WR/TR must be
held low.
In the write address reset cycle, various write address reset modes can be set synchronously with WCLK. These
reset cycles replace complicated serial address control with simple reset cycle control which requires only one
WCLK cycle. It greatly facilitates memory access.
In the Block Access mode, the WCLK signal is ignored.
LWE: Write Enable
LWE is a write enable clock input in the FIFO mode. LWE enables or disables both internal write address pointers
and data-in buffers. When LWE is low, the internal write address pointer is incremented synchronously with
WCLK. When LWE is high, even if WCLK is input, the internal write address pointer is not incremented.
In the Block Access mode, writing in the L-bank is performed when LWE goes low at the falling edge of DIN0
(RAS).
UWE: Write Enable
UWE is a write enable clock input in the FIFO mode. UWE enables or disables both internal write address
pointers and data-in buffers. When UWE is low, the internal write address pointer is incremented synchronously
with WCLK. When UWE is high, even if WCLK is input, the internal write address pointer is not incremented.
In the Block Access mode, writing in the U-bank is performed when UWE goes low at the falling edge of DIN0
(RAS).
DIN0 (RAS): Data-In
DIN0 is serial data-in in the FIFO mode.
In the Block Access mode, this pin serves as RAS. On the falling edge of this signal, the 10-bit row address (A0 to
A9) is fetched.
DIN1 (CAS): Data-In
DIN1 is serial data-in in the FIFO mode.
In the Block Access mode, this pin serves as CAS. On the falling edge of this signal, the 10-bit column address
(A0 to A9) is fetched. This column address becomes a start address in the Block Access mode. When DIN1
(CAS) is toggled while DIN0 (RAS) remains low, the read/write operation in the Block Access mode is enabled.
DIN2-11 (A0-A9): Data-Ins
DIN2-11 are serial data-ins in the FIFO mode.
In the Block Access mode, these pins serve as a row or column address input (A0 to A9). These pins fetch a row
address when DIN0 (RAS) is active or a column address when DIN1 (CAS) is active.
DIN12-23: Data-Ins
DIN12-23 are serial data-ins in the FIFO mode.
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MSM5424331
WR/TR: Write Reset/Write Transfer
WR/TR is a write reset control input in the FIFO mode. Write address reset modes are defined when WR/TR level
is high according to the “FUNCTION TABLE for write”.
When the write operation on a line is terminated, be sure to perform a write transfer operation by WR/TR in order
to store the written data in the write register to corresponding memory cells.
In the Block Access mode, the WR/TR signal is ignored.
WXINC: Write X Address Increment
WXINC is a write X address (or line address) increment control input in the FIFO mode. In the write address reset
cycle, defined by WR/TR high, the write X address (or line address) is incremented by 1 when WXINC is pulled
high with WADE/RX low.
In the Block Access mode, the WXINC signal is ignored.
WADE/RX: Write Address Enable/Write X Address Reset Logic Function
WADE/RX is a dual functional control input in the FIFO mode. WADE, one of the two functions of WADE/RX,
is a write address enable input. In the write address set cycle, X address (or line address) input from the WXAD
pin is latched into internal write X address register synchronously with WCLK.
RX, the second function of WADE/RX, works as an element to set write X address (or line address) reset mode. In
the write address reset cycle, defined by WR/TR high, the write X address is set to 0 when WADE/RX is pulled
high with WXINC low.
In the Block Access mode, the WADE/RX signal is ignored.
WXAD: Write X Address
WXAD is a write X address (or line address) input in the FIFO mode. WXAD specifies line address. 10 bits (0 to 9)
of write X address data are input serially from WXAD. The bits of an address is fetched starting from the higher
order bits. The most significant bit (A9) is ignored.
In the Block Access mode, the WXAD signal is ignored.
IE: Input Enable
IE is an input enable in the FIFO mode which controls the write operation. When IE is high, the input operation is
enabled. When IE is low, the write operation is masked. When LWE and UWE signals are low, and IE low, the
internal serial write address pointer is incremented on the rising edge of WCLK without actual write operations.
This function facilitates picture in picture function in a TV system.
In the Block Access mode, the IE signal is ignored.
WAIT:
This output pin enables interface to the MPU in the Block Access mode.
To cause the MSM5424331 to operate in the Block Access mode, set the D/F pin high and afterward set RAS low.
The output of the WAIT pin goes low while a row or column address is set. Perform the actual read or write
operation in the Block Access mode after the output of the WAIT pin goes high again.
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OPERATION MODE
FIFO Mode
The FIFO mode is set when the D/F pin is set low.
1. Write
1.1 Write operation
Before the write operation begins, X address (or line address) must be input to set the initial bit address for the
following serial write access. When LWE or UWE is low, a set of serial write data on DIN0-11 or DIN1223 is written into write registers attached to the DRAM memory arrays temporarily on the rising edge of
WCLK. The LWE pin controls the write operation of DIN0 to DIN11 (12 bits) and the UWE pin controls the
write operation of DIN12 to DIN23 (12 bits).
Following 24-bit-width serial input data is written into the memory locations in the write register designated
by an internal write address pointer which is advanced by WCLK. This enables continuous serial write on a
line. When write clock WCLK and read clock RCLK are tied together and are controlled by a common clock
or CLK, more than two MSM5424331 can be cascaded directly without any delay devices between the
MSM5424331 because the read timing is delayed by one CLK cycle to the write timing. When the write
operation on a line is terminated, be sure to perform a write transfer operation by WR/TR in order to store the
written data in the write registers to the corresponding memory cells in the DRAM memory arrays.
1.2 Write address pointer increment operation
The write address pointer is incremented synchronously with WCLK when LWE or UWE is low.
Relationship between the LWE, UWE, and IE input levels,
Write Address pointer, and data input status
WCLK Rise
LWE
Internal Write Address Pointer
UWE
IE
L
L
H
Increments both L- and U-banks.
L
H
H
Increments the L-bank only.
H
L
H
Increments the U-bank only.
L
L
L
Increments both L- and U-banks.
L
H
L
Increments the L-bank only.
H
L
L
Increments the U-bank only.
H
H
—
Stopped
Data Input
Inputted
Not Inputted
When LWE or UWE is low and IE is high, the write operation is enabled.
If IE level goes low while WCLK is active, the write operation is halted but the write address pointer will
continue to advance. That is, IE enables a write mask function. When LWE or UWE goes high, the write
address pointer stops without WCLK.
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2. Read
2.1 Read operation
Before the read operation begins, the X address (or line address) must be input for setting initial bit address
for the following serial read access.
When RE is low, a set of serial 24-bit-width read data on DO0-11, DO12-23 pins is read from read registers
attached to DRAM memory arrays on the rising edge of RCLK.
Each access time is specified by the rising edges of RCLK.
2.2 Read address pointer increment operation
The read address pointer is incremented synchronized with RCLK when RE level is low.
The output data will be undefined when the read address pointer is incremented above the last address of one
line.
3.
Initial Address Setting (Write/Read Independent)
Any read operations are prohibited in the read initial address set period. Similarly, any write operations are
prohibited in the write initial address set period. Note that read initial address set and write initial address set
can occur independently. Similarly, read access can be achieved independently from write initial address set
period and write access can be achieved independently from read initial address set cycles.
3.1 Write address setting
WADE/RX enables initial read address inputs. When WADE/RX is high, 10 bits of serial X address (or line
address) are input from higher order bits from WXAD.
The operations above enable selection of specific lines randomly and enables the start of serial write access
synchronized with write clock WCLK. Address for each line must be input between each line access. In other
words, MSM5424331’s write is achieved in a “line by line” manner. Any write operations are prohibited in
the initial write address set periods.
Serial write input enable time tSWE must be kept for starting a serial write just after the initial write address set
period. The most significant bit (A9) is ignored.
3.2 Read address setting
RADE/RX enables initial read address inputs.
When RADE/RX is high, 10 bits of serial X address (or line address) are input from higher order bits from
RXAD.
The operations above enable selection of specific lines randomly and enables the start of serial read access
synchronized with read clocks, RCLK. Address for each line must be input between each line access. In other
words, MSM5424331’s read operation is achieved in “line by line” manner.
Any read operations are prohibited in the initial read address set periods. Serial read operations are prohibited
while RADE/RX is high. Serial read port enable time tSRE must be kept for starting a serial read just after the
initial read address set period. The most significant bit (A9) is ignored.
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4.
MSM5424331
Initial Address Reset Modes (Write/Read Independent)
The initial address reset modes replace complicated read or write initial address settings with simple reset
cycles. Initial address reset modes are selected by RR high during read and WR/TR high during write. As in
normal read or write address settings, any read operations are prohibited in the read address reset cycles.
Similarly, any write operations are prohibited in the initial write address reset cycles. Note that read initial
address reset and write initial address reset can occur independently.
Similarly, read access can be achieved independently from write initial address reset cycles and write access
can be achieved independently from read initial address reset cycles.
Input addresses are stored into address registers which are connected with address counter which controls
address pointer operation. In the serial access operation, the input address into the address registers are kept.
Serial write data input enable time tSWE and serial read port read enable time tSRE must be kept for starting
serial read or write just after the initial read or write address reset cycles.
Refer to the “FUNCTION TABLE” shown later.
4.1 Line hold operation (read only)
By the “Line hold operation” logic which is composed by a combination of control inputs’ level, access is
executed starting from the first word on the current line.
4.2 Original address reset operation
By the “Original address reset” logic, the address counter is set to (0,0). After the reset mode, serial access
starts from the address (0,0) .
The address counter is reset by this reset mode but the address register, which stored input address in the
previous address reset cycle or address set cycle, is not reset. The non-initialized address can be used as a
preset address in “address jump reset” mode.
4.3 Line increment operation
By the “Line increment operation” logic, the X address counter is incremented by one from the current X
address. That is, serial access from the Y = (0) on the next line is enabled.
4.4 Address jump operation
By the “Address jump operation” logic, a jump may be caused to the initialized line address.
Note: During one reset setting cycle, a plurality of resets cannot be set.
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MSM5424331
Block Access Mode
The Block Access mode is configured when the D/F pin is set high.
1.
Write Operation
The MSM5424331 fetches a 10-bit row address form lines A0 to A9 at the falling edge of the DIN0 (RAS)
pin and a 10-bit column address (10 bits long) from the lines at the falling edge of the DIN1 (CAS) pin. With
this operation, a head address can be set arbitrarily.
For a write operation, the LWE or UWE pin must be set low at the falling edge of DIN0 (RAS). The actual
fetching of write data is performed at the falling edge of DIN1 (CAS) after tCASB. The write data is entered
from I/O pins DQ0 to DQ11. The write data is written in the L-bank at the falling edge of DIN0 (RAS) when
LWE is low and UWE is high or in the U-bank when LWE is high and UWE is low. When both LWE and
UWE are both low, data is written in either the L- or U-bank (which is undefined).
Data storage in the memory cell is executed at the rising edge of DIN0 (RAS) after the block write operation
is completed.
When changing a write operation in the FIFO mode to a write operation in the Block Access mode, it is
required to monitor on the WAIT pin whether self refresh in the FIFO mode is completed. Perform the block
write operation after the output of the WAIT pin is high.
The block read operation and FIFO operation are disabled during a block write operation.
2.
Read Operation
The MSM5424331 fetches a 10-bit row address from lines A0 to A9 at the falling edge of the DIN0 (RAS)
pin and a 10-bit column address from the lines at the falling edge of the DIN1 (CAS) pin. With this operation,
a head address can be set randomly.
For a read operation, the LWE or UWE pin must be set high at the falling edge of DIN0 (RAS). Read data is
fetches at the falling edge of DIN1 (CAS) after tCASB. The RE pin should be set low at the falling edge of
DIN1 (CAS).
The read data is output from DQ0 to DQ11 I/O pins. The L- or U-bank from which data is read is selected by
the status of the “A9” bit of the row address. Data is read from the L-bank when the “A9” bit is “0” or from
the U-bank when the “A9” bit is “1”. When changing a read operation in the FIFO mode to a read operation
in the Block Access mode, it is required to monitor on the WAIT pin whether self refresh in the FIFO mode is
completed. Perform the block read operation after the output of the WAIT pin is high.
The block write operation and FIFO operation are disabled during a block read operation.
Refresh
1.
FIFO Mode
In the FIFO mode, the MSM5424331 performs self refresh.
2.
Block Access Mode
In the Block Access mode, self refresh is disabled. Use the CAS before RAS refresh function to refresh.
Addressing from A0 to A9 pins is not required because refresh addresses are automatically given by the
built-in refresh counter.
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MSM5424331
Power On
Power must be applied to RCLK, WCLK, and IE input signals to pull them “Low”, and to RE, LWE, UWE, DIN0
(RAS), and DIN1 (CAS) input signals to pull them “High” before or when the VCC supply is turned on.
After power-up, the device is designed to begin proper operation in at least 200 µs after VCC has reached the
specified voltage (2.8 V). After 200 µs, a minimum of one line dummy write operation and read operation is
required according to the address setting mode, because the read and write address pointers are not valid after
power-up. After that, an operation can be started in the FIFO or Block Access mode.
New Data Read Access in the FIFO Mode
In order to read out “new data”, the delay between the beginning of a write address setting cycle and read address
setting cycle must be at least two lines.
Old Data Read Access in the FIFO Mode
In order to read out “old data”, the delay between the beginning of a write address setting cycle and read address
setting cycle must be more than 0 but less than a half line.
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MSM5424331
FUNCTION TABLE
1.
Write (D/F = “L”)
Mode
Write Transfer
Address Reset Mode
Address Setting Mode
No.
Description of
Operation
WR/TR WXINC WADE/RX
Internal Address Pointer
1
Write Transfer
H
L
L
2
Reset
H
L
H
X address cleared to (0, 0)
3
Line Increment
H
H
L
X address Increment to (Xn
+ 1, 0)
4
Address Jump
H
H
H
X address jump to (Xi, 0)
5
First Address Setting
L
L
H
X address set
RR
RXINC
RADE/RX
Note: For write, Line hold is not provided.
2.
Read (D/F = “L”)
Mode
Address Reset Mode
Address Setting Mode
No
Description of
Operation
Internal Address Pointer
1
Line Hold
H
L
L
X address hold to (Xn, 0)
2
Reset
H
L
H
X address cleared to (0, 0)
3
Line Increment
H
H
L
X address increment to (Xn
+ 1, 0)
4
Address Jump
H
H
H
X address jump to (Xi, 0)
5
First Address Setting
L
L
H
X address set
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MSM5424331
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Symbol
Condition
Rating
Pin Voltage
Parameter
VT
Ta = 25°C, with respect to VSS
–0.5 to 4.2 V
Short Circuit Output Current
lOS
Ta = 25°C
50 mA
Power Dissipation
PD
Ta = 25°C
1W
Operating Temperature
Topr
—
0 to 70°C
Storage Temperature
Tstg
—
–55 to 150°C
Recommended Operating Conditions
(Ta = 0 to 70°C)
Symbol
Min.
Typ.
Max.
Unit
Power Supply Voltage
Parameter
VCC
2.8
3.0
3.3
V
Power Supply Voltage
VSS
0
0
0
V
“H” Input Voltage
VIH
2.1
VCC
VCC + 0.3
V
“L” Input Voltage
VIL
–0.5
0
0.8
V
DC Characteristics
(VCC = 2.8 to 3.3 V, Ta = 0 to 70°C)
Parameter
Symbol
Condition
Min.
“H” Output Voltage
VOH
lOH = –0.1 mA
“L” Output Voltage
VOL
lOL = 0.1 mA
0 < VI < VCC
Max.
Unit
2.2
—
V
—
0.6
V
–10
10
µA
Input Leakage Current
ILI
Output Leakage Current
ILO
0 < VO < VCC
–10
10
µA
Power Supply Current
(During Operation)
ICC1
60 ns cycle
—
90
mA
Power Supply Current
(During Standby)
ICC2
Input pin = VIL/VIH
—
5
mA
Other input voltage 0 V
Capacitance
(Ta = 25°C, f = 1 MHz)
Parameter
Symbol
Max.
Unit
Input Capacitance
CI
7
pF
Output Capacitance
CO
7
pF
16/34
FEDS5424331-01
1Semiconductor
MSM5424331
AC Characteristics (1/3)
FIFO Mode
Measurement Conditions: (VCC = 2.8 to 3.3 V, Ta = 0 to 70°C)
Parameter
Symbol
Min.
Max.
Unit
tWCLK
60
—
ns
WCLK “H” Pulse Width
tWWCLH
28
—
ns
WCLK “L” Pulse Width
tWWCLL
28
—
ns
tWAS
5
—
ns
Serial Write Address Input Active Hold Time
tWAH
7
—
ns
Serial Write Address Input Inactive Hold Time
tWADH
7
—
ns
Serial Write Address Input Inactive Set-up Time
tWADS
7
Write Transfer Instruction Set-up Time
tWTRS
5
—
ns
Write Transfer Instruction Hold Time
tWTRH
7
—
ns
Write Transfer Instruction Inactive Hold Time
tWTDH
7
—
ns
Write Transfer Instruction Inactive Set-up Time
tWTDS
7
—
ns
Serial Write X Address Set-up Time
tWXAS
5
—
ns
Serial Write X Address Hold Time
tWXAH
7
—
ns
Serial Write Data Input Enable Time
tSWE
1500
—
ns
Write Instruction Set-up Time
tWES
5
—
ns
Write Instruction Hold Time
tWEH
7
—
ns
Write Instruction Inactive Hold Time
tWEDH
7
—
ns
Write Instruction Inactive Set-up Time
WCLK Cycle Time
Serial Write Address Input Active Set-up Time
ns
tWEDS
7
—
ns
Input Data Set-up Time
tDS
5
—
ns
Input Data Hold Time
tDH
12
—
ns
WR/TR-WCLK Active Set-up Time
tWRS
5
—
ns
WR/TR-WCLK Active Hold Time
tWRH
7
—
ns
WR/TR-WCLK Inactive Hold Time
tWRDH
7
—
ns
WR/TR-WCLK Inactive Set-up Time
tWRDS
7
—
ns
WXINC-WCLK Active Set-up Time
tWINS
5
—
ns
WXINC-WCLK Active Hold Time
tWlNH
7
—
ns
WXINC-WCLK Inactive Hold Time
tWINDH
7
—
ns
WXINC-WCLK Inactive Set-up Time
tWINDS
7
—
ns
WADE/RX-WCLK Active Set-up Time
tWRXS
5
—
ns
WADE/RX-WCLK Active Hold Time
tWRXH
7
—
ns
WADE/RX-WCLK Inactive Hold Time
tWRXDH
7
—
ns
WADE/RX-WCLK Inactive Set-up Time
tWRXDS
7
—
ns
tIES
5
—
ns
IE Enable Hold Time
tIEH
7
—
ns
IE Disable Set-up Time
tIEDS
7
—
ns
IE Disable Hold Time
tIEDH
7
—
ns
IE Enable Set-up Time
17/34
FEDS5424331-01
1Semiconductor
MSM5424331
AC Characteristics (2/3)
FIFO Mode
Measurement Conditions: (VCC = 2.8 to 3.3 V, Ta = 0 to 70°C)
Parameter
Symbol
Min.
Max.
Unit
tRCLK
60
—
ns
RCLK “H” Pulse Width
tWRCLH
28
—
ns
RCLK “L” Pulse Width
tWRCLL
28
—
ns
tRAS
5
—
ns
Serial Read Address Input Active Hold Time
tRAH
7
—
ns
Serial Read Address Input Inactive Hold Time
tRADH
7
—
ns
Serial Read Address Input Inactive Set-up Time
tRADS
7
—
ns
Serial Read X Address Set-up Time
tRXAS
5
—
ns
Serial Read X Address Hold Time
tRXAH
7
—
ns
RCLK Cycle Time
Serial Read Address Input Active Set-up Time
RE Enable Set-up Time
tRES
5
—
ns
RE Enable Hold Time
tREH
tAC
—
ns
RE Disable Hold Time
tREDH
7
—
ns
RE Disable Set-up Time
tREDS
7
—
ns
Read Port Read Enable Time
tSRE
1500
—
ns
Read Port Read Data Hold Time
tOH
12
—
ns
Access Time from RCLK
tAC
—
50
ns
tDDRE
12
—
ns
RR-RCLK Active Set-up Time
tRRS
5
—
ns
RR-RCLK Active Hold Time
tRRH
7
—
ns
RR-RCLK Inactive Hold Time
tRRDH
7
—
ns
RR-RCLK Inactive Set-up Time
tRRDS
7
—
ns
RXINC-RCLK Active Set-up Time
tRINS
5
—
ns
RXINC-RCLK Active Hold Time
tRINH
7
—
ns
RXINC-RCLK Inactive Hold Time
tRINDH
7
—
ns
RXINC-RCLK Inactive Set-up Time
tRINDS
7
—
ns
RADE/RX-RCLK Active Set-up Time
tRRXS
5
—
ns
RADE/RX-RCLK Active Hold Time
tRRXH
7
—
ns
RADE/RX-RCLK Inactive Set-up Time
tRRXDS
7
—
ns
RADE/RX-RCLK Inactive Hold Time
Read Data Hold Time from RE
tRRXDH
7
—
ns
BLOCK-FRAM Mode Change Set-up Time
tDFS
20
—
ns
BLOCK-FRAM Mode Change Hold Time
tDFH
5
—
ns
tT
2
30
ns
Transition Time (Rise and Fall)
18/34
FEDS5424331-01
1Semiconductor
MSM5424331
AC Characteristics (3/3)
Block Mode
Measurement Conditions: (VCC = 2.8 to 3.3 V, Ta = 0 to 70°C)
Parameter
D/F to RAS Precharge Time
Symbol
tDRP
Min.
60
Max.
—
Unit
ns
D/F to CAS Precharge Time
BLOCK Mode Set-up Time
tDCP
tBS
60
40000
—
—
ns
ns
Row Address Set-up Time
Row Address Hold Time
tASR
tAHR
0
10
—
—
ns
ns
Column Address Set-up Time
Column Address Hold Time
tASC
tAHC
0
15
—
—
ns
ns
RAS to CAS Delay Time
CAS to RAS Precharge Time
tRCD
tCRP
20
10
35
—
ns
ns
CAS Pulse Width
CAS Precharge Time
tCAS
tCP
28
28
—
—
ns
ns
BLOCK Mode Start to CAS Pulse Width
BLOCK Mode Cycle Time
tCASB
tBC
600
60
—
—
ns
ns
RAS Precharge Time (WRITE)
RAS Precharge Time (READ)
tRPW
tRPR
400
60
—
—
ns
ns
Access Time from RAS
Access Time from CAS
tRAC
tBAC
—
—
600
50
ns
ns
Data-in Set-up Time
Data-in Hold Time
tBDS
tBDH
0
15
—
—
ns
ns
Data-in Hold Time (Head Bit)
BLOCK Mode Write Hold Time
tFBDH
tBWH
585
15
—
—
ns
ns
BLOCK Mode Read Hold Time
Write Command Set-up Time
tBRH
tWCS
15
0
—
—
ns
ns
Write Command Hold Time
Read Command Set-up Time
tWCH
tRCS
15
0
—
—
ns
ns
Read Command Hold Time
RAS Hold Time
tRCH
tRSH
15
50
—
—
ns
ns
Output Data Hold Time from RE
Output Data Enable Time from RE
tDDRE
tDERE
12
—
—
40
ns
ns
Output Buffer Turn-off Delay Time
Read Data Hold Time from CAS
tOFF
tBOH
12
15
—
—
ns
ns
Write Command Set-up Time from CAS
Write Command Hold Time from CAS
tCWCS
tCWCH
0
15
—
—
ns
ns
RAS Precharge to CAS Active Time (CAS before RAS)
RAS Pulse Width (CAS before RAS)
tRPC
tRASB
10
400
—
—
ns
ns
CAS before RAS Cycle Time (CAS before RAS)
RAS Precharge Time (CAS before RAS)
tRC
tRP
465
61
—
—
ns
ns
CAS Set-up Time (CAS before RAS)
CAS Hold Time (CAS before RAS)
tCSR
tCHR
10
15
—
—
ns
ns
CAS Precharge Time (CAS before RAS)
Transition Time (Rise and Fall)
tCPN
tT
28
2
—
30
ns
ns
19/34
FEDS5424331-01
1Semiconductor
Note:
Measurement conditions
Input pulse level
Input timing reference level
Output timing reference level
Input rise/fall time
Load condition
MSM5424331
: VIH = 2.1 V, VIL = 0.8 V
: VIH = 2.1 V, VIL = 0.8 V
: VOH = 2.2 V, VOL = 0.6 V
: 2 ns
: CL = 30 pF
20/34
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
tWXAS
tWADH
tWWCLH
tWXAH
tWAS
Valid
A9
t
tWCLK DFH
tWWCLL
tDFS
tWXAH
Valid
A8
tWXAS
tWXAH
Valid
A1
tWXAS
tWXAH
Valid
A0
tWXAS
tWAH tWADS
tSWE
tIEDH
tWEDH
tIES
tWES
tDH
Valid
tDS
tDH
Low
Valid
tDS
Low
1Semiconductor
DIN0 - 11
DIN12 - 23 —
WXINC
WR/TR
IE
UWE
LWE
WXAD
WADE/RX
WCLK
D/F
—
FEDS5424331-01
MSM5424331
TIMING WAVEFORM
(FIFO Mode)
Write Cycle (Address Setting Cycle)
21/34
FEDS5424331-01
1Semiconductor
MSM5424331
(FIFO Mode)
Write Cycle (LWE/UWE Control)
—
D/F
—
Low
(N-2)CYCLE (N-1)CYCLE
N CYCLE
(N+1) CYCLE (N+2) CYCLE
tWCLK
—
WCLK
—
—
WADE/RX
Low
—
—
IE
High
—
—
WR/TR
Low
—
—
WXINC
LWE
UWE
Low
—
tWEH tWEDS tWEDH tWES
—
—
—
DIN0 - 11
DIN12 - 23 —
Valid
D(N-3)
Valid
D(N-2)
Valid
D(N-1)
Valid
D(N)
Valid
D(N+1)
Valid
D(N+2)
Write Cycle (IE Control)
—
D/F
—
Low
(N-2)CYCLE (N-1)CYCLE
N CYCLE
(N+2) CYCLE (N+3) CYCLE
tWCLK
—
WCLK
—
—
WADE/RX
LWE
UWE
Low
—
—
Low
—
—
WR/TR
Low
—
—
WXINC
Low
—
tIEH
tIEDS tIEDH
tIES
—
IE
—
—
DIN0 - 11
DIN12 - 23—
Note:
Valid
D(N-3)
Valid
D(N-2)
Valid
D(N-1)
Valid
D(N)
Valid
D(N+2)
Valid
D(N+3)
In the IE = “L” cycle, the write address pointer is incremented, though no DIN data is written and
the memory data is held.
22/34
FEDS5424331-01
1Semiconductor
MSM5424331
(FIFO Mode)
Write Cycle (Write Transfer)
—
D/F
—
Low
(N-2)CYCLE (N-1)CYCLE
N CYCLE
tWCLK
—
WCLK
—
—
WADE/RX
Low
—
tWTRS
tWTDH
—
WR/TR
tWTRH
tWTDS
—
—
WXINC
LWE
UWE
Low
—
tWEH tWEDS
—
—
DIN0 - 11 —
DIN12 - 23—
Valid
D(N-3)
Valid
D(N-2)
Valid
D(N-1)
Valid
D(N)
Note: When finishing the write operation on a line, be sure to perform a write transfer operation because
the write data on the line is stored in the memory cell.
23/34
DO0 - 23
RXINC
RR
RE
RXAD
RADE/RX
RCLK
D/F
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
tRXAS
tRADH
tWRCLH
tRAS
Valid
B9
tRXAH
tDFH
tRCLK
tWRCLL
tDFS
tRXAH
Valid
B8
tRXAS
tRXAH
Valid
B1
tRXAS
tRXAH
High-Z
Valid
B0
tRXAS
tRAH tRADS
tSRE
tREDH
tAC
tRES
Valid
tOH
Valid
Low
Low
FEDS5424331-01
1Semiconductor
MSM5424331
(FIFO Mode)
Read Cycle (Address Setting Cycle)
24/34
FEDS5424331-01
1Semiconductor
MSM5424331
(FIFO Mode)
Read Cycle (RE Control)
—
D/F
—
Low
(N-2)CYCLE (N-1)CYCLE
N CYCLE
tRCLK
(N+1) CYCLE (N+2) CYCLE
—
RCLK
—
—
RADE/RX
Low
—
—
RR
Low
—
—
RXINC
RE
DO0 - 23
Low
—
tREH
tREDS
tREDH
tRES
—
—
—
—
tDDRE
tOH
Valid
D(N-3)
Valid
D(N-2)
Valid
D(N-1)
Valid
D(N)
tAC
High-Z
Valid
D(N+1)
Valid
D(N+2)
Note: In the cycle of RE = “H”, the read address pointer is not incremented and the output enters the high
impedance state.
25/34
FEDS5424331-01
1Semiconductor
MSM5424331
(FIFO Mode)
Write Reset Mode
tDFS
—
D/F
—
—
WCLK
—
—
WADE/RX
—
—
WR/TR
tDFH
tWCLK
tWWCLL
tWWCLH
tWRXDH tWRXS tWRXH tWRXDS
tWRDH tWRS
tWRH t
WRDS
—
—
WXINC
LWE
UWE
Low
—
tWEDH
—
tWES
tSWE
—
tDS
DIN0 - 11 —
DIN12 - 23—
tDH
Valid
tDS
tDH
Valid
Note: Both the line address and word address are set to 0.
Write Line Increment Mode
tDFS
—
D/F
—
—
WCLK
—
tDFH
tWCLK
tWWCLL
tWWCLH
—
WADE/RX
—
—
WR/TR
—
—
WXINC
LWE
UWE
tWRDH tWRS
tWINDH tWINS
tWRH t
WRDS
tWINH
tWINDS
—
—
—
tWEDH
tWES
tSWE
tDS
DIN0 - 11 —
DIN12 - 23—
Valid
tDH
tDS
tDH
Valid
Note: The line address is incremented by 1 and the word address is set to 0.
26/34
FEDS5424331-01
1Semiconductor
MSM5424331
(FIFO Mode)
Write Address Jump Mode
tDFS
—
D/F
—
—
WCLK
—
—
WADE/RX
—
—
WR/TR
—
—
WXINC
LWE
UWE
tDFH
tWCLK
tWWCLL
tWWCLH
tWRXDH tWRXS tWRXH tWRXDS
tWRDH tWRS
tWRH t
WRDS
tWINDH tWINS
tWINH t
WINDS
—
—
—
DIN0 - 11 —
DIN12 - 23—
tWEDH
tWES
tSWE
tDS
Valid
tDH
tDS
tDH
Valid
Note: The line address is reset to the initialized addresses and the word address is set to 0.
27/34
FEDS5424331-01
1Semiconductor
MSM5424331
(FIFO Mode)
Read Line Hold Mode
tDFS
—
D/F
—
—
RCLK
—
tDFH
tRCLK
tWRCLL
tWRCLH
—
RADE/RX
—
RR
Low
—
tRRDH
tRRS
tRRH
tRRDS
—
—
RXINC
RE
Low
—
tREDH
—
tRES
tSRE
—
tAC
—
High-Z
DO0 - 23
tOH
Valid
—
Valid
Note: The line address is held and the word address is set to 0.
Read Reset Mode
tDFS
—
D/F
—
—
RCLK
—
—
RADE/RX
—
—
tDFH
tRCLK
tWRCLL
tWRCLH
tRRXDH tRRXS
tRRXH t
RRXDS
tRRDH tRRS
tRRH t
RRDS
RR
—
—
RXINC
RE
Low
—
tREDH
—
—
—
DO0 - 23
tRES
tSRE
tOH
tAC
High-Z
—
Valid
Valid
Note: Both the line address and word address are set to 0.
28/34
FEDS5424331-01
1Semiconductor
MSM5424331
(FIFO Mode)
Read Line Increment Mode
tDFS
—
D/F
—
tDFH
tRCLK
tWRCLL
—
RCLK
—
tWRCLH
—
RADE/RX
—
RR
Low
—
—
—
tRRS
tRRH t
RRDS
tRINDH tRINS
tRINH t
RINDS
tRRDH
RXINC
—
RE
tREDH
—
tRES
tSRE
—
tAC
—
tOH
High-Z
DO0 - 23
Valid
—
Valid
Note: The line address is incremented by 1 and the word address is set to 0.
Read Address Jump Mode
tDFS
—
D/F
—
—
RCLK
—
—
RADE/RX
—
—
tDFH
tRCLK
tWRCLL
tWRCLH
tRRXDH tRRXS tRRXH tRRXDS
tRRDH tRRS
tRRH t
RRDS
tRINDH tRINS
tRINH t
RINDS
RR
—
—
RXINC
RE
—
tREDH
—
tSRE
—
—
DO0 - 23
—
tRES
tAC
High-Z
tOH
Valid
Valid
Note: The line address is reset to the initialized addresses and the word address is set to 0.
29/34
tWCS
tRCD
tCASB
tBDS
tCWCS
tWCH
Data-In
n
tFBDH
Column
tAHR
t
tASC AHC
Row
tASR
tCRP
tBS
Open
tDCP
tDRP
Data-In
n+1
Data-In
n+2
Data-In
n+3
Data-In
n+4
Data-In
n+5
Data-In
n+6
tBDH
tCWCH
tRSH
Data-In
n+7
tBDH t
tBDH t
tBDH tBDS tBDH tBDS tBDH t
tBDH tBDS
BDS
BDS
BDS
tBC
tCP tCAS
tBDS
tBWH
Open
tWCS
tRPW
Row
1Semiconductor
Note: Data is written to L-BANK if LWE = “L” during a falling edge of RAS or is written to U-BANK if UWE = “L”. A data write to
L-BANK or to U-BANK is undefined if LWE and UWE = “L”.
DQ0 - 11
UWE
LWE
Address
CAS
RAS
WAIT
D/F
FEDS5424331-01
MSM5424331
(Block Access Mode)
Write Cycle
30/34
Open
tRCS
tRCD
tCASB
tRCH
tDERE
tRAC
Column
tAHR
tASC tAHC
Row
tASR
tCRP
tBS
tBRH
tBOH
Data-Out
n+3
Data-Out
n+2
Data-Out
n+1
Data-Out
n
tBAC
tBOH
tBAC
tBOH
tBAC
tBOH
tBAC
tBC
tCP tCAS
tBOH
Data-Out
n+5
Data-Out
n+4
tBAC
tBOH
tBAC
Data-Out
n+6
tBOH
tBAC
tRSH
tOFF
Data-Out
n+7
tDDRE
Row
Open
tRCS
tRPR
Read data is read from L-BANK if A9 of the Row address is “0” and is read from U-BANK if A9 of the Row address is “1”.
tDCP
tDRP
1Semiconductor
Note:
DQ0 - 11
RE
UWE
LWE
Address
CAS
RAS
WAIT
D/F
FEDS5424331-01
MSM5424331
(Block Access Mode)
Read Cycle
31/34
FEDS5424331-01
1Semiconductor
MSM5424331
(Block Access Mode)
CAS before RAS Refresh Cycle
D/F
High
WAIT
High
tRC
tRP
tRASB
RAS
tRP
tRPC
tCPN
CAS
tCSR
tCHR
RE
tOFF
DQ0 - 11
Open
32/34
FEDS5424331-01
1Semiconductor
MSM5424331
PACKAGE DIMENSIONS
(Unit: mm)
TSOP(2)70-P-400-0.50-K
Mirror finish
5
Package material
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
Epoxy resin
42 alloy
Solder plating (≥5µm)
0.49 TYP.
2/Nov. 13, 1998
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity
absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product
name, package name, pin number, package code and desired mounting conditions (reflow method,
temperature and times).
33/34
FEDS5424331-01
1Semiconductor
MSM5424331
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements.
Before using the product, please make sure that the information being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been chosen as an
explanation for the standard action and performance of the product. When planning to use the product, please
ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.
3.
When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation
resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified
maximum ratings or operation outside the specified operating range.
5.
Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is
granted by us in connection with the use of the product and/or the information and drawings contained herein.
No responsibility is assumed by us for any infringement of a third party’s right which may result from the use
thereof.
6.
The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not authorized for use in any system or application that requires special
or enhanced quality and reliability characteristics nor in any system or application where the failure of such
system or application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.
7.
Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products
and will take appropriate and necessary steps at their own expense for these.
8.
No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2000 Oki Electric Industry Co., Ltd.
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