This version : Dec.1999 Semiconductor MSM56V16800F 2-Bank ´ 1,048,576 Word ´ 8 Bit SYNCHRONOUS DYNAMIC RAM DESCRIPTION The MSM56V16800F is a 2-Bank ´ 1,048,576-word ´ 8 bit Synchronous dynamic RAM, fabricated in OKI’s CMOS silicon-gate process technology. The device operates at 3.3V. The inputs and outputs are LVTTL compatible. FEATURES · Silicon gate , quadruple polysilicon CMOS , 1-transistor memory cell · 2-bank ´ 1,048,576-word ´ 8bit configuration · 3.3V power supply ± 0.3V tolerance · Input : LVTTL compatible · Output : LVTTL compatible · Refresh : 4096 cycles/64 ms · Programmable data transfer mode - CAS Latency (1,2,3) - Burst Length (1,2,4,8,Full page) - Data scramble (sequential , interleave) · CBR auto-refresh, Self-refresh capability · Package: 44-pin 400mil plastic TSOP (Type II) (TSOPII44-P-400-0.80-K) (Product : MSM56V16800F-xxTS-K) xx : indicates speed rank. PRODUCT FAMILY Family Max. Frequency Access Time (Max.) tAC2 tAC3 MSM56V16800F-8A 125MHz 6ns 6ns MSM56V16800F-8 125MHz 9ns 6ns MSM56V16800F-10 100MHz 9ns 9ns 1/30 MSM56V16800F PIN CONFIGRATION (TOP VIEW) VCC 1 DQ1 2 VSS(Q) 3 DQ2 4 VCC(Q) 5 DQ3 6 VSS(Q) 7 DQ4 8 VCC(Q) 9 NC 10 NC 11 WE 12 CAS 13 RAS 14 CS 15 A11 16 A10 17 A0 18 A1 19 A2 20 A3 21 VCC 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 VSS DQ8 VSS(Q) DQ7 VCC(Q) DQ6 VSS(Q) DQ5 VCC(Q) NC NC DQM CLK CKE NC A9 A8 A7 A6 A5 A4 VSS 44-Pin Plastic TSOP (II) (K Type) Pin Name Function Pin Name Function CLK System Clock DQM Data Input/Output Mask CS Chip Select DQi Data Input/Output CKE Clock Enable VCC Power Supply (3.3V) A0–A10 Address VSS Ground (0V) A11 Bank Select Address VCCQ Data Output Power Supply (3.3V) RAS Row Address Strobe VSSQ Data Output Ground (0V) CAS Column Address Strobe NC No Connection WE Write Enable Note: The same power supply voltage must be provided to every VCC pin and VCCQ pin. The same GND voltage level must be provided to every VSS pin and VSSQ pin. 2/30 MSM56V16800F PIN DESCRIPTION CLK Fetches all inputs at the “H” edge. CS Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE, UDQM and LDQM. CKE Masks system clock to deactivate the subsequent CLK operation. If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is deactivated. CKE should be asserted at least one cycle prior to a new command. Address Row & column multiplexed. Row address : RA0 – RA10 Column Address : CA0 – CA8 A11 Slects bank to be activated during row address latch time and selects bank for precharge and read/write during column address latch time. A11=”L” : Bank A, A11=”H” : Bank B RAS CAS Functionality depends on the combination. For details, see the function truth table. WE DQM Masks the read data of two clocks later when DQM is set “H” at the “H” edge of the clock signal. Masks the write data of the same clock when DQM is set “H” at the “H” edge of the clock signal. DQi Data inputs/outputs are multiplexed on the same pin. 3/30 MSM56V16800F BLOCK DIAGRAM CKE CLK CS RAS CAS WE DQM Programing Register Timing Register Latency & Burst Controller I/O Controller Bank Controller A11 Internal Col. Address Counter Input Data Register A0 - A11 Input Buffers 8 98 Column Address Buffers 9 Sense Amplifiers Internal Row Address Counter 12 Row Address Buffers 12 8 Column Decoders Row Decoders Word Drivers 8Mb Memory Cells Row Decoders Word Drivers 8Mb Memory Cells 8 Read Data Register 8 Output Buffers 8 DQ1 - DQ8 Sense Amplifiers Column Decoders 4/30 MSM56V16800F ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (Voltages referenced to VSS) Parameter Symbol Rating Unit VIN, VOUT -0.5 to VCC + 0.5 V VCC, VCCQ -0.5 to 4.6 V Storage Temperature Tstg -55 to 150 °C Power Dissipation PD* 600 mW Short Circuit Current IOS 50 mA Operating Temperature Topr 0 to 70 °C Voltage on Any Pin Relative to VSS VCC Supply Voltage *: Ta = 25°C Recommended Operating Conditions (Voltages referenced to VSS = 0V) Parameter Symbol Min. Typ. Max. Unit VCC, VCCQ 3.0 3.3 3.6 V Input High Voltage VIH 2.0 ¾ VCC + 0.2 V Input Low Voltage VIL -0.3 ¾ 0.8 V Power Supply Voltage Capacitance (VCC = 1.4V, Ta = 25°C, f=1MHz) Parameter Input Capacitance (CLK) Input Capacitance (RAS, CAS, WE, CS, CKE, DQM, A0-A11) Input/Output Capacitance (DQ1-DQ8) Symbol Min. Max. Unit CCLK 2.5 4 pF CIN 2.5 5 pF COUT 4 6.5 pF 5/30 MSM56V16800F DC Characteristics MSM56V16800F Condition Parameter 8A Symbol Bank CKE Output High Voltage VOH ¾ ¾ Output Low Voltage VOL ¾ ¾ Input Leakage Current ILI ¾ Input Leakage Current ILO ¾ Others 8 10 Unit Note Min Max Min Max Min Max IOH = -2.0mA 2.4 ¾ 2.4 ¾ 2.4 ¾ V IOL = 2.0mA ¾ 0.4 ¾ 0.4 ¾ 0.4 V ¾ ¾ -10 10 -10 10 -10 10 µA ¾ ¾ -10 10 -10 10 -10 10 µA ¾ 70 ¾ 70 ¾ 60 mA 1,2 ¾ 105 ¾ 105 ¾ 85 mA 1,2 Both Banks CKE³VIH tCC=min. Precharge ¾ 35 ¾ 35 ¾ 30 mA 3 Average power supply current ICC3S Both Banks CKE£VIL tCC=min. Active (Clock Suspension) ¾ 3 ¾ 3 ¾ 3 mA 2 Average power supply current (Active Standby ) ICC3 One Bank Active CKE³VIH tCC=min. ¾ 40 ¾ 40 ¾ 35 mA 3 Power supply current (Burst) ICC4 Both Banks CKE³VIH tCC=min. Active ¾ 95 ¾ 90 ¾ 80 mA 1,2 Power supply current (Auto-Refresh) ICC5 One Bank Active t =min. CKE³VIH CC tRC=min. ¾ 70 ¾ 70 ¾ 60 mA 2 Average power supply current (Self-Refresh) ICC6 Both Banks CKE£VIL tCC=min. Precharge ¾ 2 ¾ 2 ¾ 2 mA Average power supply current (Power Down) ICC7 Both Banks CKE£VIL tCC=min. Precharge ¾ 2 ¾ 2 ¾ 2 mA ICC1 Average power supply current (Operating) Power supply current (Standby) Notes: 1. 2. 3. One Bank Active tCC=min. CKE³VIH tRC=min. No Burst tCC=min. t =min. Both Banks ICC1D CKE³VIH RC Active tRRD=min. No Burst ICC2 Measured with outputs open. The address and data can be changed once or left unchanged during one cycle. The address and data can be changed once or left unchanged during two cycles. 6/30 MSM56V16800F Mode Set Address Keys CAS Latency Burst Type Burst Length A6 A5 A4 CL A3 BT A2 A1 A0 BT = 0 BT = 1 0 0 0 Reserved 0 Sequential 0 0 0 1 1 0 0 1 1 1 Interleave 0 0 1 2 2 0 1 0 2 0 1 0 4 4 0 1 1 3 0 1 1 8 8 1 0 0 Reserved 1 0 0 Reserved Reserved 1 0 1 Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved 1 1 0 Reserved Reserved 1 1 1 Reserved 1 1 1 Full Page Reserved Notes: A7, A8, A9, A10 and A11 should stay “L” during mode set cycle. POWER ON SEQUENCE 1. 2. 3. 4. 5. With inputs in NOP state, turn on the power supply and start the system clock. After the VCC voltage has reached the specified level, pause for 200ms or more with the input kept in NOP state. Issue the precharge all bank command. Apply a CBR auto-refresh eight or more times. Enter the mode register setting command. 7/30 MSM56V16800F AC Characteristic (1/2) Note 1,2 MSM56V16800F Parameter Access Time from Clock 8 10 Unit Note Min. Max. Min. Max. Min. Max. 8 ¾ 8 ¾ 10 ¾ ns 10 ¾ 12 ¾ 15 ¾ ns CL = 1 20 ¾ 24 ¾ 30 ¾ ns CL = 3 ¾ 6 ¾ 6 ¾ 9 ns 3,4 ¾ 6 ¾ 9 ¾ 9 ns 3,4 ¾ 16 ¾ 22 ¾ 27 ns 3,4 CL = 3 Clock Cycles Time 8A Symbol CL = 2 CL = 2 tCC tAC CL = 1 Clock High Pulse Time tCH 3 ¾ 3 ¾ 3 ¾ ns 4 Clock Low Pulse Time tCL 3 ¾ 3 ¾ 3 ¾ ns 4 Input Setup Time tSI 2 ¾ 2 ¾ 3 ¾ ns Input Hold Time tHI 1 ¾ 1 ¾ 1 ¾ ns Output Low Impedance Time from Clock tOLZ 3 ¾ 3 ¾ 3 Output High Impedance Time from Clock tOHZ ¾ 9 ¾ 9 ¾ 8 ns Output Hold from Clock tOH 3 ¾ 3 ¾ 3 ¾ ns RAS Cycle Time tRC 70 ¾ 70 ¾ 90 ¾ ns RAS Precharge Time tRP 20 ¾ 20 ¾ 30 ¾ ns 5 5 ns 5 RAS Active Time tRAS 48 10 48 10 60 10 ns RAS to CAS Delay Time tRCD 20 ¾ 20 ¾ 30 ¾ ns Write Recovery Time tWR 8 ¾ 8 ¾ 15 ¾ ns RAS to RAS Bank Active Delay Time tRRD 20 ¾ 20 ¾ 20 ¾ ns Refresh Time tREF ¾ 64 ¾ 64 ¾ 64 ms Power-down Exit setup Time tPDE tSI +1CLK ¾ tSI +1CLK ¾ tSI +1CLK ¾ ns tT ¾ 3 ¾ 3 ¾ 3 ns Input Level Transition Time CAS to CAS Delay Time(Min.) lCCD 1 1 1 Cycle Clock Disable Time from CKE lCKE 1 1 1 Cycle Data Output High Impedance Time from UDQM, LDQM lDOZ 2 2 2 Cycle Data Input Mask Time from UDQM, LDQM lDOD 0 0 0 Cycle Data Input Mask Time from Write Command lDWD 0 0 0 Cycle 3 8/30 MSM56V16800F AC Characteristic (2/2) Note 1,2 MSM56V16800F Parameter 8A Symbol Min. 8 Max Min. 10 Max. Min. Unit Max. Data Output High Impedance Time from Precharge Command lROH CL CL CL Cycle Active Command Input Time from Mode Register Set Command Input (Min.) lMRD 3 3 3 Cycle Write Command Input Time from Output lOWD 2 2 2 Cycle Notes: 1) 2) 3) Note AC measurements assume that tT = 1ns. The reference level for timing of input signals is 1.4V. Output load. Z=50W Output 50pF (External Load) 4) 5) The access time is defined at 1.5V. If tT is longer than 1ns, then the reference level for timing of input signals is VIH and VIL. 9/30 MSM56V16800F TIMING WAVEFORM · Read & Write Cycle (Same Bank) @CAS Latency= =2, Burst Length= =4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK tRC CKE CS tRP RAS tRCD CAS ADDR Ra C a0 Rb C b0 A11 A10 Ra Rb tOH Q a0 DQ tAC Q a1 Q a2 Q a3 D b0 D b1 tOHZ D b2 D b3 tWR WE DQM Row Active Read Command Precharge Command Row Active Write Command Precharge Command 10/30 MSM56V16800F · Single Bit Read-Write-Read Cycle (Same Page) @CAS Latency= =2, Burst Length= =4 tCH 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK tCC tCL High CKE CS tHI tSI RAS tSI tHI ICCD CAS tSI ADDR Ra tSI tSI Ca tHI A11 BS A10 Ra Cb Cc BS BS tHI BS tAC tOHZ Qa DQ tOLZ BS tHI Db Qc tSI tOH lOWD tHI WE tSI DQM Row Active Read Command Write Command Precharge Command Read Command 11/30 MSM56V16800F *Notes : 1. When CS is set ”High” at a clock transition from “Low” to ”High”, all inputs except CKE, UDQM and LDQM are invalid. 2. When issuing an active, read or write command, the bank is selected by A11. A11 Active, read or write 0 Bank A 1 Bank B 3. The auto precharge function is enabled or disabled by the A10 input when the read or write command is issued. A10 A11 Operation 0 0 After the end of burst, bank A holds the idle status. 1 0 After the end of burst, bank A is precharged automatically. 0 1 After the end of burst, bank B holds the idle status. 1 1 After the end of burst, bank B is precharged automatically. 4. When issuing a precharge command, the bank to be precharged is selected by the A10 and A11 inputs. A10 A11 Operation 0 0 Bank A is precharged. 0 1 Bank B is precharged. 1 X Both banks A and B are precharged. 5. The input data and the write command are latched by the same clock (Write latency = 0). 6. The output is forced to high impedance by (1CLK+tOHZ) after UDQM, LDQM entry. 12/30 MSM56V16800F · Page Read & Write Cycle (Same Bank) @CAS Latency= =2, Burst Length= =4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE CS Bank A Active RAS CAS ICCD ADDR C a0 C b0 C c0 C d0 A11 A10 DQ Q a0 Q a1 Q b0 Q b1 D c0 lOWD D c1 D d0 tWR *Note 2 WE *Note 1 DQM Read Command Read Command *Notes: Write Command Precharge Command Write Command 1. To write data before a burst read ends, DQM should be asserted three cycles prior to the write command to avoid bus contention. 2. To assert row precharge before a burst write ends, wait tWR after the last write data input. Input data during the precharge input cycle will be masked internally. 13/30 MSM56V16800F · Read & Write Cycle with Auto Precharge @ Burst Length= =4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE CS RAS tRRD CAS ADDR Ra Rb Ra Rb Ca Cb A11 A10 WE CAS Latency=1 Q a0 DQ Q a1 Q a2 Q a3 D b0 D b1 D b2 D b3 D b0 D b1 D b2 D b3 D b0 D b1 D b2 D b3 A-Bank Precharge Start DQM CAS Latency=2 Q a0 DQ Q a1 Q a2 Q a3 A-Bank Precharge Start DQM CAS Latency=3 Q a0 DQ Q a1 Q a2 Q a3 tWR A-Bank Precharge Start DQM Row Active (A-Bank) Row Active (B-Bank) A Bank Read with Auto Precharge B Bank Write with Auto Precharge B Bank Precharge Start Point 14/30 MSM56V16800F x Bank Interleave Random Row Read Cycle @CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE CS tRC RAS tRRD CAS ADDR R Aa C Aa R Bb C Bb R Ac C Ac A11 A10 R Aa R Bb R Ac Q Aa0 Q Aa1 Q Aa2 Q Aa3 DQ Q Bb1 Q Bb2 Q Bb3 Q Bb4 Q Ac0 Q Ac1 Q Ac2 Q Ac3 WE DQM Row Active (A-Bank) Read Command (A-Bank) Row Active (B-Bank) Read Command (B-Bank) Precharge Command (A-Bank) Row Active (A-Bank) Read Command (A-Bank) Precharge Command (B-Bank) 15/30 MSM56V16800F x Bank Interleave Random Row Write Cycle @CAS Latency = 2, Burst Length =4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE CS RAS CAS ADDR R Aa C Aa R Bb C Bb R Ac C Ac A11 A10 R Aa R Bb R Ac D Aa0 D Aa1 D Aa2 D Aa3 D Bb0 D Bb1 D Bb2 D Bb3 DQ D Ac0 D Ac1 WE DQM Row Active (A-Bank) Precharge Command Write Command (A-Bank) Row Active (B-Bank) Write Command (A-Bank) (B-Bank) Row Active (A-Bank) Write Command (A-Bank) Precharge Command (B-Bank) Precharge Command (A-Bank) 16/30 MSM56V16800F x Bank Interleave Page Read Cycle @CAS Latency = 2, Burst Length =4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE *Note 1 CS RAS CAS ADDR R Aa C Aa R Bb C Bb C Ac C Bd C Ae A11 A10 R Aa R Bb Q Aa0 Q Aa1 Q Aa2 Q Aa3 Q Bb0 Q Bb1 Q Bb2 Q Bb3 Q Ac0 Q Ac1 Q Bd0 Q Bd1 Q Ae0 Q Ae1 DQ IROH WE DQM Row Active (A-Bank) Row Active (B-Bank) Read Command (A-Bank) Note: Read Command (B-Bank) Read Command (B-Bank) Read Command (A-Bank) Precharge Command (A-Bank) Read Command (A-Bank) 1. CS is ignored when RAS, CAS and WE are high at the same cycle. 17/30 MSM56V16800F · Bank Interleave Page Write Cycle @CAS Latency = 2, Burst Length= =4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE CS RAS CAS ADDR R Aa C Aa R Bb C Bb C Ac C Bd A11 A10 DQ R Aa R Ab D Aa0 D Aa1 D Aa2 D Aa3 D Bb0 D Bb1 D Bb2 D Bb3 D Ac0 D Ac1 D Bd0 WE DQM Row Active Row Active (A-Bank) Write Command (B-Bank) Write Command (B-Bank) (A-Bank) Write Command Write Command (B-Bank) Precharge Command (A-Bank) (Both Bank) 18/30 MSM56V16800F · Bank Interleave Random Row Read/Write Cycle @CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE CS RAS CAS ADDR R Aa C Aa R Bb C Bb R Ac C Ac A11 A10 R Aa R Bb Q Aa0 Q Aa1 Q Aa2 Q Aa3 DQ R Ac Q Bb0 Q Bb1 Q Bb2 Q Bb3 Q Ac0 Q Ac1 Q Ac2 Q Ac3 WE DQM Row Active (A-Bank) Row Active (B-Bank) Read Command (A-Bank) Precharge Command (A-Bank) Write Command (B-Bank) Read Command (A-Bank) Row Active (A-Bank) 19/30 MSM56V16800F · Bank Interleave Page Read/Write Cycle @CAS Latency = 2, Burst Length =4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE CS RAS CAS ADDR C Aa0 C Bb0 C Ac0 A11 A10 Q Aa0 Q Aa1 Q Aa2 Q Aa3 DQ D Bb0 D Bb1 D Bb2 D Bb3 Q Ac0 Q Ac1 Q Ac2 Q Ac3 WE DQM Read Command (A-Bank) Write Command (B-Bank) Read Command (A-Bank) 20/30 MSM56V16800F · Clock Suspension & DQM Operation Cycle @CAS Latency = 2, Burst Length =4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK *Note 1 *Note 1 CKE CS RAS CAS ADDR Ra Ca Cb Cc A11 A10 Ra Q a0 DQ1-8 Q a1 Q a2 *Note 2 Q b0 Q b1 D c0 *Note 3 tOHZ tOHZ D c2 WE DQM Row Active CLOCK Suspension Read Command Read DQM *Notes: Write DQM Read Command Read DQM Write Command Write DQM CLOCK Suspension 1. When Clock Suspension is asserted, the next clock cycle is ignored. 2. When DQM are asserted, the read data after two clock cycles is masked. 3. When DQM are asserted, the write data in the same clock cycle is masked. 21/30 MSM56V16800F · Read to Write Cycle (Same Bank) @CAS Latency = 2, Burst Length =4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE CS *Note 1 RAS tRCD CAS ADDR Ra C a0 C b0 A11 A10 Ra D a0 DQ D b0 D b1 D b2 D b3 tWR WE DQM Precharge Command Row Active Read Command *Note: Write Command 1. In Case CAS latency is 3, READ can be interrupted by WRITE. The minimum command interval is [burst length + 1] cycles. DQM must be high at least 3 clocks prior to the write command. 22/30 MSM56V16800F x Read Interruption by Precharge Command @Burst Length =8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE CS RAS CAS Ra ADDR Ca A11 Ra A10 WE óNote 1 CAS Latency=1 Q a0 DQ Q a1 Q a2 Q a3 Q a4 Q a5 lROH DQM óNote 2 CAS Latency=2 Q a0 DQ Q a1 Q a2 Q a3 Q a4 Q a5 lROH DQM óNote 3 CAS Latency=3 Q a0 DQ Q a1 Q a2 Q a3 Q a4 Q a5 lROH DQM Row Active óNotes: 1. 2. 3. Read Command Precharge Command When the CAS latency = 1, and if row precharge is asserted before a burst read ends, then the read data will not output after the next clock cycle of the precharge command. When the CAS latency = 2, and if row precharge is asserted before burst read ends, then the read data will not output after the second clock cycle of the precharge command. When the CAS latency = 3, and if row precharge is asserted before burst read ends, then the read data will not output after the second clock cycle of the precharge command. 56263 MSM56V16800F x Burst Stop Command @Burst Length =8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE CS RAS CAS ADDR Ca Cb A11 A10 WE CAS Latency=1 Q a0 DQ Q a1 Q a2 Q a3 Q a4 Q a0 Q a1 Q a2 Q a3 Q a4 Q a0 Q a1 Q a2 Q a3 Q b0 Q b1 Q b2 Q b3 Q b4 Q b0 Q b1 Q b2 Q b3 Q b4 Q b0 Q b1 Q b2 Q b3 Q b4 DQM CAS Latency=2 DQ DQM CAS Latency=3 DQ Q a4 DQM Read Command Burst Stop Command Write Command Burst Stop Command 57263 MSM56V16800F x Power Down Mode @CAS Latency = 2, Burst Length =4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK tSI CKE tPDE óNote 2 óNote 1 tSI tSI tREF (min.) CS RAS CAS Ra ADDR Ca A11 Ra A10 Q a0 DQ Q a1 Q a2 WE DQM Power-down Entry Row Active Power-down Exit óNotes: Clock Suspension Entry Read Command Clock Suspension Exit Precharge Command 1. When both banks are in precharge state, and if CKE is set low, then the MSM56V16800F enters power-down mode and maintains the mode while CKE is low. 2. To release the circuit from power-down mode, CKE has to be set high for longer than t PDE (tSI + 1CLK). 58263 MSM56V16800F x Self Refresh Cycle 0 1 2 CLK tRC CKE tSI CS RAS CAS ADDR Ra A11 BS A10 Ra DQ Hi - Z WE DQM Self Refresh Entry Self Refresh Exit Row Active 59263 MSM56V16800F x x Mode Register Set Cycle 0 1 2 3 4 5 6 Auto Refresh Cycle 0 1 2 3 4 5 6 7 8 9 10 11 CLK High CKE High CS lMRD tRC RAS CAS ADDR Key DQ Ra Hi - Z Hi - Z WE DQM MRS New Command Auto Refresh Auto Refresh 5:263 MSM56V16800F FUNCTION TRUTH TABLE (Table 1) (1/2) Current State 1 Idle Row Active Read Write Read with Auto Precharge Write with Auto Precharge CS RAS CAS WE BA ADDR H X X X X X Action NOP L H H H X X NOP L H H L BA X ILLEGAL 2 L H L X BA CA ILLEGAL 2 L L H H BA RA Row Active L L H L BA A10 NOP 4 L L L H X X Auto-Refresh or Self-Refresh 5 L L L L L OP Code H X X X X X Mode Register Write NOP L H H X X X NOP L H L H BA CA, A10 Read L H L L BA CA, A10 L L H H BA RA L L H L BA A10 Precharge L L L X X X ILLEGAL Write ILLEGAL 2 H X X X X X NOP (Continue Row Active after Burst ends) L H H H X X NOP (Continue Row Active after Burst ends) L H H L X X L H L H BA CA, A10 Term Burst, start new Burst Read 3 L H L L BA CA, A10 Term Burst, start new Burst Write 3 L L H H BA RA L L H L BA A10 L L L X X X Term Burst --> Row Active ILLEGAL 2 Term Burst, execute Row Precharge ILLEGAL H X X X X X NOP (Continue Row Active after Burst ends) L H H H X X NOP (Continue Row Active after Burst ends) L H H L X X Term Burst --> Row Active L H L H BA CA, A10 Term Burst, start new Burst Read 3 L H L L BA CA, A10 Term Burst, start new Burst Write 3 L L H H BA RA ILLEGAL 2 L L H L BA A10 Term Burst, execute Row Precharge 3 L L L X X X ILLEGAL H X X X X X NOP (Continue Burst to End and enter Row Precharge) L H H H X X NOP (Continue Burst to End and enter Row Precharge) L H H L BA X ILLEGAL 2 L H L H BA CA, A10 ILLEGAL 2 L H L L X X L L H X BA RA, A10 L L L X X X ILLEGAL ILLEGAL 2 ILLEGAL H X X X X X NOP (Continue Burst to End and enter Row Precharge) L H H H X X NOP (Continue Burst to End and enter Row Precharge) L H H L BA X ILLEGAL 2 L H L H BA CA, A10 ILLEGAL 2 L H L L X X L L H X BA RA, A10 L L L X X X ILLEGAL ILLEGAL 2 ILLEGAL 28/30 MSM56V16800F FUNCTION TRUTH TABLE (Table 1) (2/2) Current State 1 Precharge Write Recovery Row Active Refresh Mode Register Access CS RAS CAS WE BA ADDR H X X X X X NOP --> Idle after tRP Action L H H H X X NOP --> Idle after tRP L H H L BA X ILLEGAL 2 L H L X BA CA ILLEGAL 2 L L H H BA RA ILLEGAL 2 L L H L BA A10 NOP 4 L L L X X X ILLEGAL H X X X X X NOP L H H H X X NOP L H H L BA X ILLEGAL 2 L H L X BA CA ILLEGAL 2 L L H H BA RA ILLEGAL 2 L L H L BA A10 ILLEGAL 2 L L L X X X ILLEGAL H X X X X X NOP --> Row Active after tRCD L H H H X X NOP --> Row Active after tRCD L H H L BA X ILLEGAL 2 L H L X BA CA ILLEGAL 2 L L H H BA RA ILLEGAL 2 L L H L BA A10 ILLEGAL 2 L L L X X X ILLEGAL H X X X X X NOP --> Idle after tRC L H H X X X NOP --> Idle after tRC L H L X X X ILLEGAL L L H X X X ILLEGAL L L L X X X ILLEGAL H X X X X X NOP L H H H X X NOP L H H L X X ILLEGAL L H L X X X ILLEGAL L L X X X X ILLEGAL ABBREVIATIONS RA = Row Address CA = Column Address BA = Bank Address AP = Auto Precharge NOP = No OPeration command *Notes : 1. All inputs are enabled when CKE is set high for at least 1 cycle prior to the inputs. 2. Illegal to bank in specified state, but may be legal in some cases depending on the state of bank selection. 3. Satisfy the timing of lCCD and tWR to prevent bus contention. 4. NOP to bank precharging or in idle state. Precharges activated bank by BA or A10. 5. Illegal if any bank is not idle. 29/30 MSM56V16800F FUNCTION TRUTH TABLE for CKE (Table 2) Current State (n) Self Refresh Power Down All Banks Idle 6 (ABI) Any State Other than Listed Above CKEn-1 CKEn CS RAS CAS WE ADDR H X X X X X X INVALID Action L H H X X X X Exit Self Refresh --> ABI L H L H H H X Exit Self Refresh --> ABI L H L H H L X ILLEGAL L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X X NOP (Maintain Self Refresh) H X X X X X X INVALID L H H X X X X Exit Power Down --> ABI L H L H H H X Exit Power Down --> ABI L H L H H L X ILLEGAL L H L H L X X ILLEGAL L H L L X X X ILLEGAL 6 L L X X X X X NOP (Continue power down mode) H H X X X X X Refer to Table 1 H L H X X X X Enter Power Down H L L H H H X Enter Power Down H L L H H L X ILLEGAL H L L H L X X ILLEGAL H L L L H L X ILLEGAL H L L L L H X Enter Self Refresh H L L L L L X ILLEGAL L L X X X X X NOP H H X X X X X Refer to Operations in Table 1 H L X X X X X Begin Clock Suspend Next Cycle L H X X X X X Enable Clock of Next Cycle L L X X X X X Continue Clock Suspension *Notes : 6. Power-down and self-refresh can be entered only when all the banks are in an idle state. 30/30