E2E1017-27-Y3 ¡ Semiconductor MSM65X227 ¡ Semiconductor This version: Jan. 1998 MSM65X227 Previous version: Nov. 1996 8-Bit Microcontroller (with 4K-Byte EEPROM) GENERAL DESCRIPTION The MSM65X227 is a high-performance, 8-bit microcontroller that employs OKI original CPU core, the nX-8/50. The MSM65X227 includes a minimum instruction execution time of 667 ns (@6 MHz) that enables high-speed processing. It has 60K-byte program memory space, internal 4K bytes of EEPROM (general memory space), 1K-byte data memory (384 bytes for local memory space and 640 bytes for general memory space), a timer, a serial port and an A/D converter. The MSM65X227, which has no internal program ROM, is provided with the special time-division data/address bus that can be connected to an extrernal program ROM. FEATURES • Operating range Operating frequency Operating voltage Operating temperature • Memory space Program memory space Internal EEPROM Internal data memory • Minimum instruction execution time • Ample instruction set : : : : : : : : : 0 to 6MHz 4.5 to 5.5V – 40 to +85°C 128K bytes 60K bytes 4K bytes 1K bytes 667ns @ 6MHz 81 basic instructions 8/16-bit operation instructions Bit manipulation instructions Complex function instructions • Ample addressing modes • Timer : • Counter • Serial port : : 8-bit auto-reload timer ¥ 2 (one is shared with the baud rate generator) Watchdog timer ¥ 1 Time base counter ¥ 1 Serial port ¥ 1 (UART/clock synchronous system) 8 bits ¥ 4 channels 7 ports, 48 bits 5 ports ¥ 8 bits, 1 port ¥ 4 bits 1 port ¥ 4 bits 2 10 • A/D converter : • I/O port : Input-output port : Input-port : • External interrupts : • Interrupt sources : • Package: 100-pin plastic TQFP (TQFP100-P-1414-0.50-K) (Product name: MSM65X227TS-K) 1/18 OSC0 OSC1 RESET HSTOP* XT XT WR ALE CPU CORE EXWR INST. DEC. VDD GND A8-16 RD RAM (640 bytes) OSC CONT. AD0-7 RAM (384 bytes) GMAR PC ALU T/C BUS CONT. IR ¡ Semiconductor EXT.MEM. CONT. BLOCK DIAGRAM EEPROM (4K bytes) TBC WDT WUP TIMER 8-bit TIMERx2 AR BR PSW 8-bit A/D C ¥ 4ch SP LMAR I/O PORT P1 P2 P3 SIO TXD* RXD* INTERRUPT CONT. INT0* INT1* * is secondary function of each port. **P5 is a 4-bit input-output port. ***P6 is a 4-bit input only port. P4 P5** P6*** MSM65X227 2/18 AI0*- AI3* AGND VRL VRH AVDD P0 T1OUT* T0CK* GATE* ¡ Semiconductor MSM65X227 NC 1 NC 2 P0.3 3 P0.4 4 P0.5 5 P0.6 6 P0.7 7 XT 8 NC 9 XT 10 GND 11 OSC0 12 NC 13 OSC1 14 ALE 15 NC 16 76 A16 77 P2.0 78 P2.1 79 P2.2 80 P2.3 81 NC 82 P2.4 83 P2.5 84 P2.6 85 NC 86 P2.7 87 P1.0 88 NC 89 P1.1 90 P1.2 91 P1.3 92 NC 93 P1.4 94 P1.5 95 P1.6 96 P1.7 97 NC 98 P0.0 99 P0.1 100 P0.2 PIN CONFIGURATION (TOP VIEW) 75 NC 74 A15 73 A14 72 A13 71 NC 70 A12 69 A11 68 A10 67 A9 66 A8 65 VDD 64 P3.7 63 NC 62 P3.6 61 P3.5 60 NC 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC P4.0 P4.1 P4.2 P4.3 NC P4.4 NC P4.5 P4.6 P4.7 AD0 AD1 AD2 NC AD3 AD4 NC 32 VRH P5.3 51 NC 31 52 AD5 P6.3 25 P5.2 53 AD6 P6.2 24 30 54 AD7 P6.1 23 P5.1 55 P3.0 P6.0 22 29 56 P3.1 AGND 21 P5.0 57 P3.2 EXWR 20 AVDD 28 58 P3.3 RESET 19 26 59 P3.4 WR 18 VRL 27 RD 17 NC: No-connection Pin 100-Pin Plastic TQFP 3/18 ¡ Semiconductor MSM65X227 PIN DESCRIPTION Basic Functions Function Symbol Type Power Supply VDD GND — — Digital power supply (5V) Digital ground AVDD — Analog power supply (5V) AGND — Analog ground VRH — Analog reference voltage (5V) Analog reference voltage (ground) Oscillation Description VRL — OSC0 I CPU oscillation input pin OSC1 O CPU oscillation output pin XT I CPU start-up timer oscillation input pin XT O CPU start-up timer oscillation output pin RESET I System reset input: When this pin goes into the "L" state, the internal state is initialized and the execution of an instruction starts from address 0040H. The input is pulled up to VDD with an internal pull-up resistor. EXWR I External write enable pin : Sampled at a system reset and enables external EEPROM write and read during the "L" level. RD O Read signal at external memory access: Read cycle in memory is indicated when the signal goes into the "L" level during external memory access. WR O Write-signal during external memory access: Write cycle in memory is indicated when the signal goes into the "L" level during external memory access. O Address latch signal at external memory access: The MSM65X227 uses a time dividing address/data bus. This signal uses the lower 8 bits of the address as a strobe signal to latch the external latch circuit. AD0 - AD7 I/O 8-bit address/data bus: Address/data bus performs lower 8-bit address output, instruction fetch or data read/write along with the ALE, RD and WR pins. A8 - A16 O 9-bit address bus: Address bus for the upper 9 bits. Control ALE 4/18 ¡ Semiconductor MSM65X227 Basic Functions (Continued) Function Symbol Type Description I/O 8-bit input-output port (Port 0): Users can specify input or output at each bit with the port 0 direction register (P0DIR). I/O 8-bit input-output port (Port 1): Users can specify input or output at each bit with the port 1 direction register (P1DIR). In the input mode, ports can be set as inputs with a pull-up resistor at each bit. A secondary function shown in the next table is assigned at the P1.7 pin. I/O 8-bit input-output port ( Port 2): Users can specify input or output at each bit by the port 2 direction register (P2DIR). Each pin of Port 2 is assigned a secondary function shown in the next table. P3.0 - P3.7 I/O 8-bit input-output port (Port 3): Users can specify input or output at each bit by the port 3 direction register (P3DIR). A secondary function shown in the next table is assigned at the P3.0 pin. P4.0 - P4.7 I/O 8-bit input-output port (Port 4): Users can specify input or output at each bit with the port 4 direction register (P4DIR). P5.0 - P5.3 I/O 4-bit input-output port (Port 5): Users can specify input or output at each bit with the port 5 direction register (P5DIR). P6.0 - P6.3 I P0.0 - P0.7 P1.0 - P1.7 P2.0 - P2.7 Port 4-bit input port (Port 6): Each pin of Port 6 functions as an analog input channel during A/D conversion. 5/18 ¡ Semiconductor MSM65X227 Secondary Functions Function Symbol Type INT0 I Secondary function of P1.7: Input pin of external interrupt 0. "Receive" is enabled at rising/falling edges or at the "L" level. I Secondary function of P2.0: Input pin of external interrupt 1. "Receive" is enabled at rising/falling edges or at the "L" level. Can also be used as a gate signal input pin that enables/disables the count of Timer 0. External Interrupt INT1 Description Control HSTOP I Secondary function of P3.0: Hardware stop mode input pin. Changes to hardware stop mode by setting this pin to the "L" level when the HSTP bit of SBYCON is 1. In hardware stop mode, the oscillation of OSC is halted to reduce power consumption. Timer 0 T0CK I Secondary function of P 2.1: External clock input pin of Timer 0. Timer 1 T1OUT O Secondary function of P 2.2: This pin outputs a waveform with a period equal to two times of overflow of Timer 1. I/O Secondary function of P 2.3: As UART: Receive data input pin of asynchronous communication. As clock synchronization: Send/receive data input-output pin of clock synchronous communication. TXD O Secondary function of P 2.4: As UART: Send data output pin of asynchronous communication. As clock synchronization: Synchronized clock output pin of clock synchronous communication. AI0 - AI3 I Secondary function of P 6.0 to P 6.3: Functions as an analog input channel at A/D conversion. RXD Serial Port A/D Converter 6/18 ¡ Semiconductor MSM65X227 MEMORY MAPS General Memory Space Bank 1 Bank 0 0FFFFH , 0FFFFH EEPROM Local Memory Space 0F000H 1FFH Data Memory 100H 80H Local Register Set 3 Local Register Set 2 Local Register Set 1 Local Register Set 0 External Memory External Memory Vector Call Table SFR 80H 40H 30H 20H 10H 0 External Data Memory Program/Data Area Page 1 100H Data Memory Internal Memory 1000H Unavailable Area Program/Data Area Page 0 40H Internal Memory 27FH Interrupt Vector Table 20H 0 Data Memory Vector Call Table 0 7/18 ¡ Semiconductor MSM65X227 ABSOLUTE MAXIMUM RATINGS Parameter Supply Voltage Symbol Input Voltage VI Output Voltage VO Analog Reference Voltage Analog Input Voltage Maximum Power Dissipation Storage Temperature Condition VDD=AVDD VRH, VRL Ta=25°C TSTG Unit –0.3 to VDD+0.3 –0.3 to VDD+0.3 GND=AGND=0V V –0.3 to VDD+0.3 –0.3 to VDD+0.3 VAI PD Rating –0.3 to 7.0 Ta=25°C (per package) 400 Ta=25°C (per output pin) 50 Excluding EEPROM data storage –55 to +150 °C Unit mW RECOMMENDED OPERATING CONDITIONS Symbol Condition Range Supply Voltage Parameter VDD fOSC£6MHz 4.5 to 5.5 Analog Supply Voltage AVDD Analog Reference Voltage VRH* Analog Input Voltage VAI VDD=AVDD VRL=AGND=GND=0V 4.5 to 5.5 AVDD–0.5 to AVDD V VRL to VRH Memory Hold Voltage VDDMH fOSC=0Hz 2.0 to 5.5 Operating Frequency fOSC VDD=4.5V to 5.5V 1 to 6 MHz Operating Temperature Top — –40 to +85 °C * VRH should be connected to VRL if A/D converter is not used. 8/18 ¡ Semiconductor MSM65X227 ELECTRICAL CHARACTERISTICS DC Characteristics (VDD=AVDD=4.5 to 5.5V, GND=AGND=0V, Ta=–40 to +85°C) Parameter Symbol Condition 1 "H" Input Voltage 1 * VIH1 "H" Input Voltage 2 *2 VIH2 "L" Input Voltage Min. Typ. Max. CPUCLK=1MHz 2.4 — — CPUCLK=1MHz 0.7VDD — — Unit V VIL CPUCLK=1MHz — — 0.8 "H" Output Voltage VOH1 IOH=–200mA 0.75VDD — — "L" Output Voltage VOL1 IOL=1.6mA — — 0.4 Input Leakage Current 1 *3 ILI1 VI=VDD/0V — — ±1 4 Input Leakage Current 2 * ILI2 VI=VDD/0V — — ±10 "L" Input Current *5 IIL VI=0V –100 –250 –500 "L" Input Current *6 IIL VI=0V –40 –100 –200 Input Capacitance CI f=1MHz, Ta=25°C — 5 — pF IDDS Sleep mode** — 50 100 mA IDDE Sleep mode, no load — 4 10 — 20 40 Current Consumption at Standby Current Consumption during Writing to EEPROM Operating Current Consumption *1 *2 *3 *4 *5 *6 ** IDD fOSC=6MHz, no load See Figure 15-1 mA mA Excluding OSC0 and RESET OSC0 and RESET EXWR and P6 Excluding EXWR and P6 P1 in pull-up input RESET When the input ports and VREF are at 0V and the output ports are unloaded. 9/18 ¡ Semiconductor MSM65X227 AC Characteristics • External memory control (VDD=AVDD=VRH=4.5 to 5.5V, GND=AGND=VRL=0V, Ta=–40 to +85°C) Parameter Clock Cycle Symbol Condition tC — Min. Max. 167 — 75 — "L" Clock Pulse Width tCLW "H" Clock Pulse Width tCHW 75 — ALE Pulse Width tAW tC+tCHW–40 — ALE Pulse Delay Time 1 tALD1 tCLW–20 — ALE Pulse Delay Time 2 tALD2 tCLW–20 — RD Pulse Width tRW tC+tCHW–40 — RD Pulse Delay Time tRD tCLW–20 tCLW+40 WR Pulse Width tWW tC+tCHW–40 — WR Pulse Delay Time tWD tCLW–20 tCLW+40 "L" Address Setup Time tLAS tC–40 — "H" Address Setup Time tHAS tC+tCHW–40 — "L" Address Hold Time tLAH tCLW–20 — Bus Floating Time tLAZ — 20 "H" Address Hold Time tHAHR tCLW–20 — "H" Address Hold Time tHAHW tCLW–20 — Read Data Access Time tRDAA — tC+tCLW–15 Read Data Access Time tRDAR — tCHW+10 Read Data Hold Time tRDH 0 — Write Data Hold Time tWDS tC+tCHW–40 — Write Data Hold Time tWDH tCLW–20 — CL=100pF Unit ns • CPU control (VDD=AVDD=4.5 to 5.5V, GND=AGND=0V, Ta=–40 to +85°C) Parameter Symbol Condition Min. Max. Unit *1 tRESW1 — — ns RESET Pulse Width *2 tRESW2 — 20 oscillation stabilization time — — RESET Pulse Width *1 Except during power-on, sleep, and hardware stop modes *2 During power-on, sleep, and hardware stop modes 10/18 ¡ Semiconductor MSM65X227 • Peripheral control 1 (VDD = AVDD = 4.5 to 5.5V, GND = AGND = 0V, Ta = –40 to +85˚C) Parameter OSC EXI T0 * Symbol Clock Cycle External Interrupt Pulse Width External Clock Pulse Width GATE Pulse Width tC Condition MIN MAX — 167 — 4 tC — 4 tC — tEXIW Unit ns — tT0CW 1 tT0CLK * tT0GW — tT0CLK: Cycle time of timer 0 count clock selected by T0CON. • Peripheral control 2 (VDD=AVDD=4.5 to 5.5V, GND=AGND=0V, Ta=–40 to +85°C) Parameter OSC Min. Max. tC 167 — Synchronous Clock Cycle tSIC 8 tC — Synchronous Clock "L" Pulse Width tSICLW 4 tC–20 — 4 tC–20 — tSIOS 6 tC–100 — tSIOH 2 tC–100 — Input Data Setup Time tSIIS tC+tCLW+100 — Input Data Hold Time tSIIH 0 — Clock Cycle SIO (Clock Synchronous Clock "H" Synchro- Pulse Width nous Output Data Setup Time Mode) Output Data Hold Time Symbol tSICHW Condition — Unit ns 11/18 ¡ Semiconductor MSM65X227 • A/D converter characteristics (VDD = AVDD = VRH = 4.5 to 5.5V, GND = AGND = VRL = 0V, Ta = –40 to +85˚C) Parameter Symbol Resolution n Linearity Error EL Refer to the recommended circuit. Differential Linearity Error ED Zero Scale Error EZS Analog input source impedance RI £ 5kW Min. Typ. Max. Unit — 8 — bit — — +1.5 –1.5 LSB — — ±0.5 LSB — — +1.5 LSB Full Scale Error EFS — — –1.5 LSB Crosstalk ECT Refer to the measuring circuit. — — ±0.5 LSB tCONV fOSC = 6MHz — 26.7 — ms/CH Conversion Time* * Condition The conversion time immediately after G0 bit is set to "I" is 24.7µs/CH. Definition of Terms Resolution Recognizable minimum input analog value. This can be resolved into 28 = 256, that is (VRH – VRL) ÷ 256 Linearity Error Deviation between ideal conversion characteristics as an 8-bit A/D converter and actual conversion characteristics. (Not including quantization error.) Ideal conversion characteristics means a step which divides voltage between VRH and LRL into 256. Differential Linearity Error Shows the smoothness of conversion characteristics. 1LSB = (VRH – VRL) ÷ 256 is ideal for analog input voltage width corresponding to change per 1 bit of digital output. The differential linearity error is the deviation between this ideal bit size and a bit size at arbitrary point in conversion range. Zero Scale Error Deviation between ideal conversion characteristics of transfer point for digital outputs "000H" to "001H" and actual conversion characteristics. Full Scale Error Deviation between ideal conversion characteristics of transfer point for digital outputs "0FEH" to "0FFH" and actual conversion characteristics. 12/18 ¡ Semiconductor MSM65X227 Recommended circuit AVDD VDD VRH +5V + MSM65X227 – 0.1 47 µF µF RI AI0-3 0V + GND VRL Analog Voltage Input AGND 0.1 µF RI (Analog input source impedance) £ 5kW Crosstalk measuring circuit – 5kW AI0 + AI1 Analog Voltage Input 0.1 µF Crosstalk is defined as the difference of A/D conversion result between supplying the same voltage to AI0 to AI3 and supplying voltage shown in this left diagram. AI3 VRH or AGND 13/18 ¡ Semiconductor MSM65X227 EEPROM Characteristics Parameter Number of rewrites Rating 10,000 100 Data storage time 10 years Condition 100 bytes 3,996 bytes Failure rate < 1% Storage between –40 and 85°C (VDD=AVDD=4.5 to 5.5V, GND=AGND=0V, Ta=–40 to +85°C) Parameter Symbol Min. Typ. Max. Unit Write disable time after reset tINHWR — 5 — ms Write time tEEWR — 6 8 ms 14/18 ¡ Semiconductor MSM65X227 TIMING DIAGRAM External Memory Control tCHW tC OSC0 tCLW tAW ALE tRD tRW tALD1 RD tRDAR tLAS AD0-7 tLAH tRDH tLAZ INST or DATA IN ADDRESS L tRDAA tHAS tHAHR A8-16 ADDRESS H tWD tWW tALD2 tWDS tWDH WR AD0-7 ADDRESS L DATA OUT tHAHW A8-16 ADDRESS H 15/18 ¡ Semiconductor MSM65X227 CPU Control 1) RESET pulse width tRESW1, 2 RESET Peripheral control 1 tC OSC0 tCLW 1) EXI Pulse width tEXIW INT0-1 2) T0 tT0CW T0CK tT0GW GATE 16/18 ¡ Semiconductor MSM65X227 Peripheral control 2 1) SIO (Clock synchronous mode) tSFC tSFCLW tSFCHW tSFOS tSFOH tSFIS tSFIH TXD RXD (transmission) RXD (reception) 17/18 ¡ Semiconductor MSM65X227 PACKAGE DIMENSIONS (Unit : mm) TQFP100-P-1414-0.50-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.55 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 18/18