OKI MSM66P509

E2E1029-27-Y3
¡ Semiconductor
MSM66509/66P509
¡ Semiconductor
This MSM66509/66P509
version: Jan. 1998
Previous version: Nov. 1996
OLMS-66K Series 16-Bit Microcontroller
GENERAL DESCRIPTION
The MSM66509/66P509 is a high-performance 16-bit microcontroller that employs OKI
original nX-8/500 CPU core.
The MSM66509/66P509 includes a 16-bit CPU, ROM, RAM, a 10-bit A/D converter, serial ports,
flexible timers, pulse-width modulator (PWM), and I/O ports.
FEATURES
• Program memory space
Internal ROM
• Data memory space
Internal RAM
• High-speed execution
Minimum instruction execution time
• Powerful instruction set
• Abundant addressing modes
:
:
:
:
64K bytes
64K bytes
64K bytes
2K bytes
: 125nsec @ 32MHz
: Instruction set superior in orthogonal matrix
8/16-bit data transfer instructions
8/16-bit arithmetic instructions
Multiplication and division operation
instructions
Bit manipulation instructions
Bit logic instructions
ROM table reference instructions
: Register addressing
Page addressing
Pointing register indirect addressing
Stack addressing
Immediate addressing
• I/O port
Analog input port
: 1 port ¥ 16 bits
Input-output port
: 11 ports ¥ 8 bits, 1 port ¥ 4 bits
(Input/output setting available in bit unit)
• Flexible timers
Free run counters
: 19-bit ¥ 1, 16-bit ¥ 1
19-bit CAP with a divider
: 4
16-bit double buffer RTO
: 6
16-bit PWM/RTO
: 2
16-bit CAP/RTO
: 2
• 8-bit general timer
: 1
8-bit event counter
: 1
• 16-bit PWM
: 6
Input clock divider
: 4
• Serial ports
UART mode with BRG
: 1
Synchronous/UART switchable mode
with BRG
: 1
• 10-bit A/D converter
: 16 channels
1/24
¡ Semiconductor
• Transition detector
• Watchdog timer
• Interrupts
Non-maskable
Maskable
MSM66509/66P509
: 6
: 1
: 1
: Internal 32/external 2
(4-level priority can be set)
• ROM window function
• Standby modes
HALT mode
STOP mode
• Package
128-pin plastic QFP (QFP128-P-2828-0.80-BK) :
(Product name: MSM66509-¥¥¥GS-BK)
¥¥¥ indicates the code number.
2/24
P3.3/FTM11D
P3.4/CAP0
FLEXIBLE
TIMER
P6.2/RXD1
P6.3/TXD1
P6.4/RXC1
P6.5/TXC1
P6.6/RXD0
P6.7/TXD0
P7.4/PWM0
P8.1/PWM5
AVDD
VREF
AGND
AI0
CPU CORE
RAM
2K BYTES
SSP
PSW
LRB
PC
MEMORY
CONTROL
POINTING R.
LOCAL R.
ROM
64K BYTES
SERIAL
PORT
BUS PORT CONTROL
P3.7/CAP3
P10.0/RTO12
P10.1/RTO13
CONTROL
REGISTERS
EA
ALE
PSEN
RD/P7.1
WR/P7.0
WAIT/P7.2
AD0/P0.0
¡ Semiconductor
P2.5/RTO9
P2.6/FTM10
P3.0/FTM11A
P3.1/FTM11B
BLOCK DIAGRAM
P2.0/RTO4
AD7/P0.7
A8/P1.0
A15/P1.7
ALU
PWM
INSTRUCTION
DECODER
ALU CONTROL
A/D
CONVERTER
ACC, etc.
AI15
P4.0/ETMCK
P4.1/ECTCK
P4.2/TRNS0
SYSTEM CONTROL
PORT
CONTROL
INTERRUPT
OE
WDT
P11
P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
P0
PERIPHERAL
RES
OSC1
OSC0
P7.3/CLKOUT
TRANSITION
DETECTOR
3/24
MSM66509/66P509
P4.7/TRNS5
P6.0/INT0
P6.1/INT1
NMI
EVENT
TIMER
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
TRNS3/P4.5
TRNS4/P4.6
TRNS5/P4.7
P5.0
P5.1
P5.2
P5.3
NMI
RES
EA
VDD
AVDD
VREF
AI0
AI1
AI2
AI3
AI4
AI5
AI6
AI7
AI8
AI9
AI10
AI11
AI12
AI13
AI14
AI15
AGND
GND
INT0/P6.0
INT1/P6.1
RXD1/P6.2
TXD1/P6.3
RXC1/P6.4
TXC1/P6.5
RXD0/P6.6
TXD0/P6.7
GND
OSC0
OSC1
ALE
PSEN
WR/P7.0
RD/P7.1
WAIT/P7.2
CLKOUT/P7.3
PWM0/P7.4
PWM1/P7.5
PWM2/P7.6
PWM3/P7.7
VDD
PWM4/P8.0
PWM5/P8.1
P8.2
P8.3
P8.4
P8.5
P8.6
P8.7
GND
OE
AD0/P0.0
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
P4.4/TRNS2
P4.3/TRNS1
P4.2/TRNS0
P4.1/ECTCK
P4.0/ETMCK
P11.7
P11.6
P11.5
P11.4
P11.3
P11.2
P11.1
P11.0
VDD
P3.7/CAP3
P3.6/CAP2
P3.5/CAP1
P3.4/CAP0
P3.3/FTM11D
P3.2/FTM11C
P3.1/FTM11B
P3.0/FTM11A
GND
P10.7
P10.6
P10.5
P10.4
P10.3
P10.2
P10.1/RTO13
P10.0/RTO12
P2.7
¡ Semiconductor
MSM66509/66P509
PIN CONFIGURATION (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
P2.6/FTM10
P2.5/RTO9
P2.4/RTO8
P2.3/RTO7
P2.2/RTO6
P2.1/RTO5
P2.0/RTO4
VDD
P9.7
P9.6
P9.5
P9.4
P9.3
P9.2
P9.1
P9.0
P1.7/A15
P1.6/A14
P1.5/A13
P1.4/A12
P1.3/A11
P1.2/A10
P1.1/A9
P1.0/A8
GND
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
128-Pin Plastic QFP
4/24
¡ Semiconductor
MSM66509/66P509
PIN DESCRIPTIONS
Symbol
Type
Description
P0.0-P0.7/
AD0-AD7
I/O
P0: 8-bit Input-output port. Each bit can be assigned to be an input or an output.
AD: When an external memory is used, these pins output the lower 8 bits of the
address. These pins also input or output the data.
P1.0-P1.7/
A8-A15
I/O
P1: 8-bit Input-output port. Each bit can be assigned to input or output.
A: When an external memory is used, these pins output the upper 8 bits of the
address.
P2.0-P2.5/
RTO4-RTO9
P2.6/FTM10
P2.7
I/O
P2: 8-bit Input-output port. Each bit can be assigned to input or output.
RTO: Output pin for real time output
FTM10: Capture input pin or real-time output pin
I/O
P3: 8-bit Input-output port. Each bit can be assigned to input or output.
FTM11A: Capture input pin or real-time output pin
FTM11B-D: 4-port real-time output pin
CAP : Capture input pin
P4.0/ETMCK
P4.1/ECTCK
P4.2-P4.7/
TRNS0-TRNS5
I/O
P4: 8-bit Input-output port. Each bit can be assigned to input or output.
ETMCK: External clock input pin of 8-bit general timer
ECTCK: External clock input pin of 8-bit event counter
TRNS: Transition detector input pin
P5.0-P5.3
I/O
P5: 4-bit Input-output port. Each bit can be assigned to input or output.
I/O
P6: 8-bit Input-output port. Each bit can be assigned to input or output.
INT0, 1: External interrupt request input pin
RXD1 : SCI1 Receiver data input pin
TXD1 : SCI1 Transmitter data output pin
RXC1 : SCI1 Receiver circuit clock pin
TXC1 : SCI1 Transmitter circuit clock pin
RXD0 : SCI0 Receiver data input pin
TXD0 : SCI0 Transmitter data output pin
P7.0/WR
P7.1/RD
P7.2/WAIT
P7.3/CLKOUT
P7.4-P7.7/
PWM0-PWM3
I/O
P7: 8-bit Input-output port. Each bit can be assigned to input or output.
WR: Write strobe output pin for external data memory
RD: Read strobe output pin for external data memory
WAIT: CPU wait request input pin when accessing external data memory
CLKOUT: Output pin for supplying a clock to peripheral circuits
PWM: PWM output pin
P8.0-P8.1/
PWM4-PWM5
P8.2-P8.7
I/O
P8: 8-bit Input-output port. Each bit can be assigned to input or output.
PWM: PWM output pin
P9.0-P9.7
I/O
P9: 8-bit Input-output port. Each bit can be assigned to input or output.
P10.0-P10.1/
RTO12-RTO13
P10.2-P10.7
I/O
P10: 8-bit Input-output port. Each bit can be assigned to input or output.
RTO: Output pin for real time output.
P11.0-P11.7
I/O
P11: 8-bit Input-output port. Each bit can be assigned to input or output.
P3.0-P3.3/
FTM11A-FTM11D
P3.4-P3.7/
CAP0-CAP3
P6.0/INT0
P6.1/INT1
P6.2/RXD1
P6.3/TXD1
P6.4/RXC1
P6.5/TXC1
P6.6/RXD0
P6.7/TXD0
5/24
¡ Semiconductor
MSM66509/66P509
PIN DESCRIPTION (Continued)
Symbol
Type
Description
AI0-AI15
I
Analog signal input pin for A/D converter
AVDD
I
Power supply input pin for A/D converter
VREF
I
Reference voltage input pin for A/D converter
AGND
I
GND input pin for A/D converter
OSC0
I
Basic clock oscillation pin
OSC1
O
Basic clock oscillation pin
ALE
O
Timing pulse output pin to latch the lower 8 bits of the address output from port
0 when the CPU accesses the external memory
PSEN
O
Strobe pulse output pin to fetch to external program memory
When P0, P1, P7.4-P7.7, and P8-P11 are in an output state and OE pin is "H"
level, the ports go to a high-impedance state.
When P0, P1, P7.4-P7.7, and P8-P11 are in an output state and OE pin is "L"
level, the ports output "H" or "L" level.
However, when P0, P1, P7.4-P7.7, and P8-P11 are in an input state, these ports
are not under the influence of OE pin.
OE
I
NMI
I
Nonmaskable interrupt request input pin
RES
I
Low-active RESET input pin
EA
I
Normally set to "H" level. If set to "L" level, the program memory goes into
external access mode and accesses external program memory
VDD
I
Power supply pin
GND
I
Ground pin
6/24
¡ Semiconductor
MSM66509/66P509
REGISTERS
Accumulator
15
0
ACC
Control Register (CR)
Program Status Word
15
0
PSW
Bit 15 : Carry flag (CY)
Bit 14 : Zero flag (ZF)
Bit 13 : Half carry flag (HC)
Bit 12 : Data descriptor (DD)
Bit 11 : Sign flag (S)
Bit 10 : Master interrupt priority flag (MIP)
Bit 9 : Overflow flag (OV)
Bit 8 : Master interrupt enable flag (MIE)
Bit 7-3 : User flag
Bit 2-0 : System control base 2-0 (SCB2-0)
15
0
Program Counter
PC
Local Register Base
LRB
System Stack Pointer
SSP
Pointing Register (PR)
15
0
Index Register 1
Index Register 2
Data pointer
User Stack Pointer
X1
X2
DP
USP
Local Register
7
0 7
0
ER0
ER1
R1
R0
R3
R2
ER2
R5
R4
ER3
R7
R6
7/24
¡ Semiconductor
MSM66509/66P509
SFR
Address
[H]
0000
0001
0002
0003
0004
0005
0006
0007
0010
0011I
0012I
0014
0015I
0018I
001C
001DI
001EI
0020
0021
0022
0023
0024
0025I
0026
0027
0028
0029
002A
002B
002C
002DI
002E
002F
Name
System stack pointer
Local register base
Program status word
Accumulator
ROM window register
RAM ready control register
ROM ready control register
Stop code acceptor
Standby control register
Peripheral control register
Watchdog timer
TBC clock dividing counter
TBC clock dividing register
Port 0 data register
Port 1 data register
Port 2 data register
Port 3 data register
Port 4 data register
Port 5 data register
Port 6 data register
Port 7 data register
Port 0 mode register
Port 1 mode register
Port 2 mode register
Port 3 mode register
Port 4 mode register
Port 5 mode register
Port 6 mode register
Port 7 mode register
Symbol
SSP
LRBL
LRBH
PSWL
PSWH
ACCL
ACCH
ROMWIN
RAMRDY
ROMRDY
STPACP
SBYCON
PRPHF
WDT
TBCKDVC
TBCKDVR
P0
P1
P2
P3
P4
P5
P6
P7
P0IO
P1IO
P2IO
P3IO
P4IO
P5IO
P6IO
P7IO
8/16-bit
R/W Operation Reset
FF
FF
Undefined
8/16
R/W
W
R/W
8
W
R
R/W
8/16
00
00
00
00
00
FF
FF
"0"
C8
*
Halt
F0
F0
00
00
00
00
00
F0
00
00
00
00
00
00
00
F0
00
00
Note: A I mark in the address column indicates that there is a bit that does not exist in the
register.
*
The initial values of PRPHF (SFR=18H) are as follows :
When RES pin is reset : VBFF (bit 6) is set to "1" and CKOUT1 or 0 is set to "0".
When WDT, BRK instruction, and operation code trap are reset : VBFF (bit 6) keeps the value
just before it is reset and CKOUT 1 or 0 is set to "0". In any case, the state of OE pin is read
for OERD (bit 7).
8/24
¡ Semiconductor
MSM66509/66P509
SFR (Continued)
Address
[H]
0031
0032I
0033
0034
0036
0037
0038
0039I
003AI
003CI
003DI
0040
0041
0042
0043I
0044
0045
0046
0047I
0048
0049
004A
004BI
004EI
004FI
0050
0051
0052
0053
0054
0055I
0056
0057I
0058
0059
005A
005B
005C
005D
005E
005F
Name
Port 1 secondary function control register
Port 2 secondary function control register
Port 3 secondary function control register
Port 4 secondary function control register
Port 6 secondary function control register
Port 7 secondary function control register
TRNS control register 0
TRNS control register 1
Transition detector
Port 8 secondary function control register
Port 10 secondary function control register
Interrupt request register 0
Interrupt request register 1
Interrupt enable register 0
Interrupt enable register 1
Interrupt request flag disable register 0
Interrupt request flag disable register 1
NMI control register
External interrupt control register
Interrupt priority control register 00
Interrupt priority control register 01
Interrupt priority control register 10
Interrupt priority control register 11
Port 8 data register
Port 9 data register
Port 10 data register
Port 11 data register
Port 8 mode register
Port 9 mode register
Port 10 mode register
Port 11 mode register
Symbol
P1SF
P2SF
P3SF
P4SF
P6SF
P7SF
TRNSCON0
TRNSCON1
TRNSIT
P8SF
P10SF
IRQ0L
IRQ0H
IRQ1L
IRQ1H
IE0L
IE0H
IE1L
IE1H
IRQD0L
IRQD0H
IRQD1L
IRQD1H
NMICON
EXICON
IP00L
IP00H
IP01L
IP01H
IP10L
IP11H
IP11L
IP11H
P8
P9
P10
P11
P8IO
P9IO
P10IO
P11IO
8/16-bit
R/W Operation
8
8/16
8
8/16
8
R/W
8/16
Reset
00
80
00
00
00
00
00
F0
C0
FC
FC
00
00
00
F8
00
00
00
F8
00
00
00
F8
FC or 7C
F0
00
00
00
00
00
F8
00
F8
00
00
00
00
00
00
00
00
Note: A I mark in the address column indicates that there is a bit that does not exist in the
register.
9/24
¡ Semiconductor
MSM66509/66P509
SFR (Continued)
Address
[H]
0060
0061
0062I
0063I
0064I
0065
0066
0068
0069
006AI
006BI
006C
006D
006E
0070I
0071
0072
0073
0074
0075
0076
0077
0078
0079
007A
007B
007C
007D
007E
007F
0080
0081
0082
0083
0084
0085
0086
0087
0088
0089
008A
008B
008C
008D
008E
008F
Name
SCI0 timer counter
SCI0 timer register
SCI0 timer control register
SCI0 transmission control register
SCI0 reception control register
SCI0 transmission and reception buffer register
SCI0 status register
SCI1 timer counter
SCI1 timer register
SCI1 timer control register
SCI1 transmission control register
SCI1 reception control register
SCI1 transmission and reception buffer register
SCI1 status register
8-bit general timer control register
8-bit event counter
8-bit general timer counter
8-bit general timer register
Symbol
S0TM
S0TMR
S0CON
ST0CON
SR0CON
S0BUF
S0STAT
S1TM
S1TMR
S1CON
ST1CON
SR1CON
S1BUF
S1STAT
GTMCON
GEVC
GTMC
GTMR
8/16-bit
R/W Operation
8/16
8
8/16
R/W
8
8/16
Reset
00
00
02
82
12
Undefined
00
00
00
02
80
00
Undefined
00
30
00
00
00
PWM counter 0
PWC0
0000
PWM counter 1
PWC1
0000
PWM counter 2
PWC2
0000
R
16
PWM counter 3
PWC3
0000
PWM counter 4
PWC4
0000
PWM counter 5
PWC5
0000
PWR0 buffer register
PW0BF
PWR1 buffer register
PW1BF
PWR2 buffer register
PW2BF
PWR3 buffer register
PW3BF
A/DC result register 10
A/DC result register 11
A/DC result register 12
A/DC result register 13
A/DC result register 14
A/DC result register 15
A/DC result register lower 3 bits
A/DC result register lower 4 bits
ADCR10
ADCR11
ADCR12
ADCR13
ADCR14
ADCR15
LADCR3
LADCR4
R/W
8/16
R
*8/16
00
00
00
00
00
00
00
00
Undefined
Note: A I mark in the address column indicates that there is a bit that does not exist in the
register.
*
8/16 means a special word manipulation. (For details, refer to the User's Manual.)
10/24
¡ Semiconductor
MSM66509/66P509
SFR (Continued)
Address
[H]
0090
0091
0092
0093
0094
0095
0096
0097
0098
0099I
009A
009B
009C
009D
009EI
009FI
00A0
00A1
00A2
00A3
00A4
00A5
00A6
00A7
00A8
00A9
00AA
00AB
00AC
00AD
00AE
00AF
00B0
00B1
00B2
00B3
00B4
00B5
00B6
00B7
00B8I
00B9I
00BAI
00BBI
00BC
00BDI
00BE
Name
Symbol
PWR4 buffer register
PW4BF
PWR5 buffer register
PW5BF
TMR12 buffer register
TMR12BF
TMR13 buffer register
TMR13BF
PWM interrupt control register
PWM interrupt control register 1
PWM control register 0
PWM control register 1
PWM clock counter
PWM clock register
PWM run register
PWM active register
8/16-bit
R/W Operation
8/16
PWINTCON
PWINTCON1
PWCON0
PWCON1
PWDVC
PWDVR
PWRUN
PWACT
Reset
00
00
00
00
00
00
00
00
00
CC
00
00
00
00
00
C0
Timer register 0
TMR0
0000
Timer register 1
TMR1
0000
Timer register 2
TMR2
0000
Timer register 3
TMR3
Timer register 4
TMR4
Timer register 5
TMR5
Timer register 6
TMR6
0000
Timer register 7
TMR7
0000
Timer register 8
TMR8
0000
Timer register 9
TMR9
0000
Timer register 10
TMR10
0000
Timer register 11
TMR11
0000
TMR0 lower 3 bits
TMR1 lower 3 bits
TMR2 lower 3 bits
TMR3 lower 3 bits
TMR0L
TMR1L
TMR2L
TMR3L
TMSELL
TMSELH
PWCON2
1F
1F
1F
1F
00
C0
00
TM setting register
PWM control register 2
0000
R/W
0000
16
8
8/16
8
0000
Note: A I mark in the address column indicates that there is a bit that does not exist in the
register.
11/24
¡ Semiconductor
MSM66509/66P509
SFR (Continued)
Address
[H]
00C0
00C1
00C2
00C3
00C4
00C5
00C6
00C7
00C8
00C9I
00CA
00CB
00CC
00CD
00CE
00CFI
00D0I
00D1I
00D2
00D4
00D5
00D6
00D7
00D8I
00D9I
00DAI
00DBI
00DCI
00DDI
00DEI
00DFI
00E0
00E1
00E2
00E3
00E4
00E5
00E6
00E7
00E8
00E9
00EA
00EB
00ECI
00EDI
00EEI
00EFI
Name
Symbol
TMR4 buffer register
TMR4BF
TMR5 buffer register
TMR5BF
TMR6 buffer register
TMR6BF
TMR7 buffer register
TMR7BF
Timer control register
Timer counter 0 lower 3 bits
TMCON
TM0L
Timer counter 0
TM0
Timer counter 1
TM1
Capture control register 0
Capture control register 1
Event control register
TMR mode register
Timer register 12
CAPCON0
CAPCON1
EVNTCONL
EVNTCONH
TMRMODE
8/16-bit
R/W Operation Reset
00
00
00
00
8/16
00
00
00
00
00
8
1F
00
00
00
00
8/16
00
F0
R/W
88
88
00
8
0000
TMR12
16
Timer register 13
Event dividing counter 0
Event dividing counter 1
Event dividing counter 2
Event dividing counter 3
EVDV0 buffer register
EVDV1 buffer register
EVDV2 buffer register
EVDV3 buffer register
A/DC result register 0
A/DC result register 1
A/DC result register 2
A/DC result register 3
A/DC result register 4
A/DC result register 5
A/DC result register 6
A/DC result register 7
A/DC result register 8
A/DC result register 9
A/DC result register lower 0
A/DC result register lower 1
A/DC result register lower 2
A/D interrupt control register
A/DC control register L
A/DC control register H
TMR13
0000
EVDV0
EVDV1
EVDV2
EVDV3
EVDV0BF
EVDV1BF
EVDV2BF
EVDV3BF
ADCR0
ADCR1
ADCR2
ADCR3
ADCR4
ADCR5
ADCR6
ADCR7
ADCR8
ADCR9
LADCR0
LADCR1
LADCR2
ADINTCON
ADCONL
ADCONH
C0
C0
C0
C0
C0
C0
C0
C0
8/16
*8/16
R
Undefined
8
R/W
F0
80
80
Note: A I mark in the address column indicates that there is a bit that does not exist in the
register.
*
8/16 means a special word manipulation. (For details, refer to the User's Manual.)
12/24
¡ Semiconductor
MSM66509/66P509
SFR (Continued)
Address
[H]
00F0I
00F1I
00F2I
00F3I
00F4I
00F5I
00F6I
00F7I
00F8
00F9I
00FAI
00FBI
00FC
00FD
00FE
00FF
Name
RTO control register 0
RTO control register 1
RTO control register 2
RTO control register 3
RTO control register 4
RTO control register 5
RTO control register 6
RTO control register 7
RTO control register 8
RTO control register 9
RTO control register 10
PWM clock counter 34 run register
PWM clock counter 34
PWM clock register 34
Emulator using area*
Symbol
RTOCON0
RTOCON1
RTOCON2
RTOCON3
RTOCON4
RTOCON5
RTOCON6
RTOCON7
RTOCON8
RTOCON9
RTOCON10
PWDVRN
PWDVC34
PWDRC34
8/16-bit
R/W Operation Reset
F8
F8
F8
F8
FC
8/16
FC
F8
R/W
F8
00
F8
F8
8
FC
00
8/16
00
Note: A I mark in the address column indicates that there is a bit that does not exist in the
register.
*
For the emulator using area, if the write is manipulated, the write data becomes invalid, and
if the read is manipulated, the read data becomes undefined.
13/24
¡ Semiconductor
MSM66509/66P509
ADDRESSING MODES
The MSM66509/66P509 provides independent 64K-byte data and 64K-byte program spaces
with various types of addressing modes. These modes are shown below for both RAM (for data
space) and ROM (for program space).
RAM Addressing Mode (for data space)
• Register addressing
Example
INC USP
USP
• Page addressing
a) sfr page
Example
L A, sfr IRQ0
SFR
0000H
0040H
b) Fixed page
Example
ST A, fix 0C0H
RAM
0200H
02C0H
c) Current page
Example
ROR off 078H
RAM
¥¥00H
¥¥78 H
• Direct data addressing
Example
CLR dir 780H
RAM
0700H
0780H
14/24
¡ Semiconductor
MSM66509/66P509
• Pointing register indirect addressing
a) DP/X1 indirect
Example
XCHG A, [DP]
RAM
DP
b) DP indirect with post increment
Example
ADD A, [DP+]
RAM
DP
After access, DP is incremented by 2.
c) DP indirect with post increment
Example
SUB A, [DP-]
RAM
DP
After access, DP is decremented by 2.
d) DP/USP indirect with 7-bit displacement
Example
AND A, 12[DP]
–64 to +63
RAM
DP
e) X1/X2 indirect with 16-bit base
Example
XOR A, 1234H[X1]
0-65535
RAM
X1
f) X1 indirect with 8-bit register (AL, R0) displacement
Example
OR A, [X1+AL]
AL
RAM
X1
15/24
¡ Semiconductor
MSM66509/66P509
• Special bit area addressing
a) Fixed page SBA area (02C0H to 02FFH)
Example
SB sbafix 2D1H.3
RAM
02C0H
02D1H
b) Current page SBA area (¥¥C0H to ¥¥FFH)
Example
RB sbaoff 2E9H.7
RAM
¥¥C0H
¥¥E9H
ROM Addressing Mode (for program space)
• Immediate addressing
Example
MOV SSP, #7FFH
ROM
Address
xxxxH
• Table data addressing
a) Direct
Example
LC A, 5678H
ROM
5678H
b) RAM addressing indirect
Example
CMPC A, [USP]
ROM
USP
c) RAM addressing indirect with 16-bit base
Example
LC A, 1234H[ER0]
0-65535
ROM
RAM
ER0
16/24
¡ Semiconductor
MSM66509/66P509
MEMORY MAP
Program Memory Space
0000H
0000H
Vector Table Area
(74 bytes)
0049H
004AH
0069H
006AH
Internal ROM Area
(64K bytes)
VCAL Table Area
(32 bytes)
0FFFH
1000H
ACAL Area
(2K bytes)
17FFH
1800H
FFFFH
FFFFH
Data Memory Space
0000H
00FFH
0100H
01FFH
0200H
02FFH
0300H
SFR Area
Reserved Area
01FFH
0200H
FIX Area
Internal RAM Area
Area where local
register can be set
09FFH
0A00H
0208H
0210H
0238H
0FFFH
1000H
Reserved Area
X1
X2
DP
USP
X1
X2
DP
USP
X1
USP
X1
X2
DP
USP
SCB=0
SCB=1
Pointing
Register Set
SCB=7
0240H
External Memory Area
Area where ROM
window can be set
02C0H
SBA Area
(64 bytes)
FFFFH
Area where SB, RB,
JBS, and JBR
instructions can be
accessed efficiently.
0300H
17/24
¡ Semiconductor
MSM66509/66P509
ABSOLUTE MAXIMUM RATINGS
(Ta=25˚C)
Parameter
Digital Power Supply Voltage
Input Voltage
Output Voltage
Analog Power Supply Voltage
Analog Reference Voltage
Analog Input Voltage
Power Dissipation
Storage Temperature
Symbol
VDD
Condition
VI
VO
AVDD
GND=AGND=0V
VREF
VAI
PD
Ta=85°C
TSTG
Per package
Per output
—
Rating
–0.3 to +7.0
–0.3 to VDD+0.3
–0.3 to VDD+0.3
–0.3 to VDD+0.3
–0.3 to AVDD+0.3
–0.3 to VREF
855
50
–50 to +150
Unit
V
mW
°C
RECOMMENDED OPERATING CONDITIONS
Parameter
Digital Power Supply Voltage
Analog Power Supply Voltage
Analog Reference Voltage
Analog Input Voltage
Memory Hold Voltage
Operating Frequency
Symbol
VDD
AVDD
VREF
VAI
Condition
fOSC£32MHz
VDD=AVDD
—
—
4.5 to 5.5
AVDD–0.3 to AVDD
AGND to VREF
VDDH
fOSC
fOSC=0Hz
VDD=5V±10%
2.0 to 5.5
0 to 32
Ambient Temperature
Ta
—
MOS load
Fan Out
N
–40 to +85
20
2
1
TTL load
P0
P1 to P11
Range
4.5 to 5.5
Unit
V
MHz
°C
—
—
—
18/24
¡ Semiconductor
MSM66509/66P509
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD=5V±10%, Ta=–40 to +85˚C)
Parameter
Symbol
H Level Input Voltage
*1
H Level Input Voltage
*2, 5, 6
H Level Input Voltage
*7
L Level Input Voltage
*1
L Level Input Voltage
*2, 5, 6
L Level Input Voltage
*7
H Level Output Voltage
*1, 4
H Level Output Voltage
*2
L Level Output Voltage
*1, 4
L Level Output Voltage
*2
Input Leakage Current
*3, 6
Input Current
Input Current
H Level Output Current
*5
VIH
VIL
VOH
VOL
IIH/IIL
Condition
–
Min.
Typ
Max.
2.2
–
VDD+0.3
0.80VDD
–
VDD+0.3
0.85VDD
–
VDD+0.3
–0.3
–
0.8
–0.3
–
0.2VDD
–0.3
–
0.15VDD
IO=–400uA
VDD–0.4
–
–
IO=–200uA
VDD–0.4
–
–
IO=3.2mA
–
–
0.4
IO=1.6mA
–
–
0.4
–
–
1/–1
–
–
1/–250
–
VI=VDD/0V
Unit
V
µA
*7
–
–
15/–15
*1, 4
–2
–
–
–1
–
–
10
–
–
5
–
–
–
–
±2
–
5
–
–
7
–
–
4
mA
µA
H Level Output Current
*2
L Level Output Current
*1, 4
L Level Output Current
*2
IOH
VO=2.4V
IOL
Output Leakage Current *1, 2, 4
ILO
Input Capacity
CI
Output Capacity
CO
Analog Reference Current
IREF
Current Consumption
(in STOP mode)
IDDS
Current Consumption
(in HALT mode)
IDDH
Current Consumption
IDD
VO=VDD/0V
f=1MHz, Ta=25˚C
A/D in operation
–
A/D stopped
–
–
10
VDD=2V, Ta=25˚C*
–
0.2
10
*8
–
1
100
fOSC=32MHz
No load
–
30
60
–
80
140
mA
µA
pF
µA
mA
*1. Applied to P0
*2. Applied to P1 to P11
*3. Applied to Ain
*4. Applied to ALE, PSEN
*5. Applied to RES
*6. Applied to EA, OE, NMI
*7. Applied to OSC0
*8. Ports for input pins are VDD or GND, otherwise no load.
19/24
¡ Semiconductor
MSM66509/66P509
AC Characteristics
• External program memory control
(VDD=5V±10%, Ta=–40 to +85˚C)
Symbol
Min.
Max.
15.625
–
tAW
3tøW–10
–
PSEN Pusle Width
tPW
4tøW–10
–
PSEN Pulse Delay Time
tPAD
tøW–5
tøW+5
Low-Order Address Setup Time
tAAS
2tøW–10
2tøW+10
Low-Order Address Hold Time
tAAH
tøW–5
tøW+5
High-Order Address Delay Time
tAAD
tøW–0
tøW+10
High-Order Address Hold Time
tAPH
tøW–0
tøW+10
Instruction Setup Time
tIS
35
–
Instruction Hold Time
tIH
0
tøW–10
Parameter
Clock Pulse Width (OSC)
tøW
ALE Pulse Width
Condition
–
CL=50PF
Unit
ns
• External data memory control
(VDD=5V±10%, Ta=–40 to +85˚C)
Parameter
Symbol
Clock Pulse Eidth (OSC)
tøW
ALE Pulse Width
tAW
Condition
–
Min.
Max.
15.625
–
3tøW–10
–
RD Pusle Width
tRW
4tøW–10
–
WR Pulse Width
tWW
4tøW–10
–
RD Pulse Delay Time
tRAD
tøW–5
tøW+5
WR Pulse Delay Time
tWAD
tøW–5
tøW+5
Low-Order Address Setup Time
tAAS
2tøW–10
2tøW+10
Low-Order Address Hold Time
tAAH
tøW–5
tøW+5
tøW–0
tøW+10
CL=50PF
High-Order Address Setup Time
tAAD
High-Order Address Hold Time
tARH
tøW–0
tøW+10
High-Order Address Hold Time
tAWH
tøW–0
tøW+10
Memory Data Setup Time
tMS
35
-
Memory Data Hold Time
tMH
0
tøW–10
Data Delay Time
tDD
tøW–0
tøW+10
Data Hold Time
tDH
tøW–0
tøW+10
Unit
ns
20/24
¡ Semiconductor
CLK
,,
,,
,,
,
tøW
ALE
MSM66509/66P509
tøW
tAW
PSEN
tPAD
AD 0-7
PC 0-7
INST 0-7
tAAS
A 8-15
tPW
tAAH
tIS
PC 8-15
tAAD
RD
tAPH
tRAD
AD 0-7
tRW
RAP 0-7
tAAS
A 8-15
DIN 0-7
tAAH
tMS
tARH
tWAD
AD 0-7
tWW
RAP 0-7
tAAS
A 8-15
tMH
RAP 8-15
tAAD
WR
tIH
DOUT 0-7
tAAH
tDH
RAP 8-15
tAAD
tDD
tAWH
21/24
¡ Semiconductor
MSM66509/66P509
A/D CONVERTER CHARACTERISTICS
(Ta=–40 to +85˚C, AVDD=VDD=VREF=5V±10%, AGND=GND=0V, fOSC=32MHz)
Parameter
Condition
Min.
Typ.
Max.
Unit
Refer to the recommended
circuit. (Figure 1)
Analog input source
impedance
RI <= 5kW
tCONV=16µsec
–
–
10
Bit
–
–
±3
–
–
±1
0
–
+3
–
–
–3
Symbol
n
Resolution
Linearity Error
EL
Differential Linearity Error
ED
Zero Scale Error
EZS
Full Scale Error
EFS
Crosstalk
ECT
Refer to the measuring
circuit. (Figure 2)
–
–
±1
tCONV
by ADTM set data
8
–
24
Conversion Time
VREF
AVDD
+5V
VDD
+
–
RI
0.1
µF
µs/CH
47W
0.1
µF
Reference
Voltage
LSB
+
47
µF
0.1
µF
47
µF
AI 0-15
+
Analog input
AGND
GND
0V
0.1µF
RI (Analog input source impedance) <= 5kW
Figure 1 Recommended Circuit
22/24
¡ Semiconductor
–
MSM66509/66P509
5kW
AI0
+
Analog input
AI1
0.1µF
Crosstalk is defined as the
difference between the A/D
conversion result when applying the identical analog
input to AI0 to AI15 and the A/D
conversion result in the circuit
in the left figure.
AI15
VREF or AGND
Figure 2 Crosstalk Measuring Circuit
Definitions of Terms
Resolution
The minimum distinguishable analog value. For 10 bits, 210=1024, i.e. (VREF–AGND) ÷ 1024.
Linearity error
The variance between the ideal conversion characteristics as a 10-bit A/D converter and the
actual conversion characteristics. (Quantized error is therefore not included.)
In the ideal conversion, a voltage between VREF and AGND is divided into 1,024 equal steps.
Differential linearity error
The smoothness of the conversion. The width of analog input voltage corresponding to the
change by one bit of digital output is 1 LSB=(VREF–AGND) ÷ 1024 ideally. The variance
between this ideal bit size and bit size at arbitrary point in the conversion range.
Zero scale error
The variance between the ideal conversion characteristics at the switching point of digital
output "000H to 001H" and actual conversion characteristics.
Full scale error
The variance between the ideal conversion characteristics at the switching point of digital
output "3FEH to 3FFH" and actual conversion characteristics.
23/24
¡ Semiconductor
MSM66509/66P509
PACKAGE DIMENSIONS
(Unit : mm)
QFP128-P-2828-0.80-BK
QFP128-P-2828-0.80-ZK
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
Cu alloy
Solder plating
5 mm or more
5.95 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
24/24