OKI MSM66P573-TB

PEDL66573-02
1Semiconductor
MSM66573 Family
This version: Aug. 1999
Previous version: Jun.1999
Preliminary
16-Bit Microcontroller
GENERAL DESCRIPTION
The MSM66573 family of highly functional CMOS 16-bit single chip microcontrollers utilize the nX-8/500S,
Oki's proprietary CPU core.
A wide variety of internal multi-functioned timers provide timer functions such as compare out, capture, event
counter, auto reload, and PWM, and can be used for periodic and timed measurements. In addition to the main
clock and clock gear functions, there is a sub clock (32.768 kHz) that is suitable for low power applications. A
three channel serial interface and a high-speed bus interface that has separate address and data buses and does not
require external address latches are provided as interfaces to external devices.
With a 16-bit CPU core that enables high-speed 16-bit arithmetic computations and a variety of bit processing
functions, this general-purpose microcontroller is optimally suited for Digital Audio devices such as a Mini-Disc
and an MP3 player.
The flash ROM version (MSM66Q573L) programmable with a single 2.4 V (minimum) power supply and flash
ROM version (MSM66Q573) programmable with a single 5 V power supply are also included in the family. These
versions are easily adaptable to sudden specification changes and to new product versions.
APPLICATIONS
Digital Audio Control Systems
PC peripheral Control Systems
Office Electronics Control Systems
ORDERING INFORMATION
Order Code or Product Name
Package
MSM66573L-TB
MSM66573-TB
MSM66Q573L-TB
MSM66Q573-TB
MSM66P573-TB
100-pin plastic TQFP
(TQFP 100-P-1414-0.50-K)
Remark
Low voltage version
(2.4 to 3.6 V)
5V mask ROM version
(4.5 to 5.5 V)
MSM66573L flash ROM
version
MSM66573 flash ROM
version
MSM66573 OTP ROM
version (2.7 to 5.5 V)
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PEDL66573-02
1Semiconductor
MSM66573 Family
FEATURES
Name
Operating temperature
Power supply voltage/
maximum frequency
Minimum instruction
execution time
Internal ROM size
(max. external)
Internal RAM size
(max. external)
I/Oports
Timers
Serial port
A/D converter
External interrupt
Interrrupt priority
Others
OTP ROM version
Flash ROM version
MSM66573L
MSM66573
–30°C to +70°C
VDD=2.4 to 3.6 V/f=14 MHz
VDD=4.5 to 5.5 V/f=30 MHz
143 ns at 14 MHz (2.4 to 3.6 V)
67ns at 30 MHz (4.5 to 5.5 V)
61µs at 32.768 kHz (2.4 to 3.6/4.5 to 5.5 V)
64 KB
(1 MB)
4 KB
(1 MB)
75 I/O pins
(with programmable pull-up resistors)
8 input-only pins
16-bit free running timer × 1ch
Compare out/capture input × 2ch
16-bit timer (auto reload/timer out) × 1ch
8-bit auto reload timer × 1ch
8-bit auto reload timer × 3ch
(also fumctions as serial communication baud rate generator)
Watchdog timer (also functions as 8-bit auto reload timer)
Watch timer (real-time counter) × 1ch
8-bit PWM × 4ch
(can also be used as 16-bit PWM × 2ch)
UART × 1ch
Synchronous × 1ch
UART/ Synchronous × 1ch
10-bit A/D converter, 8-ch multiplexer × 1ch
Non-maskable × 1ch
Maskable × 6ch
3 levels
Separate address and data busses
Bus release function
Dual clocks
MSM66P573 (Max. f = 24 MHz)
MSM66Q573L
MSM66Q573
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PEDL66573-02
1Semiconductor
MSM66573 Family
SPECIAL FEATURES
1. High-performance CPU
The family includes the high-performance CPU, powerful bit manipulation instruction set, full symmetrical
addressing mode, and ROM WINDOW function, and also provides the best optimized C compiler support.
2. A variety of power saving modes
Attaching a 32.768-kHz crystal produces a real-time clock signal from the internal clock timer. Use of a single
clock in place of dual clocks is possible. Switching the CPU clock to this clock signal, 1/2 × main clock, or 1/4 ×
main clock, then produces operation in a low power consumption mode. The clock gear function allows a 1/2 × or
1/4 × main clock to be selected for the CPU operating clock.
The family provides a wide range of standby control functions. In addition to the usual STOP mode that stops the
oscillator, there are the quick restart STOP mode that shuts down the CPU and peripherals but leaves the oscillator
running, and the HALT mode that shuts down the CPU but leaves the peripherals running.
3. MSM66Q573L and MSM66Q573 with flash memory programmable with single power supply
In addition to the regular mask ROM version, the family includes these versions with 64KB of flash memory that
can be programmed using a single power supply. For the MSM66Q573L, an internal booster circuit derives the
necessary program voltage from the device's low (2.4 V min) power supply, and the program voltage for the
MSM66Q573 is provided with a single 5 V power supply.
4. Multifunction, high-precision analog-to-digital converter
The family includes a high-precision 10-bit analog-to-digital converter with eight channels and is ideal for such
analog control functions as processing audio signals, processing sensor inputs, detecting key switch states, and
controlling battery use in portable equipment. Each channel has its own result register readily accessible from the
software. In addition to single-channel conversions, there is also a scan function offering automatic conversion
from the user's choice of starting channel through to the last channel.
5. Multifunction PWM
The family supports both 8- and 16-bit PWM operation. Choosing between the time-base counter output or
overflow from an 8-bit auto-reload timer as the PWM counter clock source provides a wide number of possibilities
over a broad frequency range. The 16-bit PWM configuration supports a high-speed synchronization mode that
generates a high-precision output signal with less ripple suitable for digital-to-analog control applications.
6. Programmable pull-up resistors
Building the pull-up resistors into the chip contributes to overall design compactness. Making them
programmable on a per-bit basis allows complete flexibility in circuit board layout and system design. These
programmable pull-up resistors are available for all I/O pins not already assigned specific functions (such as the
oscillator connection pins).
7. High-speed bus interface
The interface to external devices uses separate data and address buses. This arrangement permits rapid bus access
for controlling the system from the microcontroller.
8. Wide support for external interrupts
There are a total of seven interrupt channels for use in communicating with external devices: six for maskable
interrupts and one for non-maskable interrupts.
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PEDL66573-02
1Semiconductor
MSM66573 Family
BLOCK DIAGRAM
TM0OUT
TM0EVT
16 bit Timer0
CLKOUT
XTOUT
Peripheral
RXD0
TXD0
RXC0
SIO0
(UART)
TM3OUT
TM3EVT
8 bit Timer3/BRG
RXD1
TXD1
RXC1
TXC1
SIO1
(UART/SYNC)
TM4OUT
8 bit Time4/BRG
SIOI3
SIOO3
SIOCK3
SIO3
(SYNC)
TM5EVT
8 bit Timer5/BRG
CPU Core
System
Control
ALU
Control
Registers
ALU Control
ACC
Memory Control
Pointing Registers
Local Registers
8 bit PWM0
8 bit PWM1
CPCM0
CPCM1
CAP/CMP
NMI
EXINT0
to
EXINT5
RTC
10 bit A/D
Converter
Interrupt
Instruction
Decoder
ROM 64K
TBC
16 bit FRC
VREF
AGND
AI0 to AI7
PC
Port Control
8 bit Timer9
LRB
Bus Port Control
8 bit Timer6/WDT
TM9OUT
TM9EVT
PSW
DSR TSR CSR
RAM 4K
PWMOUT0
PWMOUT2
PWMOUT1
PWMOUT3
SSP
XT0
XT1
OSC0
OSC1
HOLD
HLDACK
RES
EA
PSEN
RD
WR
WAIT
D0
to
D7
A0
to
A19
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
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PEDL66573-02
1Semiconductor
MSM66573 Family
80
85
90
100
1
75
5
70
10
65
15
60
20
55
50
45
40
35
30
25
P1-7/A15
P1-6/A14
P1-5/A13
P1-4/A12
P1-3/A11
P1-2/A10
P1-1/A9
P1-0/A8
P4-7/A7
P4-6/A6
P4-5/A5
P4-4/A4
P4-3/A3
P4-2/A2
P4-1/A1
P4-0/A0
GND
P0-7/D7
P0-6/D6
P0-5/D5
P0-4/D4
P0-3/D3
P0-2/D2
P0-1/D1
P0-0/D0
P6-6
P6-7
P5-4/CPCM0
P5-5/CPCM1
P5-6/TM0OUT
P5-7/TM0EVT
RES
NMI
EA
VDD
XT0
XT1
GND
OSC0
OSC1
VDD
P11-0/WAIT
P11-1/HOLD
P11-2/CLKOUT
P11-3/XTOUT
P11-6/TM9OUT
P11-7/TM9EVT
P3-1/PSEN
P3-2/RD
P3-3/WR
P10-4
P10-5
TM5EVT/P10-7
RXD1/P8-0
TXD1/P8-1
RXC1/P8-2
TXC1/P8-3
TM4OUT/P8-4
PWM2OUT/P8-6
PWM3OUT/P8-7
PWM0OUT/P7-6
PWM1OUT/P7-7
VDD
GND
HLDACK/P9-7
EXINT4/P9-0
EXINT5/P9-1
P9-2
P9-3
EXINT0/P6-0
EXINT1/P6-1
EXINT2/P6-2
EXINT3/P6-3
P6-4
P6-5
95
P10-3
SIOO3/P10-2
SIOI3/P10-1
SIOCK3/P10-0
TM3EVT/P7-5
TM3OUT/P7-4
RXC0/P7-2
GND
TXD0/P7-1
RXD0/P7-0
AGND
AI7/P12-7
AI6/P12-6
AI5/P12-5
AI4/P12-4
AI3/P12-3
AI2/P12-2
AI1/P12-1
AI0/P12-0
VREF
VDD
A19/P2-3
A18/P2-2
A17/P2-1
A16/P2-0
PIN CONFIGURATION (TOP VIEW)
100-pin Plastic TQFP
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PEDL66573-02
1Semiconductor
MSM66573 Family
85
90
100
1
80
5
75
10
70
15
65
20
60
25
55
50
45
40
35
30
P2-1/A17
P2-0/A16
P1-7/A15
P1-6/A14
P1-5/A13
P1-4/A12
P1-3/A11
P1-2/A10
P1-1/A9
P1-0/A8
P4-7/A7
P4-6/A6
P4-5/A5
P4-4/A4
P4-3/A3
P4-2/A2
P4-1/A1
P4-0/A0
GND
P0-7/D7
P0-6/D6
P0-5/D5
P0-4/D4
P0-3/D3
P0-2/D2
P0-1/D1
P0-0/D0
P3-3/WR
P3-2/RD
P3-1/PSEN
P5-4/CPCM0
P5-5/CPCM1
P5-6/TM0OUT
P5-7/TM0EVT
RES
NMI
EA
VDD
XT0
XT1
GND
OSC0
OSC1
VDD
P11-0/WAIT
P11-1/HOLD
P11-2/CLKOUT
P11-3/XTOUT
P11-6/TM9OUT
P11-7/TM9EVT
SIOI3/P10-1
SIOO3/P10-2
P10-3
P10-4
P10-5
TM5EVT/P10-7
RXD1/P8-0
TXD1/P8-1
RXC1/P8-2
TXC1/P8-3
TM4OUT/P8-4
PWM2OUT/P8-6
PWM3OUT/P8-7
PWM0OUT/P7-6
PWM1OUT/P7-7
VDD
GND
HLDACK/P9-7
EXINT4/P9-0
EXINT5/P9-1
P9-2
P9-3
EXINT0/P6-0
EXINT1/P6-1
EXINT2/P6-2
EXINT3/P6-3
P6-4
P6-5
P6-6
P6-7
95
SIOCK3/P10-0
TM3EVT/P7-5
TM3OUT/P7-4
RXC0/P7-2
GND
TXD0/P7-1
RXD0/P7-0
AGND
AI7/P12-7
AI6/P12-6
AI5/P12-5
AI4/P12-4
AI3/P12-3
AI2/P12-2
AI1/P12-1
AI0/P12-0
VREF
VDD
A19/P2-3
A18/P2-2
PIN CONFIGURATION (TOP VIEW) (continued)
100-pin Plastic QFP
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PEDL66573-02
1Semiconductor
MSM66573 Family
PIN DESCRIPTIONS
In the Type column, “I” indicates an input pin, “O” indicates an output pin, and “I/O” indicates an I/O pin.
Classification
Port
Symbol
P0_0/D0
to
P0_7/D7
P1_0/A8
to
P1_7/A15
P2_0/A16
to
P2_3/A19
P3_1/PSEN
Type
I/O
Primary function
Function
Type
I/O
8-bit I/O port
10 mA sink capability
Pull-up resistors can be
specified for each individual bit
I/O
8-bit I/O port
Pull-up resistors can be
specified for each individual bit
O
External memory access
Address output port
I/O
4-bit I/O port
Pull-up resistors can be
specified for each individual bit
O
External memory access
Address output port
I/O
3-bit I/O port
10 mA sink capability
Pull-up resistors can be
specified for each individual bit
O
External program memory
access
Read strobe output pin
External memory access
Read strobe output pin
External memory access
Write strobe output pin
External memory access
Address output port
P3_2/RD
P5_4/CPCM0
O
O
P3_3/WR
P4_0/A0
to
P4_7/A7
Secondary function
External memory access
Data I/O port
I/O
8-bit I/O port
Pull-up resistors can be
specified for each individual bit
O
I/O
4-bit I/O port
Pull-up resistors can be
specified for each individual bit
I/O
P5_5/CPCM1
I/O
Capture 0 input / Compare
0 output pin
Capture 1 input / Compare
1 output pin
O
Timer 0 timer output pin
I
Timer 0 external event input pin
I
External interrupt 0 input pin
I
External interrupt 1 input pin
P6_2/EXINT2
I
External interrupt 2 input pin
P6_3/EXINT3
I
External interrupt 3 input pin
P6_4 to P6_7
—
P5_6/TM0OUT
P5_7/TM0EVT
P6_0/EXINT0
P6_1/EXINT1
I/O
8-bit I/O port
Pull-up resistors can be
specified for each individual bit
None
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PEDL66573-02
1Semiconductor
Classification
Port
Symbol
P7_0/RXD0
MSM66573 Family
Function
Type
I
Type
Primary function
I/O
7-bit I/O port
Pull-up resistors can be
specified for each individual bit
Secondary function
SIO0 receive data input pin
O
SIO0 transmit data output pin
P7_2/RXC0
I
SIO0 external clock input pin
P7_4/TM3OUT
O
Timer 3 timer output pin
P7_5/TM3EVT
I
Timer 3 external event input pin
P7_6/PWM0OUT
O
PWM0 output pin
O
PWM1 output pin
I
SIO1 receive data input pin
O
SIO1 transmit data output pin
P7_1/TXD0
P7_7/PWM1OUT
P8_0/RXD1
I/O
P8_1/TXD1
7-bit I/O port
Pull-up resistors can be
specified for each individual bit
P8_2/RXC1
I/O
SIO1 receive clock I/O pin
SIO1 transmit clock I/O pin
P8_3/TXC1
I/O
P8_4/TM4OUT
O
Timer 4 timer output pin
P8_6/PWM2OUT
O
PWM2 output pin
P8_7/PWM3OUT
O
I
PWM3 output pin
I
External Interrupt 5 input pin
P9_0/EXINT4
I/O
P9_1/EXINT5
5-bit I/O port
Pull-up resistors can be
specified for each individual bit
External Interrupt 4 input pin
P9_2, P9_3
—
None
P9_7/HLDACK
O
HOLD mode output pin
P10_0/SIOCK3
I/O
7-bit I/O port
Pull-up resistors can be
specified for each individual bit
I/O
SIO3 transmit-receive clock I/O pin
I
SIO3 receive data input pin
P10_2/SIOO3
O
SIO3 transmit data output pin
P10_3 to P10_5
—
None
P10_7/TM5EVT
I
P10_1/SIOCI3
P11_0/WAIT
I/O
6-bit I/O port
10 mA sink capability
Pull-up resistors can be
specified for each individual bit
I
Timer 5 external event input pin
External data memory access
wait input pin
I
HOLD mode request input pin
O
Main clock pulse output pin
P11_3/XTOUT
O
Sub clock pulse output pin
P11_6/TM9OUT
O
Timer 9 timer output pin
P11_7/TM9EVT
P12_0/AI0
to
P12_7/AI7
I
Timer 9 external event input pin
I
A/D converter analog input port
P11_1/HOLD
P11_2/CLKOUT
I
8-bit input port
8/28
PEDL66573-02
1Semiconductor
Classification
Power
supply
Oscillation
Reset
Other
MSM66573 Family
Symbol
VDD
Type
I
GND
I
VREF
AGND
XT0
I
I
I
XT1
O
OSC0
I
OSC1
O
RES
NMI
EA
I
I
I
Function
Power supply pin
Connect all VDD pins to the power supply.
GND pin
Connect all GND pins to GND.
Analog reference voltage pin
Analog GND pin
Sub clock oscillation input pin
Connect to a crystal oscillator of f = 32.768 kHz.
Sub clock oscillation output pin
Connect to a crystal oscillator of f = 32.768 kHz.
The clock output is opposite in phase to XT0.
Main clock oscillation input pin
Connect to a crystal or ceramic oscillator. Or, input an external
clock.
Main clock oscillation output pin
Connect to a crystal or ceramic oscillator.
The clock output is opposite in phase to OSC0.
Leave this pin unconnected when an external clock is used.
Reset input pin
Non-maskable interrupt input pin
External program memory access input pin
If the EA pin is enabled (low level), the internal program memory is
masked and the CPU executes the program code in external
program memory through all address space.
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PEDL66573-02
1Semiconductor
MSM66573 Family
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Digital power supply voltage
VDD
Input voltage
VI
Output voltage
VO
Analog reference voltage
Condition
GND=AGND=0V
Ta=25°C
Rated value
Unit
–0.3 to +7.0
V
–0.3 to VDD+0.3
V
–0.3 to VDD+0.3
V
VREF
–0.3 to VDD+0.3
V
Analog input voltage
VAI
–0.3 to VREF
V
Power dissipation
PD
650
mW
Storage temperature
100-pin TQFP
Ta=70°C
per package
750
mW
—
100-pin QFP
–50 to +150
°C
Condition
MSM66573
fOSC≤30 MHz
MSM66Q573
MSM66573L
fOSC≤14 MHz
MSM66Q573L
Rated value
Unit
TSTG
RECOMMENDED OPERATING CONDITIONS
Parameter
Dogital power supply
voltage
Symbol
VDD
fOSC≤24 MHz
MSM66P573
Analog reference voltage
fOSC≤12 MHz
4.5 to 5.5
2.4 to 3.6
V
4.5 to 5.5
2.7 to 3.6
VREF
—
VDD–0.3 to VDD
V
Analog input voltage
VAI
—
AGND to VREF
V
Memory hold voltage
VDDH
fOSC=0Hz
MSM66573
VDD=4.5 to 5.5 V
MSM66Q573
MSM66573L
VDD=2.4 to 3.6 V
MSM66Q573L
2.0 to 5.5
V
Operating frequency
fOSC
MSM66P573
Ambient temperature
Ta
N
2 to 24
VDD=2.7 to 3.6 V
2 to 12
—
TTL load
2 to 14
VDD=4.5 to 5.5 V
MOS load
Fan out
2 to 30
P0, P3, P11
P1, P2, P4, P5,
P6, P7, P8, P9, P10
MHz
–30 to +70
°C
20
—
6
—
1
—
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PEDL66573-02
1Semiconductor
MSM66573 Family
ALLOWABLE OUTPUT CURRENT VALUES
MSM66573L/Q573L (VDD=2.4 to 3.6 V, Ta=–30 to +70°C)
MSM66573/Q573 (VDD=4.5 to 5.5 V, Ta=–30 to +70°C)
MSM66P573 (VDD=2.7 to 3.6V/4.5 to 5.5 V, Ta=–30 to +70°C)
Parameter
“H” output pin (1 pin)
“H” output pins (sum total)
“L” output pin (1 pin)
Pin
Symbol
Min.
Typ.
Max.
All output pins
Sum total of all output
pins
IOH
—
—
–2
∑ IOH
—
—
–40
IOL
—
—
P0, P3, P11
Other ports
10
5
80
Sum total of P0, P3, P11
Unit
mA
Sum total of P1, P2, P4
“L” output pins (sum total)
Sum total of P5, P6, P9
Sum total of P7, P8, P10
Sum total of all output
pins
∑ IOL
—
—
50
140
[Note]
Connect the power supply voltage to all VDD pins and the ground voltage to all GND pins.
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PEDL66573-02
1Semiconductor
MSM66573 Family
ELECTRICAL CHARACTERISTICS
DC Characteristics 1 (VDD=4.5 to 5.5 V)
MSM66573/Q573/P573 (VDD=4.5 to 5.5 V, Ta=–30 to +70°C)
Parameter
Symbol
Condition
Min.
Typ.
Max.
0.44 VDD
—
VDD+0.3
0.80 VDD
—
VDD+0.3
–0.3
—
0.16 VDD
–0.3
—
0.2 VDD
IO=–400 µA
VDD–0.4
—
—
IO=–2.0 mA
VDD–0.6
—
—
IO=–200 µA
VDD–0.4
—
—
IO=–2.0 mA
VDD–0.6
—
—
IO=3.2 mA
—
—
0.4
“H” input voltage
*1
“H” input voltage
*2, *3, *4, *5, *6, *7
VIH
—
“L” input voltage
*1
“L” input voltage
*2, *3, *4, *5, *6, *7
VIL
—
“H” output voltage
*1, *4
VOH
“H” output voltage
*2
“L” output voltage
*1, *4
VOL
“L” output voltage
*2
IO=10.0 mA
—
—
0.8
IO=1.6 mA
—
—
0.4
IO=5.0 mA
—
—
0.8
—
—
1/–1
—
—
1/–250
—
—
15/–15
Input leakage current*3, *6
Input current
*5
IIH/IIL
VI=VDD/0 V
Unit
V
µA
Input current
*7
output leakage current
*1, *2, *4
ILO
VO=VDD/0 V
—
—
±10
µA
Pull-up resistance
Rpull
VI= 0 V
25
50
100
kΩ
Input capacitance
CI
—
5
—
Output capacitance
CO
—
7
—
Analog reference supply
current
IREF
During A/D operation
—
—
4
mA
When A/D is stopped
—
—
10
µA
*1:
*2:
*3:
*4:
f=1 MHz, Ta=25°C
Applicable to P0
Applicable to P1, P2, P4, P5, P6, P7, P8, P9, P10
Applicable to P12
Applicable to P3, P11
*5:
*6:
*7:
pF
Applicable to RES
Applicable to EA, NMI
Applicable to OSC0
12/28
PEDL66573-02
1Semiconductor
MSM66573 Family
Supply current (VDD=4.5 to 5.5 V)
• MSM66573
(VDD=4.5 to 5.5 V, Ta=–30 to +70°C)
Mode
Symbol
Condition
Min.
Typ.
Max.
Unit
f=30 MHz, No Load
—
36
55
mA
CPU operation mode
IDD
f=32.768 kHz, No Load
—
60
160
µA
HALT mode
IDDH
f=30 MHz, No Load
—
23
35
mA
—
5
110
IDDS
XT is used*
XT is not
used*
OSC is stopped, XT is not
used
VDD=2 V, Ta=25°C*
—
1
100
—
0.2
10
Condition
Min.
Typ.
Max.
f=30 MHz, No Load
—
42
70
OSC is
stopped
STOP mode
µA
*: Ports used as inputs are at VDD or 0 V. Other ports are unloaded.
• MSM66Q573
(VDD=4.5 to 5.5 V, Ta=–30 to +70°C)
Mode
Symbol
Unit
mA
CPU operation mode
IDD
f=32.768 kHz, No Load
—
60
160
µA
HALT mode
IDDH
f=30 MHz, No Load
—
24
40
mA
—
5
110
IDDS
XT is used*
XT is not
used*
OSC is stopped, XT is not
used
VDD=2 V, Ta=25°C*
—
1
100
—
0.2
10
Condition
f=24 MHz, No Load
Min.
—
Typ.
60
Max.
80
f=32.768 kHz, No Load
—
114
300
µA
mA
OSC is
stopped
STOP mode
µA
*: Ports used as inputs are at VDD or 0 V. Other ports are unloaded.
• MSM66P573
(VDD=4.5 to 5.5 V, Ta=–30 to +70°C)
Mode
Symbol
CPU operation mode
IDD
HALT mode
IDDH
f=24 MHz, No Load
—
30
40
—
6
120
IDDS
XT is used*
XT is not
used*
OSC is stopped, XT is not
used
VDD=2 V, Ta=25°C*
—
1
100
—
0.2
10
OSC is
stopped
STOP mode
Unit
mA
µA
*: Ports used as inputs are at VDD or 0 V. Other ports are unloaded.
13/28
PEDL66573-02
1Semiconductor
MSM66573 Family
DC Characteristics 2 (VDD=2.4 to 3.6 V)
MSM66573L/Q573L (VDD=2.4 to 3.6 V, Ta=–30 to +70°C)
MSM66P573 (VDD=2.7 to 3.6 V, Ta=–30 to +70°C)
Parameter
Symbol
Condition
“H” input voltage
*1
“H” input voltage
*2, *3, *4, *5, *6, *7
VIH
—
“L” input voltage
*1
“L” input voltage
*2, *3, *4, *5, *6, *7
VIL
—
“H” output voltage
*1, *4
VOH
“H” output voltage
*2
“L” output voltage
*1, *4
VOL
“L” output voltage
*2
Min.
0.44VDD
Typ.
—
Max.
VDD+0.3
0.80VDD
—
VDD+0.3
–0.3
—
0.16 VDD
–0.3
—
0.2 VDD
IO=–400 µA
VDD–0.4
—
—
IO=–2.0 mA
VDD–0.8
—
—
IO=–200 µA
VDD–0.4
—
—
IO=–1.0 mA
VDD–0.8
—
—
IO=3.2 mA
—
—
0.5
IO=5.0 mA
—
—
0.9
IO=1.6 mA
—
—
0.5
IO=2.5 mA
—
—
0.9
—
—
1/–1
—
—
1/–250
—
—
15/–15
Input leakage current*3, *6
Input current
*5
IIH/IIL
VI=VDD/0 V
Unit
V
µA
Input current
*7
output leakage current
*1, *2, *4
ILO
VO=VDD/0 V
—
—
±10
µA
Pull-up resistance
Rpull
VI= 0 V
40
100
200
kΩ
—
5
—
—
7
—
During A/D operation
—
—
2
mA
When A/D is stopped
—
—
5
µA
Input capacitance
CI
Output capacitance
CO
Analog reference supply
current
IREF
*1:
*2:
*3:
*4:
f=1 MHz, Ta=25°C
Applicable to P0
Applicable to P1, P2, P4, P5, P6, P7, P8, P9, P10
Applicable to P12
Applicable to P3, P11
pF
*5: Applicable to RES
*6: Applicable to EA, NMI
*7: Applicable to OSC0
14/28
PEDL66573-02
1Semiconductor
MSM66573 Family
Supply current (VDD=2.4 to 3.6 V)
• MSM66573L
(VDD=2.4 to 3.6 V, Ta=–30 to +70°C)
Mode
Symbol
CPU operation mode
IDD
HALT mode
IDDH
Condition
Min.
Typ.
Max.
Unit
f=14 MHz, No Load
—
12
20
mA
f=32.768 kHz, No Load
f=14 MHz, No Load
—
30
130
µA
—
7
11
mA
XT is used*
XT is not
used*
OSC is stopped, XT is not
used
VDD=2 V, Ta=25°C*
—
2
110
—
1
100
—
0.2
10
OSC is
stopped
STOP mode
IDDS
µA
*: Ports used as inputs are at VDD or 0 V. Other ports are unloaded.
• MSM66Q573L
(VDD=2.4 to 3.6 V, Ta=–30 to +70°C)
Mode
Symbol
f=14 MHz, No Load
Condition
Min.
—
Typ.
13
Max.
22
Unit
mA
CPU operation mode
IDD
f=32.768 kHz, No Load
—
30
130
µA
HALT mode
IDDH
f=14 MHz, No Load
—
7
11
mA
—
3
110
IDDS
XT is used*
XT is not
used*
OSC is stopped, XT is not
used
VDD=2 V, Ta=25°C*
—
1
100
—
0.2
10
OSC is
stopped
STOP mode
µA
*: Ports used as inputs are at VDD or 0 V. Other ports are unloaded.
• MSM66P573
(VDD=2.7 to 3.6 V, Ta=–30 to +70°C)
Mode
Symbol
Condition
f=12 MHz, No Load
Min.
—
Typ.
17
Max.
24
f=32.768 kHz, No Load
—
65
160
µA
mA
CPU operation mode
IDD
HALT mode
IDDH
f=12 MHz, No Load
—
8
12
—
3
110
IDDS
XT is used*
XT is not
used*
OSC is stopped, XT is not
used
VDD=2 V, Ta=25°C*
—
1
100
—
0.2
10
OSC is
stopped
STOP mode
Unit
mA
µA
*: Ports used as inputs are at VDD or 0 V. Other ports are unloaded.
15/28
PEDL66573-02
1Semiconductor
MSM66573 Family
AC Characteristics 1 (VDD = 4.5 to 5.5 V)
(1) External program memory control
MSM66573/Q573/P573 (VDD=4.5 to 5.5 V, Ta=–30 to +70°C)
Parameter
Symbol
tcyc
Min.
33.3
Max.
—
tφWH
13
—
Clock pulse width (LOW level)
tφWL
13
—
PSEN pulse width
tPW
2tφ–15
—
PSEN pulse delay time
tPD
Address setup time
tAS
Address hold time
tAH
Cycle time
Clock pulse width (HIGH level)
Condition
fOSC=30 MHz
CL=50 pF
—
45
tφ–25
—
0
—
*1
Instruction setup time
tIS
25
Instruction hold time
tIH
0
—
tACC
—
3tφ–65*2
Read data access time
Unit
ns
—
Note: t =tcyc/2
*1: MSM66P573=30
*2: MSM66P573=3t –70
tcyc
CPUCLK
PSEN
tφWH
tφWL
tPD
tPW
PC0 to 19
A0 to A19
tAS
tAH
INST0 to 7
D0 to D7
tACC
tIS
tIH
Bus timing during no wait cycle time
16/28
PEDL66573-02
1Semiconductor
MSM66573 Family
(2) External data memory control
MSM66573/Q573/P573 (VDD=4.5 to 5.5 V, Ta=–30 to +70°C)
Parameter
Symbol
tcyc
Cycle time
Condition
fOSC=30 MHz
Min.
33.3
Max.
—
13
—
Clock pulse width (HIGH level)
tφWH
Clock pulse width (LOW level)
tφWL
13
—
RD pulse width
tRW
2tφ–15
—
WR pulse width
tWW
2tφ–15
—
RD pulse delay time
tRD
—
45
WR pulse delay time
tWD
—
45
Address setup time
tAS
tφ–25
—
Address hold time
tAH
tφ–3
—
tRS
*1
—
Read data setup time
CL=50 pF
25
Read data hold time
tRH
0
—
Read data access time
tACC
—
3tφ–65*2
Write data setup time
tWS
2tφ–30
—
Write data hold time
tWH
tφ–3
—
Unit
ns
Note: t =tcyc/2
*1: MSM66P573=30
*2: MSM66P573=3t –70
tcyc
CPUCLK
RD
tφWH
tφWL
tRD
tRW
RAP0 to 19
A0 to A19
tAS
tAH
DIN0 to 7
D0 to D7
tACC
tRS
tRH
WR
tWD
tWW
RAP0 to 19
A0 to A19
tAS
D0 to D7
tAH
DOUT0 to 7
tWS
tWH
Bus timing during no wait cycle time
17/28
PEDL66573-02
1Semiconductor
MSM66573 Family
(3) Serial port control
Master mode
MSM66573/Q573/P573 (VDD=4.5 to 5.5 V, Ta=–30 to +70°C)
Parameter
Symbol
tcyc
Cycle time
Serial clock cycle time
tSCKC
Output data setup time
tSTMXS
Output data hold time
tSTMXH
Condition
fOSC=30 MHz
Min.
33.3
CL=50 pF
Max.
—
4tcyc
—
2tφ–5
—
5tφ–10
—
Input data setup time
tSRMXS
13
—
Input data hold time
tSRMXH
0
—
Unit
ns
Note: tφ=tcyc/2
tcyc
CPUCLK
TXC/
RXC
tSCKC
SDOUT
(TXD)
tSTMXH
tSTMXS
SDIN
(RXD)
tSRMXS
tSRMXH
18/28
PEDL66573-02
1Semiconductor
MSM66573 Family
Slave mode
MSM66573/Q573/P573 (VDD=4.5 to 5.5 V, Ta=–30 to +70°C)
Parameter
Cycle time
Symbol
Condition
Min.
Max.
tcyc
fOSC=30 MHz
33.3
—
4tcyc
—
2tφ–15
—
4tφ–10
—
tSCKC
Serial clock cycle time
Output data setup time
tSTMXS
Output data hold time
tSTMXH
CL=50 pF
Input data setup time
tSRMXS
13
—
Input data hold time
tSRMXH
3
—
Unit
ns
Note: tφ=tcyc/2
tcyc
CPUCLK
TXC/
RXC
tSCKC
SDOUT
(TXD)
tSTMXH
tSTMXS
SDIN
(RXD)
tSRMXS
tSRMXH
Measurement points for AC timing (except the serial port)
VDD
0V
2.0 V
2.0 V
0.8 V
0.8 V
Measurement points for AC timing (the serial port)
VDD
0V
0.8VDD
0.8VDD
0.2VDD
0.2VDD
19/28
PEDL66573-02
1Semiconductor
MSM66573 Family
AC Characteristics 2 (VDD = 2.4 to 3.6 V)
(1) External program memory control
MSM66573L/Q573L (VDD=2.4 to 3.6 V, Ta=–30 to +70°C)
MSM66P573 (VDD=2.7 to 3.6 V, Ta=–30 to +70°C)
Parameter
Symbol
tcyc
Cycle time
Clock pulse width (HIGH level)
Clock pulse width (LOW level)
Min.
71.4
Max.
—
tφWH
28
—
tφWL
28
PSEN pulse width
tPW
PSEN pulse delay time
tPD
Address setup time
tAS
Address hold time
tAH
Condition
fOSC=14 MHz
—
2tφ–25
CL=50 pF
*1
—
—
75
tφ–40
—
-8*2
—
Instruction setup time
tIS
60
—
Instruction hold time
tIH
-8*2
—
tACC
—
3tφ–120
Read data access time
Unit
ns
Note: t =tcyc/2
*1: MSM66P573=2t –20
*2: MSM66P573=0
tcyc
CPUCLK
PSEN
tφWH
tφWL
tPD
tPW
PC0 to 19
A0 to A19
tAS
tAH
INST0 to 7
D0 to D7
tACC
tIS
tIH
Bus timing during no wait cycle time
20/28
PEDL66573-02
1Semiconductor
MSM66573 Family
(2) External data memory control
MSM66573L/Q573L (VDD=2.4 to 3.6 V, Ta=–30 to +70°C)
MSM66P573 (VDD=2.7 to 3.6 V, Ta=–30 to +70°C)
Parameter
Symbol
Condition
Min.
Max.
Cycle time
tcyc
fOSC=14 MHz
71.4
—
Clock pulse width (HIGH level)
tφWH
28
—
Clock pulse width (LOW level)
tφWL
28
—
RD pulse width
tRW
2tφ–25*1
WR pulse width
tWW
2tφ–25
*1
RD pulse delay time
tRD
—
75
WR pulse delay time
tWD
—
75
Address setup time
tAS
tφ–40
—
Address hold time
tAH
tφ–8*2
—
Read data setup time
tRS
60
—
CL=50 pF
Unit
—
—
Read data hold time
tRH
0
—
Read data access time
tACC
—
3tφ–120
Write data setup time
tWS
2tφ–40
—
Write data hold time
tWH
tφ–6
—
ns
Note: t =tcyc/2
*1: MSM66P573=2t –20
*2: MSM66P573=t –6
tcyc
CPUCLK
RD
tφWH
tφWL
tRD
tRW
RAP0 to 19
A0 to A19
tAS
tAH
DIN0 to 7
D0 to D7
tACC
tRS
tRH
WR
tWD
tWW
RAP0 to 19
A0 to A19
tAS
D0 to D7
tAH
DOUT0 to 7
tWS
tWH
Bus timing during no wait cycle time
21/28
PEDL66573-02
1Semiconductor
MSM66573 Family
(3) Serial port control
Master mode
MSM66573L/Q573L (VDD=2.4 to 3.6 V, Ta=–30 to +70°C)
MSM66P573 (VDD=2.7 to 3.6 V, Ta=–30 to +70°C)
Parameter
Symbol
tcyc
Cycle time
Condition
fOSC=14 MHz
Min.
71.4
Max.
—
Serial clock cycle time
tSCKC
4tcyc
—
Output data setup time
tSTMXS
2tφ–10
—
Output data hold time
tSTMXH
5tφ–20
—
CL=50 pF
Input data setup time
tSRMXS
21
—
Input data hold time
tSRMXH
0
—
Unit
ns
Note: t =tcyc/2
tcyc
CPUCLK
TXC/
RXC
tSCKC
SDOUT
(TXD)
tSTMXH
tSTMXS
SDIN
(RXD)
tSRMXS
tSRMXH
22/28
PEDL66573-02
1Semiconductor
MSM66573 Family
Slave mode
MSM66573L/Q573L (VDD=2.4 to 3.6 V, Ta=–30 to +70°C)
MSM66P573 (VDD=2.7 to 3.6 V, Ta=–30 to +70°C)
Parameter
Symbol
tcyc
Cycle time
Serial clock cycle time
tSCKC
Output data setup time
tSTMXS
Output data hold time
tSTMXH
Condition
fOSC=14 MHz
CL=50 pF
Min.
71.4
Max.
—
4tcyc
—
2tφ–30
—
4tφ–20
—
Input data setup time
tSRMXS
21
—
Input data hold time
tSRMXH
7
—
Unit
ns
Note: t =tcyc/2
tcyc
CPUCLK
TXC/
RXC
tSCKC
SDOUT
(TXD)
tSTMXH
tSTMXS
SDIN
(RXD)
tSRMXS
tSRMXH
Measurement points for AC timing of MSM66573L/Q573L
VDD
0V
0.44VDD
0.44VDD
0.16VDD
0.16VDD
Measurement points for AC timing of MSM66P573 (except the serial port)
VDD
2.0 V
2.0 V
0V
0.8 V
0.8 V
Measurement points for AC timing (the serial port)
VDD
0V
0.8VDD
0.8VDD
0.2VDD
0.2VDD
23/28
PEDL66573-02
1Semiconductor
MSM66573 Family
A/D Converter Characteristics 1 (VDD=4.5 to 5.5 V)
MSM6573/Q573/P573 (Ta=–30 to +70°C, VDD=VREF=4.5 to 5.5 V, AGND=GND=0 V)
Parameter
Symbol
Resolution
n
Linearity error
EL
Condition
Min.
Typ.
Max.
Unit
—
10
—
Bit
—
—
±3
—
—
±2
—
—
+3
—
—
–3
Differential Linearity error
ED
Zero scale error
EZS
Full-scale error
EFS
Refer to measurement
circuit 1
Analog input source
impedance
RI≤5 kΩ
tCONV=10.7 µs
Cross talk
ECT
Refer to measurement
circuit 2
—
—
±1
Conversion time
tCONV
Set according to ADTM set
data
10.7
—
—
LSB
µs/ch
A/D Converter Characteristics 2 (VDD=2.4 to 3.6 V)
Parameter
MSM66573L/Q573L (Ta=–30 to +70°C, VDD=VREF=2.4 to 3.6 V, AGND=GND=0 V)
MSM66P573 (Ta=–30 to +70°C, VDD=VREF=2.7 to 3.6 V, AGND=GND=0 V)
Condition
Min.
Typ.
Max.
Unit
Symbol
n
Resolution
—
10
—
—
—
±4
—
—
±3
—
—
+4
—
—
–4
Linearity error
EL
Differential Linearity error
ED
Zero scale error
EZS
Full-scale error
EFS
Refer to measurement
circuit 1
Analog input source
impedance
RI≤5 kΩ
tCONV=27.4 µs
Cross talk
ECT
Refer to measurement
circuit 2
—
—
±2
Conversion time
tCONV
Set according to ADTM set
data
27.4
—
—
Reference
voltage
VREF
0.1
µF
–
+
47
µF
Bit
LSB
s/ch
+5 V
VDD
+
+
0.1
µF
RI
AI0 to AI7
AGND
GND
47
µF
0V
Analog input
CI
RI (impedance of analog input source) ≤5 kΩ
CI ≅ 0.1 µF
Measurement Circuit 1
24/28
PEDL66573-02
1Semiconductor
–
MSM66573 Family
5 kΩ
AI0
+
AI1
Analog input
0.1 µF
to
Cross talk is the difference
between the A/D conversion
results when the same
analog input is applied to
AI0 through AI7 and the A/D
conversion results of the
circuit to the left.
AI7
VREF or AGND
Measurement Circuit 2
Definition of Terminology
1. Resolution
Resolution is the value of minimum discernible analog input.
With 10 bits, since 210 = 1024, resolution of (VREF – AGND) ÷ 1024 is possible.
2. Linearity error
Linearity error is the difference between ideal conversion characteristics and actual conversion c
haracteristics of a 10-bit A/D converter (not including quantization error).
Ideal conversion characteristics can be obtained by dividing the voltage between VREF and AGND into 1024
equal steps.
3. Differential linearity error
Differential linearity error indicates the smoothness of conversion characteristics. Ideally, the range of analog
input voltage that corresponds to 1 converted bit of digital output is 1LSB = (VREF – AGND) ÷ 1024.
Differential error is the difference between this ideal bit size and bit size of an arbitrary point in the conversion
range.
4. Zero scale error
Zero scale error is the difference between ideal conversion characteristics and actual conversion
characteristics at the point where the digital output changes from 000H to 001H.
5. Full-scale error
Full-scale error is the difference between ideal conversion characteristics and actual conversion characteristics
at the point where the digital output changes from 3FEH to 3FFH.
25/28
PEDL66573-02
1Semiconductor
MSM66573 Family
PACKAGE DIMENSIONS
(Unit: mm)
TQFP100-P-1414-0.50-K
Mirror finish
Package material
Epoxy resin
Lead frame material
42 alloy
Pin treatment
Solder plating
Solder plate thickness 5 m or more
Package weight (g)
0.55 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type
packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person on the product
name, package name, pin number, package code and desired mounting conditions (reflow method,
temperature and times).
26/28
PEDL66573-02
1Semiconductor
MSM66573 Family
(Unit: mm)
QFP100-P-1420-0.65-BK
Mirror finish
Package material
Epoxy resin
Lead frame material
42 alloy
Pin treatment
Solder plating
Solder plate thickness
5 m or more
Package weight (g)
1.29 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type
packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person on the product
name, package name, pin number, package code and desired mounting conditions (reflow method,
temperature and times).
27/28
PEDL66573-02
1Semiconductor
MSM66573 Family
NOTICE
1. The information contained herein can change without notice owing to product and/or technical
improvements. Before using the product, please make sure that the information being referred to is
up-to-date.
2.
The outline of action and examples for application circuits described herein have been chosen as
an explanation for the standard action and performance of the product. When planning to use the
product, please ensure that the external conditions are reflected in the actual circuit, assembly, and
program designs.
3.
When designing your product, please use our product below the specified maximum ratings and
within the specified operating ranges including, but not limited to, operating voltage, power
dissipation, and operating temperature.
4.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or
accident, improper handling, or unusual physical or electrical stress including, but not limited to,
exposure to parameters beyond the specified maximum ratings or operation outside the specified
operating range.
5.
Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc.
is granted by us in connection with the use of the product and/or the information and drawings
contained herein. No responsibility is assumed by us for any infringement of a third party’s right
which may result from the use thereof.
6.
The products listed in this document are intended for use in general electronics equipment for
commercial applications (e.g., office automation, communication equipment, measurement
equipment, consumer electronics, etc.). These products are not authorized for use in any system or
application that requires special or enhanced quality and reliability characteristics nor in any system
or application where the failure of such system or application may result in the loss or damage of
property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices,
aerospace equipment, nuclear power control, medical equipment, and life-support systems.
7.
Certain products in this document may need government approval before they can be exported to
particular countries. The purchaser assumes the responsibility of determining the legality of export
of these products and will take appropriate and necessary steps at their own expense for these.
8.
No part of the contents contained herein may be reprinted or reproduced without our prior
permission.
Copyright 1999 Oki Electric Industry Co., Ltd.
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