PEDL66517-03 1Semiconductor ML66517 Family This version: Nov. 1999 Previous version: Aug. 1999 Preliminary 16-Bit Microcontroller GENERAL DESCRIPTION The ML66517 family of highly functional CMOS 16-bit single chip microcontrollers utilizes the nX-8/500S, Oki's proprietary CPU core. Each device includes capture input with an internal digital filter, 10-bit A/D converter, a number of timers, and dedicated 3-phase PWM (6 outputs) function capable of generating and controlling of AC/DC motor driving waveforms. By means of the internal dedicated function for motor control, this general-purpose microcontroller is optimally suited for DC and AC motor control applications for energy saving. And the internal hardware multiplier allows high-speed arithmetic operations to be executed. And also the internal clock multiplication circuit can reduce the source frequency noise so that high-speed operations can be performed. The flash ROM versions (ML66Q517 and ML66Q515) programmable with a single 5V power supply are also included in the family. These versions are easily adaptable to quick specification changes and to new product versions. APPLICATIONS Air conditioner or inverter control Motor control for FA equipment ORDERING INFORMATION Order Code or Product Name ML66514-RB ML66Q515-RB ML66517-GA ML66Q517-GA Package 80-pin plastic QFP (QFP 80-P-1420-0.80-BK) 64-pin plastic SDIP (SDIP 64-P-750-1.778) Remark 5 V mask ROM version 5 V flash ROM version 5 V mask ROM version MSM66517 flash ROM version 1/28 PEDL66517-03 1Semiconductor ML66517 Family FEATURES Name ML66514 ML66517 Operating temperature –40°C to 85°C Power supply voltage/ Maximum frequency VDD = 4.5 to 5.5 V/f = 25 MHz Minimum instruction execution time 80 nsec @25 MHz Internal ROM size (max. external) 32 KB (64 KB) 64 KB (128 KB) Internal RAM size (max. external) 1 KB (64 KB) 2 KB (64 KB) 46 I/O pins (with pull-up resistors, programmable at the bit level), 4 input pins 56 I/O pins (with pull-up resistors, programmable at the bit level), 8 input pins I/O ports 16-bit free-running counter × 1ch Compare output/capture input × 2ch 16-bit timer (auto-reload/timer out) × 1ch 8-bit auto reload timer × 4ch (can also be used as 16-bit auto reload timer × 1ch and 8-bit auto reload timer × 2ch) 8-bit auto reload timer × 2ch Timers Capture × 2ch 8-bit auto reload timer × 2ch (also functions as serial communication baud rate generators) 8-bit auto reload timer × 1ch (also functions as a watchdog timer) 8-bit PWM × 2ch (can also be used as 16-bit PWM × 1ch) Serial port A/D converter Synchronous/UART × 2ch 10-bit × 4ch 10-bit × 8ch 3-phase PWM (AC motor control) Available 3-phase PWM (DC motor control) External interrupt Available Non-Maskable × 1ch Maskable × 2ch Interrupt priority Others Flash ROM version 8-bit PWM × 4ch (can also be used as 16-bit PWM × 2ch) Non-Maskable × 1ch Maskable × 4ch 3 levels Multiplexed address and data buses Multiplication calculator ML66Q515 (ROM = 64 KB, RAM = 2 KB) ML66Q517 2/28 PEDL66517-03 1Semiconductor ML66517 Family SPECIAL FEATURES 1. High-performance CPU The family includes the high-performance CPU, powerful bit manipulation instruction set, full symmetrical addressing mode, and ROM WINDOW function, and also provides the best optimized C compiler support. 2. 3-phase PWM circuit for generating motor drive waveforms The device includes a 16-bit three-phase PWM (six outputs) circuit designed specifically for generating AC three-phase motor or DC three-phase brushless motor drive waveforms. PWM and level outputs can be switched by compare and match circuitry and software, and the compare and match circuitry can switch the outputs in real time. The device has circuitry to fix the three-phase outputs at an inactive level by inputting malfunction signals from a motor at the specific pin. 3. Capture inputs with digital filter filters The device has two channels of capture inputs with 3/4 digital filters. The device is best suited to event interval measurement, pulse width measurement, etc. in a high noise environment such as motor control. An optimum filter can be selected according to noise width since a sampling interval of an input signal can be selected. A digital filter OFF mode can also be selected. 4. High-speed multiplier The device includes a dedicated high-speed multiplier. The calculation time, 16 bits × 16 bits = 32 bits, is 200 ns (f = 25 MHz). 5. Clock multiplication circuit The device includes a clock multiplication circuit in which the clock can be selected as a source clock (PLL OFF), 1 × clock, 2 × clock, or 4 × clock. Therefore, the use of a low frequency oscillator (external clock) allows the device to internally operate at a high speed, which achieves noise reduction and lower power consumption. 6. Flash memory version programmable with a single power supply In addition to the mask ROM versions, the family includes the versions (ML66Q517 and ML66Q515) with 64 KB flash memory that can be programmed with a single 5 V supply. 7. A high-precision A/D converter The device has a high precision 10-bit A/D converter with eight channels. An independent result register for each channel provides easy accessibility by software. The A/D converter is activated in a channel select mode, and automatic conversion is also implemented in a scan mode which scans from any designated channel to the last channel (ch 7). 8. Programmable pull-up resistors Building the pull-up resistors into the chip contributes to overall design compactness. Making them programmable on a per-bit basis allows complete flexibility in circuit board layout and system design. These programmable pull-up resistors are available for all I/O pins not already assigned specific functions (such as the oscillator connection pins). 3/28 PEDL66517-03 1Semiconductor ML66517 Family PWM output switching every 60°° of motor turn using the compare-out timer Compare register value setting CAP input Compare-match generation CAP input PWM-U PWM-UB PWM-V PWM-VB PWM-W PWM-WB PWM Output Timing (DC Motor Control) Period register setting value 16-bit counter value 0000H Underflow counts up the counter PWM-U (U) PWM-UB (U) Set by 8-bit dead-time timer (Only U and U output signals are indicated above) PWM Output Timing (AC Motor Control) 4/28 PEDL66517-03 1Semiconductor ML66517 Family BLOCK DIAGRAM TM0OUT TM0EVT TM1OUT TM1EVT TM2OUT TM2EVT CLKOUT 16-bit Timer0 CPU Core OSC0 8-bit Timer1 System Control 8-bit Timer2 TXD1 RXC1 RES Control Registers RXD1 SIO1 (UART/SYNC) TXC1 ALU Control ACC CLKSEL0 CLKSEL1 ALU Peripheral OSC1 SSP PSW LRB PC TSR CSR 8-bit Timer4/BRG RXD6 TXD6 RXC6 TXC6 SIO6 (UART/SYNC) 8-bit Timer3/BRG 8-bit Timer5 PWM1OUT PWM3OUT EA RAM 2K PWM0OUT PWM2OUT Instruction Decoder 8-bit PWM0 ROM 64K 8-bit PWM1 8-bit Timer9 INACT PWMU PWMUB PWMV PWMVB PWMW PWMWB PSEN ALE Bus Port Control TM5EVT Memory Control Pointing Registers Local Registers AI0 to AI7 AD0 to AD7 A8 to A16 TBC 8-bit Timer6/WDT CAP/CMP 10-bit A/D Converter Port Control CAP 16-bit FRC VREF AGND WR 3-phase PWM CMP CAPF0 CAPF1 CPCMF0 CPCMF1 RD P0 P1 P2 P3 P5 P6 P7 P8 P10 P11 P12 P15 P16 P17 NMI EXINT0 to Interrupt EXINT3 ML66517/ML66Q517 Block Diagram 5/28 PEDL66517-03 1Semiconductor TM0OUT TM0EVT ML66517 Family 16-bit Timer0 CPU Core OSC0 CLKOUT Peripheral System Control RXD1 TXD1 RXC1 8-bit Timer4/BRG RXD6 TXD6 RXC6 TXC6 RES Control Registers TXC1 ALU Control ACC CLKSEL0 CLKSEL1 ALU SIO1 (UART/SYNC) OSC1 SSP PSW LRB PC SIO6 (UART/SYNC) 8-bit Timer3/BRG 8-bit Timer5 8-bit PWM0 PWM1OUT 8-bit PWM1 *1 RAM 1K/2K Instruction Decoder *2 EA ROM 32K/64K 8-bit Timer9 INACT PWMU PWMUB PWMV PWMVB PWMW PWMWB PSEN ALE Bus Port Control PWM0OUT Memory Control Pointing Registers Local Registers 3-phase PWM RD WR AD0 to AD7 A8 to A15 CMP TBC CAP CAP/CMP 16-bit FRC V REF AGND AI4 to AI7 8-bit Timer6/WDT 10-bit A/D Converter NMI EXINT0 to Interrupt Port Control CAPF0 CAPF1 CPCMF0 CPCMF1 P0 P1 P3 P5 P6 P7 P8 P11 P12 P15 P16 P17 EXINT1 *1 ML66Q515 has 2KB RAM, ML66514 has 1KB RAM *2 ML66Q515 has 64KB ROM, ML66514 has 32KB ROM ML66Q515/ML66514 Block Diagram 6/28 PEDL66517-03 1Semiconductor ML66517 Family TXC6/P15-3 RXC6/P15-2 TXD6/P15-1 RXD6/P15-0 GND AGND AI7/P12-7 AI6/P12-6 AI5/P12-5 AI4/P12-4 AI3/P12-3 AI2/P12-2 AI1/P12-1 AI0/P12-0 VREF VDD PIN CONFIGURATION (TOP VIEW) 80 70 65 1 5 60 10 55 15 50 20 45 30 35 P2-0/A16 P1-7/A15 P1-6/A14 P1-5/A13 P1-4/A12 P1-3/A11 P1-2/A10 P1-1/A9 P1-0/A8 GND P3-3/WR P3-2/RD P3-1/PSEN P3-0/ALE P0-7/AD7 P0-6/AD6 P0-5/AD5 P0-4/AD4 P0-3/AD3 P0-2/AD2 P0-1/AD1 P0-0/AD0 EA RES 40 CLKSEL0 CLKSEL1 25 P6-2/EXINT2 P6-3/EXINT3 P6-4/TM1EVT P6-5/TM1OUT P6-6/TM2EVT P6-7/TM2OUT P5-6/TM0OUT P5-7/TM0EVT P10-7/TM5EVT P11-2/CLKOUT GND OSC0 OSC1 VDD RXD1/P8-0 TXD1/P8-1 RXC1/P8-2 TXC1/P8-3 PWM2OUT/P8-6 PWM3OUT/P8-7 PWM0OUT/P7-6 PWM1OUT/P7-7 VDD GND PWMU/P16-0 PWMUB/P16-1 PWMV/P16-2 PWMVB/P16-3 PWMW/P16-4 PWMWB/P16-5 INACT/P16-6 NMI CAPF0/P17-0 CAPF1/P17-1 CPCMF0/P17-2 CPCMF1/P17-3 EXINT0/P6-0 EXINT1/P6-1 75 80-Pin Plastic QFP ML66517/ML66Q517 Pin Configuration 7/28 PEDL66517-03 1Semiconductor TXC6/P15-3 RXC6/P15-2 TXD6/P15-1 RXD6/P15-0 GND AGND AI7/P12-7 AI6/P12-6 AI5/P12-5 AI4/P12-4 VREF VDD A15/P1-7 A14/P1-6 A13/P1-5 A12/P1-4 ML66517 Family 64 60 49 1 48 40 10 33 17 P1-3/A11 P1-2/A10 P1-1/A9 P1-0/A8 GND P3-3/WR P3-2/RD P3-1/PSEN P3-0/ALE P0-7/AD7 P0-6/AD6 P0-5/AD5 P0-4/AD4 P0-3/AD3 P0-2/AD2 P0-1/AD1 30 P17-2/CPCMF0 P17-3/CPCMF1 P6-0/EXINT0 P6-1/EXINT1 P5-6/TM0OUT P5-7/TM0EVT P11-2/CLKOUT GND OSC0 OSC1 VDD CLKSEL0 CLKSEL1 RES EA P0-0/AD0 RXD1/P8-0 TXD1/P8-1 RXC1/P8-2 TXC1/P8-3 PWM0OUT/P7-6 PWM1OUT/P7-7 PWMU/P16-0 PWMUB/P16-1 PWMV/P16-2 PWMVB/P16-3 PWMW/P16-4 PWMWB/P16-5 INACT/P16-6 NMI CAPF0/P17-0 CAPF1/P17-1 64-Pin Plastic QFP ML66Q515/ML66514 Pin Configuration 8/28 PEDL66517-03 1Semiconductor ML66517 Family P3-0/ALE P0-7/AD7 P0-6/AD6 P0-5/AD5 P0-4/AD4 P0-3/AD3 P0-2/AD2 P0-1/AD1 P0-0/AD0 EA RES CLKSEL1 CLKSEL0 VDD OSC1 OSC0 GND P11-2/CLKOUT P5-7/TM0EVT P5-6/TM0OUT P6-1/EXINT1 P6-0/EXINT0 P17-3/CPCMF1 P17-2/CPCMF0 P17-1/CAPF1 P17-0/CAPF0 NMI P16-6/INACT P16-5/PWMWB P16-4/PWMW P16-3/PWMVB P16-2/PWMV PSEN/P3-1 RD/P3-2 WR/P3-3 GND A8/P1-0 A9/P1-1 A10/P1-2 A11/P1-3 A12/P1-4 A13/P1-5 A14/P1-6 A15/P1-7 VDD VREF AI4/P12-4 AI5/P12-5 AI6/P12-6 AI7/P12-7 AGND GND RXD6/P15-0 TXD6/P15-1 RXC6/P15-2 TXC6/P15-3 RXD1/P8-0 TXD1/P8-1 RXC1/P8-2 TXC1/P8-3 PWM0OUT/P7-6 PWM1OUT/P7-7 PWMU/P16-0 PWMUB/P16-1 64-Pin Plastic SDIP ML66Q515/ML66514 Pin Configuration 9/28 PEDL66517-03 1Semiconductor ML66517 Family PIN DESCRIPTIONS In the Type column, “I” indicates an input pin, “O” indicates an output pin, and “I/O” indicates an I/O pin. ML66517/ML66Q517 Pin Descriptions Description Function Symbol Type Primary function Type Secondary function P0_0/AD0 to P0_7/AD7 I/O 8-bit I/O port Pull-up resistors can be specified for each individual bit I/O P1_0/A8 to P1_7/A15 I/O 8-bit I/O port Pull-up resistors can be specified for each individual bit O External memory access Address output port P2_0/A16 I/O 1-bit I/O port Pull-up resistors can be specified for each individual bit O External memory access Address output port 4-bit I/O port 10 mA sink capability Pull-up resistors can be O External memory access Address latch enable signal P3_0/ALE output pin specified for each individual bit P3_1/PSEN O I/O External memory access Address output/data I/O port External program memory access Read strobe output pin P3_2/RD O External memory access Read strobe output pin P3_3/WR O External memory access Write strobe output pin 2-bit I/O port Pull-up resistors can be specified for each individual bit O Timer 0 timer output pin I Timer 0 external event input pin 8-bit I/O port Pull-up resistors can be specified for each individual bit I External interrupt 0 input pin I External interrupt 1 input pin I External interrupt 2 input pin I External interrupt 3 input pin I Timer 1 external event input pin O Timer 1 timer output pin P6_6/TM2EVT I Timer 2 external event input pin P6_7/TM2OUT O Timer 2 timer output pin O PWM0 output pin O PWM1 output pin Port P5_6/TM0OUT P5_7/TM0EVT I/O P6_0/EXINT0 P6_1/EXINT1 P6_2/EXINT2 P6_3/EXINT3 P6_4/TM1EVT I/O P6_5/TM1OUT P7_6/PWM0OUT P7_7PWM1OUT I/O 2-bit I/O port Pull-up resistors can be specified for each individual bit 10/28 PEDL66517-03 1Semiconductor ML66517 Family ML66517/ML66Q517 Pin Descriptions (Continued) Description Function Symbol Primary function Type P8_0/RXD1 6-bit I/O port Pull-up resistors can be specified for each individual bit P8_1/TXD1 P8_2/RXC1 P8_3/TXC1 I/O I SIO1 receive data input pin O SIO1 transmit data output pin I/O SIO1 receive clock I/O pin I/O SIO1 transmit clock I/O pin P8_6/PWM2OUT O PWM2 output pin P8_7PWM3OUT O PWM3 output pin P10_7/TM5EVT I/O 1-bit I/O port Pull-up resistors can be specified I P11_2/CLKOUT I/O 1-bit I/O port Pull-up resistors can be specified O P12_0/AI0 to P12_7/AI7 P15_1/TXD6 P15_2/RXC6 Main clock pulse output pin 4-bit I/O port Pull-up resistors can be I/O P16_0/PWMU specified for each individual bit 7-bit I/O port Pull-up resistors can be specified for each individual bit P16_1/PWMUB P16_2/PWMV A/D converter analog input port I P15_3/TXC6 P16_3/PWMVB Timer 5 external event input pin 8-bit input port I P15_0/RXD6 Port Secondary function Type I/O I SIO6 receive data input pin O SIO6 transmit data output pin I/O SIO6 receive clock I/O pin I/O SIO6 transmit clock I/O pin O 3-phase PWMU output pin O 3-phase PWMUB output pin O 3-phase PWMV output pin O 3-phase PWMVB output pin P16_4/PWMW O 3-phase PWMW output pin P16_5/PWMWB O 3-phase PWMWB output pin P16_6/INACT P17_0/CAPF0 4-bit I/O port Pull-up resistors can be specified for each individual bit P17_1/CAPF1 P17_2/CPCMF0 P17_3/CPCMF1 I/O I Abnormality detect input pin I Capture 0 input pin I Capture 1 input pin I/O I/O Capture 0 input/compare 0 output pin Capture 1 input/compare 1 output pin 11/28 PEDL66517-03 1Semiconductor ML66517 Family ML66517/ML66Q517 Pin Descriptions (Continued) Function Power supply Oscillation Reset Others * Symbol Type Description VDD I Power supply pin Connect all VDD pins to the power supply.* GND I GND pin Connect all GND pins to GND.* VREF I Analog reference voltage pin AGND I Analog GND pin OSC0 I Main clock oscillation input pin Connect to a crystal or ceramic oscillator. Or, input an external clock. OSC1 O Main clock oscillation output pin Connect to a crystal or ceramic oscillator. The clock output is opposite in phase to OSC0. Leave this pin unconnected when an external clock is used. CLKSEL0 I CLKSEL1 I RES I NMI I Non-maskable interrupt input pin I External program memory access input pin If the EA pin is enabled (low level), the internal program memory is masked and the CPU executes the program code in external program memory all address space. EA Clock multiplication factor select pin Clock multiplication factor is selected from source oscillation (PLL OFF), source oscillation × 2, or source oscillation × 4 Reset input pin Each of the family devices has unique pattern routes for the internal power and ground. Connect the power supply voltage to all VDD pins and the ground potential to all GND pins. If a device may have one or more VDD or GND pins to which the power supply voltage or the ground potential is not connected, it can not be guaranteed for normal operation. 12/28 PEDL66517-03 1Semiconductor ML66517 Family ML66Q515/ML66514 Pin Descriptions Description Function Symbol Type Type P0_0/AD0 to P0_7/AD7 I/O 8-bit I/O port Pull-up resistors can be specified for each individual bit I/O P1_0/A8 to P1_7/A15 I/O 8-bit I/O port Pull-up resistors can be specified for each individual bit O 4-bit I/O port 10mA sink capability Pull-up resistors can be specified for each individual bit P3_0/ALE P3_1/PSEN O O I/O Secondary function External memory access Address output/Data I/O port External memory access Address output port External memory access Address latch enable signal output pin External program memory access Read strobe output pin External memory access P3_2/RD O P3_3/WR O External memory access Write strobe output pin P5_6/TIM0OUT P5_7/TIM0EVT Port Primary function 2-bit I/O port Pull-up resistors can be specified for each individual bit O Timer 0 timer output pin I/O I Timer 0 external event input pin 2-bit I/O port Pull-up resistors can be specified for each individual bit I External interrupt 0 input pin I/O I External interrupt 1 input pin 2-bit I/O port Pull-up resistors can be specified for each individual bit O PWM0 output pin I/O O PWM1 output pin 4-bit I/O port Pull-up resistors can be I SIO1 receive data input pin O SIO1 transmit data output pin P6_0/EXINT0 P6_1/EXINT1 P7_6/PWM0OUT P7_7/PWM1OUT P8_0/RXD1 P8_1/TXD1 P8_2/RXC1 I/O specified for each individual bit P8_3/TXC1 P11_2/CLKOUT P12_4/AI4 to P12_7/AI7 I/O P15_2/RXC6 P15_3/TXC6 1-bit I/O port Pull-up resistors can be specified I/O SIO1 receive clock I/O pin I/O SIO1 transmit clock I/O pin Main clock pulse output pin O 4-bit input port I P15_0/RXD6 P15_1/TXD6 Read strobe output pin 4-bit I/O port Pull-up resistors can be I/O A/D converter analog input port I specified for each individual bit I SIO6 receive data input pin O SIO6 transmit data output pin I/O SIO6 receive clock I/O pin I/O SIO6 transmit clock I/O pin 13/28 PEDL66517-03 1Semiconductor ML66517 Family ML66Q515/ML66514 Pin Descriptions (Continued) Description Function Symbol Type P16_0/PWMU P16_1/PWMUB P16_2/PWMV P16_3/PWMVB Port I/O Primary function 7-bit I/O port Pull-up resistors can be specified for each individual bit Type Secondary function O 3-phase PWMU output pin O 3-phase PWMUB output pin O 3-phase PWMV output pin O 3-phase PWMVB output pin P16_4/PWMW O 3-phase PWMW output pin P16_5/PWMWB O 3-phase PWMWB output pin I Abnormality detect input pin I Capture 0 input pin P16_6/INACT P17_0/CAPF0 P17_1/CAPF1 P17_2/CPCMF0 P17_3/CPCMF1 I/O 4-bit I/O port Pull-up resistors can be specified for each individual bit I Capture 1 input pin I/O Capture 0 input/compare 0 output pin I/O Capture 1 input/compare 1 output pin 14/28 PEDL66517-03 1Semiconductor ML66517 Family ML66Q515/ML66514 Pin Descriptions (Continued) Function Power supply Oscillation Reset Others * Symbol Type Description VDD I Power supply pin Connect all VDD pins to the power supply.* GND I GND pin Connect all GND pins to GND.* VREF I Analog reference voltage pin AGND I Analog GND pin OSC0 I Main clock oscillation input pin Connect to a crystal or ceramic oscillator. Or, input an external clock. OSC1 O Main clock oscillation output pin Connect to a crystal or ceramic oscillator. The clock output is opposite in phase to OSC0. Leave this pin unconnected when an external clock is used. CLKSEL0 I CLKSEL1 I RES I NMI I Non-maskable interrupt input pin I External program memory access input pin If the EA pin is enabled (low level), the internal program memory is masked and the CPU executes the program code in external program memory all address space. EA Clock multiplication factor select pin Clock multiplication factor is selected from source oscillation (PLL OFF), source oscillation × 2, or source oscillation × 4 Reset input pin Each of the family devices has unique pattern routes for the internal power and ground. Connect the power supply voltage to all VDD pins and the ground potential to all GND pins. If a device may have one or more VDD or GND pins to which the power supply voltage or the ground potential is not connected, it can not be guaranteed for normal operation. 15/28 PEDL66517-03 1Semiconductor ML66517 Family ABSOLUTE MAXIMUM RATINGS Parameter Digital power supply voltage Symbol Rating Unit –0.3 to +7.0 V –0.3 to VDD +0.3 V –0.3 to VDD +0.3 V VREF –0.3 to VDD +0.3 V VAI –0.3 to VREF V VDD Input voltage VI Output voltage VO Analog reference voltage Analog input voltage Condition GND = AGND = 0 V Ta = 25°C 80-pin QFP Power dissipation Storage temperature PD Ta = 85°C per package TSTG 600 64-pin QFP 520 64-pin SDIP 1280 — mW –50 to +150 °C Range Unit RECOMMENDED OPERATING CONDITIONS Parameter Symbol Condition Digital power supply voltage VDD fOSC ≤ 25 MHz 4.5 to 5.5 V Analog reference voltage VREF — VDD – 0.3 to VDD V Analog input voltage VAI — AGND to VREF V Memory hold voltage VDDH fOSC = 0 Hz 2.0 to 5.5 V Internal operating frequency fOSC PLL (multiplier) OFF 2 to 25 PLL (multiplier) ON 20 to 25 Ambient temperature Ta — –40 to +85 °C MOS load 20 — Fan out N TTL load P3 6 P0, P16 2 P1, P2, P5 to P8, P10, P11, P15, P17 MHz — 1 16/28 PEDL66517-03 1Semiconductor ML66517 Family ALLOWABLE OUTPUT CURRENT (1) ML66517/ML66Q517 (80-pin QFP) (VDD = 4.5 to 5.5 V, Ta = –40 to +85°C) Parameter “H” output pin (1 pin) “H” output pins (sum total) “L” output pin (1 pin) Pin Symbol Min. Typ. Max. All input pins IOH — — –2 Sum total of all output pins ∑IOH — — –50 — — 10 — — 5 P3 Other ports IOL Sum total of P0, P3 60 Unit mA Sum total of P1, P2 “L” output pins (sum total) Sum total of P7, P8, P15 Sum total of P5, P6, P10, P11, P16, P17 ∑IOL — — 50 100 Sum total of all output pins (2) ML66Q515/ML66514 (64-pin QFP/SDIP) (VDD = 4.5 to 5.5 V, Ta = –40 to +85°C) Parameter “H” output pin (1 pin) “H” output pins (sum total) “L” output pin (1 pin) Pin Symbol Min. Typ. Max. All input pins IOH — — –2 Sum total of all output pins ∑IOH — — –20 — — 10 — — 5 P3 Other ports IOL Sum total of P0, P3 “L” output pins (sum total) 50 Unit mA P1 Sum total of P5 to P8, P11, P15, P17 Sum total of all output pins ∑IOL — — 30 60 Note: Each of the family devices has unique pattern routes for the internal power and ground. Connect the power supply voltage to all VDD pins and the ground potential to all GND pins. If a device may have one or more VDD or GND pins to which the power supply voltage or the ground potential is not connected, it can not be guaranteed for normal operation. 17/28 PEDL66517-03 1Semiconductor ML66517 Family ELECTRICAL CHARACTERISTICS DC Characteristics (VDD = 4.5 to 5.5 V, Ta = –40 to +80°C) Parameter Symbol “H” input voltage *1 “H” input voltage *2 to *8 “L” input voltage *1 “L” input voltage *2 to *8 “H” output voltage *1, *4, *5 VIH — VIL — VOH “H” output voltage *2 “L” output voltage *1, *5 “L” output voltage *4 “L” output voltage *2 Condition VOL *6 Input current *8 Output leakage current IIH/IIL Typ. Max. — VDD + 0.3 0.80 VDD — VDD + 0.3 –0.3 — 0.16 VDD –0.3 — 0.2 VDD IO = –400 µA VDD – 0.4 IO = –2.0 mA VDD – 0.6 — — IO = –200 µA VDD – 0.4 — — IO = –2.0 mA VDD – 0.6 — — IO = 3.2 mA — — 0.4 IO = 5.0 mA — — 0.8 IO = 3.2 mA — — 0.4 — — 1.0 IO = 1.6 mA — — 0.4 IO = 5.0 mA — — 0.8 — — 1/–1 VI =VDD/0 V Unit — IO = 10.0 mA Input leakage current*3, *7 Input current Min. 0.44 VDD — — 1/–250 — — 15/–15 V µA ILO VO =VDD/0 V — — ± 10 µA Pull-up resistance Rpull VI = 0 V 25 50 100 kΩ Input capacitance CI — 5 — Output capacitance CO — 7 — Analog reference supply current IREF During A/D operation — — 4 mA When A/D is stopped — — 10 µA Supply current (STOP mode) IDDS 20 900 1 50 Supply current (HALT mode) IDDH — 30 40 Supply current IDD — 40 60 *1, *2, *4, *5 f = 1 MHz, Ta = 25°C ML66Q517/Q515 *9 ML66517/514 *9 f = 25 MHz, No load — pF µA mA *1: Applicable to P0 *2: Applicable to P1, P2, P6, P7, P8, P10, P11, P15, P17 *3: Applicable to P12 *4: Applicable to P3 *5: Applicable to P16 *6: Applicable to RES *7: Applicable to EA, NMI, CLKSEL0, CLKSEL1 *8: Applicable to OSC0 *9: Ports used as inputs are at VDD or 0 V. Other ports are unloaded. 18/28 PEDL66517-03 1Semiconductor ML66517 Family AC Characteristics (1) External program memory control (VDD = 4.5 to 5.5 V, Ta = –40 to +85°C) Parameter Symbol Condition Min. Max. Cycle time tcyc fOSC = 25 MHz 40 — Clock pulse width (HIGH level) tφWH 13 — Clock pulse width (LOW level) tφWL 13 — ALE pulse width tAW 2tφ – 10 — PSEN pulse width tPW 2tφ – 18 — PSEN pulse delay time tPAD tφ – 5 — Low address setup time tALS 2tφ – 15 — Low address hold time tALH tφ – 13 — High address setup time tAHS 3tφ – 30 — High address hold time CL = 50 pF Unit ns tAHH –8 — Instruction setup time tIS 30 — Instruction hold time tIH –8 tφ – 3 Note: tφ = tcyc/2 tcyc CPUCLK tφWH ALE tφWL tAW PSEN tPAD AD0 to AD7 PC0 to 7 tALS A8 to A16 tPW INST0 to 7 tALH tIS tIH PC8 to 16 tAHS tAHH Bus timing during no wait cycle time 19/28 PEDL66517-03 1Semiconductor ML66517 Family (2) External data memory control (VDD = 4.5 to 5.5 V, Ta = –40 to +85°C) Symbol Condition Min. Max. Cycle time Parameter tcyc fOSC = 25 MHz 40 — Clock pulse width (HIGH level) tφWH 13 — Clock pulse width (LOW level) tφWL 13 — ALE pulse width tAW 2tφ – 10 — RD pulse width tRW 2tφ – 18 — WR pulse width tWW 2tφ – 18 — RD pulse delay time tRAD tφ – 5 — WR pulse delay time tWAD Low address setup time tALS CL = 50 pF tφ – 5 — 2tφ – 15 — Unit ns Low address hold time tALH tφ – 13 — High address setup time tAHS 3tφ – 30 — High address hold time tAHH tφ – 3 — Read data setup time tRS 30 — Read data hold time tRH 0 tφ – 3 Write data setup time tWS 2tφ – 30 — Write data hold time tWH tφ – 3 — Note: tφ = tcyc/2 tcyc CPUCLK tφWL tφWH ALE tAW RD tRAD AD0 to AD7 RAP0 to 7 tALS A8 to A15 tRW DIN0 to 7 tRS tALH tRH RAP8 to 15 tAHH tAHS WR tWAD AD0 to AD7 RAP0 to 7 tALS A8 to A15 tWW DOUT0 to 7 tALH tWS tWH RAP8 to 15 tAHS tAHH Bus timing during no wait cycle time 20/28 PEDL66517-03 1Semiconductor ML66517 Family (3) Serial port control Master mode (Clock synchronous serial port) (VDD = 4.5 to 5.5 V, Ta = –40 to +85°C) Parameter Cycle time Symbol Condition Min. Max. tcyc fOSC = 25 MHz 40 — Serial clock cycle time tSCKC 4 tcyc — Output data setup time tSTMXS 2tφ – 5 — Output data hold time tSTMXH 5tφ – 10 — Input data setup time tSRMXS 13 — Input data hold time tSRMXH 0 — CL = 50 pF Unit ns Note: tφ = tcyc/2 tcyc CPUCLK TXC/RXC tSCKC SDOUT (TXD) tSTMXH tSTMXS SDIN (RXD) tSRMXS tSRMXH 21/28 PEDL66517-03 1Semiconductor ML66517 Family Slave mode (Clock synchronous serial port) (VDD = 4.5 to 5.5 V, Ta = –40 to +85°C) Parameter Cycle time Symbol Condition Min. Max. tcyc fOSC = 25 MHz 40 — Serial clock cycle time tSCKC 4 tcyc — Output data setup time tSTMXS 2tφ – 15 — Output data hold time tSTMXH 4tφ – 10 — CL = 50 pF Input data setup time tSRMXS 13 — Input data hold time tSRMXH 3 — Unit ns Note: tφ = tcyc/2 tcyc CPUCLK TXC/RXC tSCKC SDOUT (TXD) tSTMXH tSTMXS SDIN (RXD) tSRMXS tSRMXH Measurement points for AC timing VDD 0V 0.8 V 0.2 V 0.8 V 0.2 V 22/28 PEDL66517-03 1Semiconductor ML66517 Family A/D Converter Characteristics (Ta = –40 to +85°C, VDD = 4.5 to 5.5 V, AGND = GND = 0 V) Parameter Resolution Symbol Condition Min. Typ. Max. Unit n Refer to measurement — 10 — Bit Linearity error EL circuit 1 — — ±3 Differential linearity error ED — — ±2 Zero scale error EZS Analog input source impedance RI ≤ 5 kΩ — — +3 Full-scale error EFS tCONV = 10.7 µs — — –3 Cross talk ECT — — ±1 Conversion time tCONV 10.7 — — Refer to measurement circuit 2 Set according to ADTM set data VREF Reference voltage – 0.1 µF + 47 µF AI0 to AI7 AGND + µs/ch +5 V VDD + RI LSB 0.1 µF 47 µF GND 0V Analog input CI RI (impedance of analog input source) ≤5 kΩ CI ≅ 0.1 µF Measurement Circuit 1 – 5 kΩ AI0 + AI1 Analog input 0.1 µF to Cross talk is the difference between the A/D conversion results when the same analog input is applied to AI0 through AI7 and the A/D conversion results of the circuit to the left. AI7 VREF or AGND Measurement Circuit 2 23/28 PEDL66517-03 1Semiconductor ML66517 Family Definition of Terminology 1. Resolution Resolution is the value of minimum discernible analog input. With 10 bits, since 210 = 1024, resolution of (VREF – AGND) ÷ 1024 is possible. 2. Linearity error Linearity error is the difference between ideal conversion characteristics and actual conversion characteristics of a 10-bit A/D converter (not including quantization error). Ideal conversion characteristics can be obtained by dividing the voltage between VREF and AGND into 1024 equal steps. 3. Differential linearity error Differential linearity error indicates the smoothness of conversion characteristics. Ideally, the range of analog input voltage that corresponds to 1 converted bit of digital output is 1LSB = (VREF – AGND) ÷ 1024. Differential error is the difference between this ideal bit size and bit size of an arbitrary point in the conversion range. 4. Zero scale error Zero scale error is the difference between ideal conversion characteristics and actual conversion characteristics at the point where the digital output changes from 000H to 001H. 5. Full-scale error Full-scale error is the difference between ideal conversion characteristics and actual conversion characteristics at the point where the digital output changes from 3FEH to 3FFH. 24/28 PEDL66517-03 1Semiconductor ML66517 Family PACKAGE DIMENSIONS (Unit : mm) QFP80-P-1420-0.80-BK MIRROR FINISH Package material Epoxy resin Lead frame material 42 alloy Pin treatment Solder plating Solder plate thicknes 5 m or more Package weight (g) 1.27 TYP. Notes for Mounting the Surface Mount Type Packages The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 25/28 PEDL66517-03 1Semiconductor ML66517 Family (Unit : mm) QFP64-P-1414-0.80-BK MIRROR FINISH Package material Epoxy resin Lead frame material 42 alloy Pin treatment Solder plating Solder plate thickness 5 m or more Package weight (g) 0.87 TYP. Notes for Mounting the Surface Mount Type Packages The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 26/28 PEDL66517-03 1Semiconductor ML66517 Family (Unit : mm) SDIP64-P-750-1.778 Package material Epoxy resin Lead frame material Cu alloy Pin treatment Solder plating Solder plate thickness 5 m or more Package weight (g) 8.70 TYP. 27/28 PEDL66517-03 1Semiconductor ML66517 Family NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 1999 Oki Electric Industry Co., Ltd. 28/28