E2O0012-27-X2 This version: Jan. 1998 MSM82C84A-2RS/GS/JS Previous version: Aug. 1996 ¡ Semiconductor MSM82C84A-2RS/GS/JS ¡ Semiconductor CLOCK GENERATOR AND DRIVER GENERAL DESCRIPTION The MSM82C84A-2RS/GS is a clock generator designed to generate MSM80C86A-10 and MSM80C88A-10 system clocks of 8MHz. Due to the use of silicon gate CMOS technology, standby current is only 40 mA (MAX.), and the power consumption is very low with 16 mA (MAX.) when a 8 MHz clock is generated. FEATURES • Operating frequency of 6 to 24 MHz (CLK output 2 to 8 MHz) • 3 m silicon gate CMOS technology for low power consumption • Built-in crystal oscillator circuit • 3 V to 6 V single power supply • Built-in synchronized circuit for MSM80C86A-10 and MSM80C88A-10 READY and RESET • TTL compatible • Built-in Schmitt trigger circuit (RES input) • 18-pin Plastic DIP (DIP18-P-300-2.54): (Product name: MSM82C84A-2RS) • 20-pin Plastic QFJ (QFJ20-P-S350-1.27): (Product name: MSM82C84A-2JS) • 24-pin Plastic SOP (SOP24-P-430-1.27-K): (Product name: MSM82C84A-2GS-K) FUNCTIONAL BLOCK DIAGRAM RES x1 x2 D C RESET Q Crystal Oscillator OSC F/C 1 3 EFI 1 2 S Y N C CSYNC RDY1 PCLK S Y N C CLK AEN1 AEN2 RDY2 C≠ D CØ Q (F1) D Q READY (F2) ASYNC 1/18 ¡ Semiconductor MSM82C84A-2RS/GS/JS PIN CONFIGURATION (TOP VIEW) 1 18 VCC PCLK 2 17 X1 AEN1 3 16 X2 RDY1 4 15 ASYNC READY 5 14 EFI RDY2 6 13 F/C AEN2 7 12 OSC CLK 8 11 RES GND 9 10 RESET Vcc CSYNC 1 24 PCLK 2 23 X1 NC 3 22 X2 6 19 EFI NC 7 18 NC RDY2 8 17 F/C AEN2 9 16 OSC NC 10 15 NC CLK 11 14 RES GND 12 13 RESET 19 X1 READY 20 VCC ASYNC CSYNC NC 20 1 21 5 PCLK 4 2 AEN1 RDY1 AEN1 24 pin Plastic SOP CSYNC 3 18 pin Plastic DIP 20 pin Plastic QFJ 18 X2 RDY1 4 17 ASYNC READY 5 14 NC CLK OSC 13 NC 8 RES 12 15 F/C RESET 11 AEN2 7 GND 10 16 EFI 9 RDY2 6 (NC not connected) 2/18 ¡ Semiconductor MSM82C84A-2RS/GS/JS ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Condition MSM82C84A-2RS/JS Supply Voltage Input Voltage Output Voltage Storage Temperature Power Dissipation VCC VIN Respect to GND VOUT TSTG — PD Ta = 25°C Unit MSM82C84A-2GS –0.5 to +7 V –0.5 to VCC +0.5 V –0.5 to VCC +0.5 V –55 to +150 °C 0.8 0.7 W OPERATING RANGES Parameter Symbol Range Unit Supply Voltage VCC 3 to 6 V Operating Temperature Top –40 to +85 °C RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min. Typ. Unit Max. Supply Voltage VCC 4.5 5 5.5 V Operating Temperature Top –40 +25 +85 °C "L" Level Input Voltage VIL –0.5 — +0.8 V "H" Level Input Voltage (except RES) "H" Level Input Voltage (RES) VIH — VCC +0.5 V 2.2 0.6*VCC DC CHARACTERISTICS (VCC = 5 V ± 10%, Ta = –40 to 85°C) Parameter Symbol Condition Min. Max. Unit "L" Level Output Voltage (CLK) V OL IOL = 4 mA — 0.4 V "L" Level Output Voltage (Others) VOL IOL = 2.5 mA — 0.4 "H" Output Voltage (CLK) "H" Output Voltage (Others) VOH VCC –0.4 — VOH IOH = –4 mA IOH = –1 mA V V VCC –0.4 — V 0.2*VCC — V RES Input Hysteresis VIHR -VILR Input Leak Current (Except ASYNC) ILI 0 £ VIN £ VCC –1 +1 mA Input Current (ASYNC) ILIA 0 £ VIN £ VCC –100 +10 mA Standby Supply Current ICCS Note 1 — 40 mA Operating Supply Current ICC f = 24 MHz, CL= O PF — 16 mA Input Capacitance CIN f =1 MHz — 7 pF Note: 1. X1 ≥ VCC – 0.2 V, X2 £ 0.2 V F/C ≥ VCC – 0.2 V, ASYNC = VCC or open VIH ≥ VCC – 0.2 V, VIL £ 0.2 V 3/18 ¡ Semiconductor MSM82C84A-2RS/GS/JS AC CHARACTERISTICS (1) Symbol Min. EFI "H" Pulse Width tEHEL EFI "L" Pulse Width tELEH EFI Cycle Time Parameter (VCC = 5 V ± 10%, Ta = –40 to 85°C) Conditions Unit 13 Max. — ns 90% to 90% 17 — ns tELEL 36 — ns 10% to 10% — — 6 24 MHz — Set up Time of RDY 1 or RDY 2 to CLK Falling Edge (Active) tR1VCL 35 — ns ASYNC = High Set up Time of RDY 1 or RDY 2 to CLK Rising Edge (Active) tR1VCH 35 — ns ASYNC = Low Set up Time of RDY 1 or RDY 2 to CLK Falling Edge (Inactive) tR1VCL 35 — ns — Hold Time of RDY 1 or RDY 2 to CLK Falling Edge tCLR1X 0 — ns — Set up Time of ASYNC to CLK Falling Edge tAYVCL 50 — ns — Hold Time of ASYNC to CLK Falling Edge tCLAYX 0 — ns — Set up Time of AEN 1 (AEN 2) to RDY 1 (RDY 2) Rising Edge tA1R1V 15 — ns — Hold Time of AEN 1 (AEN 2) to CLK Falling Edge tCLA1X 0 — ns — Set up Time of CSYNC to EFI Rising Edge tYHEH 20 — ns — Hold Time of CSYNC to EFI Rising Edge tEHYL 10 — ns — CSYNC Pulse Width tYHYL 2 ¥ tELEL — ns — Set up Time of RES to CLK Falling Edge tI1HCL 65 — ns — Hold Time of RES to CLK Falling Edge tCLI1H 20 — ns — tILIH tIHIL — 15 ns — — 15 ns — Crystal Oscillator Frequency Input Rising Edge Time Input Falling Edge Time Output Load Capacitance CLK output CL = 100 pF Others 30 pF Note: Parameters where timing has not been indicated in the above table are measured at VL = 1.5 V and VH = 1.5 V for both inputs and outputs. 4/18 ¡ Semiconductor MSM82C84A-2RS/GS/JS AC CHARACTERISTICS (2) (VCC = 5 V ± 10%, Ta = -40 to 85°C) Parameter CLK Cycle Time Conditions Symbol tCLCL Min. Max. — Unit ns — 125 — ns — ns — 10 ns CLK "H" Pulse Width tCHCL — 1 T +2 3 CLCL CLK "L" Pulse Width tCLCH — 2 T –15 3 CLCL tCH1CH2 tCL2CL1 1.0 V to 3.5 V PCLK "H" Pulse Width tPHPL — TCLCL –20 tPLPH — TCLCL –20 — — ns PCLK "L" Pulse Width Time from READY Falling Edge to CLK Falling Edge tRYLCL — -8 — ns Time from READY Rising Edge to CLK Rising Edge tRYHCH — — ns Delay from CLK Falling Edge to RESET Falling Edge tCLIL — — 40 ns Delay from CLK Falling Edge to PCLK Rising Edge tCLPH — — 22 ns Delay from CLK Falling Edge to PCLK Falling Edge tCLPL — — 22 ns Delay from OSC Falling Edge to CLK Rising Edge tOLCH — –5 22 ns Delay from OSC Falling Edge to CLK Falling Edge tOLCL — 2 35 ns Output Rising Edge Time (Except CLK) tOLOH 0.8 V to 2.2 V — 15 ns Output Falling Edge Time (Except CLK) tOHOL 2.2 V to 0.8 V — 15 ns CLK Rising and Falling Edge Times Output Load Capacitance CLK Output CL = 100 pF Others 30 pF 2 T –15 3 CLCL Note: Parameters where timing has not been indicated in the above table are measured at VL = 1.5 V and VH = 1.5 V for both inputs and outputs. 5/18 ¡ Semiconductor MSM82C84A-2RS/GS/JS PIN DESCRIPTION Pin Symbol Name Input/Output Function CSYNC Clock Synchronization Single Input Synchronizing signal for output of in-phase CLK signals when more than one MSM82C84A-2 is used. The internal counter is reset when this signal is at high level, and a high level CLK output is generated. The internal counter is subsequently activated and a 33% duty CLK output is generated when this signal is switched to low level. When this signal is used, external synchronization of EFI is necessary. When the internal oscillator is used, it is necessary for this pin to be kept to be low level. PCLK Peripheral Clock Output Output This peripheral circuit clock signal is output in a 50% duty cycle at a frequency half that of the clock signal. Input The AEN1 signal enables RDY1, and the AEN2 signal RDY2. The respective RDY inputs are activated when the level applied to these pins is low. Although two separate inputs are used in multi-master systems, only the AEN which enables the RDY input to be used is to be switched to low level in the case of not using multi-master systems. AEN1 AEN2 Address Enable Signals RDY1 RDY2 Bus Ready Signals Input Completion of data bus reading and writing by the device connected to the system data bus is indicated when one of these signals is switched to high level. The relevant RDY input is enables only when the corresponding AEN is at low level. Ready Output Output This signal is obtained by synchronizing the bus ready signal with CLK. This signal is output after guaranteeing the hold time for the CPU in phase with the RDY input. Output This signal is the clock used by the CPU and peripheral devices connected to the CPU system data bus. The output waveform is generated in a 33% duty cycle at a frequency 1/3 the oscillating frequency of the crystal oscillator connected to the X1 and X2 pins, or at a frequency 1/3 the EFI input frequency. This low-level active input is used to generate a CPU reset signal. Since a Schmitt trigger is included in the input circuit for this signal, "power on resetting" can be achieved by connection of a simple RC circuit. READY CLK Clock Output RES Reset in Input RESET Reset Output Output F/C Clock Select Signal Input This signal selects the fundamental signal for generation of the CLK signal. The CLK is generated from the crystal oscillator output when this signal is at low level, and from the EFI input signal when at high level. EFI External Clock Signal Input The signal applied to this input pin generaters the CLK signal when F/C is at high level. The frequency of the input signal needs to be three times greater than the desired CLK frequency. X1, X 2 Crystal Oscillator Connecting Pins Input Crystal oscillator connections. The crystal oscillator frequency needs to be three times greater than the desired CLK frequency. OSC Crystal Resonator Output Output Crystal oscillator output. This output frequency is the same as the oscillating frequency of the oscillator connected to the X1 and X2 pins. As long as a Xtal oscillator is connected to the X1 and X2 pins, this output signal can be obtained independently even if F/C is set to high level to enable the EFI input to be used CLK generation purpose. This signal is obtained by CLK synchronization of the input signal applied to RES and is output in opposite phase to the RES input. This signal is applied to the CPU as the system reset signal. 6/18 ¡ Semiconductor MSM82C84A-2RS/GS/JS Pin Symbol Name Function ASYNC Ready synchronization select signal Input VCC — — +5 V power supply GND — — GND Input/Output Signal for selection of the synchronization mode of the READY signal generator circuit. When this signal is at low level, the READY signal is generated by double synchronization. And when at high level, the READY signal is generated by single synchronization. This pin is equipped with internal pull-up resistor. TIMING DIAGRAM CLK • PCLK • OSC Waveforms tEHEL tELEL EFI tELEH OSC tEHYL CSYNC tYHYL tOLCH tYHEH tCLCL tOLCL CLK tCH1CH2 tCHCL tCLCH tCLPL tCL2CL1 tPHPL PCLK tPLPH tCLPH RESET Waveform CLK tI1HCL tCLI1H RES tCLIL RESET 7/18 ¡ Semiconductor MSM82C84A-2RS/GS/JS READY Waveform (ASYNC = L) tR1VCH CLK tR1VCL tCLR1X RDY1 - 2 tCLR1X tA1R1V AEN1 - 2 tCLA1X tAYVCL ASYNC tCLAYX READY tRYHCH tRYLCL READY Waveform (ASYNC = H) tR1VCL tR1VCL CLK tCLR1X tCLR1X RDY1 - 2 tA1R1V tCLA1X tAYVCL tCLAYX AEN1 - 2 ASYNC tRYHCH READY tRYLCL 8/18 ¡ Semiconductor MSM82C84A-2RS/GS/JS OPERATIONAL DESCRIPTION (1) Oscillator Circuit The MSM82C84A-2 internal oscillator circuit can be driven by connecting a crystal oscillator to the X1 and X2 pins. The frequency of the crystal oscillator in this case needs to be three times greater than the desired CLK frequency. Since the oscillator circuit output (the same output as for the crystal resonator frequency) appears at the OSC pin, independent use of this output is also possible. Oscillator Circuit Example Crystal Oscillator X1 OSC C1 C2 MSM 82C84A-2 X2 When input frequency is 6 to 15 MHz C1 = C2 = 33 pF When input frequency is 15 to 24 MHz C1 = C2 = 10 pF Note: Because Oscillator circuit and values depend on crystal oscillator characteristics, OKI recommends to make contact with crystal oscillator vendor to determine the best circuit and values for customers' application. (2) Clock Generator Circuit This circuit generates two clock outputs-CLK obtained by dividing the input external clock or crystal oscillator circuit output by three, and PCLK obtained by halving CLK. CLK and PCLK are generated from the external clock applied to the EFI pin when F/C is at high level, and are generated from the crystal oscillator circuit when at low level. (3) Reset Circuit Since a Schmitt trigger circuit is used in the RES input, the MSM82C84A-2 can be reset by “power on” by connection to a simple RC circuit. If the MSM80C86A-10 or MSM80C88A-10 is used as the CPU in this case, it is necessary to keep the RES input at low level for at least 50 ms after Vcc reaches the 4.5V level. 9/18 ¡ Semiconductor MSM82C84A-2RS/GS/JS (4) Ready Circuit The READY signal generator circuit can be set to synchronization mode by ASYNC. (i) When ASYNC is at low level The RDY input is output as the READY signal by double synchronization. The high-level RDY input is synchronized once by the rising edge of the CLK of the first stage flip-flop (F1 in the circuit diagram), and then synchronized again by the falling edge of the CLK of the next stage flip-flop (F2 in the circuit diagram), resulting in output of a high-level READY output signal (see diagram below). The low-level RDY input is synchronized directly by the falling-edge of the CLK of the next stage flip-flop, resulting in output of a low-level READY output signal (see diagram below). CLK RDY READY (ii) When ASYNC is at high level The RDY input is output as the READY signal by single synchronization. Both low-level and high-level RDY inputs are synchronized by the falling edge of the CLK of the next stage flip-flop, resulting output of respective low-level and high-level READY output signals (see diagram below). CLK RDY READY 10/18 ¡ Semiconductor MSM82C84A-2RS/GS/JS EXAMPLE OF USE (CSYNC) The MSM82C84A-2 1/3 frequency divider counter is unsettled when the power is switched on. Therefore, the CSYNC pin has been included to synchronize CLK with another signal. When CSYNC is at high level, both CLK and PCLK are high-level outputs. If CSYNC is then switched to low level, CLK is output from the next input clock rising edge, and is divided by 3. If CSYNC has not been synchronized with the input clock, use the following circuit to achieve the required synchronization External Sychronizing Signal D External Clock Signal (EFI) CK≠ Q D Q CKØ CSYNC MSM 82C84A-2 EFI CLK CLK When an external clock EFI is used as the clock source External Sychronizing Signal X1 D CK≠ Q D CKØ Q CSYNC X2 MSM 82C84A-2 OSC F/C CLK CLK When the crystal oscillator is used as the clock source NOTES ON USE The MSM82C84A-2 cannot be used if the MSM80C86A-10 or MSM80C88A-10 is used within the range of 8 MHz < operating frequency £ 10 MHz. 11/18 ¡ Semiconductor MSM82C84A-2RS/GS/JS NOTICE ON REPLACING LOW-SPEED DEVICES WITH HIGH-SPEED DEVICES The conventional low speed devices are replaced by high-speed devices as shown below. When you want to replace your low speed devices with high-speed devices, read the replacement notice given on the next pages. High-speed device (New) Remarks M80C85AH Low-speed device (Old) M80C85A/M80C85A-2 M80C86A-10 M80C86A/M80C86A-2 16bit MPU M80C88A-10 M80C88A/M80C88A-2 8bit MPU M82C84A-2 M82C84A/M82C84A-5 Clock generator M81C55-5 M82C37B-5 M81C55 M82C37A/M82C37A-5 RAM.I/O, timer DMA controller M82C51A-2 M82C51A USART M82C53-2 M82C55A-2 M82C53-5 M82C55A-5 Timer PPI 8bit MPU 12/18 ¡ Semiconductor MSM82C84A-2RS/GS/JS Differences between MSM82C84A and MSM82C84A-5/MSM82C84A-2 1) Manufacturing Process All these devices use a 3 m Si-Gate CMOS process technology. The chip size of these devices is same. The chip of the MSM82C84A-5 is entirely identical to that of the MSM82C84A-2. 2) Functions Item MSM82C84A MSM82C84A-5/-2 Internal processing of ASYNC pin Normal CMOS input pin Input pin with built-in pull up resistor Notes on use The pin should have a pullup or pulldown resistor if it is unused. The value of pulldown resistor (when used) is limited. (See page 3.) 3) Electrical Characteristics 3-1) DC Characteristics Parameter Symbol MSM82C84A MSM82C84A-5/-2 ''L''Level Output Voltage (CLK) VOL 0.45 V maximum (+5 mA) 0.40 V maximum (+4 mA) ''L''Level Output Voltage (Other than CLK) VOL 0.45 V maximum (+5 mA) 0.40 V maximum (+2.5 mA) ''H''Level Output Voltage (CLK) VOH 3.7 V minimum (-1 mA) VCC-0.1 V minimum (-4 mA) ''H''Level Output Voltage (Other than CLK) VOH 3.7 V minimum (-1 mA) VCC-0.1 V minimum (-1 mA) RES Input Hysteresis Width VIHRVILR 0.25 V minimum 0.2 ¥ VCC min Input Current (ASYNC) ILIA -10 mA to +10 mA -100 mA~+10 mA Input Leak Current ILI -10 mA to +10 mA -1 mA~+1 mA ICCS 100 mA maximum 40 mA maximum Supply Current (Standby) As shown above, the MSM82C84A-5/MSM82C84A-2 satisfies the characteristics (except for VOL and input current (ASYNC) of the MSM82C84A. 13/18 ¡ Semiconductor MSM82C84A-2RS/GS/JS 3-2) AC Charasteristics 1) MSM82C84A and MSM82C84A-2 Parameter Input Rise Time Symbol MSM82C84A MSM82C84A-2 tILIH 20 ns maximum 15 ns maximum 20 ns maximum 15 ns maximum Input Fall Time tILIH CLK High Time tCHCL 65 ns minimum 1/3 tCLCL +2 ns minimum CLK Low Time tCLCH 119 ns minimum 2/3 tCLCL -15 ns minimum 15 ns maximum 10 ns maximum CLK Rise/Fall Time tCH1CH2 tCL1CL2 PCLK High Time tPHPL 180 ns minimum tCLCL -20 ns minimum PCLK Low Time tPLPH 180 ns minimum tCLCL -20 ns minimum READY Falling to CLK Rising tRYHCH 114 ns minimum 2/3 tCLCL -15 ns minimum As shown above, the MSM82C84A-2 satisfies the characteristics (except for Input Rise/Fall Time) of the MSM82C84A. 1) MSM82C84A-5 and MSM82C84A-2 Parameter Symbol MSM82C84A-5 MSM82C84A-2 EFI High Time tEHEL 20 ns minimum 13 ns minimum EFI Low Time tELEH 20 ns minimum 17 ns minimum EFI Period tELEL 66 ns minimum 36 ns minimum — 15 MHz maximum 24 MHz maximum tCHCL 200 ns minimum 125 ns minimum Crystal Frequency CLK Period As shown above, the MSM82C84A-2 satisfies the characteristics of the MSM82C84A-5. 14/18 ¡ Semiconductor MSM82C84A-2RS/GS/JS 4) Notices on use Note the following when replacing devices as the ASYNC pin is differently treated between the MSM82C84A and the MSM82C84A-5/MSM82C84A-2: Case 1: When only a pullup resistor is externally connected to. The MSM82C84A can be replaced by the MSM82C84A-2. Case 2: When only pulldown resistor is externally connected to. When the pulldown resistor is 8 kiloohms or less, the MSM82C84A can be replaced by the MSM82C84A-2. When the pulldown resistor is greater than 8 kiloohms, use a pulldown resistor of 8 kiloohms or less. Case 3: When an output of the other IC device is connected to the device. The MSM82C84A can be replaced by the MSM82C84A-2 when the IOL pin of the device to drive the ASYNC pin of the MSM82C84A-2 has an allowance of 100 mA or more. 15/18 ¡ Semiconductor MSM82C84A-2RS/GS/JS PACKAGE DIMENSIONS (Unit : mm) DIP18-P-300-2.54 Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.30 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 16/18 ¡ Semiconductor MSM82C84A-2RS/GS/JS (Unit : mm) QFJ20-P-S350-1.27 Spherical surface Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin Cu alloy Solder plating 5 mm or more 0.59 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 17/18 ¡ Semiconductor MSM82C84A-2RS/GS/JS (Unit : mm) SOP24-P-430-1.27-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.58 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 18/18