E2E0057-29-71
¡ Semiconductor
ML63512A/63514A
¡ Semiconductor
This ML63512A/63514A
version: Jul. 1999
Previous version: Jun. 1999
4-Bit Microcontroller with Built-in Level Detector, Melody Circuit, and Comparator,
Operating at 0.9 V (Min.)
GENERAL DESCRIPTION
The ML63512A/63514A is a CMOS 4-bit microcontroller with built-in level detector and
operates at 0.9 V (min.).
The ML63512A/63514A is an M6351x series mask ROM-version product of OLMS-63K family,
which employs Oki's original CPU core nX-4/250.
The program memory capacity and data memory capacity of the ML63512A differ from those of
the ML63514A.
48-pin TQFP and 64-pin TQFP packages are available for the ML63512A and ML63514A.
FEATURES
• Extensive instruction set
407 instructions
Transfer, rotate, increment/decrement, arithmetic operations, comparison, logic operations,
mask operations, bit operations, ROM table reference, stack operations, flag operations,
jump, conditional branch, call/return, control.
• Wide variety selection of addressing modes
Indirect addressing of four data memory types, with current bank register, extra bank
register, HL register and XY register.
Data memory bank internal direct addressing mode.
• Processing speed
Two clocks per machine cycle, with most instructions executed in one machine cycle.
Minimum instruction execution time : 61 ms (@ 32.768 kHz system clock)
1 ms (@ 2 MHz system clock)
• Clock generation circuit
Low-speed clock
High-speed clock
: Crystal oscillation or RC oscillation selectable by
mask option (30 to 80 kHz)
: Ceramic oscillation or RC oscillation selectable by
mask option (2 MHz max.)
• Program memory space
ML63512A: 4K words
ML63514A: 8K words
Basic instruction length is 16 bits/1 word
• Data memory space
ML63512A: 128 nibbles
ML63514A: 256 nibbles
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¡ Semiconductor
• Stack level
Call stack level
Register stack level
ML63512A/63514A
: 16 levels
: 16 levels
• I/O ports
Input ports: Selectable as input with pull-up resistor/high-impedance input
Output ports: N-channel open drain output (can directly drive LEDs)
Input-output ports: Selectable as input with pull-up resistor/high-impedance input
Selectable as N-channel open drain output/CMOS output
Can be interfaced with external peripherals that use a different power supply than this device
uses. (Power to the output port is supplied from VDDI (separate power suply))
Number of ports:
(For 48-pin packages)
Input port
: 1 port ¥ 4 bits
Output port
: 1 port ¥ 4 bits
Input-output port
: 6 ports ¥ 4 bits
(For 64-pin packages)
Input port
: 1 port ¥ 4 bits
Output port
: 1 port ¥ 4 bits
Input-output port
: 9 ports ¥ 4 bits
• Melody output function
Melody sound frequency
Tone length
Tempo
Melody data
Number of ports
Buzzer driver signal output
• Level detector
Conversion time
Dedicated input pins
Detection level
• Comparator
Offset voltage
Comparison time
Number of channels
:
:
:
:
:
:
529 to 2979 Hz (@ 32.768 kHz)
63 varieties
15 varieties
Stored in the program memory
1 (dedicated pin)
4 kHz (@ 32.768 kHz)
: Approx. 183 ms (@ 32.768 kHz)
: 2 pins (switched by software; for the secondary
functions of the input ports)
: 12 levels
: 50 mV max. (VDD = 1.5 V)
: Approx. 183 ms (@ 32.768 kHz)
: 1 (for the secondary functions of the input ports)
• Reset function
Reset through RESETB pin (RESETB pin can be pulled up by mask option)
• Power supply backup
Backup circuit (voltage multiplier) enables operation at 0.9 V minimum
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¡ Semiconductor
ML63512A/63514A
• Timers and counter
8-bit timer ¥ 2
Selectable as auto-reload mode/capture mode/clock frequency measurement mode
15-bit time base counter ¥ 1
1 Hz, 2 Hz, 4 Hz, 8 Hz, 16 Hz, 32 Hz, 64 Hz, 128 Hz, 256 Hz, 512 Hz, 1 kHz, and 2 kHz signals
can be read (@ 32.768 kHz)
• Serial port
Mode
UART communication speed
Clock frequency in synchronous mode
Data length
• Interrupt sources
External interrupt (4 sources)
Internal interrupt (10 sources)
: Selectable as UART mode/synchronous
mode
: 2TBCCLK, TBCCLK, 1/2TBCCLK, Timers 0
& 1 overflow
24 kbps Max. (when 2TBCCLK @ 80 kHz
selected)
: 30 to 80 kHz (internal clock mode), external
clock frequency
: 5 to 8 bits
: Selectable as rising edge/falling edge/both
rising and falling edges
: Time base interrupt ¥ 4 (2, 4, 16, and 32 Hz
@ 32.768 kHz)
Timer interrupt ¥ 2
Level detector interrupt ¥ 1
Serial port reception interrupt ¥ 1
Serial port transmission interrupt ¥ 1
Melody end interrupt ¥ 1
• Operating Temperature
–20 to +70°C
• Supply voltage
When backup used
When backup not used
: 0.9 to 1.8 V
(Maximum operating frequency 1 MHz)
: 1.8 to 3.5 V
(When Level detector or Comparator is
used, maximum operating frequency
2 MHz)
1.8 to 5.5 V
(When Level detector and Comparator are
not used, maximum operating frequency
2 MHz)
• Package options:
48-pin plastic TQFP (TQFP48-P-0707-0.50-K) : (Product name: ML63512A-xxxTB,
ML63514A-xxxTB)
64-pin plastic TQFP (TQFP64-P-1010-0.50-K) : (Product name: ML63512A-xxxTP,
ML63514A-xxxTP)
xxx indicates a code number.
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¡ Semiconductor
ML63512A/63514A
BLOCK DIAGRAM
An asterisk (*) indicates the port secondary function. The power to the circuits corresponding
to the signal names inside
is supplied from V DDI (power supply for interface).
nX-4/250
TIMING
CONTROL
CBR
H
L
RA
EBR
X
Y
A
SP
C
ALU
RSP
G
Z
MIE
STACK
INSTRUCTION
CAL: 16-level
DECODER
ROM
ML63512A: 4KW
ML63514A: 8KW
PC
BUS
CONTROL
IR
REG: 16-level
INT
2
RESETB
RAM
ML63512A: 128N
ML63514A: 256N
RST
TIMER
8bit ¥ 2
INT
XT0
XT1
OSC0
OSC1
TBCCLK*
HSCLK*
2
TST
INT
SIO
MELODY
OSC
4
TBC
P0.0-P0.3
P1.0-P1.3
1
CMPIN*
CMPREF*
VDDH
VDD
CB1
CB2
MD
INT
INT
LDIN0*
LDIN1*
RXC*
TXC*
RXD*
TXD*
INT
1
DATA BUS
TST1B
TST2B
TM0CAP/TM1CAP*
TM0OVF/TM1OVF*
T0CK*
T1CK*
P2.0-P2.3
Level
Detector
P3.0-P3.3
I/O
PORT
CMP
P4.0-P4.3
P5.0-P5.3
P6.0-P6.3=
BACKUP
VDDL
INT
P9.0-P9.3=
4
PA.0-PA.3=
VR
INPUT
PORT
P7.0-P7.3
OUTPUT
PORT
P8.0-P8.3
VDDI
VSS
=Port 6 (P6.0 to P6.3), Port 9 (P9.0 to P9.3) and Port A (PA.0 to PA.3) are only provided for the 64-
pin packages.
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VDDH 24
VDD
23
VSS 22
VDDI 21
P8.3 20
P8.2 19
P8.1 18
P8.0 17
P7.3/LDIN1 16
P7.2/LDIN0 15
P7.1/CMPREF 14
P7.0/CMPIN 13
37 P0.0/INT0
38 P0.1/INT1
39 P0.2/INT2
40 P0.3/INT3
41 P1.0/TM0CAP/TM0OVF
43 P1.2/T0CK
42 P1.1/TM1CAP/TM1OVF
44 P1.3/T1CK
45 P2.0/TBCCLK
46 P2.1/HSCLK
47 P2.2
48 P2.3
¡ Semiconductor
ML63512A/63514A
PIN CONFIGURATION (TOP VIEW)
P3.0/RXD
1
36 MD
P3.1/TXC
2
35 RESETB
P3.2/RXC
3
34 OSC1
P3.3/TXD
4
33 OSC0
P4.0
5
32 VSS
P4.1
6
31 TST2B
P4.2
P4.3
7
30 TST1B
8
29 XT1
P5.0
9
28 XT0
P5.1
10
27 VDDL
P5.2
11
26 CB2
P5.3
12
25 CB1
48-Pin Plastic TQFP
5/29
¡ Semiconductor
ML63512A/63514A
49 P9.2
50 P9.3
51 P0.0/INT0
52 P0.1/INT1
53 P0.2/INT2
54 P0.3/INT3
55 P1.0/TM0CAP/TM0OVF
56 P1.1/TM1CAP/TM1OVF
57 P1.2/T0CK
59 P2.0/TBCCLK
58 P1.3/T1CK
60 P2.1/HSCLK
61 P2.2
62 P2.3
63 PA.0
64 PA.1
PIN CONFIGURATION (TOP VIEW) (continued)
PA.2
1
48 P9.1
PA.3
2
47 P9.0
P3.0/RXD
3
46 MD
P3.1/TXC
4
45 RESETB
P3.2/RXC
5
44 OSC1
P3.3/TXD
6
43 OSC0
P4.0
P4.1
7
42 VSS
8
41 TST2B
P4.2
9
40 TST1B
P4.3
10
39 XT1
P5.0
11
38 XT0
P5.1
12
37 VDDL
P5.2
13
36 CB2
(NC) 32
(NC) 31
VDDH 30
VSS 28
VDD 29
VDDI 27
P8.3 26
P8.2 25
P8.0 23
P8.1 24
P7.3/LDIN1 22
33 (NC)
P7.2/LDIN0 21
16
P7.0/CMPIN 19
P6.1
P7.1/CMPREF 20
35 CB1
34 (NC)
P6.3 18
14
15
P6.2 17
P5.3
P6.0
64-Pin Plastic TQFP
Note: Pins marked as (NC) are no-connection pins which are left open.
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¡ Semiconductor
ML63512A/63514A
PIN DESCRIPTIONS
The basic functions of each pin of the ML63512A/63514A are described in Table 1.
A symbol with a slash (/) denotes a pin that has a secondary function.
Refer to Table 2 for secondary functions.
For type, "—" denotes a power supply pin, "I" an input pin, "O" an output pin, and "I/O" an inputoutput pin.
For pin, "TB" denotes a 48-pin flat package (48TQFP), and "TP" a 64-pin flat package (64TQFP).
Table 1 Pin Descriptions (Basic Functions)
Function Symbol
VDD
VSS
Power
Pin
TB
TP
23
29
22, 32 28, 42
Type
Description
—
Positive power supply
—
Negative power supply
Positive power supply pin for external interface (PORT8 supply)
VDDI
21
27
—
VDDL
27
37
—
Supply
Positive power supply pin for internal logic (internally generated).
A capacitor Cl (0.1 mF) should be connected between this pin and VSS.
Voltage multiplier pin for power supply backup (internally generated).
VDDH
24
30
—
CB1
25
35
—
Pins to connect a capacitor for voltage multiplier.
CB2
26
36
—
A capacitor (1.0 mF) should be connected between CB1 and CB2.
A capacitor Ch (1.0 mF) should be connected between this pin and VSS.
Low-speed clock oscillation pins.
XT0
28
38
I
Crystal oscillation or RC oscillation is selected by the mask option.
If crystal oscillation is selected, connect a crystal between XT0 and
XT1, and connect capacitor (CG) between XT0 and VSS.
XT1
29
39
O
If RC oscillation is selected, connect external oscillation resistor
(RCRL) between XT0 and XT1.
Oscillation
High-speed clock oscillation pins.
OSC0
33
43
I
Ceramic oscillation or RC oscillation is selected by the mask option.
If ceramic oscillation is selected, connect a ceramic resonator
between OSC0 and OSC1, and connect capacitor (CL0, CL1) between
OSC0 and VSS, OSC1 and VSS.
OSC1
34
44
O
If RC oscillation is selected, connect external oscillation resistor
TST1B
30
40
I
Input pins for testing.
TST2B
31
41
I
A pull-up resistor is internally connected to these pins.
(RCRH) between OSC0 and OSC1.
Test
Reset input pin.
Setting this pin to "L" level puts this device into a reset state.
Reset
RESETB
35
45
I
Then, setting this pin to "H" level starts executing an instruction
from address 0000H.
An internal or external pull-up resistor is selected by mask option.
Melody
MD
36
46
O
Melody output pin (non-inverted output)
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¡ Semiconductor
ML63512A/63514A
Table 1 Pin Descriptions (Basic Functions) (continued)
Function
Symbol
Pin
TB
TP
P0.0/INT0
37
51
P0.1/INT1
38
52
P0.2/INT2
39
53
P0.3/INT3
40
54
41
55
42
56
P1.2/T0CK
43
57
Type
4-bit input-output ports.
I/O
In input mode, pull-up resistor input or high-impedance
input is selectable for each bit.
In output mode, N-channel open drain output or CMOS
output is selectable for each bit.
P1.0/
TM0CAP/
Description
TM0OVF
P1.1/
TM1CAP/
I/O
TM1OVF
Port
P1.3/T1CK
44
58
P2.0/TBCCLK
45
59
P2.1/HSCLK
46
60
P2.2
47
61
P2.3
48
62
P3.0/RXD
1
3
P3.1/TXC
2
4
P3.2/RXC
3
5
P3.3/TXD
4
6
P4.0
5
7
P4.1
6
8
P4.2
7
9
P4.3
8
10
P5.0
9
11
P5.1
10
12
P5.2
11
13
P5.3
12
14
I/O
I/O
I/O
I/O
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¡ Semiconductor
ML63512A/63514A
Table 1 Pin Descriptions (Basic Functions) (continued)
Function
Symbol
Pin
TB
TP
P6.0
—
15
P6.1
—
16
Type
Description
4-bit input-output port.
In input mode, pull-up resistor input or high-impedance
I/O
input is selectable for each bit.
In output mode, N-channel open drain output or CMOS
P6.2
—
17
P6.3
—
18
Note that these pins are available for only a 64-pin package.
P7.0/CMPIN
13
19
4-bit input port.
P7.1/CMPREF
14
20
P7.2/LDIN0
15
21
P7.3/LDIN1
16
22
P8.0
17
23
P8.1
18
24
P8.2
19
25
P8.3
20
26
P9.0
—
47
P9.1
—
48
P9.2
—
49
P9.3
—
50
In output mode, N-channel open drain output or CMOS
PA.0
—
63
output is selectable for each bit.
PA.1
—
64
PA.2
—
1
PA.3
—
2
output is selectable for each bit.
Pull-up resistor input or high-impedance input is selectable
I
Port
for each bit.
4-bit output port.
O
N-channel open drain output.
4-bit input-output ports.
I/O
I/O
In input mode, pull-up resistor input or high-impedance
input is selectable for each bit.
Note that these pins are available for only a 64-pin package.
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¡ Semiconductor
ML63512A/63514A
Table 2 shows the secondary functions of each pin of the ML63512A/63514A.
Table 2 Pin Descriptions (Secondary Functions)
Function
Symbol
Pin
TB
TP
Type
Description
External 0 interrupt input pin.
P0.0/INT0
37
51
I
Edge detection can be selected from one of a rising edge,
a falling edge, or both rising and falling edges.
External 1 interrupt input pin.
P0.1/INT1
38
52
I
Edge detection can be selected from one of a rising edge,
External
a falling edge, or both rising and falling edges.
Interrupt
External 2 interrupt input pin.
P0.2/INT2
39
53
I
Edge detection can be selected from one of a rising edge,
a falling edge, or both rising and falling edges.
External 3 interrupt input pin.
P0.3/INT3
40
54
I
Edge detection can be selected from one of a rising edge,
a falling edge, or both rising and falling edges.
Capture
Timer
P1.0/TM0CAP
41
55
I
Timer 0 (TM0) capture trigger input pin.
P1.1/TM1CAP
42
56
I
Timer 1 (TM1) capture trigger input pin.
P1.0/TM0OVF
41
55
O
Timer 0 (TM0) overflow flag output pin.
P1.1/TM1OVF
42
56
O
Timer 1 (TM1) overflow flag output pin.
P1.2/T0CK
43
57
I
Timer 0 (TM0) external clock input pin.
P1.3/T1CK
44
58
I
Timer 1 (TM1) external clock input pin.
45
59
O
Low-speed oscillation clock output pin.
P2.1/HSCLK
46
60
O
High-speed oscillation clock output pin.
P3.0/RXD
1
3
I
Serial port receive data input pin.
Oscillation P2.0/TBCCLK
Output
Sync serial port clock input-output pin.
Transmit sync clock input-output pin when a serial port is used
P3.1/TXC
2
4
I/O
synchronously.
Transmit clock output when this device is used as a master processor.
Serial
Transmit clock input when this device is used as a slave processor.
Port
Sync serial port clock input-output pin.
Receive sync clock input-output pin when a serial port is used
P3.2/RXC
3
5
I/O
synchronously.
Receive clock output when this device is used as a master processor.
Receive clock input when this device is used as a slave processor.
P3.3/TXD
4
6
O
Serial port transmit data output pin.
P7.0/CMPIN
13
19
I
Comparator analog input pin.
P7.1/CMPREF
14
20
I
Comparator reference voltage input pin.
Level
P7.2/LDIN0
15
21
I
Level detector analog input pin.
Detector
P7.3/LDIN1
16
22
I
Level detector analog input pin.
Comparator
10/29
¡ Semiconductor
ML63512A/63514A
ABSOLUTE MAXIMUM RATINGS
(VSS = 0 V)
Parameter
Power Supply Voltage 1
Symbol
Condition
Rating
Unit
VDD
Ta = 25°C
–0.3 to +5.8
V
Power Supply Voltage 2
VDDI
Ta = 25°C
–0.3 to +5.8
V
Power Supply Voltage 3
VDDH
Ta = 25°C
–0.3 to +5.8
V
Power Supply Voltage 4
VDDL
Ta = 25°C
–0.3 to +5.8
V
Input Voltage 1
VIN1
VDD Input, Ta = 25°C
–0.3 to VDD + 0.3
V
Input Voltage 2
VIN2
VDDI Input, Ta = 25°C
–0.3 to VDDI + 0.3
V
Output Voltage 1
VOUT1
VDD Output, Ta = 25°C
–0.3 to VDD + 0.3
V
Output Voltage 2
VOUT2
VDDI Output, Ta = 25°C
–0.3 to VDDI + 0.3
V
Output Voltage 3
VOUT3
VDDH Output, Ta = 25°C
–0.3 to VDDH + 0.3
V
Storage Temperature
TSTG
—
–55 to +150
°C
PD
Ta = 25°C
60
mW
Power Dissipation
11/29
¡ Semiconductor
ML63512A/63514A
RECOMMENDED OPERATING CONDITIONS
• When backup is used
(VSS = 0 V)
Parameter
Operating Temperature
Operating Voltage
Crystal Oscillation Frequency
Low-Speed RC Oscillator
Frequency
External High-Speed RC
Oscillator Resistance
Symbol
Condition
Range
Unit
Top
—
–20 to +70
°C
VDD
—
0.9 to 1.8
V
VDDI
—
0.9 to 3.5
V
fXT
—
30 to 80
kHz
fCRL
RCRL = 1 MW ±10%
32
kHz
RCRH
VDD = 0.9 to 1.8 V
100 to 300
kW
• When backup is not used
(VSS = 0 V)
Parameter
Operating Temperature
Operating Voltage
Crystal Oscillation Frequency
Low-Speed RC Oscillator
Frequency
External High-Speed RC
Oscillator Resistance
Ceramic Oscillation Frequency
Symbol
Condition
Range
Unit
Top
—
–20 to +70
°C
—
1.8 to 3.5
VDD
When Level detector and
Comparator are not used
1.8 to 5.5
V
VDDI
—
1.8 to 5.5
fXT
—
30 to 80
kHz
fCRL
RCRL = 1 MW ±10%
32
kHz
RCRH
VDD = 1.8 to 5.5 V
15 to 300
kW
fCM
VDD = 2.2 to 5.5 V
300k to 1M
VDD = 2.7 to 5.5 V
200k to 2M
Hz
12/29
¡ Semiconductor
ML63512A/63514A
ELECTRICAL CHARACTERISTICS
DC Characteristics
• When backup is used
Parameter
Supply Current 1
Supply Current 2
(VDD = VDDI = 1.5 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified)
MeaSymbol
Condition
Min. Typ. Max. Unit suring
Circuit
4.8
5.3
Ta = 25°C
5.8
CPU is in HALT state
5.3
9.0
mA
IDD1 High-speed oscillation stop Ta = –20 to +50°C —
Level detector stop
5.3 15.0
Ta = –20 to +70°C —
Ta = 25°C
12.0 13.0 14.0
CPU operating
13.0 16.0 mA
IDD2 High-speed oscillation stop Ta = –20 to +50°C —
Level detector stop
Ta = –20 to +70°C —
13.0 24.0
1
CPU operating at low speed
Supply Current 3
IDD3
High-speed oscillation stop
Level detector active
(for a soft duty of about 3%)
Supply Current 4
IDD4
CPU operating at high speed
High-speed RC oscillation
RCRH = 100 kW
—
10.0
35.0
mA
—
550.0 750.0
mA
• When backup is not used
Parameter
Supply Current 1
Supply Current 2
(VDD = VDDI = 3.0 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified)
MeaSymbol
Condition
Min. Typ. Max. Unit suring
Circuit
2.1
2.4
Ta = 25°C
2.7
CPU is in HALT state
2.4
7.0
mA
IDD1 High-speed oscillation stop Ta = –20 to +50°C —
Level detector stop
2.4 10.0
Ta = –20 to +70°C —
Ta = 25°C
5.0
6.0
7.0
CPU operating
Ta
=
–20
to
+50°C
—
6.0
9.0
High-speed
oscillation
stop
mA
IDD2
Level detector stop
Ta = –20 to +70°C —
6.0 15.0
Supply Current 3
IDD3
CPU operating at low speed
High-speed oscillation stop
Level detector active
(for a soft duty of about 3%)
Supply Current 4
IDD4
CPU operating at high speed
High-speed RC oscillation
RCRH = 100 kW
Supply Current 5
IDD5
CPU operating at high speed
High-speed ceramic oscillation
(ceramic oscillation, 2 MHz)
—
6.0
25.0
mA
—
410.0 550.0
mA
—
850.0 1000.0 mA
1
13/29
¡ Semiconductor
ML63512A/63514A
DC Characteristics (continued)
(VDD = VDDI = 1.5 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified)
Parameter
(Pin Name)
Symbol
Condition
High-speed clock stop
VDDH Voltage
VDDH
VDD = 1.5 V
High-speed clock oscillation
(RC oscillation, RCRH = 100 kW)
VDDL Voltage
Crystal Oscillation Start
Voltage
Crystal Oscillation Hold
Voltage
External Crystal Oscillator
Capacitance
Internal Crystal Oscillator
Capacitance
Internal Low-Speed RC
Oscillator Capacitance
Internal High-Speed RC
Oscillator Capacitance
MeaMin. Typ. Max. Unit suring
Circuit
2.8
—
3.0
V
2.0
—
—
V
High-speed clock stop
1.0
1.5
2.0
V
High-speed clock oscillation
2.0
—
2.7
V
VSTA
Oscillation start time: within 5 seconds
1.2
—
—
V
VHOLD
—
0.9
—
—
V
CG
—
5.0
—
25.0
pF
CD
—
20.0
25.0
30.0
pF
CXT
—
10.0
15.0
20.0
pF
COS
—
8.0
12.0
16.0
pF
CIN
—
—
—
5.0
pF
VDDL
1
Input Pin Capacitance
(P0.0 to P0.3)
···
(P1.0 to P1.3)
(P7.0 to P7.3)
(P9.0 to P9.3)
(PA.0 to PA.3)
14/29
¡ Semiconductor
ML63512A/63514A
DC Characteristics (continued)
(VDD = VDDI = 1.5 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified)
Parameter
(Pin Name)
IOH1
(P6.0 to P6.3)
(P9.0 to P9.3)
(PA.0 to PA.3)
(MD)
IOL1
Output Current 2
IOH2Z
VOH1 = VDD – 0.5 V
VOL1 = 0.5 V
Output Current 3
(OSC1)
IOH3R
IOL3R
–6.0
–3.5
–1.0
mA
VDD = 5.0 V
–8.5
–5.0
–1.5
mA
VDD = 1.5 V
0.2
1.3
2.5
mA
VDD = 3.0 V
1.0
3.0
6.0
mA
VDD = 5.0 V
1.5
3.7
8.5
mA
—
—
1.0
mA
VDDI = 1.5 V
3.0
7.5
14.0
mA
VOL2 = 0.5 V
VDDI = 3.0 V
6.0
12.0
20.0
mA
VDDI = 5.0 V
8.0
15.0
28.0
mA
VOH3R = VDDH – 0.5 V
VDD = VDDH = 3.0 V
–2.5
–1.5
–0.2
mA
VDD = VDDH = 5.0 V
–3.5
–1.8
–0.5
mA
VDD = VDDH = 3.0 V
0.2
1.5
2.5
mA
VOL3R = 0.5 V
0.5
1.8
IOH3C
VOH3C = VDDH – 0.5 V
IOL3C
VOL3C = 0.5 V
IOOH
IOOL
VDD = VDDH = 5.0 V
3.5
mA
VDD = VDDH = 3.0 V
–300 –160
–60
mA
VDD = VDDH = 5.0 V
–400 –240 –100
mA
VDD = VDDH = 3.0 V
60
170
300
mA
VDD = VDDH = 5.0 V
100
210
400
mA
VOH = VDD
—
—
1.0
mA
VOL = VSS
–1.0
—
—
mA
2
···
Output Leakage
(P0.0 to P0.3)
(P1.0 to P1.3)
VDD = 3.0 V
VOH2 = VDD
(P8.0 to P8.3)
IOL2
VDD = 1.5 V
MeaMin. Typ. Max. Unit suring
Circuit
–2.5 –1.3 –0.2 mA
Condition
···
Output Current 1
(P0.0 to P0.3)
(P1.0 to P1.3)
Symbol
(P6.0 to P6.3)
(P8.0 to P8.3)
(P9.0 to P9.3)
(PA.0 to PA.3)
15/29
¡ Semiconductor
ML63512A/63514A
DC Characteristics (continued)
(VDD = VDDI = 1.5 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified)
Parameter
(Pin Name)
···
Input Current 1
(P0.0 to P0.3)
(P1.0 to P1.3)
(P7.0 to P7.3)
(P9.0 to P9.3)
(PA.0 to PA.3)
Input Current 2
Symbol
IIH1U
IIL1U
Input Current 4
VIL1 = VSS
(when pulled up)
—
—
1.0
mA
VDD = 1.5 V
–8.0
–4.0
–1.0
mA
VDD = 3.0 V
–60.0 –30.0 –10.0 mA
VDD = 5.0 V
–150.0 –90.0 –23.0 mA
VIH1 = VDD (in a high-impedance state)
—
—
1.0
mA
IIL1Z
IIH2
VIL1 = VSS (in a high-impedance state)
VIH2 = VDD
–1.0
—
—
mA
—
—
1.0
mA
–45.0 –20.0 –2.0
mA
IIL2
(OSC0)
VIH1 = VDD (when pulled up)
MeaMin. Typ. Max. Unit suring
Circuit
IIH1Z
(RESETB)
Input Current 3
Condition
IIL3
VIL2 = VSS
(when pulled up)
VDD = 1.5 V
VDD = 3.0 V
–260.0–120.0 –30.0 mA
VDD = 5.0 V
–870.0–300.0 –70.0 mA
VIL3 = VSS
VDD = VDDH = 3.0 V –350.0–170.0 –30.0 mA
(when pulled up)
VDD = VDDH = 5.0 V –750.0–450.0 –200.0 mA
IIH3R
VIH3 = VDDH
—
—
1.0
mA
IIL3R
VIL3 = VSS
–1.0
—
—
mA
IIH4
VIH4 = VDD
—
—
0.1
mA
(TST1B, TST2B)
IIL4
VIL4 = VSS
(when pulled up)
VDD = 1.5 V
–120.0 –60.0 –10.0 mA
VDD = 3.0 V
–600.0–350.0 –100.0 mA
VDD = 5.0 V
–1320.0 –770.0 –220.0 mA
3
16/29
¡ Semiconductor
ML63512A/63514A
DC Characteristics (continued)
(VDD = VDDI = 1.5 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified)
Parameter
Condition
MeaMin. Typ. Max. Unit suring
Circuit
VDD = 1.5 V
1.2
—
1.5
V
VDD = 3.0 V
2.4
—
3.0
V
···
(Pin Name)
Symbol
VDD = 5.0 V
4.0
—
5.0
V
(P7.0 to P7.3)
(P9.0 to P9.3)
(PA.0 to PA.3)
VDD = 1.5 V
0.0
—
0.3
V
VDD = 3.0 V
0.0
—
0.6
V
VDD = 5.0 V
0.0
—
1.0
V
Input Voltage 1
(P0.0 to P0.3)
(P1.0 to P1.3)
Input Voltage 2
(OSC0)
VIH1
VIL1
VIH2
VIL2
Input Voltage 3
(RESETB)
VIH3
(TST1B, TST2B)
VIL3
2.4
—
3.0
V
4.0
—
5.0
V
VDD = VDDH = 3.0 V
0.0
—
0.6
V
VDD = VDDH = 5.0 V
0.0
—
1.0
V
VDD = 1.5 V
1.35
—
1.50
V
VDD = 3.0 V
2.4
—
3.0
V
VDD = 5.0 V
4.0
—
5.0
V
VDD = 1.5 V
0.00
—
0.15
V
VDD = 3.0 V
0.0
—
0.6
V
VDD = 5.0 V
0.0
—
1.0
V
VDD = 1.5 V
0.05
0.10
0.30
V
VDD = 3.0 V
0.2
0.5
1.0
V
VDD = 5.0 V
0.25
1.00
1.50
V
4
···
Hysteresis Width
(P0.0 to P0.3)
(P1.0 to P1.3)
VDD = VDDH = 3.0 V
VDD = VDDH = 5.0 V
(P7.0 to P7.3)
(P9.0 to P9.3)
(PA.0 to PA.3)
(RESETB)
(TST1B, TST2B)
VT
17/29
¡ Semiconductor
ML63512A/63514A
Hysteresis width
Input Signal
VT
VDD
VSS
Internal Signal
VDDL
VSS
18/29
¡ Semiconductor
ML63512A/63514A
Measuring circuit 1
*1
*2
q
XT0
w
XT1
e
OSC0
r
OSC1
CB1
Cb12
CB2
VSS
VDD
VDDI
A
VDDH
Ch
VDDL
V
Cl
V
: 15 pF
CG
Cb12, Ch : 1 mF
: 0.1 mF
Cl
: 12 pF
CO
Ceramic Resonator : CSA2.00MG (2 MHz)
CSB1000J (1 MHz)
(Murata MFG.-make)
: 30 pF
CL0
: 30 pF
CL1
*1
*2
RC oscillator
RC oscillator
q
RCRL
e
RCRH
w
Ceramic oscillator
Crystal oscillator
CG
r
q
CL0
CL1
w
e
Ceramic resonator
r
19/29
¡ Semiconductor
ML63512A/63514A
Measuring circuit 2
*4
VIH
*3
INPUT
VIL
OUTPUT
VSS
VDD
VDDI
VDDH
A
VDDL
*3 Input logic circuit to determine the specified measuring conditions.
*4 Measured at the specified output pins.
Measuring circuit 3
*5
A
INPUT
OUTPUT
VSS
VDD
VDDI
VDDH
VDDL
20/29
¡ Semiconductor
ML63512A/63514A
Measuring circuit 4
VIH
*5
VIL
INPUT
OUTPUT
VSS
VDD
VDDI
VDDH
Waveform
Monitoring
VDDL
*5 Measured at the specified input pins.
21/29
¡ Semiconductor
ML63512A/63514A
AC Characteristics (Serial Interface, Serial Port)
(VDD = 0.9 to 5.5 V, VDDH = 1.8 to 5.5 V, VSS = 0 V, VDDI = 0.9 to 5.5 V, Ta = –20 to +70°C unless
otherwise specified)
(1) Synchronous Communication
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
TXC/RXC Input Fall Time
tf
—
—
—
1.0
ms
TXC/RXC Input Rise Time
tr
—
—
—
1.0
ms
TXC/RXC Input "L" Level
Pulse Width
tCWL
—
0.8
—
—
ms
TXC/RXC Input "H" Level
Pulse Width
tCWH
—
0.8
—
—
ms
TXC/RXC Input Cycle Time
tCYC
—
2.0
—
—
ms
tCYC1(O)
CPU operating at 32.768 kHz
—
30.5
—
ms
—
0.5
—
ms
TXC/RXC Output Cycle Time
CPU operating at 2 MHz
tCYC2(O)
TXD Output Delay Time
VDD = VDDH = 2.7 to 5.5 V
tDDR
Output load capacitance 10 pF
—
—
0.4
ms
RXD Input Setup Time
tDS
—
0.5
—
—
ms
RXD Input Hold Time
tDH
—
0.8
—
—
ms
Synchronous communication timing
("H" level = 4.0 V, "L" level = 1.0 V)
tCYC
TXC (P3.1)/
RXC (P3.2)
VDD (5.0 V)
tr
VSS
tf
tCWH
tCWL
tDDR
tDDR
TXD (P3.3)
VDD (5.0 V)
VSS
tDS
RXD (P3.0)
tDH
tDS
VDD (5.0 V)
VSS
22/29
¡ Semiconductor
ML63512A/63514A
(2) UART Communication
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Transmit Baud Rate
TBRT
TBRT = 1/fBRT
TCR = 1/fOSC
TBRT–TCR
TBRT
TBRT+TCR
s
Receive Baud Rate
RBRT
RBRT = 1/fBRT
RBRT¥0.97
RBRT
RBRT¥1.03
s
fBRT: Baud rates (2TBCCLK, TBCCLK, 1/2TBCCLK, Timer 0/1 overflow)
UART communication timing
("H" level = 4.0 V, "L" level = 1.0 V)
TBRT
VDD (5.0 V)
TXD (P3.3)
VSS
RBRT
RXD (P3.0)
VDD (5.0 V)
VSS
23/29
¡ Semiconductor
ML63512A/63514A
AC Characteristics
(VDD = VDDI = 0.9 to 5.5 V, VSS = 0 V, Ta = –20 to + 70°C unless otherwise specified)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
External Interrupt Enable
Pulse Width (Rising Edge)
tWH
—
20
—
—
ns
External Interrupt Enable
Pulse Width (Falling Edge)
tWL
—
20
—
—
ns
tNUL
Interrupt enable, MIE = 1
CPU operating under
the NOP instruction
System clock: 32.768 kHz
13.0
—
65.1
ms
External Interrupt Disable
Time
AC characteristics timing
P0.0 to P0.3
(Interrupt on the rising edge)
tWH
tNUL
P0.0 to P0.3
(Interrupt on the falling edge)
tWL
tNUL
P0.0 to P0.3
(Interrupt on both rising and falling edges)
tNUL
24/29
¡ Semiconductor
ML63512A/63514A
Comparator Electrical Characteristics
(VDD = 0.9 V, VSS = 0 V, Ta = –20 to +70°C)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Vcoff
—
—
—
30
mV
Vcin
—
VSS
—
VDD
V
TC
System clock: 32.768 kHz
—
183
—
ms
Comparator Supply
IDDCMP
Comparator operating
—
30
90
mA
Current
IDSCMP
Comparator stopped
—
—
0.1
mA
Comparator Offset
Voltage
Comparator Input
Voltage
Comparator Conversion
Time
Remarks
CMPIN
CMPREF
Conceptual diagram of comparator supply current
The conceptual diagram of the comparator supply current IDDCMP and IDSCMP is shown below.
IDD
(VSS)
[mA]
IDDCMP
IDSCMP
Sampling reference voltage
Level detector stopped
Comparing
reference
voltage with
input voltage
Level detector operating
t [ms]
Level detector stopped
25/29
¡ Semiconductor
ML63512A/63514A
Level Detector Electrical Characteristics
(VDD = 0.9 V, VSS = 0 V, Ta = –20 to +70°C)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
VLD
—
VSS
—
VDD
V
TC
System clock: 32.768 kHz
—
183
—
ms
Level Dtector Supply
IDDLD
Level detector operating
—
80
130
mA
Current
IDSLD
Level detector stopped
—
—
0.1
mA
Level Detector Input
Voltage
Level Detector Conversion
Time
Remarks
LDIN0, 1
Conceptual diagram of level detector supply current
The conceptual diagram of the level detector supply current IDDLD and IDSLD is shown below.
IDD
(VSS)
[mA]
IDDLD
IDSLD
Sampling reference voltage
Level detector stopped
Comparing
reference
voltage with
input voltage
Level detector operating
t [ms]
Level detector stopped
26/29
¡ Semiconductor
ML63512A/63514A
Level Detector Input Levels and Output Codes
(VDD = 0.9 to 1.8 V: when backup is used, VDD = 1.8 to 3.5 V: when backup is not used;
VSS = 0 V, Ta = –20 to +70°C)
Input Level [V]
LDOUT
Level Detector
Min.
Max.
Operation State
bit 3
bit 2
bit 1
bit 0
1440/1500 ¥ VDD
VDD
OFF state
1
1
1
1
1306/1500 ¥ VDD
1366/1500 ¥ VDD
1
0
1
1
1190/1500 ¥ VDD
1250/1500 ¥ VDD
1
0
1
0
1074/1500 ¥ VDD
1134/1500 ¥ VDD
1
0
0
1
958/1500 ¥ VDD
1018/1500 ¥ VDD
1
0
0
0
842/1500 ¥ VDD
902/1500 ¥ VDD
0
1
1
1
726/1500 ¥ VDD
786/1500 ¥ VDD
0
1
1
0
610/1500 ¥ VDD
670/1500 ¥ VDD
0
1
0
1
494/1500 ¥ VDD
554/1500 ¥ VDD
0
1
0
0
378/1500 ¥ VDD
438/1500 ¥ VDD
0
0
1
1
262/1500 ¥ VDD
322/1500 ¥ VDD
0
0
1
0
146/1500 ¥ VDD
206/1500 ¥ VDD
0
0
0
1
VSS
88/1500 ¥ VDD
0
0
0
0
ON state
27/29
¡ Semiconductor
ML63512A/63514A
PACKAGE DIMENSIONS
(Unit : mm)
TQFP48-P-0707-0.50-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.13 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type
packages, which are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person
on the product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
28/29
¡ Semiconductor
ML63512A/63514A
(Unit : mm)
TQFP64-P-1010-0.50-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.26 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type
packages, which are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person
on the product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
29/29
E2Y0002-29-62
NOTICE
1.
The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.
3.
When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
4.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5.
Neither indemnity against nor license of a third party’s industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party’s right which may result from the use thereof.
6.
The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.
7.
Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
the legality of export of these products and will take appropriate and necessary steps at their
own expense for these.
8.
No part of the contents contained herein may be reprinted or reproduced without our prior
permission.
9.
MS-DOS is a registered trademark of Microsoft Corporation.
Copyright 1999 Oki Electric Industry Co., Ltd.
Printed in Japan