TI TPS2071

TPS2070, TPS2071
FOUR-PORT USB HUB POWER CONTROLLERS
SLVS287A – SEPTEMBER 2000 – REVISED FEBRUARY 2001
D
D
D
D
D
D
D
D
D
D
DAP PACKAGE
(TOP VIEW)
Complete USB Hub Power Solution
Meets USB Specifications 1.1 and 2.0
Independent Thermal and Short-Circuit
Protection
3.3-V Regulator for USB Hub Controller
Overcurrent Logic Outputs
4.5-V to 5.5-V Operating Range
CMOS- and TTL-Compatible Enable Inputs
185 µA Bus-Power Supply Current
Available in 32-Pin HTSSOP PowerPAD
–40°C to 85°C Ambient Temperature Range
NC
EN1
AGND
NC
PG
SP
SP
NC
VEXT
GATE
3.3V_OUT
BPMODE†
DP0_RST
EN_REG
EN2
DGND
description
The TPS2070 and TPS2071 provide a complete
USB hub power solution by incorporating four
major functions: current-limited power switches
for four ports, a 3.3-V 100-mA regulator, a 5-V
regulator controller for self power, and a DP0 line
control to signal attach/detach of the hub.
These devices are designed to meet bus-powered and self-powered hub requirements. These
devices are also designed for hybrid hub
implementations and allow for automatic switching from self-powered mode to bus-powered
mode if loss of self-power is experienced (can be
disabled by applying a logic high to BP_DIS).
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
NC – No internal connection
† Pin 12 is active low (BPMODE) for TPS2070 and
active high (BPMODE) for TPS2071.
simplified hybrid-hub diagram‡
D+
D–
OUT1
SP
GATE
For applications not requiring a 5-V regulator
controller, use the TPS2074 or TPS2075 device.
5V
GND
OUT2
TPS2070
VEXT
DP0_RST
Power
Supply
D+
D–
OUT3
5V
GND
OUT4
BP
3.3 V_OUT
Each port has a current-limited 107-mΩ Nchannel MOSFET high-side power switch for
500 mA self-powered operation. Each port also
has a current-limited 560-mΩ N-channel MOSFET high-side power switch for 100-mA bus-powered operation. All the N-channel MOSFETs are
designed without parasitic diodes, preventing
current backflow into the inputs.
PG_DLY
BP_DIS
BP
OUT1
OUT2
OUT3
OUT4
OC4
OC3
OC2
OC1
EN4
EN3
CP_M
CP_P
VCP
BPMODE
1.5
kΩ
Downstream
Ports
Upstream
Port
Hub
Controller
DM0
5V
GND
5V
GND
DP2
DM2
DP3
DM3
DP4
DM4
DP0
D+
D–
D+
D–
DP1
DM1
VCC EN OC
D+
D–
5V
GND
‡ See Figure 38 for complete implementation.
SELECTION GUIDE
TA
USB HUB POWER CONTROLLERS
Four port with internal LDO controller
Four-port
PACKAGED DEVICES
PIN COUNT
32
– 40°C to 85°C
Four port without internal LDO controller
Four-port
24
BPMODE
HTSSOP (DAP)†
SSOP (DB)
—
Active low
TPS2070DAP
Active high
TPS2071DAP
—
Active low
—
TPS2074DB
—
TPS2075DB
Active high
† The DAP package is available taped and reeled. Add an R suffix to the device type (e.g., TPS2070DAPR).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
Copyright  2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
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1
TPS2070, TPS2071
FOUR-PORT USB HUB POWER CONTROLLERS
SLVS287A – SEPTEMBER 2000 – REVISED FEBRUARY 2001
functional block diagram
3.3 V/100 mA LDO
3.3 V_OUT
PG
PG_DLY
BP
S1
OUT1
SP
S2
SP
S3
OUT2
S4
S5
OUT3
S6
S7
OUT4
S8
DPO_RST
BP_DIS
AGND
DGND
Control
Logic
EN1
OC1
EN2
OC2
EN3
OC3
EN4
GATE
VEXT
VCP
2
OC4
LDO
Controller
CP_P
BPMODE (TPS2070)
BPMODE (TPS2071)
CP_M EN_REG
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• DALLAS, TEXAS 75265
TPS2070, TPS2071
FOUR-PORT USB HUB POWER CONTROLLERS
SLVS287A – SEPTEMBER 2000 – REVISED FEBRUARY 2001
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
NC
1
EN1
2
No internal connection
AGND
3
NC
4
PG
5
O
Logic output, power good
SP
6
I
Self-power voltage input, connects to local power supply
SP
7
I
Self-power voltage input, connects to local power supply
NC
8
VEXT
9
I
Input voltage for the external voltage regulator
GATE
10
O
Output gate drive for an external N-channel MOSFET
3.3V_OUT
BPMODE†
11
O
3.3-V internal voltage regulator output
12
O
A logic signal that indicates if the outputs source from the bus-powered supply. BPMODE (TPS2070) or
BPMODE (TPS2071) can be used to signal hub controller.
DP0_RST
13
O
Connects to DP signal from upstream hub/host through an external 1.5-kΩ resistor
EN_REG
14
I
Active-high enable, enables external voltage regulator. Connect to BP or GND
EN2
15
I
Active-low enable for OUT2
DGND
16
Digital ground
VCP
17
Charge-pump output, source for an external voltage-regulator driver. Recommend 0.1-µF capacitor to
DGND.
CP_P
18
Charge-pump-capacitor connection from CP_M. Recommend 0.01-µF between CP_P and CP_M.
CP_M
19
EN3
20
EN4
OC1
I
Active-low enable for OUT1
Analog ground
No internal connection
No internal connection
Charge-pump-capacitor connection from CP_P. Recommend 0.01-µ between CP_P and CP_M.
I
Active-low enable for OUT3
21
I
Active-low enable for OUT4
22
O
Logic output, overcurrent response for OUT1
OC2
23
O
Logic output, overcurrent response for OUT2
OC3
24
O
Logic output, overcurrent response for OUT3
OC4
25
O
Logic output, overcurrent response for OUT4
OUT4
26
O
Power switch output for downstream ports
OUT3
27
O
Power switch output for downstream ports
OUT2
28
O
Power switch output for downstream ports
OUT1
29
O
Power switch output for downstream ports
BP
30
I
Bus power voltage input, connect to VBUS
BP_DIS
31
I
Active-high logic input, disables autoswitch to bus power when self power is disconnected. Connect to BP
or GND
PG_DLY‡
32
Adjusts the PG time delay with a capacitor to ground. Adjust the pulsewidth to fit the application.
† Pin 12 is active low for TPS2070 and active high for TPS2071.
‡ Use the following formula to calculate the capacitance needed; C = (desired pulsewidth × 3 × 10–6)/1.22
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3
TPS2070, TPS2071
FOUR-PORT USB HUB POWER CONTROLLERS
SLVS287A – SEPTEMBER 2000 – REVISED FEBRUARY 2001
detailed description
BP
The bus-powered supply input (BP) serves as the source for the internal 3.3-V LDO and for all logic functions
in the device. In bus-powered mode, BP also serves as the source for all the outputs (OUTx). If BP is below the
undervoltage threshold, all power switches will turn off and the LDO will be disabled. BP must be connected to
a voltage source in order for the device to operate.
SP
The self-powered supply input (SP) serves as the source for all the outputs (OUTx) in self-powered mode. The
enable logic for the SP switches requires that BP be connected to a voltage source.
OUT1, OUT2, OUT2, OUT4
OUTx are the outputs of the integrated power switches.
3.3V_OUT
The internal 3.3-V LDO output can be used to supply up to 100 mA current to low-power functions, such as hub
controllers.
VEXT
VEXT is used to generate a 5-V source for the SP input by using the internal LDO controller and an external
N-channel MOSFET. This pin connects to a 6-V to 9-V power supply and to the drain of the MOSFET if the
external LDO is needed.
GATE
GATE is the output of the 5-V LDO controller and connects to the gate of the external MOSFET.
EN_REG
The active-high input, EN_REG, is used to enable the 5-V regulator controller. EN_REG is compatible with TTL
and CMOS logic levels.
DP0_RST
DP0_RST functions as a hub reset when a 1.5-kΩ resistor is connected between DP0_RST and the upstream
DP0 data line in a hub system. To provide a clean attach signal on DP0 data line, the DP0_RST output goes
low momentarily (because of the upstream pulldown resistor) to discharge any parasitic charge on the cable,
then goes to 3-state and finally outputs a high signal. The low and Hi-Z pulse widths are adjustable using a
capacitor between PG_DLY and ground, and are approximately 50% of the power-good time delay. Detachment
is signaled by a Hi-Z on DP0_RST. Both DP0_RST and PG will transition high at the same time.
Power Good (PG)
The power good (PG) function serves as a reset for a USB hub controller. PG is asserted low when the output
voltage on the internal voltage regulator is below a fixed threshold. A time delay to ensure a stable output voltage
before PG goes high is adjustable using a small-value ceramic capacitor from PG_DLY to ground.
PG_DLY
PG_DLY connects to an external capacitor to adjust the time delay for PG and DP0_RST. For USB applications,
a 0.1-µF capacitor is recommended, however, reference the USB Hub Controller data sheet to determine the
needed pulsewidth criteria.
4
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TPS2070, TPS2071
FOUR-PORT USB HUB POWER CONTROLLERS
SLVS287A – SEPTEMBER 2000 – REVISED FEBRUARY 2001
detailed description (continued)
BP_DIS
BP_DIS is used to enable or disable the autoswitching function between bus-powered mode and self-powered
mode. When BP_DIS is connected low and the voltage on SP is greater than the undervoltage-lockout (UVLO)
threshold, the device will switch to self-powered operation automatically; if the SP voltage falls lower than the
UVLO threshold, the device will switch to bus-powered operation. When BP_DIS is connected high, the
autoswitching function is disabled and the device will not autoswitch to bus-powered operation if the SP voltage
is below the UVLO threshold.
BPMODE or BPMODE
BPMODE (TPS2070) or BPMODE (TPS2071) is an output that signals when the device is in bus-powered
mode. The logic state is set according to the voltages on BP, SP, and BP_DIS. For the TPS2070, BPMODE
outputs a low signal to indicate bus-powered mode or a high signal to indicate self-powered mode. For the
TPS2071, BPMODE outputs a high signal to indicate bus-powered mode or a low signal to indicate self-powered
mode. This output can be used to inform a USB hub controller to configure for bus-powered mode or
self-powered mode.
OC1, OC2, OC3, OC4
OCx is an output signal that is asserted (active low) when an overcurrent or overtemperature condition is
encountered for the corresponding channel. OCx will remain asserted until the overcurrent or overtemperature
condition is removed.
EN1, EN2, EN3, EN4,
The active-low logic input ENx enables or disables the power switches in the device. The enable input is
compatible with both TTL and CMOS logic levels. The switches will not turn on until 3.3V_OUT is above the PG
threshold.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Input voltage range: VI(BP), VI(SP), VI(ENx), VI(EN_REG), VI(BP_DIS) . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V
VI(VEXT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 10 V
Output voltage range: VO(OUTx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V
VO(3.3V_OUT), VO(PG_DLY), VO(OCx), VO(BPMODE),
VO(DP0_RST), VO(PG) . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VO (3.3V_OUT) 0.3 V
VO(GATE), VO(CP_M), VO(CP_P), VO(VCP) . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V
Continuous output current: IO(OUTx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . internally limited
IO(3.3V_OUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . internally limited
Maximum output current:
IO(VCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±30 mA
IO(BPMODE) or IO(BPMODE), IO(DP0_RST), IO(PG), IO(OCx) . . . . . . . . . . ±10 mA
IO(GATE), sourcing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700 µA
IO(GATE), sinking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –2.2 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡ All voltages are with respect to GND.
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5
TPS2070, TPS2071
FOUR-PORT USB HUB POWER CONTROLLERS
SLVS287A – SEPTEMBER 2000 – REVISED FEBRUARY 2001
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
32-DAP
32-DAP†
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
1162.8 mW
11.6 mW/°C
639.5 mW
465.1 mW
4255.3 mW
42.5 mW/°C
2340.4 mW
1702.1 mW
† Using PowerPAD as heatsink.
recommended operating conditions
VI(BP)
VI(SP)
Input voltage
Continuous output current, IO
MIN
MAX
4.5
5.5
0
5.5
VI(VEXT)
VI(BP_DIS)
0
9
0
5.5
VI(ENx)
VI(EN_REG)
0
5.5
0
V
5.5
BP to OUTx (per switch)
100
SP to OUTx (per switch)
500
BP to 3.3V_OUT
UNIT
mA
100
Operating virtual junction temperature, TJ
-40
125
°C
electrical characteristics over recommended operating junction temperature range,
4.5 V ≤ VI(BP) ≤ 5.5 V, 4.85 V ≤ VI(SP) ≤ 5.5 V, 6 V ≤ VI(VEXT) ≤ 9 V, ENx = 0 V, EN_REG = 0 V,
BP_DIS = 0 V (unless otherwise noted)
input current
PARAMETER
IInputt currentt att BP
BP, switches
it h
disabled
TEST CONDITIONS†
No load
N
l d on OUTx
OUT and
d 3.3V_OUT,
3 3V OUT
ENx = VI(BP)
II(BP)
I
t currentt att BP
it h
Input
BP, switches
enabled
IInputt currentt att SP
SP, switches
it h
disabled
N load
l d on OUTx
OUT and
d 3.3V_OUT,
3 3V OUT
No
ENx = 0 V
No load
N
l d on OUTx
OUT and
d 3.3V_OUT,
3 3V OUT
ENx = VI(SP)
II(SP)
IInputt currentt att SP
SP, switches
it h
enabled
II(VEXT)
No load
N
l d on OUTx
OUT and
d 3.3V_OUT,
3 3V OUT
ENx = 0V
Input current at VEXT, LDO
controller disabled
VI(EN_REG) = 0 V or Hi-Z,
VI(BP) = 5 V,
VI(SP) = Hi-Z
Input current, at VEXT, LDO
controller enabled
VI(EN_REG) = 5 V,
VI(BP) = 5 V,
VI(SP) = Hi-Z
TYP
MAX
VI(SP) = Hi-Z
VI(SP) = 0 V
MIN
185
240
185
240
VI(SP) = 5 V
VI(SP) = Hi-Z
175
210
185
240
VI(SP) = 0 V
VI(SP) = 5 V
185
240
175
210
VI(BP) = Hi-Z
VI(BP) = 0 V
90
115
90
115
VI(BP) = 5 V
VI(BP) = Hi-Z
115
140
90
115
VI(BP) = 0 V
VI(BP) = 5 V
UNIT
µA
µA
µA
µA
90
115
115
140
200
360
µA
10
mA
† Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS2070, TPS2071
FOUR-PORT USB HUB POWER CONTROLLERS
SLVS287A – SEPTEMBER 2000 – REVISED FEBRUARY 2001
electrical characteristics over recommended operating junction temperature range,
4.5 V ≤ VI(BP) ≤ 5.5 V, 4.85 V ≤ VI(SP) ≤ 5.5 V, 6 V ≤ VI(VEXT) ≤ 9 V, ENx = 0 V, EN_REG = 0 V,
BP_DIS = 0 V (unless otherwise noted) (continued)
power switches
PARAMETER
Static
drain-source
on-state
resistance
i t
rDS(on)
DS( )
Ilkg(OUTx)
TEST CONDITIONS
SP to
OUTx
BP to
OUTx
L k
Leakage
currentt att
OUTx (no load on
3.3V_OUT)
3 3V OUT)
Short circuit current
Short-circuit
(per output)†
MIN
TYP
MAX
VI(SP) = VI(BP) = 5 V
V, IOx
0.5
5A
O =0
TA = 25°C
TA = 70°C
107
VI(BP) = 4
4.5
5V
V,
TA = 25°C
TA = 70°C
560
630
900
ENx = VI(BP) = 5.5 V, VI(SP) = Hi-Z,
OUTx connected to ground, VI(VIN) = Hi-Z
TJ = 25°C
0.5
10
ENx = VI(BP) = VI(SP) = 5.5 V,
OUTx connected to ground, VI(EXT) = Hi-Z
TJ = 25°C
0.5
10
ENx = VI(BP) = Hi-Z or 0 V,
VI(VEXT) = VI(SP)= VI(OUTx) = 5.5 V
TJ = 25°C
0.5
10
ENx = VI(BP) = VI(SP) = Hi-Z or 0 V,
VI(VEXT) = VI(OUTx) = 5.5 V
TJ = 25°C
0.5
10
ENx = VI(BP) = VI(SP) = VI(VEXT) = Hi–Z or 0 V,
VI(OUTx) = 5.5 V
TJ = 25°C
0.5
10
VI(SP) = Open
Open, IOx
0.1
1A
O =0
125
160
VI(BP) = VI(SP) = 5 V,
OUTx connected to GND,
Device enabled into short circuit
0.6
0.9
1.2
VI(BP) = 5 V, VI(SP) = open,
OUTx connected to GND, device enabled into short
circuit
0.12
0.2
0.3
UNIT
mΩ
µA
A
† Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
input signals (ENx, EN_REG, BP_DIS)
PARAMETER
VIH
VIL
High-level input voltage
II
Input current
TEST CONDITIONS
MIN
TYP
MAX
2
Low-level input voltage
0.8
Pullup
ENx (active low)
Pulldown
VI(ENx) = 0 V
VI(EN_REG) = 5 V
5
EN_REG (active high)
BP_DIS (active high)
VI(BP_DIS) = 5 V
5
POST OFFICE BOX 655303
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5
UNIT
V
µA
7
TPS2070, TPS2071
FOUR-PORT USB HUB POWER CONTROLLERS
SLVS287A – SEPTEMBER 2000 – REVISED FEBRUARY 2001
electrical characteristics over recommended operating junction temperature range,
4.5 V ≤ VI(BP) ≤ 5.5 V, 4.85 V ≤ VI(SP) ≤ 5.5 V, 6 V ≤ VI(VEXT) ≤ 9 V, ENx = 0 V, EN_REG = 0 V,
BP_DIS = 0 V (unless otherwise noted) (continued)
output signals (BPMODE or BPMODE, OCx, DPO_RST)
PARAMETER
VOH
VOL
TEST CONDITIONS
High-level
g
output
voltage
Low-level output voltage
BPMODE
4.25 V ≤ VI(BP) ≤ 5.5 V,
4.5 V ≤ VI(SP) ≤ 5.5 V
BPMODE
4.25 V ≤ VI(BP) ≤ 5.5 V,
VI(SP) < 4 V
OCx
4.25 V ≤ VI(BP) ≤ 5.5 V,
VI(ENx) = 3.3 V or Hi-Z
DPO_RST
4.25 V ≤ VI(BP) ≤ 5.5 V,
VI(PG_DLY) = 3.3 V
BPMODE
4.25 V ≤ VI(BP) ≤ 5.5 V,
VI(SP) < 4 V
BPMODE
4.25 V ≤ VI(BP) ≤ 5.5 V,
4.5 V ≤ VI(SP) ≤ 5.5 V
OCx
4.25 V ≤ VI(BP) ≤ 5.5 V,
OUTx = 0 V
MIN
TYP
MAX
UNIT
2.4
2.4
IO = 2 mA
V
2.4
2.4
0.4
IO = 3.2
3 2 mA
0.4
IO(OC) = 3.2 mA
0.4
VO(BPMODE)≤ 0.4 V
VO(BPMODE)≤ 0.4 V,
1.5
VI(BP)
Minimum input voltage at BP for low-level
low level
output
IO = 300 µA,
IO = 300 µA,
VI(SP) = 5 V
Ilkg
Hi-Z leakage current at DP0_RST
0 V ≤ VI(DPO_RST) ≤ 3.3 V, VI(SP) = 0 V,
VI(BP) = 5.5 V, VI(PG_DLY) = 0.9 V
td
Overcurrent response delay time
(see Note 1)
1.5
V
V
–5
5
µA
1
10
ms
NOTE 1: Specified by design, not tested in production.
undervoltage lockout (SP, BP, VEXT)
PARAMETER
TEST CONDITIONS
MIN
SP
Start threshold
BP
Vhys
y
Hysteresis voltage (see Note 1)
4.25
4
BP
3.75
VEXT
2.50
SP
300
BP
300
VEXT
150
POST OFFICE BOX 655303
UNIT
V
3
SP
NOTE 1: Specified by design, not tested in production.
8
MAX
4.5
VI(SP) = Hi-Z
VEXT
Stop threshold
TYP
• DALLAS, TEXAS 75265
V
mV
TPS2070, TPS2071
FOUR-PORT USB HUB POWER CONTROLLERS
SLVS287A – SEPTEMBER 2000 – REVISED FEBRUARY 2001
electrical characteristics over recommended operating junction temperature range,
4.5 V ≤ VI(BP) ≤ 5.5 V, 4.85 V ≤ VI(SP) ≤ 5.5 V, 6 V ≤ VI(VEXT) ≤ 9 V, ENx = 0 V, EN_REG = 0 V,
BP_DIS = 0 V, CL(3.3V_OUT) = 10 µF (unless otherwise noted)
internal voltage regulator
PARAMETER
VO
TEST CONDITIONS
Output voltage, dc
VI(BP) = 4.25 V to 5.5 V,
IO = 100 mA
Dropout voltage
Line regulation
VI(BP) = 4.25 V to 5.25 V, IO = 5 mA
VI(BP) = 4.25 V,
IO = 5 mA to 100 mA
VI(BP) = 4.25 V, 3.3V_OUT connected to GND
Load regulation
IOS
Short-circuit current limit†
VI(3.3V_OUT) = 3.3 V
Pulldown transistor at 3.3V_OUTPUT
(see Note 1)
PSRR
IO = 5 mA to 100 mA
VI(3.3V_OUT) = 1 V
Power-supply ripple rejection (see Note 1)
F = 1 kHz, CL(3.3V_OUT) = 4.7 µF,
ESR = 0.25 Ω , IO = 5 mA,
VI(BP)PP = 100 mV
Low-level trip threshold voltage at PG
Vhys
VOH
Hysteresis voltage at PG (see Note 1)
VOL
Vref
Low-level output voltage at PG
High-level output voltage at PG
MIN
TYP
MAX
3.2
3.3
3.4
V
0.1
%/v
0.6
0.2
Charge current at PG_DLY
0.3
10
A
mA
5
40
dB
2.94
50
Reference voltage at PG_DLY
V
0.6%
0.12
2.88
4.25 V ≤ VI(BP) ≤ 5.25 V, IO = 2 mA
4.25 V ≤ VI(BP) ≤ 5.25 V, IO = 3.2 mA
UNIT
3
100
2.4
V
mV
V
0.4
V
1.22
V
3
uA
td
Delay time at PG (see Notes 1 and 2)
CL(PG_DLY) = 0.47 µF
190
ms
† Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
NOTES: 1. Specified by design, not tested in production.
2. The PG delay time (td) is calculated using the PG_DLY reference voltage and charge current:
t
+
d
C
V
ref
L(PG_DLY)
Charge Current
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
TPS2070, TPS2071
FOUR-PORT USB HUB POWER CONTROLLERS
SLVS287A – SEPTEMBER 2000 – REVISED FEBRUARY 2001
electrical characteristics over recommended operating junction temperature range,
4.5 V ≤ VI(BP) ≤ 5.5 V, 4.85 V ≤ VI(SP) ≤ 5.5 V, 6 V ≤ VI(VEXT) ≤ 9 V, ENx = 0 V, EN_REG = 3.3 V,
BP_DIS = 0 V, CL(SP) = 220 µF (unless otherwise noted)
voltage regulator controller
PARAMETER
TEST CONDITIONS
VO(CP)
Output voltage, charge pump
VI(VEXT) = 6 V,
C(CP_P) = 10 nF,
IO(VCP) = 5 mA
C(VCP)=100 nF
fosc
Oscillator frequency (see Note 1)
6 V ≤ VI(VEXT) ≤ 9 V, IO(VCP) = 5 mA,
VO(VCP)= 10 V
MIN
TYP
MAX
10
UNIT
V
850
kHz
Sourcing
VI(VCP) = 9 V, VO(GATE) = 7.5 V,
VI(SP) = 4.5 V
500
µA
Sinking
VI(VCP) = 9 V, VO(GATE) = 5.5 V,
VI(SP) = 5.5 V
1.5
mA
Gate drive current
Open-loop gain (see Note 1)
VI(VEXT) = 6 V, 0.5 V ≤ VO(GATE) ≤ 9 V
Reference voltage at VI(SP), using external
regulator
VI(VEXT) = 6 V to 9 V,
Gate clamp voltage
Gate to SP
IRLZ24N FET
80
4.90
5.1
dB
5.25
10
V
V
NOTE 1: Specified by design, not tested in production.
power switch timing requirements
TEST CONDITIONS†
PARAMETER
ton
toff
ff
tr
BP to OUTx
switch
Turnon time (see Note 1)
SP to OUTx
switch
BP to OUTx
switch
Turnoff time (see Note 1)
time output (see Note 1)
Rise time,
VI(BP) = 5 V, VI(SP) = open, TA = 25°C,
CL = 100 µF, RL = 50 Ω
VI(SP) = VI(BP) = 5 V, TA = 25°C,
CL = 100 µF, RL = 10 Ω
BP to OUTx
switch
VI(BP) = 5 V, VI(SP) = open, TA = 25°C,
CL = 100 µF, RL = 50 Ω
VI(SP) = VI(BP) = 5 V, TA = 25°C,
CL = 100 µF, RL = 10 Ω
VI(BP) = 5 V, VI(SP) = open, TA = 25°C,
CL = 100 µF, RL = 50 Ω
SP to OUTx
switch
VI(SP) = VI(BP) = 5 V, TA = 25°C,
CL = 100 µF, RL = 10 Ω
SP to OUTx
switch
MIN
TYP
MAX
UNIT
4.5
ms
4.5
15
ms
10
4
ms
3
BP to OUTx
switch
VI(BP) = 5 V, VI(SP) = open, TA = 25°C,
10
CL = 100 µF, RL = 50 Ω
time output (see Note 1)
tf
Fall time,
ms
SP to OUTx
VI(SP) = VI(BP) = 5 V, TA = 25°C,
3
switch
CL = 100 µF, RL = 10 Ω
† Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
NOTE 1. Specified by design, not tested in production.
thermal shutdown
PARAMETER
TJ
Thermal shutdown
Hysteresis
10
MIN
TYP
First
140
Second
150
First
15
Second
25
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MAX
UNIT
°C
°C
TPS2070, TPS2071
FOUR-PORT USB HUB POWER CONTROLLERS
SLVS287A – SEPTEMBER 2000 – REVISED FEBRUARY 2001
PARAMETER MEASUREMENT INFORMATION
Current
Meter
IN
50%
VI(ENx)
DUT
50%
tpd(off)
ton
OUT
+
toff
tpd(on)
90%
VO(OUTx)
10%
90%
10%
tr
TEST CIRCUIT
tf
90%
VO(OUTx)
10%
Figure 1. Current Limit Response
90%
10%
TIMING
Figure 2. Timing and Internal Voltage Regulator
Transition Waveforms
VI(BP) = 5 V
TA = 25°C
CL = 10 µF
RL = 50 Ω
VI(EN)
(2 V/div)
VI(EN)
(2 V/div)
VO(out)
(2 V/div)
VI(BP) = 5V
TA = 25°C
CL = 10 µF
RL = 50 Ω
VO(OUT)
(2 V/div)
0
2
4
6
8
10 12
t – time – ms
14
16
18
20
Figure 3. Turnon Delay and Rise Time
(BP Switch)
POST OFFICE BOX 655303
0
2
4
6
8
10 12
t – time – ms
14
16
18
20
Figure 4. Turnoff Delay and Fall Time
(BP Switch)
• DALLAS, TEXAS 75265
11
TPS2070, TPS2071
FOUR-PORT USB HUB POWER CONTROLLERS
SLVS287A – SEPTEMBER 2000 – REVISED FEBRUARY 2001
PARAMETER MEASUREMENT INFORMATION
VI(BP) = VI(SP) = 5 V
TA = 25°C
CL = 10 µF
RL = 10 Ω
VI(BP) = VI(SP) = 5V
TA = 25°C
CL = 10 µF
RL = 10 Ω
VI(EN)
(2 V/div)
VI(EN)
(2 V/div)
VO(out)
(2 V/div)
VO(OUT)
(2 V/div)
0
2
4
6
8
10 12
t – time – ms
14
16
18
20
0
Figure 5. Turnon Delay and Rise Time
(SP Switch)
2
4
6
VI(BP)
(2 V/div)
VO
3.3V_OUT)
(1 V/div)
VO
(3.3V_OUT)
(1 V/div)
8
12
16 20 24
t – time – ms
28
32
36
40
Figure 7. Turnon Delay and Rise Time
(3.3V_OUT)
12
16
18
20
TA = 25°C
CL = 4.7 µF
RL = 33 Ω
VI(BP)
(2 V/div)
4
14
Figure 6. Turnoff Delay and Fall Time
(SP Switch)
TA = 25°C
CL = 4.7 µF
RL = 33 Ω
0
8
10 12
t – time – ms
POST OFFICE BOX 655303
0
20
40
60
80 100 120 140 160 180 200
t – time – ms
Figure 8. Turnoff Delay and Fall Time
(3.3V_OUT)
• DALLAS, TEXAS 75265
TPS2070, TPS2071
FOUR-PORT USB HUB POWER CONTROLLERS
SLVS287A – SEPTEMBER 2000 – REVISED FEBRUARY 2001
PARAMETER MEASUREMENT INFORMATION
VO
(3.3V_OUT)
(2 V/div)
VO
(3.3V_OUT)
(2 V/div)
VO
(PG_DLY)
(2 V/div)
VI(BP) = 5 V
TA = 25°C
CL(PG_DLY) = 0.47 µF
0
400
800
1200
VI(BP) = 5 V
TA = 25°C
CL(PG_DLY) = 0.47 µF
VO(PG)
(2 V/div)
1600
2400
3200
4000
2000
2800
3600
t – time – ms
0
Figure 9. PG_DLY Rise Time With a 0.47-µF Capacitor
100 200 300 400 500 600 700 800 900 1000
t – time – ms
Figure 10. Turnon Delay (3.3V_OUT to PG)
VI(BP) = 5 V
TA = 25°C
CL(PG_DLY) = 0.47 µF
VI(BP) = 5 V
TA = 25°C
VO
(3.3V_OUT)
(2 V/div)
VI(EN)
(2 V/div)
VO(PG)
(2 V/div)
IO(OUT)
(0.1A/div)
0
1
2
3
4
5
6
t – time – ms
7
8
9
10
Figure 11. Turnoff Time (3.3V_OUT to PG)
POST OFFICE BOX 655303
0
1
2
3
4
5
6
t – time – ms
7
8
9
10
Figure 12. Short-Circuit Current (BP Switch),
Device Enabled Into Short
• DALLAS, TEXAS 75265
13
TPS2070, TPS2071
FOUR-PORT USB HUB POWER CONTROLLERS
SLVS287A – SEPTEMBER 2000 – REVISED FEBRUARY 2001
PARAMETER MEASUREMENT INFORMATION
VI(BP) = VI(SP) = 5 V
TA = 25°C
VI(BP) = VI(SP) = 5 V
TA = 25°C
VI(EN)
(2 V/div)
VO(OC)
(2 V/div)
IO(OUT)
(0.5 A/div)
IO(OUT)
(0.5 A/div)
0
1
2
3
4
5
6
t – time – ms
7
8
9
0
10
1
2
3
VO(OC)
(2 V/div)
VO(PG)
(2 V/div)
IO(OUT)
(0.1 A/div)
VO
(3.3V_OUT)
(1 V/div)
2
3
4
5
6
t – time – ms
7
8
9
10
0
2
9
POST OFFICE BOX 655303
4
6
8
10 12
t – time – ms
14
16
18
Figure 16. SP to BP Automatic
Switchover Enabled
Figure 15. OC Response (BP Switch),
Device Enabled Into Short
14
8
10
VI(BP) = 5 V
TA = 25°C
BP_DIS = 0 V or Open
CL(3.3 V_OUT) = 4.7 µF
RL(3.3 V_OUT) = 33 Ω
CL(PG_DLY) = 0.47 µF
VI(BP) = 5 V
TA = 25°C
1
7
Figure 14. OC Response (SP Switch),
Device Enabled Into Short
Figure 13. Short-Circuit Current (SP Switch),
Device Enabled Into Short
0
4
5
6
t – time – ms
• DALLAS, TEXAS 75265
20
TPS2070, TPS2071
FOUR-PORT USB HUB POWER CONTROLLERS
SLVS287A – SEPTEMBER 2000 – REVISED FEBRUARY 2001
PARAMETER MEASUREMENT INFORMATION
VI(BP) = 5 V
TA = 25°C
BP_DIS = 0 V or Open
VI(BP) = 5 V
TA = 25°C
BP_DIS = 5 V
VO(PG)
(2 V/div)
VO(PG)
(2 V/div)
VO
(3.3V_OUT)
(1 V/div)
VO
(DPO_RST)
(1 V/div)
0
1
2
3
4
5
6
t – time – ms
7
8
9
0
10
Figure 17. SP to BP Automatic
Switchover Disabled
40
80
120 160 200 240 280 320 360 400
t – time – ms
Figure 18. SP to BP Automatic
Switchover Enabled
VI(BP) = 5 V
TA = 25°C
BP_DIS = 5 V
5.25 V
VI(BP)
4.25 V
VO(PG)
(2 V/div)
∆VO
(3.3V_OUT)
(0.05 V/div)
VO
(DPO_RST)
(1 V/div)
TA = 25°C
CL (3.3 V–OUT) = 4.7 µF
IO (3.3 V–OUT) = 100 mA
0
40
80
120 160 200 240 280 320 360 400
t – time – ms
Figure 19. SP to BP Automatic
Switchover Disabled
POST OFFICE BOX 655303
0
100 200 300 400 500 600 700 800 900 1000
t – time – µs
Figure 20. Line Transient Response
• DALLAS, TEXAS 75265
15
TPS2070, TPS2071
FOUR-PORT USB HUB POWER CONTROLLERS
SLVS287A – SEPTEMBER 2000 – REVISED FEBRUARY 2001
PARAMETER MEASUREMENT INFORMATION
TA = 25°C
CL (3.3 V_OUT) = 10 µF
IO(3.3 V_OUT)
(100 mA/div)
∆VO
(3.3 V_OUT)
(100 mV/div)
0
100 200 300 400 500 600 700 800 900 1000
t – Time – µs
Figure 21. Load Transient Response
TYPICAL CHARACTERISTICS
BP SUPPLY CURRENT
vs
INPUT VOLTAGE
BP SUPPLY CURRENT
vs
JUNCTION TEMPERATURE
205
196
VI(BP) = 5 V
200
192
190
Output Enabled
188
186
184
Output Disabled
182
I I(BP) – Supply Current – µ A
I I(BP) – Supply Current – µ A
194
195
185
Output Disabled
180
175
170
180
–60 –40 –20
0
20
40
60
80
100 120 140
165
4.25
TJ – Junction Temperature – °C
Figure 22
16
Output Enabled
190
4.5
5.25
4.75
5
VI(BP) – Input Voltage – V
Figure 23
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5.5
TPS2070, TPS2071
FOUR-PORT USB HUB POWER CONTROLLERS
SLVS287A – SEPTEMBER 2000 – REVISED FEBRUARY 2001
TYPICAL CHARACTERISTICS
SP SUPPLY CURRENT
vs
INPUT VOLTAGE
SP SUPPLY CURRENT
vs
JUNCTION TEMPERATURE
120
120
VI(SP) = 5 V
115
I I(SP) – Supply Current –
µA
I I(SP) – Supply Current – µ A
115
110
Outputs Disabled
105
Outputs Enabled
100
Outputs Disabled
110
Outputs Enabled
105
100
95
4.5
95
–60 –40 –20 0
20 40 60 80 100 120 140
TJ – Junction Temperature – °C
200
VI(SP) = 5 V
160
140
120
100
80
60
40
20
0
–40
85
0
25
TJ – Junction Temperature – °C
125
DS(on) – Static Drain-Source On-State Resistance – m Ω
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
(SELF-POWER SWITCHES)
180
5.5
Figure 25
r
r
DS(on) – Static Drain-Source On-State Resistance – mΩ
Figure 24
5
VI(SP) – Input Voltage – V
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
(BUS POWER SWITCHES)
800
700
600
VI(BP) = 5.5 V
500
VI(BP) = 4.5 V
400
300
200
100
0
–40
0
25
85
TJ – Junction Temperature – °C
125
Figure 27
Figure 26
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• DALLAS, TEXAS 75265
17
TPS2070, TPS2071
FOUR-PORT USB HUB POWER CONTROLLERS
SLVS287A – SEPTEMBER 2000 – REVISED FEBRUARY 2001
TYPICAL CHARACTERISTICS
SHORT-CIRCUIT OUTPUT CURRENT
vs
JUNCTION TEMPERATURE
(BUS-POWER SWITCHES)
SHORT-CIRCUIT OUTPUT CURRENT
vs
JUNCTION TEMPERATURE
(BUS-POWER SWITCHES)
300
250
VI(BP) = 5.5 V
280
I OS – Short-Circuit Output Current – mA
I OS – Short-Circuit Output Current – mA
VI(BP) = 4.25 V
260
240
220
200
180
160
140
–40
0
25
85
230
210
190
170
150
130
110
–40
125
TJ – Junction Temperature – °C
SHORT-CIRCUIT OUTPUT CURRENT
vs
JUNCTION TEMPERATURE
(SELF-POWER SWITCHES)
I OS – Short-Circuit Output Current – mA
VI(SP) = 5 V
980
960
940
920
900
880
860
840
820
0
25
85
TJ – Junction Temperature – °C
125
VI(BP) – Input Voltage (BP Undervoltage Lockout) – V
INPUT VOLTAGE (BP UNDERVOLTAGE LOCKOUT)
vs
JUNCTION TEMPERATURE
1000
4.25
Start Threshold
4.2
4.15
4.1
4.05
4
3.95
3.9
3.85
Stop Threshold
3.8
3.75
–50
Figure 30
18
125
Figure 29
Figure 28
800
–40
0
25
85
TJ – Junction Temperature – °C
100
0
50
TJ – Junction Temperature – °C
Figure 31
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150
TPS2070, TPS2071
FOUR-PORT USB HUB POWER CONTROLLERS
SLVS287A – SEPTEMBER 2000 – REVISED FEBRUARY 2001
TYPICAL CHARACTERISTICS
INPUT CURRENT
vs
JUNCTION TEMPERATURE
150
4.5
4.45
VI(VEXT) = 6 V
EN_REG = LOW
Start Threshold
145
4.4
I I(VEXT)– Input Current – µ A
VI(SP) – Input Voltage (SP Undervoltage Lockout) – V
INPUT VOLTAGE (SP UNDERVOLTAGE LOCKOUT)
vs
JUNCTION TEMPERATURE
4.35
4.3
4.25
4.2
4.15
140
135
130
125
4.1
Stop Threshold
4.05
4
–50
100
0
50
TJ – Junction Temperature – °C
120
–50
150
Figure 32
INPUT CURRENT
vs
INPUT VOLTAGE
5
VI(BP) = 5 V,
EN_REG = HIGH,
C(VCP) = 0.1 µF,
C(CP_P) = 0.01 µF,
TA = 25°C
6
I I(VEXT) – Input Current – mA
I I(VEXT) – Input Current – mA
7
VI(VEXT) = 6 V
EN_REG = HIGH
4.8
4.7
4.6
4.5
4.4
4.3
4.2
–50
150
Figure 33
INPUT CURRENT
vs
JUNCTION TEMPERATURE
4.9
100
0
50
TJ – Junction Temperature – °C
5
4
3
2
1
0
50
100
TJ – Junction Temperature – °C
150
0
6
Figure 34
7
8
VI(VEXT) – Input Voltage – V
9
Figure 35
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TPS2070, TPS2071
FOUR-PORT USB HUB POWER CONTROLLERS
SLVS287A – SEPTEMBER 2000 – REVISED FEBRUARY 2001
TYPICAL CHARACTERISTICS
UNDERVOLTAGE LOCKOUT
vs
JUNCTION TEMPERATURE
SUPPLY CURRENT
vs
INPUT VOLTAGE
2.9
VI(BP) = 5 V,
EN_REG = LOW,
C(VCP) = 0.1 µF,
C(CP_P) = 0.01 µF,
TA = 25°C
200
Start Threshold
VI(VEXT) – Undervoltage Lockout – V
I I(VEXT)– Input Current – µ A
250
150
100
50
0
6
6.5
8
8.5
7.5
VI(VEXT) – Input Voltage – V
7
9
2.85
2.8
2.75
2.7
2.65
2.6
–50
Figure 36
Stop Threshold
100
0
50
TJ – Junction Temperature – °C
150
Figure 37
APPLICATION INFORMATION
external capacitor requirements
A 0.1-µF ceramic bypass capacitor and a 10-µF bulk capacitor between BP and AGND, close to the device, are
recommended. Similarly, a 0.1-µF ceramic and a 68-µF bulk capacitor, from SP to AGND, and from VEXT to
AGND if an external 5-V LDO is required, are recommended because of much higher current in the self-powered
mode.
From each of the outputs (OUTx) to ground, a 33-µF or higher valued bulk capacitor is recommended when the
output load is heavy. This precaution reduces power-supply transients. Additionally, bypassing the outputs with
a 0.1-µF ceramic capacitor improves the immunity of the device to short-circuit transients.
An output capacitor connected between 3.3V_OUT and GND is required to stabilize the internal control loop.
The internal LDO is designed for a capacitor range of 4.7 µF to 33 µF with an ESR of 0.2 Ω to 10 Ω. Solid
tantalum-electrolytic, aluminum-electrolytic and multilayer ceramic capacitors are all suitable.
Ceramic capacitors have different types of dielectric material, each exhibiting different temperature and voltage
variations. The most common types are X5R, X7R, Y5U, Z5U, and NPO. The NPO type ceramic capacitors are
generally the most stable over temperature. However, the X5R and X7R are also relatively stable over
temperature (with the X7R being the more stable of the two) and are therefore acceptable for use. The Y5U and
Z5U types provide high capacitance in a small geometry, but exhibit large variations over temperature. For this
reason, the Y5U and Z5U are not generally recommended.
20
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TPS2070, TPS2071
FOUR-PORT USB HUB POWER CONTROLLERS
SLVS287A – SEPTEMBER 2000 – REVISED FEBRUARY 2001
APPLICATION INFORMATION
external capacitor requirements (continued)
A transient condition occurs because of a sudden increase in output current. The output capacitor reduces the
transient effect by providing the additional current needed by the load. Depending on the current demand at the
output, a voltage drop will occur across the internal resistance, ESR, of the capacitor. Using a low ESR capacitor
will help minimize this voltage drop. A larger capacitor will also reduce the voltage drop by supplying the current
demand for a longer time, versus that provided by a smaller capacitor.
overcurrent
An internal sense FET checks for overcurrent conditions. Unlike current-sense resistors, sense FETs do not
increase the series resistance of the current path. When an overcurrent condition is detected, the device
maintains a constant output current and reduces the output voltage accordingly. Complete shutdown occurs
only if the fault is present long enough to activate thermal limiting.
Three possible overload conditions can occur. In the first condition, the output has been shorted before the
device is enabled or before BP and SP have been applied. The TPS2070 and TPS2071 sense the short and
immediately switch into a constant-current output.
In the second condition, the short occurs while the device is enabled. At the instant the short occurs, very high
currents may flow for a very short time before the current-limit circuit can react. After the current-limit circuit has
tripped (reached the overcurrent trip threshold), the device switches into constant-current mode.
In the third condition, the load has been gradually increased beyond the recommended operating current. The
current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is
exceeded. The TPS2070 and TPS2071 are capable of delivering current up to the current-limit threshold without
damaging the device. Once the threshold has been reached, the device switches into its constant-current mode.
OC response
The OCx output is asserted (active low) when an overcurrent or overtemperature condition is encountered and
will remain asserted until the overcurrent or overtemperature condition is removed. Connecting a heavy
capacitive load to an enabled device can cause momentary false overcurrent reporting from the inrush current
flowing through the device and charging the downstream capacitor. The TPS2070 and TPS2071 are designed
to reduce false overcurrent reporting by implementing an internal deglitch circuit. This circuit eliminates the need
for an external filter, which requires extra components. Also, using low-ESR electrolytic capacitors on the
outputs can reduce erroneous overcurrent reporting by providing a low-impedance energy source to lower the
inrush current flow through the device during hot-plug events. The OCx outputs are logic outputs thereby
requiring no pullup or pulldown resistors.
POST OFFICE BOX 655303
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21
TPS2070, TPS2071
FOUR-PORT USB HUB POWER CONTROLLERS
SLVS287A – SEPTEMBER 2000 – REVISED FEBRUARY 2001
APPLICATION INFORMATION
power dissipation and junction temperature
The major source of power dissipation for the TPS2070 and TPS2071 comes from the internal voltage regulator
and the N-channel MOSFETs. Checking the power dissipation and junction temperature is always a good
design practice. Begin by determining the rDS(on) of the N-channel MOSFET according to the input voltage and
operating temperature. As an initial estimate, use the highest operating ambient temperature of interest and
read rDS(on) from the graphs shown under the typical characteristics section of this data sheet. Using this value,
the power dissipation per switch can be calculated by:
PD
+ rDS(on)
I2
Multiply this number by four to get the total power dissipation coming from the N-channel MOSFETs.
ǒ
Ǔ
The power dissipation for the internal voltage regulator is calculated using:
PD
+
V
I(BP)
–V
O(min)
I
O(OUT)
ǒ
The total power dissipation for the device becomes:
P D(total)
+ PD(voltage regulator) )
4
P
D(switch)
Ǔ
Finally, calculate the junction temperature:
TJ
Where:
+ PD
R qJA
) TA
TA = ambient temperature °C
RθJA = Thermal resistance °C/W, equal to inverting of derating factor found on the power dissipation
table in this data sheet.
Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,
repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally
sufficient to get a reasonable answer.
22
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS2070, TPS2071
FOUR-PORT USB HUB POWER CONTROLLERS
SLVS287A – SEPTEMBER 2000 – REVISED FEBRUARY 2001
APPLICATION INFORMATION
thermal protection
Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for
extended periods. The faults force the TPS2070 and TPS2071 into constant-current mode at first, which causes
the voltage across the high-side switch to increase; under short-circuit conditions, the voltage across the switch
is equal to the input voltage. The increased dissipation causes the junction temperature to rise to high levels.
The protection circuit senses the junction temperature of the switch and shuts it off. Hysteresis is built into the
thermal sense circuit, and after the device has cooled approximately 20 degrees the switch turns back on. The
switch continues to cycle in this manner until the load fault or input power is removed.
The TPS2070 and TPS2071 implement a dual thermal trip to allow fully independent operation of the power
distribution switches. In an overcurrent or short-circuit condition the junction temperature rises. Once the die
temperature rises to approximately 140°C, the internal thermal-sense circuitry determines which power switch
is in an overcurrent condition and turns only that power switch off, thus isolating the fault without interrupting
operation of the adjacent power switch. If the die temperature exceeds the first thermal trip point of 140°C and
reaches 150°C, the device turns off. The OC output is asserted (active low) when overtemperature or
overcurrent occurs.
undervoltage lockout (UVLO)
An undervoltage lockout ensures that the device (LDO and switches) is in the off state at power up. The UVLO
will also keep the device from being turned on until the power supply has reached the start threshold (see
undervoltage lockout table), even if the switches are enabled. The UVLO will activate whenever the input
voltage falls below the stop threshold as defined in the undervoltage lockout table. This facilitates the design
of hot-insertion systems where it is not possible to turn off the power switches before input power is removed.
Upon reinsertion, the power switches will be turned on with a controlled rise time to reduce EMI and voltage
overshoots.
self-power to bus-power or bus-power to self-power transition
An autoswitching function between bus-powered mode and self-powered mode is a feature of the TPS2070 and
TPS2071. When this feature is enabled (BP_DIS is inactive) and SP is removed or applied, a transition will be
initiated. The transition sequence begins with the internal LDO being turned off and its external capacitance
discharged. Any enabled switches are also turned off and the external capacitors discharged. Once the LDO
and switch outputs are low, the internal logic will turn the LDO back on. This entire sequence occurs whenever
power to the SP input is removed or applied, regardless of the source of power, i.e., an external power supply
or the use of the external regulator.
POST OFFICE BOX 655303
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23
TPS2070, TPS2071
FOUR-PORT USB HUB POWER CONTROLLERS
SLVS287A – SEPTEMBER 2000 – REVISED FEBRUARY 2001
APPLICATION INFORMATION
universal serial bus (USB) applications
The universal serial bus (USB 1.1) interface is a 12-Mb/s, 1.5-Mb/s, or 480 Mb/s (USB 2.0), multiplexed serial
bus designed for low-to-medium bandwidth PC peripherals (e.g., keyboards, printers, scanners, and mice). The
four-wire USB interface is conceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are
provided for differential data, and two lines are provided for 5-V power distribution.
USB data is a 3.3-V-level signal, but power is distributed at 5 V to allow for voltage drops in cases where power
is distributed through more than one hub or across long cables. Each function must provide its own regulated
3.3 V from the 5-V input or its own internal power supply.
The USB specification defines the following five classes of devices, each differentiated by power-consumption
requirements:
D
D
D
D
D
Hosts/self-powered hubs (SPH)
Bus-powered hubs (BPH)
Low-power, bus-powered functions
High-power, bus-powered functions
Self-powered functions
Self-powered and bus-powered hubs distribute data and power to downstream functions. The TPS2070 and
TPS2071 can provide power-distribution solutions for hybrid hubs that need switching between BPH and SPH
according to power availability and application requirements.
USB power-distribution requirements
USB can be implemented in several ways, and, regardless of the type of USB device being developed, several
power-distribution features must be implemented.
D
Hosts/self-powered hubs must:
–
–
–
D
Bus-powered hubs must:
–
–
–
–
–
D
Current-limit downstream ports
Report overcurrent conditions on USB VBUS
Output 5.25 V to 4.75 at 500 mA
Enable/disable power to downstream ports
Power up at <100 mA
Limit inrush current (<44 Ω and 10 µF)
Output 5.25 V to 4.4 at 100 mA
Not send power back upstream
Functions must:
–
–
–
Limit inrush currents
Power up at <100 mA
Not send power back upstream (SP functions)
The feature set of the TPS2070 and TPS2071 allows them to meet each of these requirements. The integrated
current-limiting and overcurrent reporting is required by hosts and self-powered hubs. The logic-level enable
and controlled rise times meet the needs of both input and output ports on hubs, as well as the input ports for
bus-powered functions
24
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS2070, TPS2071
FOUR-PORT USB HUB POWER CONTROLLERS
SLVS287A – SEPTEMBER 2000 – REVISED FEBRUARY 2001
APPLICATION INFORMATION
USB hybrid hub
A USB hybrid hub can be simply implemented using the TPS2071 USB power controller and a TUSB2046 USB
hub controller as shown in Figure 38. The TPS2071 USB power controller provides all the power needs to the
four downstream ports and meets all the USB power specifications for both self-powered hubs and bus-powered
hubs. The power controllers integrated 3.3-V LDO is used to provide power for the hub controller and any other
local functions (e.g. transient suppressor SN75240 ), which saves board space and cost. The TPS2071 also
provides the hub controller with a power good (PG) signal that connects to the RESET input of the hub controller
to automatically reinitialize the hub when switching between self-powered mode and bus-powered mode
whenever the self-power supply is connected or disconnected. The amount of time in which the hub controller
is kept in a reset state is controlled by a capacitor connected between the PG_DLY pin of the power controller
and ground.
By using an external N-channel MOSFET and the TPS2071 internal voltage-regulator controller, a regulated
5-V self-powered source can be generated from an input voltage range of 6 V to 9 V (see Figure 38). In this
configuration, the internal voltage regulator controller is enabled by connecting the EN_REG input to the BP
input. Using the internal voltage regulator controller also requires connecting a 0.01 µF capacitor between CP_P
and CP_M of the TPS2071 power controller. Also, a 0.1-µF capacitor is needed between VCP of the power
controller and ground.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
25
TPS2070, TPS2071
FOUR-PORT USB HUB POWER CONTROLLERS
SLVS287A – SEPTEMBER 2000 – REVISED FEBRUARY 2001
APPLICATION INFORMATION
Downstream
Ports
TUSB2046B
Upstream
Ports
D+
DP1
DM1
D+
DP0
D–
DM0
A
C
B
D
GND
5V
SN75240
A
C
EECLK
EEDATA
B
D
EXTMEM
DP2
D+
D–
GND
SN75240
RESET
VCC1_3.3
0.1 µF
5V
DM2
DP3
DM3
BUSPWR
10 µF
GND
33 µF
SUSPEND
0.1 µF
D–
SN75240
A
C
B
D
5V
33 µF
VCC2_3.3
DP4
DM4
D+
TPS2071
XTAL1
33 pF
6 MHz
1.5 kΩ
33 pF
XTAL2
D–
PWRON1
OVRCUR1
EN1
OC1
OUT1
PWRON2
EN2
OC2
OUT3
OVRCUR2
GND
OUT2
5V
33 µF
EN3
OC3
PWRON3
TSTPLL
TSTMODE OVRCUR3
PWRON4
GND
OVRCUR4
GND
D+
D–
EN4
OC4
GND
5V
OUT4
VCP
3.3 V
SP
4.7 µF
0.1 µF
0.1 µF
SP
GATE
68 µF
BP_DIS
CP_P
0.01 µF
†
†
6 V to 9 V
Supply
CP_M
IRLZ24N
VEXT
68 µF
PG_DLY
0.1 µF
0.1 µF
PG
BPMODE
1.5 kΩ
33 µF
0.1 µF
AGND
DGND
DP0_RST
BP
EN_REG
† This hybrid hub can also be implemented by connecting a 5-V power supply to the SP input of the TPS2071 and eliminating the external FET.
However, this type of implementation is best suited for the TPS2074/75 (refer to the TPS2074, TPS2075 data sheet for details).
Figure 38. USB Hybrid Hub Using TPS2071 Power Controller and TUSB2046 Hub Controller
26
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS2070, TPS2071
FOUR-PORT USB HUB POWER CONTROLLERS
SLVS287A – SEPTEMBER 2000 – REVISED FEBRUARY 2001
MECHANICAL DATA
DAP (R-PDSO-G**)
PowerPAD PLASTIC SMALL-OUTLINE PACKAGE
38 PINS SHOWN
0,30
0,19
0,65
38
0,13 M
20
Thermal Pad
(see Note D)
6,20
NOM
8,40
7,80
0,15 NOM
Gage Plane
1
19
0,25
A
0°– 8°
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
28
30
32
38
A MAX
9,80
11,10
11,10
12,60
A MIN
9,60
10,90
10,90
12,40
DIM
4073257/A 07/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane.
This pad is electrically and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO-153
PowerPAD is a trademark of Texas Instruments.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
27
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPS2070DAP
ACTIVE
HTSSOP
DAP
32
46
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
TPS2071DAP
ACTIVE
HTSSOP
DAP
32
46
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
TPS2071DAPG4
ACTIVE
HTSSOP
DAP
32
46
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
TPS2071DAPR
ACTIVE
HTSSOP
DAP
32
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
TPS2071DAPRG4
ACTIVE
HTSSOP
DAP
32
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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Addendum-Page 1
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