TUSB2046BI-Q1 www.ti.com SLLSE50 – SEPTEMBER 2010 4-PORT HUB FOR THE UNIVERSAL SERIAL BUS WITH OPTIONAL SERIAL EEPROM INTERFACE Check for Samples: TUSB2046BI-Q1 FEATURES 1 • • • • • • • • • • • • • • • • • • • • (1) Fully Compliant With the USB Specification as a Full-Speed Hub: TID #30220231 32-Terminal LQFP (1) Package With a 0.8-mm Terminal Pitch or QFN Package with a 0.5-mm Terminal Pitch 3.3-V Low Power ASIC Logic Integrated USB Transceivers State Machine Implementation Requires No Firmware Programming One Upstream Port and Four Downstream Ports All Downstream Ports Support Full-Speed and Low-Speed Operations Two Power Source Modes – Self-Powered Mode – Bus-Powered Mode Power Switching and Overcurrent Reporting Is Provided Ganged or Per Port Supports Suspend and Resume Operations Supports Programmable Vendor ID and Product ID With External Serial EEPROM 3-State EEPROM Interface Allows EEPROM Sharing Push-Pull Outputs for PWRON Eliminate the Need for External Pullup Resistors Noise Filtering on OVRCUR Provides Immunity to Voltage Spikes Package Pinout Allows 2-Layer PCB Low EMI Emission Achieved by a 6-MHz Crystal Input Migrated From Proven TUSB2040 Hub Lower Cost Than the TUSB2040 Hub Enhanced System ESD Performance Supports 6-MHz Operation Through a Crystal Input or a 48-MHz Input Clock VF PACKAGE (TOP VIEW) RHB PACKAGE (TOP VIEW) JEDEC descriptor S-PQFP-G for low profile quad flat pack (LQFP). 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated TUSB2046BI-Q1 SLLSE50 – SEPTEMBER 2010 www.ti.com DESCRIPTION/ORDERING INFORMATION The TUSB2046B is a 3.3-V CMOS hub device that provides one upstream port and four downstream ports in compliance with the Universal Serial Bus (USB) specification as a full-speed hub. Because this device is implemented with a digital state machine instead of a microcontroller, no firmware programming is required. Fully-compliant USB transceivers are integrated into the ASIC for all upstream and downstream ports. The downstream ports support both full-speed and low-speed devices by automatically setting the slew rate according to the speed of the device attached to the ports. The configuration of the BUSPWR terminal selects either the bus-powered or the self-powered mode. Configuring the GANGED input determines the power switching and overcurrent detection modes for the downstream ports. External power-management devices, such as the TPS2044, are required to control the 5-V source to the downstream ports according to the corresponding values of the PWRON terminal. Upon detecting any overcurrent conditions, the power-management device sets the corresponding OVRCUR terminal of the TUSB2046B to a logic low. If GANGED is high, all PWRON outputs switch together and if any OVRCUR is activated, all ports transition to the power-off state. If GANGED is low, the PWRON outputs and OVRCUR inputs operate on a per-port basis. The TUSB2046B provides the flexibility of using a 6-MHz or a 48-MHz clock. The logic level of the TSTMODE terminal controls the selection of the clock source. When TSTMODE is low, the output of the internal APLL circuitry is selected to drive the internal core of the device. When TSTMODE is high, the TSTPLL/48MCLK input is selected as the input clock source and the APLL circuitry is powered down and bypassed. The internal oscillator cell is also powered down while TSTMODE is high. Low EMI emission is achieved because the TUSB2046B is able to utilize a 6-MHz crystal input. Connect the crystal as shown in Figure 6. An internal PLL then generates the 48-MHz clock used to sample data from the upstream port and to synchronize the 12 MHz used for the USB clock. If low-power suspend and resume are desired, a passive crystal or resonator must be used. However, a 6-MHz oscillator may be used by connecting the output to the XTAL1 terminal and leaving the XTAL2 terminal open. The oscillator TTL output must not exceed 3.6 V. For 48-MHz operation, the clock cannot be generated with a crystal using the XTAL2 output because the internal oscillator cell supports only the fundamental frequency. See Figure 7 and Figure 8 in the input clock configuration section for more detailed information regarding the input clock configuration. The EXTMEM terminal enables or disables the optional EEPROM interface. When the EXTMEM terminal is high, the product ID (PID) displayed during enumeration is the general-purpose USB hub. For this default, terminal 5 is disabled and terminal 6 functions as the GANGED input terminal. If custom PID and vendor ID (VID) descriptors are desired, the EXTMEM terminal must be low (EXTMEM = 0). For this configuration, terminals 5 and 6 function as the EEPROM interface with terminals 5 and 6 functioning as EECLK and EEDATA, respectively. See Table 1 for a description of the EEPROM memory map. Other useful features of the TUSB2046B include a package with a 0.8-mm terminal pitch for easy PCB routing and assembly, push-pull outputs for the PWRON terminals eliminate the need for pullup resistors required by traditional open-collector I/Os, and OVRCUR terminals have noise filtering for increased immunity to voltage spikes. ORDERING INFORMATION PACKAGE (1) TA –40°C to 85°C (1) 2 QFN – RHB Reel of 3000 ORDERABLE PART NUMBER TUSB2046BIRHBRQ1 TOP-SIDE MARKING TUSB 2046BQ1 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TUSB2046BI-Q1 TUSB2046BI-Q1 www.ti.com SLLSE50 – SEPTEMBER 2010 FUNCTIONAL BLOCK DIAGRAM DP0 DM0 1 2 USB Transceiver 32 27 SUSPND TSTPLL/48MCLK 30 XTAL1 29 Suspend/Resume Logic and Frame Timer HUB Repeater OSC/PLL XTAL2 SIE 4 26 6 SIE Interface Logic Serial EEPROM Interface 5 RESET EXTMEM EEDATA/GANGED EECLK Port 1 Logic Port 2 Logic Hub/Device Command Decoder Port 3 Logic 8 BUSPWR Port 4 Logic USB Transceiver 24 DP4 23 DM4 USB Transceiver 20 DP3 19 DM3 USB Transceiver 16 DP2 15 DM2 USB Transceiver 12 DP1 Hub Power Logic 10, 14, 18, 22 OVRCUR1 – OVRCUR4 11 DM1 9, 13, 17, 21 PWRON1 – PWRON4 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TUSB2046BI-Q1 3 TUSB2046BI-Q1 SLLSE50 – SEPTEMBER 2010 www.ti.com TERMINAL FUNCTIONS TERMINAL NAME BUSPWR DM0 DM1–DM4 DP0 DP1–DP4 EECLK NO. I/O DESCRIPTION 8 I Power source indicator. BUSPWR is an active-high input that indicates whether the downstream ports source their power from the USB cable or a local power supply. For the bus-power mode, this terminal must be pulled to 3.3 V, and for the self-powered mode, this terminal must be pulled low. Input must not change dynamically during operation. 2 I/O Root port USB differential data minus. DM0 paired with DP0 constitutes the upstream USB port. 11, 15, 19, 23 I/O USB differential data minus. DM1–DM4 paired with DP1–DP4 support up to four downstream USB ports. 1 I/O Root port USB differential data plus. DP0 paired with DM0 constitutes the upstream USB port. 12, 16, 20, 24 I/O USB differential data plus. DP1–DP4 paired with DM1–DM4 support up to four downstream USB ports. 5 O EEPROM serial clock. When EXTMEM is high, the EEPROM interface is disabled. The EECLK terminal is disabled and must be left floating (unconnected). When EXTMEM is low, EECLK acts as a 3-state serial clock output to the EEPROM with a 100-mA internal pulldown. EEDATA/ GANGED 6 I/O EEPROM serial data/power-management mode indicator. When EXTMEM is high, EEDATA/GANGED selects between ganged or per-port power overcurrent detection for the downstream ports. When EXTMEM is low, EEDATA/GANGED acts as a serial data I/O for the EEPROM and is internally pulled down with a 100-mA pulldown. This standard TTL input must not change dynamically during operation. EXTMEM 26 I When EXTMEM is high, the serial EEPROM interface of the device is disabled. When EXTMEM is low, terminals 5 and 6 are configured as the clock and data terminals of the serial EEPROM interface, respectively. GND 7, 28 GND terminals must be tied to ground for proper operation. OVRCUR1 – OVRCUR4 10, 14, 18, 22 I Overcurrent input. OVRCUR1–OVRCUR4 are active low. For per-port overcurrent detection, one overcurrent input is available for each of the four downstream ports. In the ganged mode, any OVRCUR input may be used and all OVRCUR terminals must be tied together. OVRCUR terminals are active low inputs with noise filtering logic. PWRON1 – PWRON4 9, 13, 17, 21 O Power-on/-off control signals. PWRON1–PWRON4 are active low, push-pull outputs. Push-pull outputs eliminate the pullup resistors which open-drain outputs require. However, the external power switches that connect to these terminals must be able to operate with 3.3-V inputs because these outputs cannot drive 5-V signals. RESET 4 I RESET is an active low TTL input with hysteresis and must be asserted at power up. When RESET is asserted, all logic is initialized. Generally, a reset with a pulse width between 100 ms and 1 ms is recommended after 3.3-V VCC reaches its 90%. Clock signal has to be active during the last 60 ms of the reset window. SUSPND 32 O Suspend status. SUSPND is an active high output available for external logic power-down operations. During the suspend mode, SUSPND is high. SUSPND is low for normal operation. TSTMODE 31 I Test/mode terminal. TSTMODE is used as a test terminal during production testing. This terminal must be tied to ground or 3.3-V VCC for normal 6-MHz or 48-MHz operation, respectively. TSTPLL/ 48MCLK 27 I/O Test/48-MHz clock input. TSTPLL/48MCLK is used as a test terminal during production testing. This terminal must be tied to ground for normal 6-MHz operation. If 48-MHz input clock is desired, a 48-MHz clock source (no crystal) can be connected to this input terminal. VCC 3, 25 3.3-V supply voltage XTAL1 30 I Crystal 1. XTAL1 is a 6-MHz crystal input with 50% duty cycle. An internal PLL generates the 48-MHz and 12-MHz clocks used internally by the ASIC logic. XTAL2 29 O Crystal 2. XTAL2 is a 6-MHz crystal output. This terminal must be left open when using an oscillator. 4 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TUSB2046BI-Q1 TUSB2046BI-Q1 www.ti.com SLLSE50 – SEPTEMBER 2010 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range (2) –0.5 3.6 V VI Input voltage range –0.5 VCC + 0.5 V VO Output voltage range –0.5 VCC + 0.5 IIK Input clamp current VI < 0 V or VI < VCC ±20 mA IOK Output clamp current VO < 0 V or VO < VCC ±20 mA Tstg Storage temperature range –65 150 °C TA Operating free-air temperature range –40 85 °C (1) (2) TUSB2046BI UNIT V Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage levels are with respect to GND. RECOMMENDED OPERATING CONDITIONS PARAMETER VCC Supply voltage VI VO MIN TUSB2046BI NOM MAX UNIT 3.3 3.6 V Input voltage, TTL/LVCMOS 0 VCC V Output voltage, TTL/LVCMOS 0 VCC V VIH(REC) High-level input voltage, signal-ended receiver 2 VCC V VIL(REC) Low-level input voltage, signal-ended receiver 0.8 V VIH(TTL) High-level input voltage, TTL/LVCMOS 2 VCC V VIL(TTL) Low-level input voltage, TTL/LVCMOS 0 0.8 V TA Operating free-air temperature –40 85 °C R(DRV) External series, differential driver resistor 22 (–5%) 22 (5%) f(OPRH) Operating (dc differential driver) high speed mode 12 Mb/s f(OPRL) Operating (dc differential driver) low speed mode 1.5 Mb/s VICR Common mode, input range, differential receiver tt Input transition times, TTL/LVCMOS TJ Junction temperature range TUSB2046BI Ω 0.8 2.5 V 0 25 ns –40 115 °C Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TUSB2046BI-Q1 5 TUSB2046BI-Q1 SLLSE50 – SEPTEMBER 2010 www.ti.com ELECTRICAL CHARACTERISTICS over recommended ranges of operating free-air temperature and supply voltage (unless otherwise noted) PARAMETER TEST CONDITIONS TTL/LVCMOS VOH High-level output voltage USB data lines TTL/LVCMOS VOL Low-level output voltage VIT+ Positive input threshold VIT– Negative-input threshold Vhys Input hysteresis (1) (VT+ – VT–) IOZ High-impedance output current IIL USB data lines IOH = –4 mA MIN R(DRV) = 15 kΩ to GND IOH = –12 mA (without R(DRV)) MAX 2.8 V VCC – 0.5 IOL = 4 mA 0.5 R(DRV) = 1.5 kΩ to 3.6 V 0.3 IOL = 12 mA (without R(DRV)) 0.5 TTL/LVCMOS Single-ended V 1.8 0.8 0.8 V ≤ VICR ≤ 2.5 V V 1 TTL/LVCMOS 0.3 0.7 300 500 Single-ended 0.8 V ≤ VICR ≤ 2.5 V TTL/LVCMOS V = VCC or GND (2) ±10 USB data lines 0 V ≤ VO ≤ VCC ±10 Low-level input current TTL/LVCMOS VI = GND IIH High-level input current TTL/LVCMOS VI = VCC z0(DRV) Driver output impedance (3) USB data lines Static VOH or VOL 7.1 VID Differential input voltage USB data lines 0.8 V ≤ VICR ≤ 2.5 V 0.2 ICC Input supply current (1) (2) (3) V 1.8 0.8 V ≤ VICR ≤ 2.5 V TTL/LVCMOS Single-ended UNIT VCC – 0.5 mV mA –1 mA 1 mA 19.9 Ω V Normal operation Suspend mode 40 mA 1 mA Applies for input buffers with hysteresis. Applies for open drain buffers. Characterization only. Limits are approved by design and are not production tested. DIFFERENTIAL DRIVER SWITCHING CHARACTERISTICS Full Speed Mode over recommended ranges of operating free-air temperature and supply voltage, CL = 50 pF (unless otherwise noted) MIN MAX tr Transition rise time for DP or DM PARAMETER See Figure 1 and Figure 2 TEST CONDITIONS 4 20 ns tf Transition fall time for DP or DM See Figure 1 and Figure 2 4 20 ns 90 110 % 1.3 2.0 V (1) t(RFM) Rise/fall time matching VO(CRS) Signal crossover output voltage (1) (1) (tr/tf) × 100 UNIT Characterized only. Limits are approved by design and are not production tested. DIFFERENTIAL DRIVER SWITCHING CHARACTERISTICS Low Speed Mode over recommended ranges of operating free-air temperature and supply voltage, CL = 50 pF (unless otherwise noted) MIN MAX UNIT tr Transition rise time for DP or DM (1) PARAMETER CL = 200 pF to 600 pF, TEST CONDITIONS See Figure 1 and Figure 2 75 300 ns tf Transition fall time for DP or DM (1) CL = 200 pF to 600 pF, See Figure 1 and Figure 2 75 300 ns (tr/tf) × 100 80 120 % CL = 200 pF to 600 pF 1.3 2.0 V (1) t(RFM) Rise/fall time matching VO(CRS) Signal crossover output voltage (1) (1) 6 Characterized only. Limits are approved by design and are not production tested. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TUSB2046BI-Q1 TUSB2046BI-Q1 www.ti.com SLLSE50 – SEPTEMBER 2010 22 Ω 1.5 kΩ 15 kΩ 22 Ω 15 kΩ Figure 1. Differential Driver Switching Load V ID - Diff erential Receiver Input Sensitivity - V Figure 2. Differential Driver Timing Waveforms 1.5 1.3 1 0.5 0.2 0 0 3 1 2 3.6 0.8 2.5 VICR - Common Mode Input Rang e - V 4 Figure 3. Differential Receiver Input Sensitivity vs Common Mode Input Range Vhys Logic high VCC VIH VIT+ VIT- VIL Logic low 0V Figure 4. Single-Ended Receiver Input Signal Parameter Definitions Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TUSB2046BI-Q1 7 TUSB2046BI-Q1 SLLSE50 – SEPTEMBER 2010 www.ti.com APPLICATION INFORMATION A major advantage of USB is the ability to connect 127 functions configured in up to 6 logical layers (tiers) to a single personal computer (see Figure 5). PC With Root Hub Monitor With 4-Port Hub (Self-Powered) Printer With 4-Port Hub (Self-Powered) Scanner Digital Scanner Figure 5. USB-Tiered Configuration Example Another advantage of USB is that all peripherals are connected using a standardized four-wire cable that provides both communication and power distribution. The power configurations are bus-powered and self-powered modes. The maximum current that may be drawn from the USB 5-V line during power up is 100 mA. For the bus-powered mode, a hub can draw a maximum of 500 mA from the 5-V line of the USB cable. A bus-powered hub must always be connected downstream to a self-powered hub unless it is the only hub connected to the PC and there are no high-powered functions connected downstream. In the self-powered mode, the hub is connected to an external power supply and can supply up to 500 mA to each downstream port. High-powered functions may draw a maximum of 500 mA from each downstream port and may only be connected downstream to self-powered hubs. Per the USB specification, in the bus-powered mode, each downstream port can provide a maximum of 100 mA of current, and in the self-powered mode, each downstream port can provide a maximum of 500 mA of current. Both bus-powered and self-powered hubs require overcurrent protection for all downstream ports. The two types of protection are individual-port management (individual-port basis) or ganged-port management (multiple-port basis). Individual-port management requires power-management devices for each individual downstream port, but adds robustness to the USB system because, in the event of an overcurrent condition, the USB host only powers down the port that has the condition. The ganged configuration uses fewer power management devices and thus has lower system costs, but in the event of an overcurrent condition on any of the downstream ports, all the ganged ports are disabled by the USB host. Using a combination of the BUSPWR and EEDATA/GANGED inputs, the TUSB2046B supports four modes of power management: bus-powered hub with either individual-port power management or ganged-port power management, and the self-powered hub with either individual-port power management or ganged-port power management. Texas Instruments supplies the complete hub solution with the TUSB2036 (2/3-port), TUSB2046B, and the TUSB2077 (7-port) hubs along with the power-management devices needed to implement a fully USB specification-compliant system. 8 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TUSB2046BI-Q1 TUSB2046BI-Q1 www.ti.com SLLSE50 – SEPTEMBER 2010 USB Design Notes The following sections provide block diagram examples of how to implement the TUSB2046B device. Note, even though no resistors are shown, pullup, pulldown, and series resistors must be used to properly implement this device. Figure 6 is an example of how to generate the 6-MHz clock signal. CL XTAL1 XTAL2 C1 C2 NOTE: This figure assumes a 6-MHz fundamental crystal that is parallel loaded. The component values of C1, C2, and Rd are determined using a crystal from Fox Electronics – part number HC49U-6.00MHz 30\50\0-70\20, which means ±30 ppm at 25°C and ±50 ppm from 0°C to 70°C. The characteristics for the crystal include a load capacitance (CL) of 20 pF, maximum shunt capacitance (Co) of 7 pF, and the maximum ESR of 50 Ω. In order to insure enough negative resistance, use C1 = C2 = 27 pF. The resistor Rd is used to trim the gain, and Rd = 1.5 kΩ is recommended. Figure 6. Crystal Tuning Circuit Input Clock Configuration The input clock configuration logic of TUSB2046B is enhanced to accept a 6-MHz crystal or 48-MHz on-the-board clock source with a simple tie-off change on TSTMODE (terminal 31). • A 6-MHz input clock configuration is shown in Figure 7. In this mode, both TSTMODE and TSTPLL/48MCLK terminals must be tied to ground. The hub is configured to use the 6-MHz clock on terminals 30 and 29, which are XTAL1 and XTAL2, respectively, on the TUSB2046B. This is identical to the TUSB2046. Figure 7. 6-MHz Input Clock Configuration • A 48-MHz input clock configuration is shown in Figure 8. In this mode, both TSTMODE and XTAL1 terminals must be tied to 3.3-V VCC. The hub accepts the 48-MHz clock input on TSTPLL/48MCLK (terminal 27). XTAL2 must be left floating (open) for this configuration. Only the oscillator or the onboard clock source is accepted for this mode. A crystal can not be used for this mode, since the chip’s internal oscillator cell only supports the fundamental frequency. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TUSB2046BI-Q1 9 TUSB2046BI-Q1 SLLSE50 – SEPTEMBER 2010 www.ti.com TUSB2046B USB HUB 3.3 V 30 XTAL1 29 Open XTAL2 31 TSTMODE 48-MHz Oscillator or on Board Clock Source 27 TSTPLL/48MCLK Figure 8. 48-MHz Input Clock Configuration Figure 9 is a block diagram example of how to connect the external EEPROM if a custom product ID and vendor ID are desired. Figure 10 shows the EEPROM read operation timing diagram. Figure 11, Figure 12, and Figure 13 illustrate how to connect the TUSB2046B device for different power source and port power-management combinations. Ω Figure 9. Typical Application of the TUSB2046B USB Hub 10 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TUSB2046BI-Q1 TUSB2046BI-Q1 www.ti.com SLLSE50 – SEPTEMBER 2010 Programming the EEPROM An SGS Thompson M93C46 EEPROM, or equivalent, stores the programmable VID and PID. When the EEPROM interface is enabled (EXTMEM = 0), the EECLK and EEDATA are internally pulled down (100 mA) inside the TUSB2046B. The internal pulldowns are disabled when the EEPROM interface is disabled (EXTMEM = 1). The EEPROM is programmed with the three 16-bit locations as shown in Table 1. Connecting terminal 6 of the EEPROM high (ORG = 1) organizes the EEPROM memory into 64×16-bit words. Table 1. EEPROM Memory Map ADDRESS D15 D14 D13 D12–D8 D7–D0 00000 0 GANGED 00000 00000 00000000 00001 VID High-byte VID Low-byte 00010 PID High-byte PID Low-byte XXXXXXXX The D and Q signals of the EEPROM must be tied together using a 1-kΩ resistor with the common I/O operations forming a single-wire bus. After system power-on reset, the TUSB2046B performs a one-time access read operation from the EEPROM if the EXTMEM terminal is pulled low and the chip select(s) of the EEPROM is connected to the system power-on reset. Initially, the EEDATA terminal is driven by the TUSB2046B to send a start bit (1) which is followed by the read instruction (10) and the starting-word address (00000). Once the read instruction is received, the instruction and address are decoded by the EEPROM, which then sends the data to the output shift register. At this point, the hub stops driving the EEDATA terminal and the EEPROM starts driving. A dummy (0) bit is then output and the first three 16-bit words in the EEPROM are output with the most significant bit (MSB) first. The output data changes are triggered by the rising edge of the clock provided by the TUSB2046B on the EECLK terminal. The SGS-Thompson M936C46 EEPROM is recommended because it advances to the next memory location by automatically incrementing the address internally. Any EEPROM used must have the automatic internal address advance function. After reading the three words of data from the EEPROM, the TUSB2046B puts the EEPROM interface into a high-impedance condition (pulled down internally) to allow other logic to share the EEPROM. The EEPROM read operation is summarized in Figure 10. For more details on EEPROM operation, refer to SGS-Thompson Microelectronics M93C46 Serial Microwire Bus EEPROM data sheet. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TUSB2046BI-Q1 11 12 D C S Start Submit Documentation Feedback Product Folder Link(s) :TUSB2046BI-Q1 A5 Hub Driving Data Line Read OP Code(10) Other Address Bits A1 6 Bit Address (000000) A0 Dummy Bit MSB of The First Word D15 Other LSB of Data Bits Third Word D0 EEPROM Driving Data Line D14 48 Data Bits MSB of Fourth Word XX Don’t Care 3-Stated With Internal Pulldown TUSB2046BI-Q1 SLLSE50 – SEPTEMBER 2010 www.ti.com Figure 10. EEPROM Read Operation Timing Diagram Copyright © 2010, Texas Instruments Incorporated TUSB2046BI-Q1 www.ti.com SLLSE50 – SEPTEMBER 2010 Bus-Powered Hub, Ganged-Port Power Management When used in bus-powered mode, the TUSB2046B supports up to four downstream ports by controlling a TPS2041 device which is capable of supplying 100 mA of current to each downstream port. Bus-powered hubs must implement power switching to ensure current demand is held below 100 mA when the hub is hot-plugged into the system. Utilizing the TPS2041 for ganged-port power management provides overcurrent protection for the downstream ports. The SN75240 transient suppressors reduce inrush current and voltage spikes on the data lines. The OVRCUR signals must be tied together for a ganged operation. 3.3 V 1.5 kΩ Downstream Ports D D+ SN75240 A SN75240 3.3 V LDO A Ferrite Beads A C B D 15 kΩ 15 kΩ GND A 5V 100 µF 15 kΩ D- B 15 kΩ D+ DFerrite Beads GND A C B D 15 kΩ 15 kΩ SN75240 5V A 100 µF B 15 kΩ 15 kΩ TPS2041 EN D+ D- A Ferrite Beads GND IN IN 5V 1 µF 100 µF B OUT OUT OUT OC D+ DFerrite Beads GND 5V 100 µF B NOTES: A. TPS2041 and SN75240 are Texas Instruments devices. The OCn outputs of the TPS204n are open drain. A 10-kΩ pullup is recommended. B. 120 µF per hub is the minimum required per the USB specification, version 1.1. However, TI recommends a 100-µF, low ESR, tantalum capacitor per port for immunity to voltage droop. C. LDO is a 5-V-to-3.3-V voltage regulator D. All USB DP, DM signal pairs require series resistors of approximately 27Ω to ensure proper termination. An optional filter capacitor of about 22 pF is recommended for EMI suppression. This capacitor, if used, must be placed between the hub terminal and the series resistor, as per section 7.1.6 of the USB specification. Figure 11. TUSB2046B Bus-Powered Hub, Ganged-Port Power-Management Application Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TUSB2046BI-Q1 13 TUSB2046BI-Q1 SLLSE50 – SEPTEMBER 2010 www.ti.com Self-Powered Hub, Ganged-Port Power Management The TUSB2046B can also be implemented for ganged-port power management in a self-powered configuration. The implementation is very similar to the bus-powered example with the exception that a self-powered port supplies 500 mA of current to each downstream port. The overcurrent protection can be provided by a TPS2044 quad device or a TPS2024 single power switch. 1.5 kΩ D SN75240 A Ω Ω 3.3 V LDO C SN75240 Ω Ω A 100 µF B Ω Ω SN75240 Ω Ω TPS2044 A 100 µF B A 100 µF 100 µF B B NOTES: A. TPS2044, TPS2042, and SN75240 are Texas Instruments devices. The TPS2042 can be substituted for the TPS2044. The OCn outputs of the TPS204n are open drain. A 10-kΩ pullup is recommended. B. 120 µF per hub is the minimum required per the USB specification, version 1.1. However, TI recommends a 100-µF, low ESR, tantalum capacitor per port for immunity to voltage droop. C. LDO is a 5-V-to-3.3-V voltage regulator D. All USB DP, DM signal pairs require series resistors of approximately 27Ω to ensure proper termination. An optional filter capacitor of about 22 pF is recommended for EMI suppression. This capacitor, if used, must be placed between the hub terminal and the series resistor, as per section 7.1.6 of the USB specification. Figure 12. TUSB2046B Self-Powered Hub, Ganged-Port Power-Management Application 14 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TUSB2046BI-Q1 TUSB2046BI-Q1 www.ti.com SLLSE50 – SEPTEMBER 2010 Self-Powered Hub, Individual-Port Power Management In a self-powered configuration, the TUSB2046B can be implemented for individual-port power management when used with the TPS2044, because it is capable of supplying 500 mA of current to each downstream port and can provide current limiting on a per-port basis. When the hub detects a fault on a downstream port, power is removed from only the port with the fault and the remaining ports continue to operate normally. Self-powered hubs are required to implement overcurrent protection and report overcurrent conditions. The SN75240 transient suppressors reduce inrush current and voltage spikes on the data lines. D 1.5 kΩ SN75240 Ω Ω A SN75240 3.3 V LDO A C 100 µF Ω Ω B Ω Ω SN75240 A B 100 µF TPS2044 A 100 µF 100 µF B B NOTES: A. TPS2044, TPS2042, and SN75240 are Texas Instruments devices. Two TPS2042 devices can be substituted for the TPS2044. The OCn outputs of the TPS204n are open drain. A 10-kΩ pullup is recommended. B. 120 µF per hub is the minimum required per the USB specification, version 1.1. However, TI recommends a 100-µF, low ESR, tantalum capacitor per port for immunity to voltage droop. C. LDO is a 5-V-to-3.3-V voltage regulator D. All USB DP, DM signal pairs require series resistors of approximately 27Ω to ensure proper termination. An optional filter capacitor of about 22 pF is recommended for EMI suppression. This capacitor, if used, must be placed between the hub terminal and the series resistor, as per section 7.1.6 of the USB specification. Figure 13. TUSB2046B Self-Powered Hub, Individual-Port Power-Management Application Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TUSB2046BI-Q1 15 PACKAGE OPTION ADDENDUM www.ti.com 8-Oct-2010 PACKAGING INFORMATION Orderable Device TUSB2046BIRHBRQ1 Status (1) Package Type Package Drawing ACTIVE QFN RHB Pins Package Qty 32 3000 Eco Plan (2) Green (RoHS & no Sb/Br) Lead/ Ball Finish MSL Peak Temp (3) CU NIPDAU Level-3-260C-168 HR Samples (Requires Login) Purchase Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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