ETC PI6C2402

PI6C2402
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Phase-Locked Loop Clock Driver
Product Features
Product Description
• 2X CLK_IN on CLK_OUT
The PI6C2402 features a low-skew, low-jitter, phase-locked loop
(PLL) clock driver. By connecting the feedback CLK_OUT output
to the feedback FB_IN input, the propagation delay from the
CLK_IN input to any clock output will be nearly zero. The PI6C2402
provides 2X CLK_IN on CLK_OUT output.
• High-Performance Phase-Locked-Loop Clock Distribution
for Networking, ATM, 100/134 MHz Registered DIMM
Synchronous DRAM modules for server/workstation/
PC applications
• Zero Input-to-Output delay
Application
• Low jitter: Cycle-to-Cycle jitter ±100ps max.
If the system designer needs more than 16 outputs with the features
just described, using two or more zero-delay buffers such as
PI6C2509Q, and PI6C2510Q, is likely to be impractical. The deviceto-device skew introduced can significantly reduce the performance. Pericom recommends the use of a zero-delay buffer and an
eighteen output non-zero-delay buffer. As shown in
Figure 1, this combination produces a zero-delay buffer with all the
signal characteristics of the original zero-delay buffer, but with as
many outputs as the non-zero-delay buffer part. For example, when
combined with an eighteen output non-zero delay buffer, a system
designer can create a seventeen-output zero-delay buffer.
• On-chip series damping resistor at clock output drivers
for low noise and EMI reduction
• Operates at 3.3V VCC
• Wide range of Clock Frequencies
• Package:
Plastic 8-pin SOIC Package (W)
Logic Block Diagram
CLK_IN
2
FB_IN
Product Pin Configuration
CLK_OUT
PLL
S
CLK_IN
1
AVCC
2
AGND
3
CLK_OUT
4
8-Pin
W
8
FB_IN
7
VCC
6
GND
5
S
Feedback
Control Input
Reference
Clock
Signal
CLK_OUT
S
Output Source
PLL Shutdown
1
PLL
N
0
CLK_IN
Y
V
Zero Delay
Buffer
PI6C2402
18 Output
Non-Zero
Delay
Buffer
17
Figure 1. This Combination Provides Zero-Delay Between the
Reference Clocks Signal and 17 Outputs
1
PS8418C
08/02/02
PI6C2402
Phase-Locked
Loop
Clock
Driver
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Pin Functions
Pin Name
Pin Numbe r
Type
De s cription
CLK_IN
1
I
AVCC
2
Power
Analog power.
AGND
3
Ground
Analog ground.
CLK_OUT
4
O
Clock output. The output provides low- skew copies of CLK_IN and
has an embedded series- damping resistor.
S
5
I
Control Input S. S is used to bypass the PLL for test purposes. When S is strapped to
ground, PLL is bypassed and CLK_IN is buffered directly to the device outputs.
GND
6
Ground
Ground.
VCC
7
Power
Power supply.
FB_IN
8
I
Reference Clock input. CLK_IN allows spread spectrum clock input
Feedback input. FB_IN provides the feedback signal to the internal PLL.
Absolute Maximum Ratings (Over operating free-air temperature range, see Note 1)
Symbol
Parame te r
M in.
M a x.
Units
VI
Input voltage range
–0.5
VCC + 0.5
VO
Output voltage range
–0.5
VCC + 0.5
VI_DC
DC input voltage
–0.5
+5.0
IO_DC
DC output current
o
Power
Maximum power dissipation at TA= 55 C in still air
TSTG
Storage temperature
–65
V
100
mA
1.0
W
150
o
C
Note:
1. Stress beyond those listed under “absolute maximum ratings” may cause permanent damage to the device.
Recommended Operating Conditions
Symbol
VCC
Parame te r
Supply voltage
Commercial
Supply voltage
Industrial
VIH
High level input voltage
VIL
Low level input voltage
VI
Input voltage
TA
Te mpe rature
M in.
M a x.
3.0
3.6
3.135
3.465
Units
2.0
V
0.8
Operating free- air temperature
Commercial
Operating free- air temperature
Industrial
2
0
VCC
0
70
–40
85
ºC
PS8418C
08/02/02
PI6C2402
Phase-Locked
Loop
Clock
Driver
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Electrical Characteristics
(Over recommended operating free-air temperature range)
Symbol
IC C
Te s t Condition
VI = VC C or GND; IO = 0(2)
VI = VC C or GND; IO =
CI
VI = VC C or GND
CO
VO = VC C or GND
IO H
IO L
Te mpe rature
0 (2 )
VCC
Commercial
Industrial
M in.
Typ.
M ax.
3.6V
10
3.465V
10
µA
4
3.3V
pF
6
VO UT = 2.4V
–12
VO UT = 2.0V
–18
VO UT = 0.8V
18
VO UT = 0.55V
12
Units
mA
Note:
2. Continuous Output Current
AC Specifications Timing Requirements
(Over recommended ranges of supply voltage and operating free-air temperature, CL = 25pF)
Symbol
FCLOCK
DCYI
Parame te r
Te s t Condition
M in.
Typ.
M ax.
Units
Clock frequency
Commercial
25
134
Clock frequency
Industrial
25
100
40
60
%
1
ms
Input clock duty cycle
Stabilization time after power up
tp
Phase error without jitter(3)
CLK_IN↑ at 100MHz and 66MHz
–150
+150
tj
Jitter, cycle- to- cycle
At 100MHz and 66MHz
–100
+100
45
55
Duty cycle
tr
Rise- time, 0.4V to 2.0V
1.0
tf
Fall- time, 2.0V to 0.4V
1.1
MHz
ps
%
ns
Note:
3. This switching parameter is guaranteed by design.
3
PS8418C
08/02/02
PI6C2402
Phase-Locked
Loop
Clock
Driver
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8-pin Plastic SOIC (W) Package
8
.149
.157
3.78
3.99
.0099
.0196
1
.189
.196
0.25
x 45˚
0.50
.0075
.0098
0-8˚
4.80
5.00
.016
.026
0.406
0.660
0.19
0.25
0.40 .016
1.27 .050
.053
.068
.2284
.2440
5.80
6.20
1.35
1.75
SEATING PLANE
REF
.050
BSC
1.27
.0040 0.10
.0098 0.25
.013 0.330
.020 0.508
X.XX DENOTES DIMENSIONS
X.XX IN MILLIMETERS
Ordering Information
Orde ring Code
Package Name
Package Type
Ope rating Range
PI6C2402W
W8
8- pin 150- mil SOIC
Commercial
PI6C2402- WI
W8
8- pin 150- mil SOIC
Industrial
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
4
PS8418C
08/02/02