PERICOM PI6C2401WE

PI6C2401
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Phase-Locked Loop Clock Driver
Product Features
Product Description
• High-Performance Phase-Locked-Loop Clock Distribution for
Networking, ATM, 100/134 MHz Registered DIMM Synchronous DRAM modules for server/workstation/PC applications
The PI6C2401 features a low-skew, low-jitter, phase-locked loop
(PLL) clock driver. By connecting the feedback CLK_OUT output
to the feedback FB_IN input, the propagation delay from the
CLK_IN input to any clock output will be nearly zero.
• Zero Input-to-Output delay
• Low jitter: Cycle-to-Cycle jitter ± 100ps max.
Application
• On-chip series damping resistor at clock output drivers
for low noise and EMI reduction
If the system designer needs more than 16 outputs with the features
just described, using two or more zero-delay buffers such as
PI6C2509Q, and PI6C2510Q, is likely to be impractical. The deviceto-device skew introduced can significantly reduce
the performance. Pericom recommends the use of a zero-delay
buffer and an eighteen output non-zero-delay buffer . As shown in
Figure 1, this combination produces a zero-delay buffer with all the
signal characteristics of the original zero-delay buffer, but with as
many outputs as the non-zero-delay buffer part. For example, when
combined with an eighteen output non-zero delay buffer, a system
designer can create a seventeen-output zero-delay buffer.
• Operates at 3.3V VCC
• Packaged in Plastic 8-pin SOIC Package (W)
Pb-free and Green Available
• Wide range of Clock Frequencies
Logic Block Diagram
Product Pin Configuration
CLK_IN
CLK_OUT
PLL
FB_IN
CLK_IN
1
AVCC
2
AGND
3
CLK_OUT
4
S
Feedback
Reference
Clock
Signal
CLK_OUT
FB_IN
7
VCC
6
GND
5
S
Control Input
18 Output
Non-Zero
Delay
Buffer
V
Zero Delay
Buffer
PI6C2401
8-Pin
W
8
17
S
Output Source
PLL Shutdown
1
PLL
N
0
CLK_IN
Y
Figure 1. This Combination Provides Zero-Delay Between
the Reference Clocks Signal and 17 Outputs
1
PS8419C
01/12/05
PI6C2401
Phase-Locked
Loop
Clock
Driver
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Pin Functions
Pin Name
Pin Numbe r
Type
De s cription
CLK_IN
1
I
AVCC
2
Power
Analog power supply.
AGND
3
Ground
Analog ground.
CLK_OUT
4
O
Clock outputs. The output provides low- skew copies of CLK_IN
and has an embedded series- damping resistor.
S
5
I
Control Input S. S is used to bypass the PLL for test purposes.
When S is strapped to ground, PLL is bypassed and CLK_IN
is buffered directly to the device outputs.
GND
6
Ground
Ground.
VCC
7
Power
Power supply.
FB_IN
8
I
Reference Clock input. CLK_IN allows spread spectrum clock input.
Feedback input. FBIN provides the feedback signal to the internal PLL.
DC Specifications (Absolute maximum ratings over operating free-air temperature range)
Symbol
Parame te r
VI
Input voltage range
VO
Output voltage range
M in.
−0.5
M a x.
Units
VCC + 0.5
V
VI_DC
DC input voltage
+5.0
IO_DC
DC output current
100
mA
Power
Maximum power dissipation at TA= 55oC in still air
1.0
W
TSTG
Storage temperature
15 0
oC
- 65
Note: Stress beyond those listed under “absolute maximum ratings” may cause permanent damage to the device.
Parame te r
Te s t Conditions
VCC
ICC
VI = VCC or GND; IO = 0(1)
3.6V
CI
VI = VCC or GND
M in.
Typ.
Units
10
µA
4
3.3V
CO
M ax.
pF
VO = VCC or GND
6
Note:
1. Continuous output current
2
PS8419C
01/12/05
PI6C2401
Phase-Locked
Loop
Clock
Driver
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Recommended Operating Conditions
Symbol
Parame te r
M in.
M ax.
3.6
VC C
Supply voltage
3.0
VIH
High level input voltage
2.0
VIL
Low level input voltage
VI
Input voltage
0
VC C
TA
Operating free- air temperature
0
70
Units
V
0.8
ºC
Electrical Characteristics
(Over recommended operating free-air temperature range Pull Up/Down Currents, VCC = 3.0V)
Symbol
Parame te r
Condition
M in.
M ax.
VO U T = 2.4V
−12
VO U T = 2.0V
−18
Pull- up current
IO H
Pull- down current
IO L
VO U T = 0.8V
18
VO U T = 0.55V
12
Units
mA
AC Specifications Timing Requirements
(Over recommended ranges of supply voltage and operating free-air temperature)
Symbol
Parame te r
M in.
M ax.
Units
FCLOCK
Clock frequency
25
134
MHz
DCYI
Input clock duty cycle
40
60
%
1
ms
Stabilization Time after power up
Switching Characteristics
(Over recommended ranges of supply voltage and operating free-air temperature, CL=30pF)
VCC= 3.3V ± 0.3V, 0-70 °C
Parame te r
From
To
tphase error without jitter
CLK_IN ↑ at 100 MHz
and 66 MHz
FB_IN↑
M in.
Typ.
M a x.
Units
+175
ps
Jitter, cycle- to- cycle
At 100 MHz and 66 MHz
CLK_OUT
Duty cycle
tr, rise- time, 0.4V to 2.0V
CLK_OUT
–150
+150
35
65
%
1. 0
ns
tf, fall- time, 2.0V to 0.4V
1.1
Note: These switching parameters are guaranteed by design.
3
PS8419C
01/12/05
PI6C2401
Phase-Locked
Loop
Clock
Driver
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Package Mechanical Information
Plastic 8-pin SOIC Package
8
.149
.157
3.78
3.99
.0099
.0196
1
.189
.196
0.25
x 45˚
0.50
.0075
.0098
0-8˚
4.80
5.00
0.19
0.25
0.40 .016
1.27 .050
.016
.026
0.406
0.660
.053
.068
.2284
.2440
5.80
6.20
1.35
1.75
SEATING PLANE
REF
.050
BSC
1.27
.0040 0.10
.0098 0.25
.013 0.330
.020 0.508
X.XX DENOTES DIMENSIONS
X.XX IN MILLIMETERS
Ordering Information
Orde ring Code
Package Code
Package Type
Ope rating Range
PI6C2401W
W
8- pin 150- mil SOIC
Commercial
PI6C2401WE
W
Pb- free and Green
8- pin 150- mil SOIC
Commercial
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
4
PS8419C
01/12/05