CY7B991V
3.3 V RoboClock® Low Voltage
Programmable Skew Clock Buffer
3.3 V RoboClock® Low Voltage Programmable Skew Clock Buffer
Features
Functional Description
■
All output pair skew <100 ps typical (250 ps max)
■
3.75 MHz to 80 MHz output operation
■
User-selectable output functions:
❐ Selectable skew up to 18 ns
❐ Inverted and non-inverted
❐ Operation at one-half and one-quarter input frequency
❐ Operation at 2 × and 4 × input frequency (input as low as
3.75 MHz)
■
Zero input to output delay
■
50% duty cycle outputs
■
Low-voltage transistor-transistor logic (LVTTL) outputs drive
50 terminated lines
■
Operates from a single 3.3 V supply
■
Low operating current
■
32-pin plastic leaded chip carrier (PLCC) package
■
Low cycle-to-cycle jitter (100 ps typical)
The CY7B991V 3.3 V RoboClock® low-voltage programmable
skew clock buffer (LVPSCB) offers user-selectable control over
system clock functions. These multiple output clock drivers
provide the system integrator with functions necessary to
optimize the timing of high-performance computer systems.
Each of the eight individual drivers – arranged in four pairs of
user controllable outputs – can drive terminated transmission
lines with impedances as low as 50 . This delivers minimal
output skews and full-swing logic levels (LVTTL).
Each output is hardwired to one of nine delay or function
configurations. Delay increments of 0.7 to 1.5 ns are determined
by the operating frequency, with outputs able to skew up to ±6
time units from their nominal ‘zero’ skew position. The
completely-integrated phase-locked loop (PLL) allows external
load and transmission line delay effects to be canceled. When
this ‘zero delay’ capability of the LVPSCB is combined with the
selectable output skew functions, the user can create
output-to-output delays of up to ±12 time units.
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems.
When combined with the internal PLL, these divide functions
enable distribution of a low frequency clock that is multiplied by
two or four at the clock destination. This feature minimizes clock
distribution difficulty, allowing maximum system clock speed and
flexibility.
For a complete list of related resources, click here.
Logic Block Diagram
TEST
PHASE
FREQ
DET
FB
REF
FILTER
VCO AND
TIME UNIT
GENERATOR
FS
4F0
4F1
3F0
3F1
4Q0
SELECT
INPUTS
(THREE
LEVEL)
4Q1
SKEW
3Q0
3Q1
SELECT
2F0
2F1
2Q0
MATRIX
2Q1
1Q0
1F0
1F1
Cypress Semiconductor Corporation
Document Number: 38-07141 Rev. *K
•
1Q1
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 18, 2016
CY7B991V
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 3
Block Diagram Description .............................................. 4
Phase Frequency Detector and Filter .......................... 4
VCO and Time Unit Generator .................................... 4
Skew Select Matrix ...................................................... 4
Test Mode .......................................................................... 5
Operational Mode Descriptions ...................................... 6
Maximum Ratings ............................................................. 9
Operating Range ............................................................... 9
Electrical Characteristics ................................................. 9
Capacitance .................................................................... 10
Thermal Resistance ........................................................ 10
AC Test Loads and Waveforms ..................................... 10
Switching Characteristics (-2 option) ........................... 11
Switching Characteristics (-5 Option) .......................... 12
Document Number: 38-07141 Rev. *K
Switching Characteristics (-7 Option) .......................... 13
AC Timing Diagrams ...................................................... 14
Ordering Information ...................................................... 15
Package Diagram ............................................................ 16
Acronyms ........................................................................ 17
Document Conventions ................................................. 17
Units of Measure ....................................................... 17
Document History Page ................................................. 18
Sales, Solutions, and Legal Information ...................... 20
Worldwide Sales and Design Support ....................... 20
Products .................................................................... 20
PSoC®Solutions ....................................................... 20
Cypress Developer Community ................................. 20
Technical Support ..................................................... 20
Page 2 of 20
CY7B991V
Pinouts
FS
VCCQ
REF
GND
4
3
2
1
32 31 30
29
2F1
3F0
TEST
Figure 1. 32-pin PLCC pinout
2F0
7
27
1F1
VCCQ
8
26
1F0
VCCN
9
25
VCCN
4Q1
10
24
1Q0
4Q0
11
23
1Q1
GND
12
22
GND
GND
13
21
14 15 16 17 18 19 20
GND
2Q0
4F1
2Q1
GND
VCCN
28
FB
6
3Q0
4F0
VCCN
5
3Q1
3F1
Pin Definitions
Pin Name
Pin Number
I/O
Description
REF
1
I
Reference frequency input. This input supplies the frequency and timing against which
all functional variations are measured.
FB
17
I
PLL feedback input (typically connected to one of the eight outputs).
FS
3
I
Three-level frequency range select. See Table 1.
1F0, 1F1
26, 27
I
Three-level function select inputs for output pair 1 (1Q0, 1Q1). See Table 2.
2F0, 2F1
29, 30
I
Three-level function select inputs for output pair 2 (2Q0, 2Q1). See Table 2.
3F0, 3F1
4, 5
I
Three-level function select inputs for output pair 3 (3Q0, 3Q1). See Table 2.
4F0, 4F1
6, 7
I
Three-level function select inputs for output pair 4 (4Q0, 4Q1). See Table 2.
TEST
31
I
Three-level select. See test mode section under the block diagram descriptions.
1Q0, 1Q1
24, 23
O
Output pair 1. See Table 2.
2Q0, 2Q1
20, 19
O
Output pair 2. See Table 2.
3Q0, 3Q1
15, 14
O
Output pair 3. See Table 2.
4Q0, 4Q1
11, 10
O
VCCN
9, 16, 18, 25
PWR
VCCQ
2, 8
PWR
Power supply for internal circuitry.
GND
12, 13, 21, 22,
28, 32
PWR
Ground.
Document Number: 38-07141 Rev. *K
Output pair 4. See Table 2.
Power supply for output drivers.
Page 3 of 20
CY7B991V
Block Diagram Description
Skew Select Matrix
The phase frequency detector and filter blocks accept inputs
from the reference frequency (REF) input and the feedback (FB)
input. They generate correction information to control the
frequency of the voltage controlled oscillator (VCO). These
blocks, along with the VCO, form a PLL that tracks the incoming
REF signal.
The skew select matrix is comprised of four independent
sections. Each section has two low-skew, high fanout drivers
(xQ0, xQ1), and two corresponding three-level function select
(xF0, xF1) inputs. Table 2 shows the nine possible output
functions for each section as determined by the function select
inputs. All times are measured with respect to the REF input
assuming that the output connected to the FB input has 0tU
selected.
VCO and Time Unit Generator
Table 2. Programmable Skew Configurations [1]
Phase Frequency Detector and Filter
The VCO accepts analog control inputs from the PLL filter block.
It generates a frequency that is used by the time unit generator
to create discrete time units, selected in the skew select matrix.
The operational range of the VCO is determined by the FS
control pin. The time unit (tU) is determined by the operating
frequency of the device and the level of the FS pin as shown in
Table 1.
Table 1. Frequency Range Select and tU
FS[2, 3]
LOW
fNOM (MHz)
Min
Max
15
30
Calculation[1]
1
Approximate
t U = -----------------------f NOM N Frequency (MHz) At
Function Selects
Output Functions
1F1, 2F1, 1F0, 2F0, 1Q0, 1Q1,
3F1, 4F1 3F0, 4F0 2Q0, 2Q1
–4tU
3Q0, 3Q1
4Q0, 4Q1
LOW
LOW
LOW
MID
–3tU
–6tU
–6tU
LOW
HIGH
–2tU
–4tU
–4tU
MID
LOW
–1tU
–2tU
–2tU
MID
MID
0tU
0tU
0tU
Divide by 2 Divide by 2
MID
HIGH
+1tU
+2tU
+2tU
HIGH
LOW
+2tU
+4tU
+4tU
where N =
Which tU = 1.0 ns
44
22.7
HIGH
MID
+3tU
+6tU
+6tU
HIGH
HIGH
+4tU
Divide by 4
Inverted
MID
25
50
26
38.5
HIGH
40
80
16
62.5
Notes
1. For all three state inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination
circuitry holds an unconnected input to VCC/2.
2. The level to be set on FS is determined by the “normal” operating frequency (fNOM) of the VCO and Time Unit Generator (see Logic Block Diagram). Nominal frequency
(fNOM) always appears at the outputs when they are operated in their undivided modes (see Table 2). The frequency appearing at the REF and FB inputs is fNOM
when the output connected to FB is undivided. The frequency of the REF and FB inputs is fNOM/2 or fNOM/4 when the part is configured for a frequency multiplication
using a divided output as the FB input.
3. When the FS pin is selected HIGH, the REF input must not transition upon power up until VCC has reached 2.8 V.
Document Number: 38-07141 Rev. *K
Page 4 of 20
CY7B991V
Test Mode
The TEST input is a three-level input. In normal system operation, this pin is connected to ground, allowing the CY7B991V to operate
as explained in the Block Diagram Description on page 4. For testing purposes, any of the three-level inputs can have a removable
jumper to ground or be tied LOW through a 100- resistor. This enables an external tester to change the state of these pins.
If the TEST input is forced to its MID or HIGH state, the device operates with its internal phase locked loop disconnected, and input
levels supplied to REF directly controls all outputs. Relative output to output functions are the same as in normal mode.
In contrast with normal operation (TEST tied LOW), all outputs function based only on the connection of their own function select
inputs (xF0 and xF1) and the waveform characteristics of the REF input.
U
U
U
U
U
U
t 0 +1t
t 0 +2t
t 0 +3t
t 0 +4t
t 0 +5t
t 0 +6t
t0
t 0 – 1t U
t 0 – 2t U
t 0 – 3t U
t 0 – 4t U
t 0 – 5t U
t 0 – 6t U
Figure 2. Typical Outputs with FB Connected to a Zero Skew Output Test Mode [4]
FBInput
REFInput
1Fx
2Fx
3Fx
4Fx
(N/A)
LM
– 6t U
LL
LH
– 4t U
LM
(N/A)
– 3t U
LH
ML
– 2t U
ML
(N/A)
– 1t U
MM
MM
MH
(N/A)
+1t U
HL
MH
+2t U
HM
(N/A)
+3t U
0tU
HH
HL
+4t U
(N/A)
HM
+6t U
(N/A)
LL/HH
DIVIDED
(N/A)
HH
INVERT
Note
4. FB connected to an output selected for “zero” skew (that is, xF1 = xF0 = MID).
Document Number: 38-07141 Rev. *K
Page 5 of 20
CY7B991V
Operational Mode Descriptions
Figure 3. Zero Skew and Zero Delay Clock Driver
REF
LOAD
SYSTEM
CLOCK
Z0
L1
FB
REF
FS
4F0
4F1
4Q0
4Q1
3F0
3F1
3Q0
3Q1
2F0
2F1
2Q0
2Q1
1F0
1F1
1Q0
1Q1
LOAD
L2
Z0
LOAD
L3
Z0
L4
LOAD
TEST
Z0
LENGTH L1 = L2 = L3 = L4
Figure 2 shows the LVPSCB configured as a zero skew clock buffer. In this mode, the CY7B991V is the basis for a low-skew clock
distribution tree. When all of the function select inputs (×F0, ×F1) are left open, the outputs are aligned and drive a terminated
transmission line to an independent load. The FB input is tied to any output in this configuration and the operating frequency range
is selected with the FS pin. The low skew specification, coupled with the ability to drive terminated transmission lines (with impedances
as low as 50 ), enables efficient printed circuit board design.
Figure 4. Programmable Skew Clock Driver
REF
SYSTEM
CLOCK
FB
REF
FS
4F0
4F1
LOAD
L1
LOAD
4Q0
4Q1
3F0
3F1
2F0
2F1
3Q0
3Q1
1F0
1F1
1Q0
1Q1
Z0
L2
Z0
LOAD
L3
2Q0
2Q1
Z0
L4
LOAD
TEST
LENGTH L1 = L2
L3 < L2 by 6 inches
L4 > L2 by 6 inches
Figure 4 shows a configuration to equalize skew between metal
traces of different lengths. In addition to low skew between
outputs, the LVPSCB is programmed to stagger the timing of its
outputs. The four groups of output pairs are each programmed
to different output timing. Skew timing is adjusted over a wide
range in small increments using the function select pins. In this
configuration, the 4Q0 output is sent back to FB and configured
for zero skew. The other three pairs of outputs are programmed
to yield different skews relative to the feedback. By advancing
the clock signal on the longer traces or retarding the clock signal
on shorter traces, all loads receive the clock pulse at the same
time.
Figure 4 shows the FB input connected to an output with 0 ns
skew (xF1, xF0 = MID) selected. The internal PLL synchronizes
Document Number: 38-07141 Rev. *K
Z0
the FB and REF inputs and aligns their rising edges to make
certain that all outputs have precise phase alignment.
Clock skews are advanced by ±6 time units (tU) when using an
output selected for zero skew as the feedback. A wider range of
delays is possible if the output connected to FB is also skewed.
Since “Zero Skew”, +tU, and –tU are defined relative to output
groups, and the PLL aligns the rising edges of REF and FB, wider
output skews are created by proper selection of the xFn inputs.
For example, a +10 tU between REF and 3Qx is achieved by
connecting 1Q0 to FB and setting 1F0 = 1F1 = GND, 3F0 = MID,
and 3F1 = High. (Since FB aligns at –4 tU, and 3Qx skews to +6
tU, a total of +10 tU skew is realized.) Many other configurations
are realized by skewing both the outputs used as the FB input
and skewing the other outputs.
Page 6 of 20
CY7B991V
Figure 5. Inverted Output Connections
REF
FB
REF
FS
Figure 7. Frequency Divider Connections
4F0
4F1
4Q0
4Q1
3F0
3F1
3Q0
3Q1
2F0
2F1
2Q0
2Q1
1F0
1F1
1Q0
1Q1
REF
20 MHz
TEST
7B991V–11
Figure 5 shows an example of the invert function of the LVPSCB.
In this example the 4Q0 output used as the FB input is
programmed for invert (4F0 = 4F1 = HIGH) while the other three
pairs of outputs are programmed for zero skew. When 4F0 and
4F1 are tied high, 4Q0 and 4Q1 become inverted zero phase
outputs. The PLL aligns the rising edge of the FB input with the
rising edge of the REF. This causes the 1Q, 2Q, and 3Q outputs
to become the “inverted” outputs to the REF input. By selecting
the output connected to FB, you can have two inverted and six
non-inverted outputs or six inverted and two non-inverted
outputs. The correct configuration is determined by the need for
more (or fewer) inverted outputs. 1Q, 2Q, and 3Q outputs can
also be skewed to compensate for varying trace delays
independent of inversion on 4Q.
Figure 6. Frequency Multiplier with Skew Connections
REF
20 MHz
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
simultaneously and are out of phase on their rising edge. This
enables the designer to use the rising edges of the 1⁄2 frequency
and 1⁄4 frequency outputs without concern for rising edge skew.
The 2Q0, 2Q1, 1Q0, and 1Q1 outputs run at 80 MHz and are
skewed by programming their select inputs accordingly. Note
that the FS pin is wired for 80 MHz operation as that is the
frequency of the fastest output.
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
40 MHz
20 MHz
80 MHz
7B991V–12
Figure 6 shows the LVPSCB configured as a clock multiplier. The
3Q0 output is programmed to divide by four and is sent back to
FB. This causes the PLL to increase its frequency until the 3Q0
and 3Q1 outputs are locked at 20 MHz, while the 1Qx and 2Qx
outputs run at 80 MHz. The 4Q0 and 4Q1 outputs are
programmed to divide by two that results in a 40 MHz waveform
at these outputs. Note that the 20- and 40-MHz clocks fall
Document Number: 38-07141 Rev. *K
FB
REF
FS
4F0
4F1
4Q0
4Q1
10 MHz
3F0
3F1
2F0
2F1
3Q0
3Q1
5 MHz
1F0
1F1
TEST
1Q0
1Q1
2Q0
2Q1
20 MHz
7B991V–13
Figure 7 shows the LVPSCB in a clock divider application. 2Q0
is sent back to the FB input and programmed for zero skew. 3Qx
is programmed to divide by four. 4Qx is programmed to divide by
two. Note that the falling edges of the 4Qx and 3Qx outputs are
aligned. This enables use of the rising edges of the 1⁄2 frequency
and 1⁄4 frequency without concern for skew mismatch. The 1Qx
outputs are programmed to zero skew and are aligned with the
2Qx outputs. In this example, the FS input is grounded to
configure the device in the 15 to 30 MHz range since the highest
frequency output is running at 20 MHz.
Figure 8 on page 8 shows some of the functions that are
selectable on the 3Qx and 4Qx outputs. These include inverted
outputs and outputs that offer divide-by-2 and divide-by-4 timing.
An inverted output enables the system designer to clock different
subsystems on opposite edges without suffering from the pulse
asymmetry typical of non-ideal loading. This function enables
each of the two subsystems to clock 180 degrees out of phase,
but still is aligned within the skew specification.
The divided outputs offer a zero delay divider for portions of the
system that divide the clock by either two or four, and still remain
within a narrow skew of the “1X” clock. Without this feature, an
external divider is added, and the propagation delay of the
divider adds to the skew between the different clock signals.
These divided outputs, coupled with the PLL, enable the
LVPSCB to multiply the clock rate at the REF input by either two
or four. This mode allows the designer to distribute a low
frequency clock between various portions of the system. It also
locally multiplies the clock rate to a more suitable frequency,
while still maintaining the low skew characteristics of the clock
driver. The LVPSCB performs all of the functions described in
this section at the same time. It can multiply by two and four or
divide by two (and four) at the same time that it shifts its outputs
over a wide range or maintains zero skew between selected
outputs.
Page 7 of 20
CY7B991V
Figure 8. Multi-Function Clock Driver
REF
LOAD
Z0
80 MHz
INVERTED
FB
REF
FS
20 MHz
DISTRIBUTION
CLOCK
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
LOAD
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
20 MHz
Z0
LOAD
80 MHz
ZERO SKEW
Z0
80 MHz
SKEWED –3.125 ns (–4tU)
LOAD
Z0
Figure 9. Board-to-Board Clock Distribution
LOAD
REF
Z0
L1
FB
SYSTEM
CLOCK
REF
FS
4F0
4F1
LOAD
3F0
3F1
2F0
2F1
3Q0
3Q1
1F0
1F1
1Q0
1Q1
Z0
L2
4Q0
4Q1
LOAD
L3
2Q0
2Q1
Z0
L4
TEST
Z0
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
LOAD
LOAD
Figure 9 shows the CY7B991V connected in series to construct a zero skew clock distribution tree between boards. Delays of the
downstream clock buffers are programmed to compensate for the wire length (that is, select negative skew equal to the wire delay)
necessary to connect them to the master clock source, approximating a zero delay clock tree. Cascaded clock buffers accumulate
low frequency jitter because of the non-ideal filtering characteristics of the PLL filter. Do not connect more than two clock buffers in a
series.
Document Number: 38-07141 Rev. *K
Page 8 of 20
CY7B991V
Maximum Ratings
Output current into outputs (LOW) ............................. 64 mA
Static discharge voltage
(MIL-STD-883, Method 3015) .................................. >2001 V
Operating outside these boundaries may affect the performance
and life of the device. These user guidelines are not tested.
Latch up current ...................................................... >200 mA
Storage temperature .................................. –65 °C to 150 °C
Operating Range
Ambient temperature
with power applied ..................................... –55 °C to 125 °C
Range
Supply voltage to ground potential ..............–0.5 V to +7.0 V
Ambient Temperature
Commercial
DC input voltage ..........................................–0.5 V to +7.0 V
Industrial
VCC
0 °C to 70 °C
3.3 V 10%
–40 °C to 85 °C
3.3 V 10%
Electrical Characteristics
Over the Operating Range
Parameter [5]
Description
Test Conditions
VOH
Output HIGH voltage
VCC = Min, IOH = –12 mA
VOL
Output LOW voltage
VCC = Min, IOL = 35 mA
VIH
CY7B991V
Min
Max
Unit
2.4
–
V
–
0.45
V
Input HIGH voltage
(REF and FB inputs only)
2.0
VCC
V
VIL
Input LOW voltage
(REF and FB inputs only)
–0.5
0.8
V
VIHH
Three-level input HIGH
Voltage (Test, FS, xFn) [6]
Min VCC Max.
0.87 × VCC
VCC
V
VIMM
Three-level input MID
voltage (Test, FS, xFn) [6]
Min VCC Max.
0.47 × VCC 0.53 × VCC
VILL
Three-level input LOW
voltage (Test, FS, xFn) [6]
Min VCC Max.
IIH
Input HIGH leakage current
(REF and FB inputs only)
IIL
V
0.0
0.13 × VCC
V
VCC = Max, VIN = Max.
–
20
A
Input LOW leakage current
(REF and FB inputs only)
VCC = Max, VIN = 0.4 V
–20
–
A
IIHH
Input HIGH current (Test, FS,
xFn)
VIN = VCC
–
200
A
IIMM
Input MID current (Test, FS, xFn) VIN = VCC/2
–50
50
A
IILL
Input LOW current (Test, FS, xFn) VIN = GND
–200
–
A
–200
–
mA
–
95
mA
–
100
mA
–
19
mA
[7]
IOS
Short circuit current
ICCQ
Operating current used by
internal circuitry
VCCN = VCCQ = Max,
All Input Selects Open
ICCN
Output buffer current per output
pair [8]
VCCN = VCCQ = Max, IOUT = 0 mA,
Input Selects Open, fMAX
VCC = Max, VOUT = GND (25 °C only)
Commercial
Military / Industrial
Notes
5. See the last page of this specification for Group A subgroup testing information.
6. These inputs are normally wired to VCC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold
unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs glitch and the PLL requires an additional tLOCK time before all datasheet
limits are achieved.
7. CY7B991V is tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only.
8. Total output current per output pair is approximated by the following expression that includes device current plus load current:
CY7B991V:ICCN = [(4 + 0.11F) + [((835 –3F)/Z) + (.0022FC)]N] x 1.1
Where
F = frequency in MHz
C = capacitive load in pF
Z = line impedance in ohms
N = number of loaded outputs; 0, 1, or 2
FC = F × C
Document Number: 38-07141 Rev. *K
Page 9 of 20
CY7B991V
Electrical Characteristics (continued)
Over the Operating Range
Parameter [5]
PD
Description
CY7B991V
Test Conditions
Power dissipation per output pair VCCN = VCCQ = Max, IOUT = 0 mA,
Input Selects Open, fMAX
Min
Max
–
104
Unit
mW
Capacitance
Parameter [9, 10]
Description
Test Conditions
Input capacitance
CIN
Max
Unit
10
pF
Test Conditions
32-pin PLCC
Package
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance,
according to EIA/JESD51.
44
°C/W
26
°C/W
TA = 25 °C, f = 1 MHz, VCC = 3.3 V
Thermal Resistance
Parameter [10]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
AC Test Loads and Waveforms
Figure 10. AC Test Loads and Waveforms
VCC
R1
CL
R2
3.0 V
R1=100
R2=100
CL = 30 pF
(Includes fixture and probe capacitance)
TTL AC Test Load
2.0 V
Vth =1.5 V
0.8 V
0.0 V
ns
2.0 V
Vth =1.5 V
0.8 V
1 ns
TTL Input Test Waveform
Notes
9. Applies to REF and FB inputs only. Tested initially and after any design or process changes that may affect these parameters.
10. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-07141 Rev. *K
Page 10 of 20
CY7B991V
Switching Characteristics (-2 option)
Over the Operating Range
Parameter [11, 12]
fNOM
CY7B991V-2
Description
Operating clock Frequency in MHz
Min
Typ
Max
FS = LOW [11, 13]
15
–
30
FS = MID [11, 13]
25
–
50
FS = HIGH [11, 13, 14]
Unit
MHz
40
–
80
tRPWH
REF pulse width HIGH measured at 1/2 × VCCQ threshold
3.65
–
–
ns
tRPWL
REF pulse width LOW measured at 1/2 × VCCQ threshold
3.65
–
–
ns
tU
Programmable skew unit
tSKEWPR
Zero output matched-pair skew (XQ0, XQ1)[15, 16]
–
0.05
0.2
ns
tSKEW0
Zero output skew (all outputs)[15, 17]
–
0.1
0.25
ns
–
0.1
0.5
ns
–
0.5
1.0
ns
–
0.25
0.5
ns
–
0.5
0.9
ns
See Table 1
outputs)[15, 18]
tSKEW1
Output skew (rise-rise, fall-fall, same class
tSKEW2
Output skew (rise-fall, nominal-inverted, divided-divided)[15, 18]
outputs)[15, 18]
tSKEW3
Output skew (rise-rise, fall-fall, different class
tSKEW4
Output skew (rise-fall, nominal-divided, divided-inverted)[15, 18]
skew[19, 20]
tDEV
Device-to-device
tPD
Propagation delay, REF rise to FB rise
variation[21]
tODCV
Output duty cycle
tPWH
Output HIGH time deviation from 50%[22]
tPWL
Output LOW time deviation from
50%[22]
tORISE
Output rise time[22, 23]
time[22, 23]
tOFALL
Output fall
tLOCK
PLL lock time[24]
tJR
Cycle-to-cycle output jitter
–
–
1.25
ns
–0.25
0.0
+0.25
ns
–0.65
0.0
+0.65
ns
–
–
2.0
ns
–
–
1.5
ns
0.15
1.0
1.2
ns
0.15
1.0
1.2
ns
–
–
0.5
ms
RMS[19]
–
–
25
ps
Peak[19]
–
100
200
ps
Notes
11. The level to be set on FS is determined by the “normal” operating frequency (fNOM) of the VCO and Time Unit Generator (see Logic Block Diagram). Nominal frequency
(fNOM) always appears at the outputs when they are operated in their undivided modes (see Table 2). The frequency appearing at the REF and FB inputs is fNOM
when the output connected to FB is undivided. The frequency of the REF and FB inputs is fNOM/2 or fNOM/4 when the part is configured for a frequency multiplication
using a divided output as the FB input.
12. Test measurement levels for the CY7B991V are TTL levels (1.5 V to 1.5 V). Test conditions assume signal transition times of 2 ns or less and output loading as shown in the
AC Test Loads and Waveforms unless otherwise specified.
13. For all three state inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination
circuitry holds an unconnected input to VCC/2.
14. When the FS pin is selected HIGH, the REF input must not transition upon power up until VCC has reached 2.8 V.
15. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded
with 30 pF and terminated with 50 to VCC/2 (CY7B991V).
16. tSKEWPR is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0tU.
17. tSKEW0 is defined as the skew between outputs when they are selected for 0tU. Other outputs are divided or inverted but not shifted.
18. There are three classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-2 or
Divide-by-4 mode).
19. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
20. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC ambient temperature, air flow, etc.)
21. tODCV is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications.
22. Specified with outputs loaded with 30 pF for the CY7B991V–5 and –7 devices. Devices are terminated through 50 to VCC/2. tPWH is measured at 2.0 V. tPWL is measured
at 0.8 V.
23. tORISE and tOFALL measured between 0.8 V and 2.0 V.
24. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured
from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
Document Number: 38-07141 Rev. *K
Page 11 of 20
CY7B991V
Switching Characteristics (-5 Option)
Over the Operating Range
Parameter [25, 26]
fNOM
CY7B991V-5
Description
Operating clock frequency in MHz
Min
Typ
Max
FS = LOW [25, 27]
15
–
30
FS = MID [25, 27]
25
–
50
FS = HIGH [25, 27]
Unit
MHz
40
–
80
tRPWH
REF pulse width HIGH measured at 1/2 × VCCQ threshold
3.65
–
–
ns
tRPWL
REF pulse width LOW measured at 1/2 × VCCQ threshold
3.65
–
–
ns
tU
Programmable skew unit
tSKEWPR
Zero output matched-pair skew (XQ0, XQ1)[28, 29]
–
0.1
0.25
ns
tSKEW0
Zero output skew (all outputs)[28, 29]
–
0.25
0.5
ns
–
0.6
0.7
ns
–
0.5
1.0
ns
–
0.5
0.7
ns
–
0.5
1.0
ns
See Table 1
outputs)[28, 30]
tSKEW1
Output skew (rise-rise, fall-fall, same class
tSKEW2
Output skew (rise-fall, nominal-inverted, divided-divided)[28, 30]
outputs)[28, 30]
tSKEW3
Output skew (rise-rise, fall-fall, different class
tSKEW4
Output skew (rise-fall, nominal-divided, divided-inverted)[28, 30]
skew[32, 33]
tDEV
Device-to-device
tPD
Propagation delay, REF rise to FB rise
variation[34]
tODCV
Output duty cycle
tPWH
Output HIGH time deviation from 50%[35]
tPWL
Output LOW time deviation from
50%[35]
tORISE
Output rise time[35, 36]
Output fall
tLOCK
PLL lock time[36]
tJR
Cycle-to-cycle output jitter
–
1.25
ns
0.0
+0.5
ns
–1.0
0.0
+1.0
ns
–
–
2.5
ns
–
–
3
ns
0.15
1.0
1.5
ns
0.15
1.0
1.5
ns
–
–
0.5
ms
RMS[32]
–
–
25
ps
Peak-to-peak[32]
–
–
200
ps
time[35, 36]
tOFALL
–
–0.5
Notes
25. The level to be set on FS is determined by the “normal” operating frequency (fNOM) of the VCO and Time Unit Generator (see Logic Block Diagram). Nominal frequency
(fNOM) always appears at the outputs when they are operated in their undivided modes (see Table 2). The frequency appearing at the REF and FB inputs is fNOM
when the output connected to FB is undivided. The frequency of the REF and FB inputs is fNOM/2 or fNOM/4 when the part is configured for a frequency multiplication
using a divided output as the FB input.
26. Test measurement levels for the CY7B991V are TTL levels (1.5 V to 1.5 V). Test conditions assume signal transition times of 2 ns or less and output loading as shown in the
AC Test Loads and Waveforms unless otherwise specified.
27. For all three state inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination
circuitry holds an unconnected input to VCC/2.
28. tSKEWPR is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0tU.
29. tSKEW0 is defined as the skew between outputs when they are selected for 0tU. Other outputs are divided or inverted but not shifted.
30. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC ambient temperature, air flow, etc.)
31. CL = 0 pF. For CL = 30 pF, tSKEW0 = 0.35 ns.
32. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded
with 30 pF and terminated with 50 to VCC/2 (CY7B991V).
33. tODCV is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications.
34. Specified with outputs loaded with 30 pF for the CY7B991V–5 and –7 devices. Devices are terminated through 50 to VCC/2. tPWH is measured at 2.0 V. tPWL is measured
at 0.8 V.
35. tORISE and tOFALL measured between 0.8 V and 2.0 V.
36. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured
from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
Document Number: 38-07141 Rev. *K
Page 12 of 20
CY7B991V
Switching Characteristics (-7 Option)
Over the Operating Range
Parameter [37, 38]
fNOM
CY7B991V–7
Description
Operating clock Frequency in MHz
Min
Typ
Max
FS = LOW [37, 39]
15
–
30
FS = MID [37, 39]
25
–
50
FS = HIGH [37, 39]
Unit
MHz
40
–
80
tRPWH
REF pulse width HIGH measured at 1/2 × VCCQ threshold
3.65
–
–
ns
tRPWL
REF pulse width LOW measured at 1/2 × VCCQ threshold
3.65
–
–
ns
tU
Programmable skew unit
tSKEWPR
Zero output matched pair skew (XQ0, XQ1)[40, 41]
–
0.1
0.25
ns
tSKEW0
Zero output skew (All Outputs)[40, 42]
–
0.3
0.75
ns
–
0.6
1.0
ns
–
1.0
1.5
ns
–
0.7
1.2
ns
–
1.2
1.7
ns
See Table 1
outputs)[43, 44]
tSKEW1
Output skew (rise-rise, fall-fall, same class
tSKEW2
Output skew (rise-fall, nominal-inverted, divided-divided)[40, 45]
outputs)[40, 45]
tSKEW3
Output skew (rise-rise, fall-fall, different class
tSKEW4
Output skew (rise-fall, nominal-divided, divided-inverted)[40, 45]
skew[43, 46]
tDEV
Device-to-device
tPD
Propagation delay, REF rise to FB rise
variation[46]
tODCV
Output duty cycle
tPWH
Output HIGH time deviation from 50%[47]
tPWL
Output LOW time deviation from
50%[47]
tORISE
Output rise time[47, 48]
Output fall
tLOCK
PLL lock time[49]
tJR
Cycle-to-cycle output jitter
–
1.65
ns
0.0
+0.7
ns
–1.2
0.0
+1.2
ns
–
–
3
ns
–
–
3.5
ns
0.15
1.5
2.5
ns
0.15
1.5
2.5
ns
–
–
0.5
ms
RMS[50]
–
–
25
ps
Peak-to-peak[50]
–
–
200
ps
time[47, 48]
tOFALL
–
–0.7
Notes
37. The level to be set on FS is determined by the “normal” operating frequency (fNOM) of the VCO and Time Unit Generator (see Logic Block Diagram). Nominal frequency
(fNOM) always appears at the outputs when they are operated in their undivided modes (see Table 2). The frequency appearing at the REF and FB inputs is fNOM
when the output connected to FB is undivided. The frequency of the REF and FB inputs is fNOM/2 or fNOM/4 when the part is configured for a frequency multiplication
using a divided output as the FB input.
38. Test measurement levels for the CY7B991V are TTL levels (1.5 V to 1.5 V). Test conditions assume signal transition times of 2 ns or less and output loading as shown in the
AC Test Loads and Waveforms unless otherwise specified.
39. For all three state inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination
circuitry holds an unconnected input to VCC/2.
40. tSKEWPR is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0tU.
41. tSKEW0 is defined as the skew between outputs when they are selected for 0tU. Other outputs are divided or inverted but not shifted.
42. CL = 0 pF. For CL = 30 pF, tSKEW0 = 0.35 ns.
43. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded
with 30 pF and terminated with 50 to VCC/2 (CY7B991V).
44. There are three classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-2 or
Divide-by-4 mode).
45. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC ambient temperature, air flow, etc.)
46. tODCV is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications.
47. Specified with outputs loaded with 30 pF for the CY7B991V–5 and –7 devices. Devices are terminated through 50 to VCC/2. tPWH is measured at 2.0 V. tPWL is measured
at 0.8 V.
48. tORISE and tOFALL measured between 0.8 V and 2.0 V.
49. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured
from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
50. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-07141 Rev. *K
Page 13 of 20
CY7B991V
AC Timing Diagrams
tREF
tRPWL
tRPWH
REF
tODCV
tPD
tODCV
FB
tJR
Q
tSKEWPR,
tSKEW0,1
tSKEWPR,
tSKEW0,1
OTHER Q
tSKEW2
tSKEW2
INVERTED Q
tSKEW3,4
tSKEW3,4
tSKEW3,4
REF DIVIDED BY 2
tSKEW1,3, 4
tSKEW2,4
REF DIVIDED BY 4
Document Number: 38-07141 Rev. *K
Page 14 of 20
CY7B991V
Ordering Information
Speed (ps)
250
500
Ordering Code
Package Type
Operating
Range
CY7B991V-2JC
32-pin PLCC
Commercial
CY7B991V-2JCT
32-pin PLCC – Tape and Reel
Commercial
CY7B991V-5JI
32-pin PLCC
Industrial
CY7B991V-5JIT
32-pin PLCC – Tape and Reel
Industrial
CY7B991V-2JXC
32-pin PLCC
Commercial
CY7B991V-2JXCT
32-pin PLCC – Tape and Reel
Commercial
CY7B991V-5JXC
32-pin PLCC
Commercial
CY7B991V-5JXCT
32-pin PLCC – Tape and Reel
Commercial
CY7B991V-5JXI
32-pin PLCC
Industrial
CY7B991V-5JXIT
32-pin PLCC – Tape and Reel
Industrial
CY7B991V-7JXC
32-pin PLCC
Commercial
CY7B991V-7JXCT
32-pin PLCC – Tape and Reel
Commercial
Pb-free
250
500
750
Ordering Code Definitions
CY 7B991V
-
X
J
X
X
X
X = blank or T
blank = Tube; T = Tape and Reel
Temperature Range: X = C or I
C = Commercial = 0 C to +70 C; I = Industrial = –40 C to 85 C
X = Pb-free; X Absent = Leaded
Package Type:
J = 32-pin PLCC
Device Option (Performance): X = 2 or 5 or 7
Base Part Number
Company ID: CY = Cypress
Document Number: 38-07141 Rev. *K
Page 15 of 20
CY7B991V
Package Diagram
Figure 11. 32-pin PLCC (0.453 × 0.553 Inches) J32 Package Outline, 51-85002
51-85002 *E
Document Number: 38-07141 Rev. *K
Page 16 of 20
CY7B991V
Acronyms
Document Conventions
Table 3. Acronyms Used in this Document
Units of Measure
Acronym
Description
Table 4. Units of Measure
CMOS
Complementary Metal Oxide Semiconductor
FB
Feedback
°C
degree Celsius
LVPSCB
Low-Voltage Programmable Skew Clock Buffer
k
kilohm
LVTTL
Low-Voltage Transistor-Transistor Logic
µA
microampere
PLL
Phase-Locked Loop
µs
microsecond
PLCC
Plastic Leaded Chip Carrier
mA
milliampere
RF
Reference Frequency
ms
millisecond
RMS
Root Mean Square
mW
milliwatt
VCO
Voltage Controlled Oscillator
MHz
megahertz
ns
nanosecond
ohm
pF
picofarad
ps
picosecond
V
volt
W
watt
Document Number: 38-07141 Rev. *K
Symbol
Unit of Measure
Page 17 of 20
CY7B991V
Document History Page
Document Title: CY7B991V, 3.3 V RoboClock® Low Voltage Programmable Skew Clock Buffer
Document Number: 38-07141
Revision
ECN
Submission
Date
Orig. of
Change
**
110250
12/17/01
SZV
Change from Specification number: 38-00641 to 38-07141.
*A
293239
See ECN
RGL
Updated Features:
Removed “Jitter < 200 ps peak-to-peak (< 25 ps RMS)”.
Added “Jitter 100 ps (typical)”.
Updated Switching Characteristics (-2 option):
Added typical value of tJR parameter as “100 ps” corresponding to “Peak”.
Updated Ordering Information:
Updated part numbers.
*B
1199925
See ECN
KVM /
AESA
Removed “Switching Characteristics (-2 option)”.
Updated Ordering Information:
No change in part numbers.
Changed format only.
*C
1286064
See ECN
AESA
Change status from Preliminary to Final.
*D
2584293
10/10/08
AESA
Added Switching Characteristics (-2 option).
Updated to new template.
*E
2761988
09/10/09
CXQ
Updated Test Mode:
Replaced “100W resistor” with “100 resistor”.
Updated Ordering Information:
No change in part numbers.
Replaced “Pb” with “pin” in “Package Type” column.
*F
2905834
04/06/2010
CXQ
Updated Ordering Information:
Removed inactive part numbers CY7B991V-5JC, CY7B991V-5JCT,
CY7B991V-7JC and CY7B991V-7JCT.
Updated Package Diagram.
*G
3041840
09/29/2010
CXQ
Fixed various format and typographical errors.
Updated Pinouts:
Updated Figure 1 (Fixed pin 8 label).
Updated Pin Definitions:
Added “Pin Number” column.
Updated Electrical Characteristics:
Removed values from “Max” column of ILL and IOS parameters and added the
same values in “Min” column.
Removed note “These inputs are normally wired to VCC, GND, or left
unconnected (actual threshold voltages vary as a percentage of VCC). Internal
termination resistors hold unconnected inputs at VCC/2. If these inputs are
switched, the function and timing of the outputs may glitch and the PLL may
require an additional tLOCK time before all datasheet limits are achieved.” and
its reference in “Description” column of PD parameter.
*H
4161003
10/16/2013
CINM
Updated Package Diagram:
spec 51-85002 – Changed revision from *C to *D.
Updated to new template.
Completing Sunset Review.
*I
4598452
12/16/2014
TAVA
Updated Functional Description:
Added “For a complete list of related resources, click here.” at the end.
Added AC Timing Diagrams.
Document Number: 38-07141 Rev. *K
Description of Change
Page 18 of 20
CY7B991V
Document History Page (continued)
Document Title: CY7B991V, 3.3 V RoboClock® Low Voltage Programmable Skew Clock Buffer
Document Number: 38-07141
Revision
ECN
Submission
Date
Orig. of
Change
*J
4644120
01/28/2015
TAVA
Updated Switching Characteristics (-2 option):
Updated description of tRPWH and tRPWL parameters.
Changed minimum value of tRPWH parameter from 5 ns to 3.65 ns.
Changed minimum value of tRPWL parameter from 5 ns to 3.65 ns.
Updated Switching Characteristics (-5 Option):
Updated description of tRPWH and tRPWL parameters.
Changed minimum value of tRPWH parameter from 5 ns to 3.65 ns.
Changed minimum value of tRPWL parameter from 5 ns to 3.65 ns.
Updated Switching Characteristics (-7 Option):
Updated description of tRPWH and tRPWL parameters.
Changed minimum value of tRPWH parameter from 5 ns to 3.65 ns.
Changed minimum value of tRPWL parameter from 5 ns to 3.65 ns.
Updated Package Diagram:
spec 51-85002 – Changed revision from *D to *E.
*K
5276098
05/18/2016
PSR
Updated Electrical Characteristics:
Updated Note 8 (Replaced “FC = F < C” with “FC = F × C”).
Added Thermal Resistance.
Updated to new template.
Document Number: 38-07141 Rev. *K
Description of Change
Page 19 of 20
CY7B991V
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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Forums | Projects | Video | Blogs | Training | Components
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cypress.com/support
cypress.com/psoc
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cypress.com/wireless
© Cypress Semiconductor Corporation, 2001-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
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Document Number: 38-07141 Rev. *K
Revised May 18, 2016
Page 20 of 20