PI6C41202 PI6C41204 PI6C41204A 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 LVCMOS to LVPECL Driver Features Description • Up to Four LVPECL outputs PI6C4120x is a high-performance LVCMOS or LVTTL to LVPECL clock buffer. The PI6C41204 is a 4 output version with 2 selectable inputs, pin compatible with ICS8535-01. PI6C41204A is the enhanced version with extra power and ground pins to minimize noise and jitter. The PI6C41202 is similar to the PI6C41204 except it has two outputs. • • • • • • • Selectable CLK0 or CLK1 inputs LVCMOS or LVTTL input level 30ps max output skew 150ps max part-to-part skew 1.9ns max propagation delay 266 MHz output frequency Packaging (Pb-free & Green available): -14-pin TSSOP - 20-pin TSSOP Pin Configuration PI6C41204/A Block Diagram PI6C41204/A D CLK_EN LE CLK0 0 CLK1 1 Vee CLK_EN CK_SEL CLK0 nc/Vee CLK1 nc/Vee nc/Vee nc/Vcc Vcc Q Q0 nQ0 Q1 nQ1 CLK_SEL Q2 nQ2 Q3 nQ3 Block Diagram PI6C41202 Vee CLK_EN CK_SEL CLK0 Vee CLK1 Vcc Q LE CLK0 0 CLK1 1 20 2 19 3 18 4 5 17 20-Pin 16 6 15 7 14 8 13 9 12 10 11 Q0 nQ0 Vcc Q1 nQ1 Q2 nQ2 Vcc Q3 nQ3 Pin Configuration PI6C41202 D CLK_EN 1 Q0 nQ0 Q1 nQ1 CLK_SEL 1 1 14 2 13 3 14-Pin 12 4 11 5 10 6 9 7 8 Vcc Q0 nQ0 nc Q1 nQ1 Vcc PS8626D 05/11/05 PI6C4120x LVCMOS to LVPECL Driver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Table 1a. Pin Description for PI6C41204 N umbe r N a me Type D e s criptio n 1 Vee P o wer 2 C LK _EN Inp ut P ullup 3 C LK _S EL Inp ut P ulld o wn C lo ck select inp ut: LO W = C LK 0 , HIGH = C LK 1 LVC MO S o r LVTTL inp ut level. 4 C LK 0 Inp ut P ulld o wn LVC MO S o r LVTTL clo ck inp ut. 6 C LK 1 Inp ut P ulld o wn LVC MO S o r LVTTL inp ut level. 5, 7, 8, 9 NC Unused N o C o nnect 10, 13, 18 Vcc P o wer 3 . 3 V sup p ly 11, 12 nQ 3 , Q 3 O utp ut LVP EC L o utp ut p air. 14, 15 nQ 2 , Q 2 O utp ut LVP EC L o utp ut p air. 16, 17 nQ 1, Q 1 O utp ut LVP EC L o utp ut p air. 19, 20 nQ 0 , Q 0 O utp ut LVP EC L o utp ut p air. Gro und . S ynchro nizing clo ck enab le. When HIGH, clo ck o utp uts fo llo w clo ck inp ut. When LO W, Q are lo w, nQ are high. LVC MO S o r LVTTL inp ut level. Table 1b. Pin Description for PI6C41204A N umbe r N a me Type D e s criptio n 1, 5, 7, 8 Vee P o wer 2 C LK _EN Inp ut P ullup 3 C LK _S EL Inp ut P ulld o wn C lo ck select inp ut: LO W = C LK 0 , HIGH = C LK 1 LVC MO S o r LVTTL inp ut level 4 C LK 0 Inp ut P ulld o wn LVC MO S o r LVTTL clo ck inp ut. 6 C LK 1 Inp ut P ulld o wn LVC MO S o r LVTTL inp ut level. 9, 10, 13, 18 Vcc P o wer 3 . 3 V sup p ly 11, 12 nQ 3 , Q 3 O utp ut LVP EC L o utp ut p air. 14, 15 nQ 2 , Q 2 O utp ut LVP EC L o utp ut p air. 16, 17 nQ 1, Q 1 O utp ut LVP EC L o utp ut p air. 19, 20 nQ 0 , Q 0 O utp ut LVP EC L o utp ut p air. Gro und . S ynchro nizing clo ck enab le. When HIGH, clo ck o utp uts fo llo w clo ck inp ut. When LO W, Q are lo w, nQ are high. LVC MO S o r LVTTL inp ut level. 2 PS8626D 05/11/05 PI6C4120x LVCMOS to LVPECL Driver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Table 1c. Pin Description for PI6C41202 Numbe r Name Type De s cription 1, 5 Vee Power 2 CLK_EN Input Pullup 3 CLK_SEL Input Pulldown Clock select input: LOW = CLK0, HIGH = CLK1 LVCMOS or LVTTL input level. 4 CLK0 Input Pulldown LVCMOS or LVTTL clock input. 6 CLK1 Input Pulldown LVCMOS or LVTTL input level. 7, 8, 14 Vcc Power 3.3V supply 9, 10 nQ1, Q1 Output LVPECL output pair. 12, 13 nQ0, Q0 Output LVPECL output pair. Ground. Synchronizing clock enable. When HIGH, clock outputs follow clock input. When LOW, Q are low, nQ are high. LVCMOS or LVTTL input level. Table 2. Pin Characteristics S y mbo l Pa ra me te r Te s t Co nditio ns C LK 0 , C LK 1 C IN M in. Ty p. M ax. Units 3.2 Inp ut C ap acitance pF C LK _ EN C LK _ S EL 2.7 RP ULLUP Inp ut P ullup Resisto r 80 RP ULLDO WN Inp ut P ulld o wn Resisto r 80 K o hm 3 PS8626D 05/11/05 PI6C4120x LVCMOS to LVPECL Driver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Table 3a. Control Input Function Table Inputs Outputs CLK_EN CLK_SEL Se le cte d Source Q0 thru Q3* nQ0 thru nQ3* 0 0 CLK0 Disabled ; LOW Disabled ; HIGH 0 1 CLK1 Disabled ; LOW Disabled ; HIGH 1 0 CLK0 Enabled Enabled 1 1 CLK1 Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in figure1. In the active mode, the state of the outputs are a function of the CLK0 and CLK1 inputs as described in Table 3b. Disabled Enabled CLK0, CLK1 CLK_EN nQ0 - nQ3* Q0 - Q3* Figure 1. CLK_EN Timing Diagram Table 3b. Clock Input Function Table Inputs Outputs CLK0 or CLK1 Q0 thru Q3* nQ0 thru nQ3* 0 LOW HIGH 1 HIGH LOW Note: *PI6C41204 and PI6C41204A have four differential outputs. Q0 through Q3 and nQ0 through nQ3. PI6C41202 has two differential outputs. Q0 through Q1 and nQ0 through nQ1. 4 PS8626D 05/11/05 PI6C4120x LVCMOS to LVPECL Driver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested) Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Storage Temperature ...................................................................–65°C to +150°C Ambient Temperature with Power Applied .................................. –40°C to +85°C Supply Voltage, VCC .................................................................................................. +4.6V Input/Output Voltage ........................................................... –0.5V to VCC + 0.5V Table 4a. Operating Conditions (Commercial) Symbol Parame te r M in. Typ. M ax. Units VCC Supply Voltage 3.135 3.3 3.465 V IEE Supply Current 50 mA TA Ambient Temperature 70 °C 0 Table 4b. LVCMOS/LVTTL DC Characteristics, (VCC = 3.3V ± 5%, TA = 0°C to +70°C) Symbol VIH Parame te r Input High Voltage Te s t Conditions M in. Typ. M ax. CLK0,CLK1 2 3.765 CLK_EN CLK_SEL 2 3.765 Units V VIL IIH IIL Input Low Voltage Input High Current Input Low Current CLK0, CLK1 — 0.3 0.8 CLK_EN CLK_SEL — 0.3 0.8 CLK0,CLK1 CLK_SEL VIN = VCC = 3.465V 150 CLK_EN VIN = VCC = 3.465V 5 μA CLK0, CLK1 CLK_SEL VIN =0V, VCC = 3.465V —5 CLK_EN VIN =0V, VCC = 3.465V — 150 5 PS8626D 05/11/05 PI6C4120x LVCMOS to LVPECL Driver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Table 4c. LVPECL DC Characteristics (V CC = 3.3V ± 5%, TA = 0°C to +70°C) S y mbo l Pa ra me te r Te s t Co nditio ns M in. Ty p. M ax. VO H O utp ut High Vo ltage N o te 1 VC C - 1 . 4 VC C - 1 . 0 VO L O utp ut Lo w Vo ltage N o te 1 VC C - 2 . 0 VC C - 1 . 7 VS WIN G P eak - to - P eak O utp ut Vo ltage S wing 0.6 0.85 Units V Note: 1. Outputs terminated with 50ohm to VCC - 2V Table 5. AC Characteristics, (V CC = 3.3V ± 5%, TA = 0°C to +70°C (Note 3) S ymbo l Pa ra me te r Te s t Co nditio ns fMAX Maximum Inp ut F req uency tPLH P ro p agatio n Delay Lo w to High : N o te 4 tPHL P ro p agatio n Delay High to Lo w : N o te 4 ts ( o ) O utp ut S kew : N o te 5 ts k ( p p ) P a r t to P a r t S k e w : N o te 6 tDC O utp ut Duty C ycle 48 tr /tf O utp ut Rise / F all time 2 0 % to 8 0 % 100 VC C to VO X M in. Typ. 1.0 M ax. Units 266 MHz 1.9 ns VC C to VO X 1.0 1.9 11 30 ps 150 50 52 % 400 ps Notes: 3. All parameters measured at 266MHz unless noted otherwise. The part does not add jitter. 4. Measured from the VDD/2 point of the input to the differential output crossing point. 5. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output crossing points differential. 6. Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Measured at the output crossing points differential. 6 PS8626D 05/11/05 PI6C4120x LVCMOS to LVPECL Driver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Table 5a. Operating Conditions (Industrial) Symbol Parame te r M in. Typ. M ax. Units VCC Supply Voltage 3.135 3.3 3.465 V IEE Supply Current 50 mA TA Ambient Temperature 85 °C –40 Table 5b. LVCMOS/LVTTL DC Characteristics, (VCC = 3.3V ± 5%, TA = –40°C to +85°C) Symbol VIH Parame te r Input High Voltage Te s t Conditions M in. Typ. M ax. CLK0,CLK1 2 3.765 CLK_EN CLK_SEL 2 3.765 Units V VIL IIH IIL Input Low Voltage Input High Current Input Low Current CLK0, CLK1 — 0.3 0.8 CLK_EN CLK_SEL — 0.3 0.8 CLK0,CLK1 CLK_SEL VIN = VCC = 3.465V 150 CLK_EN VIN = VCC = 3.465V 5 μA CLK0, CLK1 CLK_SEL VIN =0V, VCC = 3.465V —5 CLK_EN VIN =0V, VCC = 3.465V — 150 7 PS8626D 05/11/05 PI6C4120x LVCMOS to LVPECL Driver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Table 5c. LVPECL DC Characteristics (V CC = 3.3V ± 5%, TA = –40°C to +85°C) S y mbo l Pa ra me te r Te s t Co nditio ns M in. Ty p. M ax. VO H O utp ut High Vo ltage N o te 1 VC C - 1 . 4 VC C - 1 . 0 VO L O utp ut Lo w Vo ltage N o te 1 VC C - 2 . 0 VC C - 1 . 7 VS WIN G P eak - to - P eak O utp ut Vo ltage S wing 0.6 0.85 Units V Note: 1. Outputs terminated with 50ohm to VCC - 2V Table 6. AC Characteristics, (V CC = 3.3V ± 5%, TA = –40°C to +85°C, See Note 3) S ymbo l Pa ra me te r Te s t Co nditio ns fMAX Maximum Inp ut F req uency tPLH P ro p agatio n Delay Lo w to High : N o te 4 tPHL P ro p agatio n Delay High to Lo w : N o te 4 ts ( o ) O utp ut S kew : N o te 5 ts k ( p p ) P a r t to P a r t S k e w : N o te 6 tDC O utp ut Duty C ycle 45 tr/tf O utp ut Rise / F all time 2 0 % to 8 0 % 100 VCC to VOX M in. Typ. 1.0 M ax. Units 266 MHz 1.9 ns VCC to VOX 1.0 1.9 11 100 ps 150 50 55 % 400 ps Notes: 3. All parameters measured at 266MHz unless noted otherwise. The part does not add jitter. 4. Measured from the VDD/2 point of the input to the differential output crossing point. 5. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output crossing points differential. 6. Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Measured at the output crossing points differential. 8 PS8626D 05/11/05 PI6C4120x LVCMOS to LVPECL Driver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 VCC SCOPE Z = 50-Ohm Qx LVPECL 50-Ohm VCC = 2V Z = 50-Ohm nQx 50-Ohm VEE = -1.3V ± 0.165V Figure2. 2-3.3V Output Load Test Circuit Qx Qx Part 1 nQx nQx Qy Qy Part 2 nQy nQy tsk(0) tsk(0) Figure 4. Part-to-Part Skew Figure 3. Output Skew 80% 80% CLK0, CLK1 VSWING Clock Inputs and Outputs Q0, Q3 20% 20% nQ0, nQ3 tF tR tPD Figure 5. Input and Output Rise and Fall Time Figure 6. Propagation Delay nQ0, nQ3 Q0, Q3 Pulse Width tPERIOD odc = tPW tPERIOD Figure 7. odc & tPERIOD 9 PS8626D 05/11/05 PI6C4120x LVCMOS to LVPECL Driver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Packaging Mechanical: 14-Pin TSSOP (L) 14 0.004 0.09 0.008 0.20 0.169 0.177 4.3 4.5 0.45 0.75 0.018 0.030 0.240 0.264 1 0.193 0.201 4.90 5.10 6.1 6.7 0.047 1.20 max. SEATING PLANE 0.0256 typical 0.65 0.007 0.012 0.19 0.30 0.002 0.05 0.006 0.15 10 PS8626D 05/11/05 PI6C4120x LVCMOS to LVPECL Driver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Packaging Mechanical: 20-Pin TSSOP (L) 20 .169 .177 4.3 4.5 1 .252 .260 6.4 6.6 .0256 BSC 0.65 .004 0.09 .008 0.20 .047 1.20 Max .007 .012 0.19 0.30 0.45 0.75 SEATING PLANE .018 .030 .238 .269 6.1 6.7 .002 0.05 .006 0.15 Ordering Information Ordering Code PI6C41202L PI6C41202LE PI6C41204L PI6C41204LE PI6C41204LI PI6C41204LIE PI6C41204AL PI6C41204ALE Package Code L L L L L L L L Package Type 14-pin1 73-mil TSSOP Pb-free & Green, 14-pin1 73-mil TSSOP 20-pin 173-mil TSSOP Pb-free & Green, 20-pin 173-mil TSSOP 20-pin 173-mil TSSOP Pb-free & Green, 20-pin 173-mil TSSOP 20-pin 173-mil TSSOP Pb-free & Green, 20-pin 173-mil TSSOP Operating Temperature Commercial Commercial Commercial Commercial Industrial Industrial Commercial Commercial Notes: 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com 11 PS8626D 05/11/05