PMC PM4354

PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
PM4354
COMET-QUAD
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER/FRAMER
DATASHEET
RELEASED
ISSUE 6: MAY 2001
PMC-Sierra, Inc.
105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
CONTENTS
1
FEATURES........................................................................................................................ 1
1.1
RECEIVER SECTION: ......................................................................................... 2
1.2
TRANSMITTER SECTION:.................................................................................. 3
2
APPLICATIONS................................................................................................................. 6
3
REFERENCES .................................................................................................................. 7
4
APPLICATION EXAMPLE ............................................................................................... 10
5
BLOCK DIAGRAM........................................................................................................... 11
6
DESCRIPTION ................................................................................................................ 12
7
PIN DIAGRAM................................................................................................................. 14
8
PIN DESCRIPTION ......................................................................................................... 16
9
FUNCTIONAL DESCRIPTION ........................................................................................ 33
9.1
QUADRANTS ..................................................................................................... 33
9.2
RECEIVE INTERFACE....................................................................................... 33
9.3
CLOCK AND DATA RECOVERY (CDRC) .......................................................... 36
9.4
RECEIVE JITTER ATTENUATOR (RJAT) ......................................................... 38
9.5
T1 INBAND LOOPBACK CODE DETECTOR (IBCD)........................................ 39
9.6
T1 PULSE DENSITY VIOLATION DETECTOR (PDVD).................................... 39
9.7
T1 FRAMER (T1-FRMR).................................................................................... 39
9.8
E1 FRAMER (E1-FRMR).................................................................................... 40
9.9
RECEIVE ELASTIC STORE (RX-ELST)............................................................ 46
9.10
SIGNALING EXTRACTOR (SIGX)..................................................................... 47
9.11
PERFORMANCE MONITOR COUNTERS (T1/E1-PMON) ............................... 47
9.12
T1 AUTOMATIC PERFORMANCE REPORT GENERATION (APRM) .............. 48
9.13
T1 ALARM INTEGRATOR (ALMI) ...................................................................... 48
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
i
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
10
ISSUE 6
9.14
HDLC RECEIVER (RDLC) ................................................................................. 49
9.15
BIT ORIENTED CODE DETECTOR (RBOC) .................................................... 49
9.16
RECEIVE PER-CHANNEL SERIAL CONTROLLER (RPSC) ............................ 50
9.17
PSEUDO RANDOM BINARY SEQUENCE GENERATION AND DETECTION
(PRBS) ............................................................................................................... 50
9.18
BACKPLANE RECEIVE SYSTEM INTERFACE (BRIF)..................................... 50
9.19
BACKPLANE TRANSMIT SYSTEM INTERFACE (BTIF) .................................. 54
9.20
TRANSMIT PER-CHANNEL SERIAL CONTROLLER (TPSC) .......................... 57
9.21
TRANSMIT ELASTIC STORE (TX-ELST) ......................................................... 58
9.22
T1 BASIC TRANSMITTER (T1-XBAS) .............................................................. 58
9.23
E1 TRANSMITTER (E1-TRAN).......................................................................... 59
9.24
T1 INBAND LOOPBACK CODE GENERATOR (XIBC) ..................................... 59
9.25
PULSE DENSITY ENFORCER (XPDE)............................................................. 59
9.26
T1 SIGNALING ALIGNER (SIGA) ...................................................................... 59
9.27
BIT ORIENTED CODE GENERATOR (XBOC).................................................. 60
9.28
HDLC TRANSMITTER (TDPR).......................................................................... 60
9.29
TRANSMIT JITTER ATTENUATOR (TJAT) ....................................................... 61
9.30
LINE TRANSMITTER ......................................................................................... 66
9.31
TIMING OPTIONS (TOPS) ................................................................................ 66
9.32
JTAG TEST ACCESS PORT.............................................................................. 66
9.33
MICROPROCESSOR INTERFACE ................................................................... 66
NORMAL MODE REGISTER DESCRIPTION ................................................................ 68
10.1
11
NORMAL MODE REGISTER MEMORY MAP ................................................... 68
TEST FEATURES DESCRIPTION................................................................................ 328
11.1
12
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
JTAG TEST PORT ........................................................................................... 328
OPERATION.................................................................................................................. 331
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
ii
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
12.1
CONFIGURING THE COMET-QUAD FROM RESET ..................................... 331
12.2
SERVICING INTERRUPTS.............................................................................. 338
12.3
USING THE PERFORMANCE MONITORING FEATURES ............................ 338
12.4
USING THE INTERNAL HDLC TRANSMITTER.............................................. 343
12.5
USING THE INTERNAL HDLC RECEIVER ..................................................... 346
12.6
T1 AUTOMATIC PERFORMANCE REPORT FORMAT .................................. 350
12.7
USING THE TRANSMIT LINE PULSE GENERATOR ..................................... 352
12.8
USING THE LINE RECEIVER.......................................................................... 372
12.9
USING THE PRBS GENERATOR AND DETECTOR ...................................... 381
12.10
USING THE PER-CHANNEL SERIAL CONTROLLERS AND SIGX ............... 381
12.10.1 INITIALIZATION .................................................................................. 381
12.10.2 DIRECT ACCESS MODE.................................................................... 382
12.10.3 INDIRECT ACCESS MODE ................................................................ 382
12.11
T1/E1 FRAMER LOOPBACK MODES............................................................. 383
12.11.1 LINE LOOPBACK................................................................................ 383
12.11.2 PAYLOAD LOOPBACK ....................................................................... 383
12.11.3 PER-CHANNEL LOOPBACK .............................................................. 384
12.11.4 DIAGNOSTIC DIGITAL LOOPBACK................................................... 385
12.12
RSYNC GENERATION .................................................................................... 385
12.13
BACKPLANE CONFIGURATION ..................................................................... 386
12.13.1 RECEIVE CLOCK MASTER: FULL T1/E1 MODE SETTINGS ........... 387
12.13.2 RECEIVE CLOCK MASTER: NX64KBIT/S MODE SETTINGS .......... 388
12.13.3 RECEIVE CLOCK MASTER: CLEAR CHANNEL MODE SETTINGS 388
12.13.4 RECEIVE CLOCK SLAVE: FULL T1/E1 MODE SETTINGS............... 389
12.13.5 RECEIVE CLOCK SLAVE: H-MVIP MODE SETTINGS...................... 389
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
iii
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
12.13.6 RECEIVE CLOCK SLAVE: FULL T1/E1 WITH CCS H-MVIP MODE
SETTINGS .......................................................................................... 391
12.13.7 TRANSMIT CLOCK MASTER: FULL T1/E1 MODE SETTINGS ........ 392
12.13.8 TRANSMIT CLOCK MASTER: NX64KBIT/S MODE SETTINGS ....... 393
12.13.9 TRANSMIT CLOCK MASTER: CLEAR CHANNEL MODE SETTINGS393
12.13.10 TRANSMIT CLOCK SLAVE: FULL T1/E1 MODE SETTINGS.......... 394
12.13.11 TRANSMIT CLOCK SLAVE: CLEAR CHANNEL MODE SETTINGS394
12.13.12 TRANSMIT CLOCK SLAVE: H-MVIP MODE SETTINGS................. 395
12.13.13 TRANSMIT CLOCK SLAVE: FULL T1/E1 WITH CCS H-MVIP MODE
SETTINGS .......................................................................................... 397
12.14
H-MVIP DATA FORMAT ................................................................................... 398
12.15
JTAG SUPPORT .............................................................................................. 401
12.15.1 TAP CONTROLLER ............................................................................ 403
13
FUNCTIONAL TIMING .................................................................................................. 410
13.1
BACKPLANE RECEIVE SERIAL CLOCK AND DATA INTERFACE TIMING ... 410
13.2
BACKPLANE RECEIVE H-MVIP TIMING ........................................................ 415
13.3
BACKPLANE TRANSMIT SERIAL CLOCK AND DATA INTERFACE TIMING 416
13.4
BACKPLANE TRANSMIT H-MVIP TIMING ..................................................... 424
14
ABSOLUTE MAXIMUM RATINGS ................................................................................ 426
15
D.C. CHARACTERISTICS ............................................................................................ 427
16
MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS.............................. 429
17
COMET-QUAD TIMING CHARACTERISTICS ............................................................. 433
17.1
RSTB TIMING .................................................................................................. 433
17.2
XCLK INPUT TIMING....................................................................................... 433
17.3
TRANSMIT BACKPLANE INTERFACE (FIGURE 83, FIGURE 84)................. 434
17.4
RECEIVE BACKPLANE INTERFACE (FIGURE 85, FIGURE 86) ................... 437
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
iv
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
18
ORDERING AND THERMAL INFORMATION............................................................... 445
19
MECHANICAL INFORMATION ..................................................................................... 446
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
v
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
LIST OF FIGURES
FIGURE 1
- WIRELESS BASE STATION APPLICATION....................................................... 10
FIGURE 2
- V5.2 INTERFACE APPLICATION........................................................................ 10
FIGURE 3
- COMET-QUAD BLOCK DIAGRAM ..................................................................... 11
FIGURE 4
- PIN DIAGRAM..................................................................................................... 15
FIGURE 5
- EXTERNAL ANALOG INTERFACE CIRCUITS................................................... 34
FIGURE 6:
- T1 JITTER TOLERANCE .................................................................................... 37
FIGURE 7:
- COMPLIANCE WITH ITU-T SPECIFICATION G.823 FOR E1 INPUT JITTER .. 38
FIGURE 8:
- CRC MULTIFRAME ALIGNMENT ALGORITHM................................................. 43
FIGURE 9:
- RECEIVE CLOCK MASTER: FULL T1/E1 .......................................................... 51
FIGURE 10: - RECEIVE CLOCK MASTER: NX64KBIT/S ......................................................... 51
FIGURE 11: - RECEIVE CLOCK MASTER: CLEAR CHANNEL ............................................... 52
FIGURE 12: - RECEIVE CLOCK SLAVE: FULL T1/E1.............................................................. 52
FIGURE 13: - RECEIVE CLOCK SLAVE: H-MVIP..................................................................... 52
FIGURE 14: - RECEIVE CLOCK SLAVE: FULL T1/E1 WITH CCS H-MVIP ............................. 53
FIGURE 15: - TRANSMIT CLOCK MASTER: FULL T1/E1 ....................................................... 54
FIGURE 16: - TRANSMIT CLOCK MASTER: NX64KBIT/S ...................................................... 55
FIGURE 17: - TRANSMIT CLOCK MASTER: CLEAR CHANNEL............................................. 55
FIGURE 18: - TRANSMIT CLOCK SLAVE: FULL T1/E1 ........................................................... 55
FIGURE 19: - TRANSMIT CLOCK SLAVE: CLEAR CHANNEL ................................................ 56
FIGURE 20: - TRANSMIT CLOCK SLAVE: H-MVIP .................................................................. 56
FIGURE 21: - TRANSMIT CLOCK SLAVE: FULL T1/E1 WITH CCS H-MVIP........................... 57
FIGURE 22: - TJAT JITTER TOLERANCE ................................................................................ 63
FIGURE 23: - TJAT MINIMUM JITTER TOLERANCE VS. XCLK ACCURACY......................... 64
FIGURE 24: - TJAT JITTER TRANSFER................................................................................... 65
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
vi
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
FIGURE 25
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- TRANSMIT TIMING OPTIONS ........................................................................... 91
FIGURE 26: - FER COUNT VS. BER (E1 MODE)................................................................... 340
FIGURE 27: - CRCE COUNT VS. BER (E1 MODE)................................................................ 341
FIGURE 28: - FER COUNT VS. BER (T1 ESF MODE) ........................................................... 341
FIGURE 29: - CRCE COUNT VS. BER (T1 ESF MODE) ........................................................ 342
FIGURE 30: - CRCE COUNT VS. BER (T1 SF MODE) .......................................................... 343
FIGURE 31: - TYPICAL DATA FRAME .................................................................................... 349
FIGURE 32: - EXAMPLE MULTI-PACKET OPERATIONAL SEQUENCE ............................... 349
FIGURE 33: - LINE LOOPBACK.............................................................................................. 383
FIGURE 34: - PAYLOAD LOOPBACK ..................................................................................... 384
FIGURE 35: - DIAGNOSTIC DIGITAL LOOPBACK................................................................. 385
FIGURE 36
- RSYNC GENERATION ..................................................................................... 386
FIGURE 37: - BOUNDARY SCAN ARCHITECTURE .............................................................. 402
FIGURE 38: - TAP CONTROLLER FINITE STATE MACHINE ................................................ 404
FIGURE 39: - INPUT OBSERVATION CELL (IN_CELL) ......................................................... 407
FIGURE 40: - OUTPUT CELL (OUT_CELL) OR ENABLE CELL (ENABLE)........................... 408
FIGURE 41: - BIDIRECTIONAL CELL (IO_CELL) ................................................................... 409
FIGURE 42: - LAYOUT OF OUTPUT ENABLE AND BIDIRECTIONAL CELLS ...................... 409
FIGURE 43: - T1 RECEIVE CLOCK MASTER : FULL T1/E1 MODE ...................................... 410
FIGURE 44:
- E1 RECEIVE CLOCK MASTER : FULL T1/E1 MODE ..................................... 410
FIGURE 45: - T1 RECEIVE CLOCK MASTER: NX64KBIT/S MODE ...................................... 411
FIGURE 46: - E1 RECEIVE CLOCK MASTER : NX64KBIT/S MODE ..................................... 411
FIGURE 47: - T1/E1 RECEIVE CLOCK MASTER : CLEAR CHANNEL MODE ...................... 412
FIGURE 48: - T1 RECEIVE CLOCK SLAVE: FULL T1/E1 MODE ........................................... 412
FIGURE 49: - E1 RECEIVE CLOCK SLAVE: FULL T1/E1 MODE........................................... 412
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
vii
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
FIGURE 50: - E1 RECEIVE CLOCK SLAVE: FULL T1/E1 MODE (CMS=1) ........................... 413
FIGURE 51: - T1 RECEIVE 2.048 MHZ CLOCK SLAVE: FULL T1/E1 MODE ........................ 413
FIGURE 52: - CONCENTRATION HIGHWAY INTERFACE TIMING, EXAMPLE 1 .................. 414
FIGURE 53: - CONCENTRATION HIGHWAY INTERFACE TIMING, EXAMPLE 2 .................. 414
FIGURE 54: - RECEIVE CLOCK SLAVE: H-MVIP MODE ........................................................ 415
FIGURE 55: - T1 RECEIVE CLOCK SLAVE: H-MVIP MODE................................................... 415
FIGURE 56: - E1 RECEIVE CLOCK SLAVE: H-MVIP MODE................................................... 416
FIGURE 57: - TRANSMIT BACKPLANE: CMS=0, FE=1, DE=1, BTFP IS INPUT..................... 417
FIGURE 58: - TRANSMIT BACKPLANE: CMS=0, FE=1, DE=0, BTFP IS INPUT..................... 417
FIGURE 59: - TRANSMIT BACKPLANE: CMS=1, FE=1, DE=1, BTFP IS INPUT..................... 417
FIGURE 60: - TRANSMIT BACKPLANE: CMS=1, FE=0, DE=1, BTFP IS INPUT..................... 417
FIGURE 61: - TRANSMIT BACKPLANE: CMS=0, FE=1, DE=1, BTFP IS OUTPUT ................ 417
FIGURE 62: - TRANSMIT BACKPLANE: CMS=0, FE=1, DE=0, BTFP IS OUTPUT ................ 418
FIGURE 63: - T1 TRANSMIT CLOCK MASTER : FULL T1/E1 MODE..................................... 418
FIGURE 64: - E1 TRANSMIT CLOCK MASTER : FULL T1/E1 MODE .................................... 418
FIGURE 65: - T1 TRANSMIT CLOCK MASTER: NX64KBIT/S MODE (DE=1, FE=0) ............. 419
FIGURE 66: - E1 TRANSMIT CLOCK MASTER : NX64KBIT/S MODE (DE=1, FE=0) ............ 419
FIGURE 67: - T1 TRANSMIT CLOCK MASTER: NX64KBIT/S MODE (DE=0, FE=0) .............. 419
FIGURE 68: - E1 TRANSMIT CLOCK MASTER: NX64KBIT/S MODE (DE=0, FE=0) .............. 420
FIGURE 69: - T1/E1 TRANSMIT CLOCK MASTER : CLEAR CHANNEL MODE .................... 420
FIGURE 70: - T1 TRANSMIT CLOCK SLAVE: FULL T1/E1 MODE ......................................... 421
FIGURE 71: - E1 TRANSMIT CLOCK SLAVE : FULL T1/E1 MODE ........................................ 421
FIGURE 72: - T1 TRANSMIT 2.048 MHZ CLOCK SLAVE : FULL T1/E1 MODE...................... 422
FIGURE 73: - T1/E1 TRANSMIT CLOCK SLAVE : CLEAR CHANNEL MODE ......................... 422
FIGURE 74: - CONCENTRATION HIGHWAY INTERFACE TIMING, EXAMPLE1 .................... 423
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
viii
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
FIGURE 75: - CONCENTRATION HIGHWAY INTERFACE TIMING, EXAMPLE 2 .................. 423
FIGURE 76: - TRANSMIT CLOCK SLAVE: H-MVIP MODE ..................................................... 424
FIGURE 77: - T1 TRANSMIT CLOCK SLAVE: H-MVIP MODE ................................................ 424
FIGURE 78: - E1 TRANSMIT CLOCK SLAVE: H-MVIP MODE ................................................ 425
FIGURE 79: - MICROPROCESSOR INTERFACE READ TIMING.......................................... 430
FIGURE 80: - MICROPROCESSOR INTERFACE WRITE TIMING........................................ 432
FIGURE 81: - RSTB TIMING ................................................................................................... 433
FIGURE 82: - XCLK INPUT TIMING........................................................................................ 433
FIGURE 83
- BACKPLANE TRANSMIT INPUT TIMING DIAGRAM ...................................... 434
FIGURE 84
- BACKPLANE TRANSMIT OUTPUT TIMING DIAGRAM .................................. 436
FIGURE 85
- BACKPLANE RECEIVE INPUT TIMING DIAGRAM ......................................... 438
FIGURE 86
- BACKPLANE RECEIVE OUTPUT TIMING DIAGRAM ..................................... 439
FIGURE 87: - H-MVIP TRANSMIT DATA AND FRAME PULSE TIMING ................................ 440
FIGURE 88: - H-MVIP RECEIVE DATA TIMING...................................................................... 441
FIGURE 89: - TRANSMIT LINE INTERFACE TIMING ............................................................ 442
FIGURE 90: - JTAG PORT INTERFACE TIMING.................................................................... 443
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
ix
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
LIST OF TABLES
TABLE 1:
- EXTERNAL COMPONENT DESCRIPTIONS ..................................................... 35
TABLE 2 :
- TERMINATION RESISTORS, TRANSFORMER RATIOS AND TRL .................. 35
TABLE 3:
- E1-FRMR FRAMING STATES ............................................................................ 44
TABLE 4
- NORMAL MODE REGISTER MEMORY MAP .................................................... 68
TABLE 5
- TJAT FIFO OUTPUT CLOCK SOURCE ............................................................ 88
TABLE 6
- TJAT PLL SOURCE............................................................................................. 89
TABLE 7
- TRANSMIT TIMING OPTIONS SUMMARY ........................................................ 89
TABLE 8
- LOSS OF SIGNAL THRESHOLDS ................................................................... 103
TABLE 9
- RECEIVE BACKPLANE NX64KBIT/S MODE SELECTION.............................. 126
TABLE 10
- RECEIVE BACKPLANE RATE .......................................................................... 128
TABLE 11
- E1 RECEIVE BACKPLANE FRAME PULSE CONFIGURATIONS ................... 131
TABLE 12
- RECEIVE BACKPLANE BIT OFFSET FOR CMS = 0....................................... 137
TABLE 13
- RECEIVE BACKPLANE BIT OFFSET FOR CMS = 1....................................... 137
TABLE 14
- TRANSMIT BACKPLANE NX64KBIT/S MODE SELECTION ........................... 141
TABLE 15
- TRANSMIT BACKPLANE RATE ....................................................................... 143
TABLE 16
- TRANSMIT BACKPLANE BIT OFFSET FOR CMS = 0 .................................... 150
TABLE 17
- TRANSMIT BACKPLANE BIT OFFSET FOR CMS = 1 .................................... 150
TABLE 18
- T1 FRAMING MODES....................................................................................... 152
TABLE 19
- LOOPBACK CODE CONFIGURATIONS .......................................................... 157
TABLE 20
- SIGX INDIRECT REGISTER MAP.................................................................... 170
TABLE 21
- SIGX INDIRECT REGISTERS 10H - 1FH: CURRENT TIMESLOT/CHANNEL
SIGNALING DATA ...................................................................................................................... 172
TABLE 22
- SIGX INDIRECT REGISTERS 20H - 3FH: DELAYED TIMESLOT/CHANNEL
SIGNALING DATA ...................................................................................................................... 172
TABLE 23
- INDIRECT REGISTERS 40H - 5FH: PER-TIMESLOT CONFIGURATION ...... 173
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
x
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
TABLE 24
- SIGX PER-CHANNEL T1 DATA CONDITIONING ............................................ 174
TABLE 25
- SIGX PER-CHANNEL E1 DATA CONDITIONING ............................................ 174
TABLE 26
- T1 FRAMING FORMATS .................................................................................. 177
TABLE 27
- T1 ZERO CODE SUPPRESSION FORMATS................................................... 177
TABLE 28
- TRANSMIT IN-BAND CODE LENGTH ............................................................. 179
TABLE 29
- T1 FRAMING MODES....................................................................................... 192
TABLE 30
- TPSC INDIRECT REGISTER MAP................................................................... 208
TABLE 31
- TPSC INDIRECT REGISTERS 20H-3FH: PCM DATA CONTROL BYTE......... 210
TABLE 32
- TPSC TRANSMIT DATA CONDITIONING ........................................................ 211
TABLE 33
- TRANSMIT TEST PATTERN MODES .............................................................. 211
TABLE 34
- TRANSMIT ZERO CODE SUPPRESSION FORMATS .................................... 212
TABLE 35
- TPSC INDIRECT REGISTERS 40H-5FH: IDLE CODE BYTE.......................... 213
TABLE 36
- TPSC INDIRECT REGISTERS 60H-7FH: SIGNALING/E1 CONTROL BYTE . 213
TABLE 37
- TRANSMIT PER-TIMESLOT DATA MANIPULATION....................................... 214
TABLE 38
- A-LAW DIGITAL MILLIWATT PATTERN ........................................................... 214
TABLE 39
- µ-LAW DIGITAL MILLIWATT PATTERN ........................................................... 215
TABLE 40
- RPSC INDIRECT REGISTER MAP .................................................................. 219
TABLE 41
- RPSC INDIRECT REGISTERS 20H-3FH: PCM DATA CONTROL BYTE ........ 221
TABLE 42
- RECEIVE TEST PATTERN MODES ................................................................. 221
TABLE 43
BYTE
- RPSC INDIRECT REGISTERS 40H-5FH: DATA TRUNK CONDITIONING CODE
222
TABLE 44
BYTE
- RPSC INDIRECT REGISTERS 61H-7FH: SIGNALING TRUNK CONDITIONING
223
TABLE 45
- NMNI SETTINGS .............................................................................................. 232
TABLE 46
- E1 SIGNALING INSERTION MODE ................................................................. 233
TABLE 47
- E1 TIMESLOT 0 BIT 1 INSERTION CONTROL SUMMARY ............................ 235
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
xi
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
TABLE 48
- NATIONAL BITS CODEWORD SELECT .......................................................... 243
TABLE 49
- G.704 CRC-4 MULTIFRAME ............................................................................. 244
TABLE 50
- EXAMPLE SA BIT PROGRAMMING ................................................................ 245
TABLE 51
- TIMESLOT 0 BIT POSITION ALLOCATION ..................................................... 260
TABLE 52
- SIGNALING MULTIFRAME TIMESLOT 16, FRAME 0 BIT POSITIONS.......... 263
TABLE 53
- E1-FRMR CODEWORD SELECT..................................................................... 265
TABLE 54
- RECEIVE PACKET BYTE STATUS................................................................... 294
TABLE 55
- CLOCK SYNTHESIS MODE ............................................................................. 299
TABLE 56
- ALOS DETECTION/CLEARANCE THRESHOLDS........................................... 320
TABLE 57
- BOUNDARY SCAN REGISTER ........................................................................ 329
TABLE 58
- DEFAULT SETTINGS........................................................................................ 331
TABLE 59
- ESF FRAME FORMAT ...................................................................................... 332
TABLE 60
- SF FRAME FORMAT ........................................................................................ 334
TABLE 61
- T1DM FRAME FORMAT ................................................................................... 335
TABLE 62
- E1 FRAME FORMAT......................................................................................... 336
TABLE 63
- PMON POLLING SEQUENCE .......................................................................... 337
TABLE 64
- ESF FDL PROCESSING ................................................................................... 338
TABLE 65:
- PMON COUNTER SATURATION LIMITS (E1 MODE)..................................... 339
TABLE 66:
- PMON COUNTER SATURATION LIMITS (T1 MODE) ..................................... 339
TABLE 67:
- PERFORMANCE REPORT MESSAGE STRUCTURE AND CONTENTS ....... 350
TABLE 68:
- PERFORMANCE REPORT MESSAGE STRUCTURE NOTES ....................... 351
TABLE 69:
- PERFORMANCE REPORT MESSAGE CONTENTS ....................................... 351
TABLE 70
- T1.102 TRANSMIT WAVEFORM VALUES FOR T1 LONG HAUL (LBO 0 DB):353
TABLE 71
- T1.102 TRANSMIT WAVEFORM VALUES FOR T1 LONG HAUL (LBO 7.5 DB):
354
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
xii
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
TABLE 72
- T1.102 TRANSMIT WAVEFORM VALUES FOR T1 LONG HAUL (LBO 15 DB):
355
TABLE 73
- T1.102 TRANSMIT WAVEFORM VALUES FOR T1 LONG HAUL (LBO 22.5 DB):
356
TABLE 74
- T1.102 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (0 - 110 FT.):
357
TABLE 75
220 FT.):
- T1.102 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (110 –
358
TABLE 76
330 FT.):
- T1.102 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (220 –
359
TABLE 77
440 FT.):
- T1.102 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (330 –
360
TABLE 78
550 FT.):
- T1.102 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (440 –
361
TABLE 79
660 FT.):
- T1.102 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (550 –
362
TABLE 80
- TR62411 TRANSMIT WAVEFORM VALUES FOR T1 LONG HAUL (LBO 0 DB):
363
TABLE 81
- TR62411 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (0 - 110 FT.):364
TABLE 82
220 FT.):
- TR62411 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (110 –
365
TABLE 83
330 FT.):
- TR62411 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (220 –
366
TABLE 84
440 FT.):
- TR62411 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (330 –
367
TABLE 85
550 FT.):
- TR62411 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (440 –
368
TABLE 86
660 FT.):
- TR62411 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (550 –
369
TABLE 87
- TRANSMIT WAVEFORM VALUES FOR E1 120 OHM:.................................... 370
TABLE 88
- TRANSMIT WAVEFORM VALUES FOR E1 75 OHM:...................................... 371
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
xiii
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
TABLE 89
- LINE RECEIVER CONFIGURATION REGISTERS .......................................... 372
TABLE 90
- LINE RECEIVER RAM PROGRAMMING REGISTERS ................................... 373
TABLE 91
- SEQUENCE TO FOLLOW RLPS RAM PROGRAMMING................................ 374
TABLE 92
- RLPS EQUALIZER RAM TABLE (T1 MODE) ................................................... 375
TABLE 93
- RLPS EQUALIZER RAM TABLE (E1 MODE) ................................................... 378
TABLE 94:
- DATA AND CAS T1 H-MVIP FORMAT .............................................................. 399
TABLE 95:
- DATA AND CAS E1 H-MVIP FORMAT .............................................................. 399
TABLE 96:
- CCS T1 H-MVIP FORMAT ................................................................................ 400
TABLE 97:
- CCS E1 H-MVIP FORMAT ................................................................................ 400
TABLE 98:
- ABSOLUTE MAXIMUM RATINGS .................................................................... 426
TABLE 99:
- D.C. CHARACTERISTICS ................................................................................ 427
TABLE 100:
- MICROPROCESSOR INTERFACE READ ACCESS........................................ 429
TABLE 101:
- MICROPROCESSOR INTERFACE WRITE ACCESS ...................................... 431
TABLE 102:
- RTSB TIMING ................................................................................................... 433
TABLE 103:
- XCLK INPUT (FIGURE 82) ............................................................................... 433
TABLE 104
- TRANSMIT BACKPLANE INTERFACE ............................................................ 434
TABLE 105
- RECEIVE BACKPLANE INTERFACE ............................................................... 437
TABLE 106:
- H-MVIP TRANSMIT TIMING (FIGURE 87) ....................................................... 440
TABLE 107:
- H-MVIP RECEIVE TIMING (FIGURE 88).......................................................... 441
TABLE 108:
- TRANSMIT LINE INTERFACE TIMING (FIGURE 89) ...................................... 441
TABLE 109:
- JTAG PORT INTERFACE ................................................................................. 442
TABLE 110:
- ORDERING INFORMATION ............................................................................. 445
TABLE 111:
- THERMAL INFORMATION................................................................................ 445
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
xiv
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
1
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
FEATURES
•
Monolithic device which integrates four, full-featured T1 and E1 framers and T1 and E1 short haul and
long haul line interfaces.
•
Software selectable between T1/J1 and E1 operation on a per-device basis.
•
Meets or exceeds T1 and E1 shorthaul and longhaul network access specifications including ANSI
T1.102, T1.403, T1.408, AT&T TR 62411, ITU-T G.703, G.704 as well as ETSI 300-011, CTR-4, CTR12 and CTR-13.
•
Provides encoding and decoding of B8ZS, HDB3 and AMI line codes.
•
Provides receive equalization, clock recovery and line performance monitoring.
•
Provides transmit and receive jitter attenuation.
•
Provides digitally programmable long haul and short haul line build out.
•
Provides four full-featured HDLC controllers, each with 128-byte transmit and receive FIFO buffers.
•
Automatically generates and transmits DS-1 performance report messages to ANSI T1.231 and ANSI
T1.408 specifications.
•
Supports Nx64Kbit/s fractional bandwidth backplane.
•
Supports transfer of PCM data to/from 1.544MHz and 2.048MHz system-side devices. Also supports
a fractional T1 or E1 system interface with independent backplane receive/backplane transmit
Nx64Kbit/s rates. Supports a 2.048 MHz system-side interface for T1 mode without external clock
gapping.
•
Supports 8.192 Mbit/s, H-100 compatible, H-MVIP on the system interface for all T1 or E1 links, a
separate 8.192 Mbit/s H-MVIP system interface for all T1 or E1 CAS channels and a separate 8.192
Mbit/s H-MVIP system interface for all T1 or E1 CCS, V5.1/V5.2, and GR.303 channels.
•
Provides a selectable, per channel independent de-jittered T1 or E1 recovered clock for system timing
and redundancy.
•
Provides PRBS generators and detectors on each tributary for error testing at DS1, E1 and Nx64Kbit/s
rates as recommended in ITU-T O.151 and O.152.
•
Provides robbed bit signaling extraction and insertion on a per-DS0 basis.
•
Register level compatibility with the PM4388 TOCTL Octal T1 Framer, the PM6388 EOCTL Octal E1
Framer, the PM4351 COMET E1/T1 transceiver, and the PM8315 TEMUX T1/E1 Framer with
integrated Mapper and M13 MUX.
•
Provides an 8-bit microprocessor bus interface for configuration, control, and status monitoring.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
1
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
•
Uses line rate system clock.
•
Provides an IEEE P1149.1 (JTAG) compliant test access port (TAP) and controller for boundary scan
test.
•
Implemented in a low power 5 V tolerant 2.5/3.3 V CMOS technology.
•
Available in a high density 208-pin fine pitch PBGA (17 mm by 17 mm) package.
•
Provides a -40°C to +85°C Industrial temperature operating range.
1.1
Receiver section:
1
•
Typical signal recovery of up to -43dB at 1024kHz (E1) and up to -44dB at 772kHz (T1/J1).
•
Guaranteed minimum signal recovery of -32dB at 1024kHz (E1) and -36dB at 772kHz (T1/J1).
•
Recovers clock and data using a digital phase locked loop for high jitter tolerance.
•
Frames to ITU-T G.704 basic and CRC-4 multiframe formatted E1 signals. The framing procedures
are consistent ITU-T G.706 specifications.
•
Frames to DSX/DS-1 signals in SF and ESF formats.
•
Frames to TTC JT-G704 multiframe formatted J1 signals. Supports the alternate CRC-6 calculation
for Japanese applications. Frames in the presence of and detects the “Japanese Yellow” alarm.
•
Tolerates more than 0.3 UI peak-to-peak, high frequency jitter as required by AT&T TR 62411 and
Bellcore TR-TSY-000170.
•
Detects violations of the ANSI T1.403 12.5% pulse density rule over a moving 192-bit window.
•
Provides loss of signal detection as per ITU-T G.775 and ANSI T1.231. Red, Yellow, and AIS alarm
detection and integration are according to ANSI T1.231 specifications.
•
Provides programmable in-band loopback activate and deactivate code detection.
•
Supports line and path performance monitoring according to AT&T and ANSI specifications.
Accumulators are provided for counting ESF CRC-6 errors, framing bit errors, line code violations and
loss of frame or change of frame alignment events.
•
Provides performance monitoring counters sufficiently large as to allow performance monitor counter
polling at a minimum rate of once per second. Optionally, updates the performance monitoring
counters and interrupts the microprocessor once per second, timed to the receive line.
1
1
Based on actual results using PIC-22 gauge cable emulation. Refer to the COMET-QUAD Evaluator
Board for design recommendations (PMC-1991237).
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
2
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
•
Provides ESF bit-oriented code detection and an HDLC/LAPD interface for terminating the ESF facility
data link.
•
Supports polled or interrupt-driven servicing of the HDLC interface.
•
Extracts the data link in ESF mode and extracts a datalink in the E1 national use bits.
•
Extracts 4-bit codewords from the E1 national use bits as specified in ETS 300 233
•
Extracts up to three HDLC links, to an H-MVIP Bus, to support the D-channel for ISDN Primary Rate
Interfaces and the C-channels for V5.1/V5.2 interfaces. Detects the V5.2 link identification signal.
•
Provides a two-frame elastic store buffer for backplane rate adaptation that performs controlled slips
and indicates slip occurrence and direction.
•
Provides DS-1 robbed bit signaling extraction, with optional data inversion, programmable idle code
substitution, digital milliwatt code substitution, bit fixing, and two superframes of signaling debounce
on a per-channel basis.
•
Frames to the E1 signaling multiframe alignment when enabled and extracts channel associated
signaling. Alternatively, a common channel signaling data link may be extracted from timeslot 16.
•
Indicates signaling state change, and two superframes of signaling debounce on a per-DS0 basis.
•
Provides trunk conditioning which forces programmable trouble code substitution and signaling
conditioning on all channels or on selected channels.
•
Provides diagnostic, line loopbacks and per-DS0 payload loopback.
•
A pseudo-random sequence user selectable from 2 –1, 2 –1 or 2 –1, may be detected in the
T1/E1 stream in either the backplane receive or backplane transmit directions. The detector counts
pattern errors using a 24-bit saturating PRBS error counter.
•
Provides four single-rail PCM and signaling data outputs for 1.544 Mbit/s or 2.048 Mbit/s backplane
buses.
1.2
11
15
20
Transmitter section:
•
Supports transfer of transmitted single rail PCM and signaling data from 1.544 Mbit/s and 2.048 Mbit/s
backplane buses.
•
Generates DSX-1 shorthaul and DS-1 longhaul pulses with programmable pulse shape compatible
with AT&T, ANSI and ITU requirements.
•
Generates E1 pulses compliant to G.703 recommendations.
•
Provides a digitally programmable pulse shape extending up to 5 transmitted bit periods for custom
long haul pulse shaping applications.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
3
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
•
Provides line outputs that are current limited and may be tristated for protection or in redundant
applications.
•
Provides a digital phase locked loop for generation of a low jitter transmit clock complying with all jitter
attenuation, jitter transfer and residual jitter specifications of AT&T TR 62411 and ETSI TBR 12 and
TBR 13.
•
Provides a FIFO buffer for jitter attenuation and rate conversion in the transmit path.
•
Provides a two-frame payload slip buffer to allow independent backplane and line timing.
•
A pseudo-random sequence user selectable from 2 –1, 2 –1 or2 –1, may be inserted into or
detected from the T1 or E1 stream in either the backplane receive or backplane transmit directions.
•
Transmits G.704 basic and CRC-4 multiframe formatted E1 signals or D4, SF or ESF formatted
DSX/DS-1 signals.
•
Transmits the “Japanese Yellow” alarm. Transmits TTC JT-G704 multiframe formatted J1 signals.
Supports the alternate ESF CRC-6 calculation for Japanese applications.
•
Supports unframed mode and framing bit, CRC, or data link by-pass.
•
Provides signaling insertion, programmable idle code substitution, digital milliwatt code substitution,
and data inversion on a per channel basis.
•
Provides trunk conditioning which forces programmable trouble code substitution and signaling
conditioning on all channels or on selected channels.
•
Provides minimum ones density through Bell (bit 7), GTE or DDS zero code suppression on a per
channel basis.
•
Detects violations of the ANSI T1.403 12.5% pulse density rule over a moving 192-bit window and
optionally stuffs ones to maintain minimum ones density.
•
Allows insertion of framed or unframed in-band loopback code sequences.
•
Allows insertion of a data link in ESF mode. Optionally inserts a datalink in the E1 national use bits.
•
Supports 4-bit codeword insertion in the E1 national use bits as specified in ETS 300 233
•
Inserts, from an H-MVIP bus, up to three HDLC links to support the D-channel for ISDN Primary Rate
Interfaces and the C-channels for V5.1/V5.2 interfaces.
•
Supports transmission of the alarm indication signal (AIS) and the Yellow alarm signal. Supports
“Japanese Yellow” alarm generation.
•
Provides ESF bit-oriented code generation.
11
15
20
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
4
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Synchronous System Interfaces:
•
Provides an 8.192 Mbit/s H-MVIP data interface for synchronous access to all the T1 DS0s or E1
timeslots. Compatible with H-MVIP PCM backplanes supporting 8.192 Mbit/s.
•
Provides an 8.192 Mbit/s H-MVIP interface for synchronous access to all channel associated signaling
(CAS) bits for all T1 DS0s or E1 timeslots. The CAS bits occupy one nibble of every byte on the HMVIP interfaces and are repeated over the entire T1 or E1 multi-frame.
•
Provides an 8.192 Mbit/s H-MVIP interface for common channel signaling (CCS) channels as well as
V5.1 and V5.2 channels. In T1 mode DS0 24 is available through this interface. In E1 mode timeslots
15, 16 and 31 are available through this interface.
•
All links accessed via the H-MVIP interface will be synchronously timed to the common H-MVIP clock
and frame alignment signals: CMV8MCLK, CMVFPB, CMVFPC
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
5
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
2
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
APPLICATIONS
•
Wireless Base Station, Transceiver or Digital Loop Carrier
•
DSLAM
•
Metro Optical Access Equipment
•
Voice Gateway
•
Enterprise Router
•
SONET/SDH Multiplexer
•
Channel and Data Service Units (CSU/DSU)
•
Digital Private Branch Exchanges (PBX)
•
Digital Access Cross-Connect Systems (DACS)
•
ISDN Primary Rate Interfaces (PRI)
•
Test Equipment
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
6
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
3
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
REFERENCES
1. ANSI - T1.101-1987 - American National Standard for Telecommunications - Digital Hierarchy
- Timing Synchronization.
2. ANSI - T1.102-1993 - American National Standard for Telecommunications - Digital Hierarchy
- Electrical Interfaces.
3. ANSI - T1.107-1995 - American National Standard for Telecommunications - Digital Hierarchy
- Formats Specification.
4. ANSI - T1.231-1993 - American National Standard for Telecommunications - Layer 1 InService Digital Transmission Performance Monitoring
5. ANSI - T1.403-1995 - American National Standard for Telecommunications - Carrier to
Customer Installation - DS-1 Metallic Interface Specification.
6. ANSI - T1.408-1990 - American National Standard for Telecommunications - Integrated
Services Digital Network (ISDN) Primary Rate - Customer Installation Metallic Interfaces
Layer 1 Specification.
7. T1M1.3/91-003R3 - American National Standard for Telecommunications - In-Service Digital
Transmission Performance Monitoring Draft Standard.
8. TA-TSY-000147 - Bell Communications Research - DS-1 Rate Digital Service Monitoring Unit
Functional Specification, Issue 1, October, 1987.
9. AT&T - PUB 54016 - Requirements For Interfacing Digital Terminal Equipment To Services
Employing The Extended Superframe Format, October 1984.
10. AT&T - TR 62411 - Accunet T1.5 - Service Description and Interface Specification,
December 1990.
11. AT&T - TR 62411 - Accunet T1.5 - Service Description and Interface Specification, Addendum
1, March 1991.
12. AT&T - TR 62411 - Accunet T1.5 - Service Description and Interface Specification, Addendum
2, October 1992.
13. AT&T - Interface Specification - Concentration Highway Interface - November 1990.
14. TR-TSY-000170 - Bellcore – Digital Cross-Connect System Requirements and Objectives,
Issue 1, November 1985.
15. TR-N1WT-000233 - Bell Communications Research - Wideband and Broadband Digital
Cross-Connect Systems Generic Criteria, Issue 3, November 1993.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
7
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
16. TR-NWT-000303 - Bell Communications Research - Integrated Digital Loop Carrier Generic
Requirements, Objectives, and Interface, Issue 2, December, 1992.
17. TR-TSY-000499 - Bell Communications Research - Transport Systems Generic
Requirements (TSGR): Common Requirement, Issue 5, December, 1993.
18. TR-TSY-000820 - Bell Communications Research - OTGR: Network Maintenance Transport
Surveillance - Generic Digital Transmission Surveillance, Section 5.1, Issue 1, June 1990.
19. ETSI - ETS 300 011 - ISDN Primary Rate User-Network Interface Specification and Test
Principles, 1992.
20. ETSI - ETS 300 233 - Access Digital Section for ISDN Primary Rates.
21. ETSI - ETS 300 324-1 - Signaling Protocols and Switching (SPS); V interfaces at the Digital
Local Exchange (LE) V5.1 Interface for the Support of Access Network (AN) Part 1: V5.1
Interface Specification, February 1994.
22. ETSI - ETS 300 347-1 - Signaling Protocols and Switching (SPS); V Interfaces at the Digital
Local Exchange (LE) V5.2 Interface for the Support of Access Network (AN) Part 1: V5.2
Interface Specification, September 1994.
23. ETSI - CTR 4 - Integrated Services Digital Network (ISDN); Attachment requirements for
terminal equipment to connect to an ISDN using ISDN primary rate access, November 1995.
24. ETSI - CTR 12 - Business Telecommunications (BT); Open Network Provision (ONP)
technical requirements; 2 048 kbit/s digital unstructured leased lines (D2048U) Attachment
requirements for terminal equipment interface, December 1993.
25. ETSI - CTR 13 - Business Telecommunications (BTC); 2 048 kbit/s digital structured leased
lines (D2048S); Attachment requirements for terminal equipment interface, January 1996.
26. FCC Rules - Part 68.308 - Signal Power Limitations.
27. ITU-T - Recommendation G.703 - Physical/Electrical Characteristics of Hierarchical Digital
Interface, Geneva, 1991.
28. ITU-T - Recommendation G.704 - Synchronous Frame Structures Used at Primary
Hierarchical Levels, July 1995.
29. ITU-T - Recommendation G.706 - Frame Alignment and CRC Procedures Relating to G.704
Frame Structures, 1991.
30. ITU-T - Recommendation G.732 – Characteristics of Primary PCM Multiplex Equipment
Operating at 2048 kbit/s, 1993.
31. ITU-T - Recommendation G.711 – Pulse Code Modulation (PCM) of Voice Frequencies, 1993.
32. ITU-T - Recommendation G.775 - Loss of Signal (LOS), November 1994.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
8
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
33. ITU-T Recommendation G.802, - Interworking Between Networks Based on Different Digital
Hierarchies and Speech Encoding Laws, 1993.
34. ITU-T Recommendation G.823, - The Control of Jitter and Wander Within Digital Networks
Which are Based on the 2048 kbit/s Hierarchy, 1993.
35. ITU-T Recommendation G.964, - V-Interfaces at the Digital Local Exchange (LE) - V5.1
Interface (Based on 2048 kbit/s) for the Support of Access Network (AN), June 1994.
36. ITU-T Recommendation G.965, - V-Interfaces at the Digital Local Exchange (LE) - V5.2
Interface (Based on 2048 kbit/s) for the Support of Access Network (AN), March 1995.
37. ITU-T - Recommendation I.431 - Primary Rate User-Network Interface – Layer 1
Specification, 1993.
38. ITU-T Recommendation O.151, - Error Performance Measuring Equipment For Digital
Systems at the Primary Bit Rate and Above, 1988.
39. ITU-T Recommendation O.152 - Error Performance Measuring Equipment for Bit Rates of 64
kbit/s and N X 64 kbit/s, October 1992
40. ITU-T Recommendation O.153 - Basic Parameters for the Measurement of Error
Performance at Bit Rates below the Primary Rate, October 1992.
41. ITU-T Recommendation Q.921 - ISDN User-Network Interface Data Link Layer Specification,
March 1993.
42. International Organization for Standardization, ISO 3309:1984 - High-Level Data Link Control
Procedures -- Frame Structure.
43. TTC Standard JT-G703 - Physical/Electrical Characteristics of Hierarchical Digital Interfaces,
1995.
44. TTC Standard JT-G704 - Frame Structures on Primary and Secondary Hierarchical Digital
Interfaces, 1995.
45. TTC Standard JT-G706 - Frame Synchronization and CRC Procedure
46. TTC Standard JT-I431 - ISDN Primary Rate User-Network Interface Layer 1 - Specification,
1995.
47. Nippon Telegraph and Telephone Corporation - Technical Reference for High-Speed Digital
Leased Circuit Services, Third Edition, 1990.
48. GO-MVIP - Multi-Vendor Integration Protocol, MVIP-90 Release 1.1, 1994.
49. GO-MVIP – H-MVIP Standard, Release 1.1a, 1997.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
9
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
4
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
APPLICATION EXAMPLE
Figure 1
- Wireless Base Station Application
Tx/Rx
RF
Subsystem
PM4351
COMET
DS3
or
Fibre Optics
PM8313
D3MX
or
PM5342
SPECTRA
Basestation
Switch
Fabric
Public
Switched
Telephone
Network
Software
Selectable
T1/E1/J1
Framer
T1/E1/J1
Longhaul/
Shorthaul
LIU
PM4351
COMET
PM4354 COMET-Quad
Intel or Motorola µP
CDMA/TDMA/GSM
PM4354 COMET-Quad
Base Transceiver Station
PM4354 COMET-Quad
●
●
●
PM4354 COMET-Quad
Base Station Controller
Figure 2
- V5.2 Interface Application
Linecard
Linecard
PM5342
SPECTRA
-155
PM5362
TUPP+
T1/E1/J1
Framer
Switch
Fabric
T1/E1/J1
LH/SH
LIU
PM4354 COMET-Quad
PM4354 COMET-Quad
Intel or
Motorola
µP
PM7364
FREEDM-32
V5.2
4 x E1
Bundle
T1/E1/J1
LH/SH
LIU
Switch
Fabric
T1/E1/J1
Framer
Linecard
PM4354 COMET-Quad
PM7364
FREEDM-32
µP
PM4354 COMET-Quad
Access Concentrator
PM4354 COMET-Quad
Central Office Switch
Subscribers
STM-1
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
●
●
●
●
●
●
10
XCLK
RLPS
Receive LIU
JTAG
Test Access
Port
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
RJAT
Digital Jitter
Attenuator
One of Four
T1 or E1
Tranceiver / Framers
CDRC
Clock and Data
Recovery
PMON
Performance
Monitor
Counters
T1/E1-FRMR
Frame
Alignment,
Alarm
Extraction
FRAM
Framer RAM
PDVD
Pulse Density
Violation
Detector
RBOC
Bit Oriented
Code Detector
RDLC
HDLC
Receiver
XBOC
Bit Oriented
Code
Generator
IBCD
Inband
Loopback
Code Detector
ALMI
Alarm
Integrator
T1-APRM
Auto
Performance
Response
Monitor
TDPR
HDLC
Transmitter
Rx-ELST
Receive
Elastic Store
SIGX
Signalling
Extractor
TPSC
Per-DS0
Controller
RPSC
Per-DSO
Controller
PRBS
Pattern
Generator/
Detector
BRIF
Backplane
Receive
System
Interface
MPIF
MicroProcessor
Interface
BTCLK[1:4]
CCSBRD/
MVBRD
BRPCM[1]/CASBRD
BRPCM[2:4]
BRSIG[1:4]
BRFP[1:4]
BRCLK[1:4]
CMV8MCLK
CMVFPC
CMVFPB
PIO
D[7:0]
INTB
RSTB
ALE
CSB
WRB
RDB
A[10:0]
MVBTD
CCSBTD
BTPCM[1]/CASBTD
BTPCM[2:4]
BTSIG[1:4]
BTFP[1:4]
ISSUE 6
RVREF[1:4]
RXRING[1:4]
RXTIP[1:4]
TDO
TDI
TCK
TMS
TRSTB
TOPS
Timing Options
CSD
Clock
Synthesis and
Distribution
XPDE
Pulse Density
Enforcer
BTIF
Backplane
Transmit
System
Interface
Figure 3
CTCLK
RSYNC
TJAT
Digital Jitter
Attenuator
Tx-ELST
Transmit
Elastic Store
5
TXCM[1:4]
XLPG
Transmit LIU
T1-XBAS/E1-TRAN
BasicTransmitter:
Frame Generation,
Alarm Insertion,
Signaling Insertion,
Trunk Conditioning
PMC-1990315
TXRING1[1:4]
TXRING2[1:4]
TXTIP1[1:4]
TXTIP2[1:4]
XIBC
Inband
Loopback
Code
Generator
RELEASED
PM4354 COMET-QUAD
DATASHEET
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
BLOCK DIAGRAM
- COMET-QUAD Block Diagram
11
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
6
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
DESCRIPTION
The PM4354 Four Channel Combined E1/T1/J1 Transceiver and Framer (COMET-QUAD) is a
feature-rich monolithic integrated circuit suitable for use in long haul and short haul T1, J1 and E1
systems with a minimum of external circuitry. The COMET-QUAD is software configurable,
allowing feature selection without changes to external wiring.
Analog circuitry is provided to allow direct reception of long haul E1 and T1/J1 compatible signals
typically with up to 43 dB cable loss at 1024 kHz (E1) and up to 44 dB cable loss at 772 kHz
(T1/J1) using a minimum of external components. Typically, only line protection, a transformer
and a line termination resistor are required.
The COMET-QUAD recovers clock and data from the line and frames to incoming data. In T1
mode, it can frame to SF and ESF signal formats. In E1 mode, the COMET-QUAD frames to
basic G.704 E1 signals and CRC-4 multiframe alignment signals, and automatically performs the
G.706 interworking procedure. AMI, HDB3 and B8ZS line codes are supported.
The COMET-QUAD supports detection of various alarm conditions such as loss of signal, pulse
density violation, Red alarm, Yellow alarm, and AIS alarm in T1 mode and loss of signal, loss of
frame, loss of signaling multiframe and loss of CRC multiframe in E1 mode. The COMET-QUAD
also supports reception of remote alarm signal, remote multiframe alarm signal, and alarm
indication signal in E1 mode. The presence of Yellow and AIS patterns in T1 mode and remote
alarm and AIS patterns in E1 mode is detected and indicated. In T1 mode, the COMET-QUAD
integrates Yellow, Red, and AIS alarms as per industry specifications. In E1 mode, the COMETQUAD integrates Red and AIS alarms.
Performance monitoring with accumulation of CRC-6 errors, framing bit errors, line code
violations, and loss of frame events are provided in T1 mode. In E1 mode, CRC-4 errors, far end
block errors, framing bit errors, and line code violation are monitored and accumulated.
The COMET-QUAD provides one receive HDLC controller per channel for the detection and
termination of messages in the ESF facility data link (T1), national use bits (E1), or in any arbitrary
timeslot (T1 or E1). In T1 mode, the COMET-QUAD also detects the presence of in-band loop
back codes and ESF bit oriented codes. Detection and optional debouncing of the 4-bit Sa-bit
codewords defined in ITU-T G.704 and ETSI 300-233 is supported. An interrupt may be
generated on any change of state of the Sa codewords.
Dual (transmit and receive) elastic stores for slip buffering and rate adaptation to backplane timing
are provided, as is a signaling extractor that supports signaling debounce, signaling freezing, idle
code substitution, digital milliwatt tone substitution, data inversion, and signaling bit fixing on a perchannel basis. Receive side data and signaling trunk conditioning is also provided.
In T1 mode, the COMET-QUAD generates framing for SF and ESF formats. In E1 mode, the
COMET-QUAD generates framing for a basic G.704 E1 signal. The signaling multiframe
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
12
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
alignment structure and the CRC multiframe structure may be optionally inserted. Framing can be
optionally disabled.
Internal analog circuitry allows direct transmission of long haul and short haul T1 and E1
compatible signals using a minimum of external components. Typically, only line protection, a
transformer and an optional line termination resistor are required. Digitally programmable pulse
shaping allows transmission of DSX-1 compatible signals up to 655 feet from the cross-connect,
E1 short haul pulses into 120 ohm twisted pair or 75 ohm coaxial cable, E1 long haul pulses into
120 ohm twisted pair as well as long haul DS-1 pulses into 100 ohm twisted pair with integrated
support for LBO filtering as required by the FCC rules. In addition, the programmable pulse shape
extending over 5-bit periods allows customization of short haul and long haul line interface circuits
to application requirements.
In the transmit path, the COMET-QUAD supports signaling insertion, idle code substitution, digital
milliwatt tone substitution, data inversion, and zero code suppression on a per-channel basis.
Zero code suppression may be configured to Bell (bit 7), GTE, or DDS standards, and can also be
disabled. Transmit side data and signaling trunk conditioning is also provided. Signaling bit
transparency from the backplane may be enabled.
The COMET-QUAD provides one transmit HDLC controller per channel. These controllers may
be used for the transmission of messages in the ESF data link (T1), national use bits (E1), or in
any timeslot (T1 or E1). In T1 mode, the COMET-QUAD can be configured to generate in-band
loop back codes and ESF bit oriented codes. In E1 mode, transmission of the 4-bit Sa codewords
defined in ITU-T G.704 and ETSI 300-233 is supported.
To provide for V5 applications where up to three HDLC channels are contained in each E1, the
COMET-QUAD provides a CCS H-MVIP interface. This interface allows the HDLC channels to be
inserted or extracted for external processing.
Each channel of the COMET-QUAD can generate a low jitter transmit clock from a variety of clock
references, and also provides jitter attenuation in the receive path. A low jitter recovered T1 clock
can be routed outside the COMET-QUAD for network timing applications.
Serial PCM interfaces to each T1/E1 framer allow 1.544 Mbit/s or 2.048 Mbit/s backplane
receive/backplane transmit system interfaces to be directly supported. Tolerance of gapped
clocks allows other backplane rates to be supported with a minimum of external logic.
For synchronous backplane systems, 8.192 Mbit/s H-MVIP interfaces are provided for access to
PCM data, channel associated signaling (CAS) and common channel signaling (CCS) for each T1
or E1. The CCS signaling H-MVIP interface is independent of the 64 Kbit/s PCM and CAS H-MVIP
access. The use of the H-MVIP interface requires that common clocks and frame pulse be used
along with T1/E1 elastic stores.
The COMET-QUAD is configured, controlled and monitored via a generic 8-bit microprocessor
bus through which all internal registers are accessed. All sources of interrupts can be masked
and acknowledged through the microprocessor interface.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
13
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
7
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
PIN DIAGRAM
The COMET-QUAD is packaged in a 208-pin PBGA package having a body size of 17mm by
17mm and a ball pitch of 1.0 mm. The center 16 balls are not used as signal I/Os and are thermal
balls.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
14
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Figure 4
- Pin Diagram
1
2
3
A
D (2)
D (1)
TXRING 1
(1)
B
D (3)
VSS33 (1)
D (0)
C
D (4)
D (5)
D
VSS33 (2)
D (6)
E
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
4
C ASBRD_B
BRCLK (1) BRSIG (1)
RPCM (1)
6
TAVD2 (1) TAVD3 (1) TAVD1 (1)
7
RXRING
(1)
8
9
10
VDD33 (2)
TXC M (1)
TAVS1 (1)
RXTIP (1)
TXRING 2
(1)
RAVS2 (1) RAVS1 (1)
11
12
Q AVD (1) RVREF (2)
RES (5)
Q AVS (1)
TXRING 2
(2)
TAVS2 (2)
RXRING
(2)
TAVD1 (2) TAVD3 (2)
RXTIP (2)
TAVS1 (2)
14
15
16
A (1)
A (3)
A (5)
A
A (0)
A (2)
A (4)
A (6)
B
TXRING 1
(2)
VSS33 (9)
A (7)
A (8)
C
RDB
A (10)
A (9)
D
ALE
WRB
C SB
E
INTB
BRCLK (2)
F
TXC M (2) TAVD2 (2)
208 PBGA
BRFP (1)
13
RVREF (1) RAVS1 (2) RAVD2 (2) TXTIP2 (2) TAVS3 (2) TXTIP1 (2)
TXTIP1 (1) TAVS3 (1) TXTIP2 (1) RAVD2 (1) RAVD1 (1) RAVD1 (2) RAVS2 (2)
VDD33 (1) TAVS2 (1)
D (7)
5
RSTB
F
C MVFPC
C MVFPB
BTCLK (1)
C ASBTD_B
TPCM (1)
G
VDDC 25
(1)
VSSC25
(1)
BTSIG (1)
VSSQ 33
(1)
G ND
G ND
G ND
G ND
VSSC 25
(5)
BRFP (2)
BRSIG (2) VDD33 (5)
G
H
VSSC 25
(2)
VDDQ 33
(1)
VDDC 25
(2)
BTFP (1)
G ND
G ND
G ND
G ND
BTPCM (2)
BTFP (2)
VDDC 25
(5)
BTC LK (2)
H
J
VDDC 25
(3)
VSS33 (3)
VSSC 25
(3)
RES[ 4]
G ND
G ND
G ND
G ND
XC LK
BTSIG (2)
RES[3]
VDDC25
(8)
J
K
MVBTD
C CSBTD
G ND
G ND
G ND
G ND
VSSQ 33
(2)
VDDQ 33
(2)
VDDC 25
(6)
VSSC25
(6)
K
L
VDDC 25
(4)
BTC LK (3)
VSSC 25
(4)
VSS33 (6)
RES[1]
VSSC 25
(7)
C TC LK
L
M
BTFP (3)
VSS33 (8)
BTSIG (3) BTPCM (3)
VDDC 25
(7)
BTC LK (4)
BTSIG (4) BTPCM (4)
M
BTFP (4)
VDD33 (6) BRPC M (4) BRCLK (4)
N
BRPC M (2) VSS33 (5)
C MV8MC
VDD33 (3)
LK
TOP VIEW
MVBRD_C
CSBRD
N
BRC LK (3) VDD33 (4)
RES[2]
TAVS2 (3)
TXRING 2
(3)
RAVS2 (3) RAVS1 (3)
C AVS
CAVD
RXTIP (4)
TAVS1 (4)
P
BRPC M (3) BRSIG (3)
TRSTB
TXTIP1 (3)
TXC M (3)
TAVS1 (3)
RES (6)
RVREF (4)
RXRING
(4)
TAVD1 (4) TAVD3 (4) TAVD2 (4) VSS33 (7)
TXRING 1
(3)
TAVS3 (3) TXTIP2 (3) RAVD2 (3) RAVD1 (3) RAVS1 (4) RAVS2 (4)
R
BRFP (3)
VSS33 (4)
TMS
T
TDO
TCK
TDI
1
2
3
TAVD2 (3) TAVD3 (3) TAVD1 (3)
4
5
6
RXTIP (3)
RXRING
(3)
7
TXRING 2
(4)
TXC M (4)
BRFP (4)
BRSIG (4)
P
TAVS2 (4) TXTIP1 (4) Q AVD (2)
PIO
RSYNC
R
TXRING 1
(4)
Q AVS (2)
RES (8)
RES (7)
T
13
14
15
16
RVREF (3) RAVD1 (4) RAVD2 (4) TXTIP2 (4) TAVS3 (4)
8
9
10
11
12
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
15
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
8
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
PIN DESCRIPTION
By convention, where a bus of four pins is present, the index indicates to which quadrant the pin
applies. With BRCLK[1:4], for example, BRCLK[1] applies to quadrant #1, BRCLK[2] applies to
quadrant #2, BRCLK[3] applies to quadrant #3, and BRCLK[4] applies to quadrant #4.
Pin Name
Type
Pin No. Function
T1 and E1 System Side Serial Clock and Data Interface
BRCLK[1]
BRCLK[2]
BRCLK[3]
BRCLK[4]
I/O
E2
F16
N1
N16
Backplane Receive Clocks (BRCLK[1:4]). The Backplane Receive Clock,
BRCLK[x], is used to update BRPCM[x] and BRSIG[x] and to either update or
sample BRFP[x], depending on the direction of BRFP[x]. The active edge of
BRCLK[x] for sampling/updating BRPCM[x], BRSIG[x], and BRFP[x] is
configurable.
In Receive Clock Master Mode, BRCLK[x] is configured as an output and can
be either a 1.544 MHz or 2.048 MHz clock derived from the recovered line
rate timing, with optional jitter attenuation.
When in Receive Clock Master: Nx64Kbit/s mode, BRCLK[x] is gapped
during the framing bit position (T1 mode only) and optionally for between 1
and 24 DS0 channels or 1 and 32 timeslots in the associated BRPCM[x]
stream.
When in Receive Clock Slave: Full T1/E1 mode, BRCLK[x] is configured as
an input and is either a 1.544MHz clock in T1 mode or a 2.048MHz clock in
T1 or E1 modes. BRCLK[x] is a nominal 1.544 or 2.048 MHz clock +/50ppm with a 50% duty cycle.
When in Receive Clock Slave: H-MVIP mode, BRCLK[x] is configured as an
input and is unused. In this mode, it is recommended that BRCLK[x] be
connected via an external resistor to ground.
After a reset, BRCLK[x] is configured as an input.
BRSIG[1]
BRSIG[2]
BRSIG[3]
BRSIG[4]
Output E3
G15
P2
P16
Backplane Receive Signaling (BRSIG[1:4]). Each BRSIG[x] contains the
extracted channel associated signaling bits for each channel in the frame,
repeated for the entire superframe. Each channel's associated signaling bits
are valid in bit locations 5,6,7,8 of the channel and are channel-aligned with
the BRPCM[x] data stream.
When in Receive Clock Slave: H-MVIP mode, BRSIG[x] is unused and driven
low.
BRSIG[x] is updated on the active edge of BRCLK[x].
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
16
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Pin Name
Type
Pin No. Function
BRFP[1]
BRFP[2]
BRFP[3]
BRFP[4]
I/O
E4
G14
R1
P15
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Backplane Receive Frame Pulse (BRFP[1:4]). When the Receive Clock
Master mode is active, BRFP[x] is configured as an output and indicates the
frame alignment or the superframe alignment of the backplane receive
stream, BRPCM[x]. BRFP[x] is updated on the active edge of BRCLK[x].
Receive Clock Master T1 mode:
If basic frame alignment is desired, BRFP[x] pulses high for one BRCLK[x]
cycle during bit 1 of each 193-bit frame. Optionally, BRFP[x] may pulse high
every second frame to ease the identification of data link bits. If superframe
alignment is desired, BRFP[x] pulses high for one BRCLK[x] cycle during bit
1 of frame 1 of every 12-frame or 24-frame superframe. Optionally, BRFP[x]
may pulse high every second superframe to ease the conversion between SF
and ESF.
Receive Clock Master E1 mode:
If basic frame alignment is desired, BRFP[x] pulses high for one BRCLK[x]
cycle during bit 1 of each 256-bit frame. Optionally, BRFP[x] may pulse high
every second frame to ease the identification of NFAS frames. If multiframe
alignment is desired, BRFP[x] transitions high to mark bit 1 of frame 1 of
every 16-frame signaling multiframe and transitions low following bit 1 of
frame 1 of every 16-frame CRC multiframe. Note that if the signaling and
CRC multiframe alignments are coincident, BRFP[x] pulses high for one
BRCLK[x] cycle every 16 frames.
Receive Clock Slave mode:
When the elastic store is enabled (and Clock Slave mode is active on the
backplane receive side), BRFP[x] is configured as an input and is used to
frame align the backplane receive data to the system frame alignment.
When frame alignment is required, a pulse at least 1 BRCLK[x] cycle wide
must be provided on BRFP[x] a maximum of once every frame (193 bit times
in T1, 256 bit times in E1). BRFP[x] is sampled on the active edge of
BRCLK[x].
When in the Receive Clock Master: Clear Channel or Receive Clock Slave:
H-MVIP mode, BRFP[x] is unused and it is recommended that BRFP[x] be
configured as an input and be connected via an external resistor to ground.
After a reset, BRFP[x] is configured as an input.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
17
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Pin Name
Type
BRPCM[1] /
CASBRD
BRPCM[2]
BRPCM[3]
BRPCM[4]
Output E1
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Pin No. Function
F13
P1
N15
Backplane Receive Data (BRPCM[1:4]). Each BRPCM[x] signal contains
the recovered data stream that may have been passed through the elastic
store.
When a Clock Slave backplane receive mode is active, the BRPCM[x]
stream has passed through the elastic store and is aligned to the backplane
receive timing.
When in T1 Receive Clock Slave mode with BRCLK[x] configured as a
2.048MHz clock, the mapping of the BRPCM[x] data stream is configurable.
In Receive Clock Slave: H-MVIP mode, BRPCM[2], BRPCM[3], and
BRPCM[4] are unused and driven low. BRPCM[1] shares the same pin as the
H-MVIP CAS signal CASBRD. In Receive Clock Slave: H-MVIP mode, the
output becomes CASBRD. Out of reset, this output defaults to BRPCM[1].
When in Receive Clock Master: Clear Channel mode, the unframed
backplane receive data appears on BRPCM[x] with no frame alignment or
signaling.
BRPCM[x] is updated on the active edge of BRCLK[x].
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
18
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Pin Name
Type
Pin No. Function
BTCLK[1]
BTCLK[2]
BTCLK[3]
BTCLK[4]
I/O
F3
H16
L2
M14
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Backplane Transmit Clock (BTCLK[1:4]). The active edge of the
Backplane Transmit Clock, BTCLK[x], is used to sample the associated
BTSIG[x] and BTPCM[x], and is used to update BTFP[x]. The active edge is
configured in the BTIF Configuration register.
When a Transmit Clock Master mode is active, BTCLK[x] is an output and is
a version of the transmit clock[x] which is generated from the receive
recovered clock or the common transmit clock, CTCLK.
When in T1 Transmit Clock Master: Nx64Kbit/s mode, BTCLK[x] is gapped
during the framing bit position and optionally for between 1 and 23 DS0
channels in the associated BTPCM[x] stream. When in E1 Transmit Clock
Master: Nx64Kbit/s mode, BTCLK[x] is gapped for between 1 and 31 channel
timeslots in the associated BTPCM[x] stream.
When in Transmit Clock Master: Clear Channel mode, the unframed
backplane transmit data is sampled on BTPCM[x] with no frame alignment or
signaling.
When in a Transmit Clock Slave mode, BTCLK[x] is configured as an input
and is used to time the backplane transmit interface. BTCLK[x] is either a
1.544MHz clock in T1 mode or a 2.048MHz clock in T1 or E1 modes.
BTCLK[x] is a nominal 1.544 or 2.048 MHz clock +/- 50ppm with a 50% duty
cycle.
When in Transmit Clock Slave: H-MVIP mode, BTCLK[x] is configured as an
input and is unused. In this mode, it is recommended that BTCLK[x] be
connected via an external resistor to ground.
After a reset, BTCLK[x] is configured as an input.
BTSIG[1]
BTSIG[2]
BTSIG[3]
BTSIG[4]
Input
G3
J14
M3
M15
Backplane Transmit Signaling (BTSIG[1:4]). The BTSIG[x] input carries
the signaling bits for each channel in the transmit data frame, repeated for
the entire superframe. Each channel's signaling bits are in bit locations
5,6,7,8 of the channel and are channel-aligned with the BTPCM[x] data
stream. When in Transmit Clock Slave: H-MVIP mode, BTSIG[x] is unused.
BTSIG[x] is sampled on the active edge of BTCLK[x].
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
19
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Pin Name
Type
Pin No. Function
BTFP[1]
BTFP[2]
BTFP[3]
BTFP[4]
I/O
H4
H14
M1
N13
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Backplane Transmit Frame Pulse (BTFP[1:4]). When BTFP[x] is
configured as an input, and may be used to frame align the transmitters to
the system backplane.
T1 mode:
If only frame alignment is required, a pulse at least one BTCLK[x] cycle wide
must be provided on BTFP[x] at multiples of 193 bit periods. If superframe
alignment is required, transmit superframe alignment must be enabled, and
BTFP[x] must be brought high for at least one BTCLK[x] cycle to mark bit 1
of frame 1 of every 12-frame or 24-frame superframe.
E1 mode:
If basic frame alignment only is required, a pulse at least one BTCLK[x] cycle
wide must be provided on BTFP[x] at multiples of 256 bit periods. If
multiframe alignment is required, transmit multiframe alignment must be
enabled, and BTFP[x] must be brought high to mark bit 1 of frame 1 of every
16-frame signaling multiframe and brought low following bit 1 of frame 1 of
every 16-frame CRC multiframe. This mode allows both multiframe
alignments to be independently controlled using the single BTFP[x] signal.
Note that if the signaling and CRC multiframe alignments are coincident,
BTFP[x] must pulse high for one BTCLK[x] cycle every 16 frames.
When BTFP[x] is configured as an output (only valid when the transmit
backplane clock rate is no greater than 2.048 MHz), transmit frame
alignment is derived internally, and BTFP[x] is updated on the active edge of
BTCLK[x]. BTFP[x] pulses high for one cycle to indicate the first bit of each
frame or multiframe, as optioned.
When in Transmit Clock Slave: H-MVIP mode, BTFP[x] is configured as an
input and is unused. In this mode, it is recommended that BTFP[x] be
connected via an external resistor to ground.
After a reset, BTFP[x] is configured as an input.
BTPCM[1] /
CASBTD
BTPCM[2]
BTPCM[3]
BTPCM[4]
Input
F4
H13
M4
M16
Backplane Transmit Data (BTPCM[1:4]). The non-return to zero, digital
backplane transmit data streams to be transmitted are input on these pins.
BTPCM[x] may present a 1.544 Mbit/s, 2.048 Mbit/s or sub-rate Nx64Kbit/s
data stream. BTPCM[x] is sampled on the active edge of BTCLK[x].
BTPCM[2:4] are unused in Transmit Clock Slave: H-MVIP mode. BTPCM[1]
shares the same pin as the Transmit Clock Slave: H-MVIP Channel
Associated Signaling pin, CASBTD. By default this input is BTPCM[1].
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
20
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
Pin Name
ISSUE 6
Type
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Pin No. Function
MVIP System Side Interfaces
MVBTD
Input
K1
MVIP Backplane Transmit Data (MVBTD). In Transmit Clock Slave: HMVIP mode, the 8.192 Mbit/s backplane transmit data streams to be
transmitted are input on MVBTD. MVBTD carries the channels of four
complete T1’s or E1’s formatted according to the H-MVIP standard. MVBTD
carries the backplane transmit data equivalent to BTPCM[1:4].
MVBTD is aligned to the common H-MVIP 16.384 MHz clock, CMV8MCLK,
the 4.096 MHz frame pulse clock, CMVFPC, and frame pulse, CMVFPB.
MVBTD is sampled on every second rising edge of CMV8MCLK as fixed by
the common H-MVIP frame pulse clock, CMVFPC.
When not in Transmit Clock Slave: H-MVIP mode, MVBTD is unused.
CASBTD /
BTPCM[1]
Input
F4
Channel Associated Signaling Backplane Transmit Data (CASBTD).
CASBTD carries the Channel Associated Signaling (CAS) stream to be
transmitted in the T1 DS0s or E1 timeslots. CASBTD carries CAS for four
complete T1’s or E1’s formatted according to the H-MVIP standard. CASBTD
carries the backplane transmit signaling equivalent to BTSIG[1:4]. CASBTD
carries the corresponding CAS values of the channel data carried in MVBTD.
CASBTD is aligned to the common H-MVIP 16.384MHz clock, CMV8MCLK,
the 4.096 MHz frame pulse clock, CMVFPC, and frame pulse, CMVFPB.
CASBTD is sampled on every second rising edge of CMV8MCLK as fixed by
the common H-MVIP frame pulse clock, CMVFPC.
CASBTD shares the same pin as BTPCM[1]. In Transmit Clock Slave: HMVIP Mode, this input is CASBTD. In all other Transmit modes, this input is
BTPCM[1].
CCSBTD
Input
K2
Common Channel Signaling Backplane Transmit Data (CCSBTD). In T1
mode, CCSBTD carries the common channel signaling to be transmitted in
timeslot 24 of each of the 4 T1’s. In E1 mode, CCSBTD carries up to 3
timeslots (15,16, 31) to be transmitted in each of the 4 E1’s. CCSBTD is
formatted according to the H-MVIP standard.
CCSBTD is aligned to the common H-MVIP 16.384 MHz clock, CMV8MCLK,
the 4.096 MHz frame pulse clock, CMVFPC, and frame pulse, CMVFPB.
CCSBTD is sampled on every second rising edge of CMV8MCLK as fixed by
the common H-MVIP frame pulse clock, CMVFPC.
CCSBTD can be optionally enabled in either Transmit Clock Slave: Full
T1/E1 mode or Transmit Clock Slave: H-MVIP mode. In other modes,
CCSBTD is unused.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
21
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
Pin Name
ISSUE 6
Type
CMV8MCLK Input
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Pin No. Function
K3
Common 8M H-MVIP Clock (CMV8MCLK). The Common 8.192 Mbit/s HMVIP Data Clock, CMV8MCLK, provides the data clock for receive and
transmit links configured for operation in 8.192 Mbit/s H-MVIP mode.
CMV8MCLK is used to sample data on MVBRD, MVBTD, CASBRD,
CASBTD, CCSBRD and CCSBTD. CMV8MCLK is nominally a 50% duty
cycle clock with a frequency of 16.384 MHz.
The Transmitter and Receiver streams are independently enabled for HMVIP access. When enabled, all four Transmitter (or Receiver) streams are
enabled for H-MVIP access. When both the Transmitter and the Receiver HMVIP accesses are disabled, CMV8MCLK is unused.
CMVFPB
Input
F2
Common H-MVIP Frame Pulse (CMVFPB). The active low Common HMVIP Frame Pulse, CMVFPB, for 8.192 Mbit/s H-MVIP signals references
the beginning of each frame for interfaces operating in 8.192 Mbit/s H-MVIP
mode.
The CMVFPB frame pulse occurs every 125us and is sampled on the falling
edge of CMVFPC.
The Transmitter and Receiver interfaces are independently enabled for HMVIP access. When enabled, all four Transmitter (or Receiver) streams are
enabled for H-MVIP access. When both the Transmitter and the Receiver HMVIP accesses are disabled, CMVFPB is unused.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
22
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Pin Name
Type
MVBRD /
Output L4
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Pin No. Function
H-MVIP Backplane Receive Data (MVBRD). MVBRD carries the recovered
T1 or E1 channels that have passed through the elastic store. Each MVBRD
signal carries the channels of four complete T1’s or E1’s. MVBRD carries the
T1 or E1 data equivalent to BRPCM[1:4].
MVBRD is aligned to the common H-MVIP 16.384 MHz clock, CMV8MCLK,
frame pulse clock, CMVFPC, and frame pulse, CMVFPB. MVBRD is updated
on every second rising edge of the common H-MVIP 16.384 MHz clock,
CMV8MCLK, as fixed by the common H-MVIP frame pulse clock, CMVFPC.
CCSBRD
Common Channel Signaling Backplane Receive Data (CCSBRD). In T1
mode, CCSBRD carries the Common Channel Signaling (CCS) channels
extracted from each of the 4 T1’s. In E1 mode, CCSBRD carries up to 3
timeslots (15,16, 31) from each of the 4 E1’s. CCSBRD is formatted
according to the H-MVIP standard.
CCSBRD is aligned to the common H-MVIP 16.384 MHz clock, CMV8MCLK,
the 4.096 MHz frame pulse clock, CMVFPC, and frame pulse, CMVFPB.
CCSBRD is updated on every second rising edge of CMV8MCLK as fixed by
the common H-MVIP frame pulse clock, CMVFPC.
CCSBRD shares the same pin as MVBRD. In Receive Clock Slave: H-MVIP
mode, this output is MVBRD. In Receive Clock Slave: Full T1/E1 mode,
CCSBRD can be optionally enabled. In all other modes, this output is unused
and driven low.
CASBRD /
BRPCM[1]
Output E1
Channel Associated Signaling Backplane Receive Data (CASBRD).
CASBRD carries the Channel Associated Signaling (CAS) stream extracted
from all the T1 or E1 channels. CASBRD carries CAS for four complete T1’s
or E1’s. CASBRD carries the T1 or E1 signaling equivalent to BRSIG[1:4].
CASBRD carries the corresponding CAS values of the channel carried in
MVBRD.
CASBRD is aligned to the common H-MVIP 16.384 MHz clock, CMV8MCLK,
the 4.096 MHz frame pulse clock, CMVFPC, and frame pulse, CMVFPB.
CASBRD is updated on every second rising edge of CMV8MCLK as fixed by
the common H-MVIP frame pulse clock, CMVFPC.
CASBRD shares the same pin as BRPCM[1]. In Receive Clock Slave: HMVIP mode, this output is CASBRD. In all other modes, this output is
BRPCM[1]. By default this output is BRPCM[1].
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
23
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Pin Name
Type
Pin No. Function
CMVFPC
Input
F1
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Common H-MVIP Frame Pulse Clock (CMVFPC). The common H-MVIP
frame pulse clock provides the frame pulse clock for operation with 8.192
Mbit/s H-MVIP access.
CMVFPC is used to sample CMVFPB. CMVFPC is nominally a 50% duty
cycle clock with a frequency of 4.096 MHz. The falling edge of CMVFPC
must be aligned with the falling edge of CMV8MCLK with no more than
±10ns skew.
The Transmitter and Receiver streams are independently enabled for HMVIP access. When H-MVIP access is enabled, all four Transmitter (or
Receiver) streams are enabled for H-MVIP access. When both the
Transmitter and the Receiver H-MVIP accesses are disabled, CMVFPC is
unused.
Transmit Line Interface
TXTIP1[1]
TXTIP1[2]
TXTIP1[3]
TXTIP1[4]
Analog B4
Output A13
P4
R13
TXTIP2[1]
TXTIP2[2]
TXTIP2[3]
TXTIP2[4]
B6
A11
R6
T11
TXRING1[1] Analog A3
TXRING1[2] Output C13
TXRING1[3]
R4
TXRING1[4]
T13
TXRING2[1]
TXRING2[2]
TXRING2[3]
TXRING2[4]
D5
B11
N5
R11
Transmit Analog Positive Pulse (TXTIP1[1:4] and TXTIP2[1:4]). When
the transmit analog line interface is enabled, the TXTIP1[x] and TXTIP2[x]
analog outputs drive the transmit line pulse signal through an external
matching transformer. Both TXTIP1[x] and TXTIP2[x] are normally
connected to the positive lead of the transformer primary. Two outputs are
provided for better signal integrity and must be shorted together on the
board.
After a reset, TXTIP1[x] and TXTIP2[x] are high impedance. The HIGHZ bit
of the quadrant’s XLPG Line Driver Configuration register (addresses 0F0H,
1F0H, 2F0H, 3F0H) must be programmed to logic 0 to remove the high
impedance state.
Transmit Analog Negative Pulse (TXRING1[1:4] and TXRING2[1:4]).
When the transmit analog line interface is enabled, the TXRING1[x] and
TXRING2[x] analog outputs drive the transmit line pulse signal through an
external matching transformer. Both TXRING1[x] and TXRING2[x] are
normally connected to the negative lead of the transformer primary. Two
outputs are provided for better signal integrity and must be shorted together
on the board.
After a reset, TXRING1[x] and TXRING2[x] are high impedance. The HIGHZ
bit of the quadrant’s XLPG Line Driver Configuration register (addresses
0F0H, 1F0H, 2F0H, 3F0H) must be programmed to logic 0 to remove the
high impedance state.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
24
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Pin Name
Type
TXCM[1]
TXCM[2]
TXCM[3]
TXCM[4]
Analog C5
I/O
D12
P5
N12
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Pin No. Function
Transmit Common Mode (TXCM[1:4]). This pin is the common mode for
the Transmit analog. It requires a 4.7µF capacitor to analog ground and two
12.7Ω resistors to the corresponding TXRING and TXTIP.
Receive Line Interface
RXTIP[1]
RXTIP[2]
RXTIP[3]
RXTIP[4]
Analog C7
Input D10
P7
N10
Receive Analog Positive Pulse (RXTIP[1:4]). When the analog receive
line interface is enabled, RXTIP[x] samples the received line pulse signal
from an external isolation transformer. RXTIP[x] is normally connected
directly to the positive lead of the receive transformer secondary.
RVREF[1]
RVREF[2]
RVREF[3]
RVREF[4]
Analog A8
I/O
C9
T8
P9
Receive Voltage Reference (RVREF[1:4]). This pin must be connected to
an external RC network consisting of a 100 kΩ resistor connected in parallel
with a 10 nF capacitor to analog ground.
RXRING[1]
RXRING[2]
RXRING[3]
RXRING[4]
Analog A7
Input C10
T7
P10
Receive Analog Negative Pulse (RXRING[1:4]). When the analog receive
line interface is enabled, RXRING[x] samples the received line pulse signal
from an external isolation transformer. RXRING[x] is normally connected
directly to the negative lead of the receive transformer secondary.
Timing Options Control
XCLK
Input
J13
Crystal Clock Input (XCLK). This signal provides a stable, global timing
reference for the COMET-QUAD internal circuitry via an internal clock
synthesizer. XCLK is a nominally jitter free clock at 1.544 MHz in T1 mode
and 2.048 MHz in E1 mode.
In T1 mode, a 2.048 MHz clock may be used as a reference. When used in
this way, however, the intrinsic jitter specifications to AT&T TR62411 may not
be met.
CTCLK
Input
L16
Common Transmit Clock (CTCLK). This input signal can be used as a
reference for the transmit line rate generation. CTCLK may be any multiple of
8 kHz (N x 8 kHz, where 1≤N≤256) so long as CTCLK has minimal jitter
when divided down to 8 kHz. When the CTCLK frequency differs from the
transmit line rate, the transmit jitter attenuation block (TJAT) must be enabled
to synthesize and jitter attenuate the transmit clock. When the CTCLK
frequency is the same as the transmit line rate, CTCLK is optionally jitter
attenuated by the TJAT. When CTCLK jitter attenuation is enabled, the
CTCLK frequency should be programmed into the TJAT Jitter Attenuation
Divider N1 Control register.
The COMET-QUAD may be configured to ignore the CTCLK input and utilize
the Receive recovered clock or the backplane transmit clock.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
25
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Pin Name
Type
RSYNC
Output R16
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Pin No. Function
Recovered Clock Synchronization Signal (RSYNC). This output signal is
the jitter attenuated recovered receiver line rate clock (1.544 or 2.048 MHz)
of one of the four T1 or E1 channels or, optionally, the jitter attenuated
recovered clock synchronously divided by 193 (T1 mode) or 256 (E1 mode)
to create a 8 kHz timing reference signal. When 8 kHz, the RSYNC phase is
independent of frame alignment and is not affected by framing events. The
default is to source RSYNC from quadrant #1. The RJATBYP register bit has
no effect on RSYNC.
When the COMET-QUAD is in a loss of signal state, RSYNC is derived from
the XCLK input or, optionally, is held high.
PIO
I/O
R15
RES[1]
RES[2]
RES[3]
RES[4]
RES[8]
Output L14
N3
J15
J4
T15
RES[5]
RES[6]
Analog D8
I/O
P8
RES[7]
Input
T16
Programmable I/O (PIO). PIO is an input/output pin controlled by a
COMET-QUAD register bit. When configured as an output, the PIO pin can,
under software control, be used to configure external circuitry. When
configured as an input, a COMET-QUAD register bit reflects the state of the
PIO pin.
Reserved (RES[1:4], RES[8]). Reserved.
These pins must be left unconnected.
Reserved (RES[5:6]). Reserved.
These pins must be connected to an analog ground.
Reserved (RES[7]). Reserved.
This pin must be tied low.
ATB[1]
ATB[2]
Analog D8
I/O
P8
Analog Test Bus (ATB[1:2]). Reserved for COMET-QUAD production test.
This pin must be connected to an analog ground for normal operation.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
26
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
Pin Name
ISSUE 6
Type
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Pin No. Function
Microprocessor Interface
A[0]
A[1]
A[2]
A[3]
A[4]
A[5]
A[6]
A[7]
A[8]
A[9]
A[10]
Input
B13
A14
B14
A15
B15
A16
B16
C15
C16
D16
D15
Address Bus (A[10:0]). This bus selects specific registers during COMETQUAD register accesses.
RDB
Input
D14
Active Low Read Enable (RDB). This signal is low during COMET-QUAD
register read accesses. The COMET-QUAD drives the D[7:0] bus with the
contents of the addressed register while RDB and CSB are low.
WRB
Input
E15
Active Low Write Strobe (WRB). This signal is low during a COMET-QUAD
register write access. The D[7:0] bus contents are clocked into the
addressed register on the rising WRB edge while CSB is low.
CSB
Input
E16
Active Low Chip Select (CSB). CSB must be low to enable COMET-QUAD
register accesses. CSB must go high at least once after power up to clear
internal test modes. If CSB is not used, it should be tied to an inverted
version of RSTB, in which case, RDB and WRB determine register
accesses. To ensure normal operation, the RSTB pin should be driven low
and the CSB pin driven high concurrently following power up.
ALE
Input
E14
Address Latch Enable (ALE). This signal is active high and latches the
address bus contents, A[10:0], when low. When ALE is high, the internal
address latches are transparent. ALE allows the COMET-QUAD to interface
to a multiplexed address/data bus. The ALE input has an internal pull up
resistor.
INTB
Output F15
Active low Open-Drain Interrupt (INTB). This signal goes low when an
unmasked interrupt event is detected on any of the internal interrupt sources.
Note that INTB will remain low until all active, unmasked interrupt sources
are acknowledged at their source at which time, INTB will tristate.
OD
RSTB
Input
E13
Active Low Reset (RSTB). This signal provides an asynchronous COMETQUAD reset. RSTB is a Schmidt triggered input with an internal pull up
resistor.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
27
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Pin Name
Type
Pin No. Function
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
I/O
B3
A2
A1
B1
C1
C2
D2
D3
Bidirectional Data Bus (D[7:0]). This bus provides COMET-QUAD register
read and write accesses.
TDO
Output T1
Test Data Output (TDO). This signal carries test data out of the COMETQUAD via the IEEE P1149.1 test access port. TDO is updated on the falling
edge of TCK. TDO is a tri-state output that is tri-stated except when
scanning of data is in progress.
TDI
Input
T3
Test Data Input (TDI). This signal carries test data into the COMET-QUAD
via the IEEE P1149.1 test access port. TDI is sampled on the rising edge of
TCK. TDI has an internal pull up resistor.
TCK
Input
T2
Test Clock (TCK). This signal provides timing for test operations that can be
carried out using the IEEE P1149.1 test access port.
TMS
Input
R3
Test Mode Select (TMS). This signal controls the test operations that can be
carried out using the IEEE P1149.1 test access port. TMS is sampled on the
rising edge of TCK. TMS has an internal pull up resistor.
TRSTB
Input
P3
Active low Test Reset (TRSTB). This signal provides an asynchronous
COMET-QUAD test access port reset via the IEEE P1149.1 test access port.
TRSTB is a Schmidt triggered input with an internal pull up resistor. TRSTB
must be asserted during the power up sequence.
JTAG Interface
Note that if not used, TRSTB must be connected to the RSTB input.
Analog Power and Ground Pins
TAVD1[1]
TAVD1[2]
TAVD1[3]
TAVD1[4]
Analog A6
Power C11
T6
P11
Transmit Analog Power (TAVD1[1:4]). TAVD1[1:4] provides power for the
transmit LIU reference circuitry. TAVD1[1:4] should be connected to analog
+3.3 V.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
28
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Pin Name
Type
TAVD2[1]
TAVD2[2]
TAVD2[3]
TAVD2[4]
Analog A4
Power D13
T4
P13
TAVD3[1]
TAVD3[2]
TAVD3[3]
TAVD3[4]
A5
C12
T5
P12
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Pin No. Function
Transmit Analog Power (TAVD2[1:4], TAVD3[1:4]). TAVD2[1:4] and
TAVD3[1:4] supply power for the transmit LIU output drivers. TAVD2[1:4] and
TAVD3[1:4] should be connected to analog +3.3 V.
CAVD
Analog N9
Power
Clock Synthesis Unit Analog Power (CAVD). CAVD supplies power for the
transmit clock synthesis unit. CAVD should be connected to analog +3.3 V.
TAVS1[1]
TAVS1[2]
TAVS1[3]
TAVS1[4]
Analog C6
Ground D11
P6
N11
Transmit Analog Ground (TAVS1[1:4]). TAVS1[1:4] provides ground for the
transmit LIU reference circuitry. TAVS1[1:4] should be connected to analog
GND.
TAVS2[1]
TAVS2[2]
TAVS2[3]
TAVS2[4]
Analog C4
Ground B12
N4
R12
Transmit Analog Ground (TAVS2[1:4], TAVS3[1:4]). TAVS2[1:4] and
TAVS3[1:4] supply ground for the transmit LIU output drivers. TAVS2[1:4]
and TAVS3[1:4] should be connected to analog GND.
TAVS3[1]
TAVS3[2]
TAVS3[3]
TAVS3[4]
B5
A12
R5
T12
CAVS
Analog N8
Ground
Clock Synthesis Unit Analog Ground (CAVS). CAVS supplies ground for
the transmit clock synthesis unit. CAVS should be connected to analog
GND.
RAVD1[1]
RAVD1[2]
RAVD1[3]
RAVD1[4]
Analog B8
Power B9
R8
T9
Receive Analog Power (RAVD1[1:4]). RAVD1[1:4] supplies power for the
receive LIU input equalizer. RAVD1[1:4] should be connected to analog
+3.3 V.
RAVD2[1]
RAVD2[2]
RAVD2[3]
RAVD2[4]
Analog B7
Power A10
R7
T10
Receive Analog Power (RAVD2[1:4]). RAVD2[1:4] supplies power for the
receive LIU peak detect and slicer. RAVD2[1:4] should be connected to
analog +3.3 V.
RAVS1[1]
RAVS1[2]
RAVS1[3]
RAVS1[4]
Analog D7
Ground A9
N7
R9
Receive Analog Ground (RAVS1[1:4]). RAVS1[1:4] supplies ground for the
receive LIU input equalizer. RAVS1[1:4] should be connected to analog
GND.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
29
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Pin Name
Type
Pin No. Function
RAVS2[1]
RAVS2[2]
RAVS2[3]
RAVS2[4]
Analog D6
Ground B10
N6
R10
Receive Analog Ground (RAVS2[1:4]). RAVS2[1:4] supplies ground for the
receive LIU peak detect and slicer. RAVS2[1:4] should be connected to
analog GND.
QAVD[1]
QAVD[2]
Analog C8
Power R14
Quiet Analog Power (QAVD[1:2]). QAVD[1:2] supplies power for the core
analog circuitry. QAVD[x] should be connected to analog +3.3 V.
QAVS[1]
QAVS[2]
Analog D9
Ground T14
Quiet Analog Ground (QAVS[1:2]). QAVS[1:2] supplies ground for the core
analog circuitry. QAVS[x] should be connected to analog GND.
Digital Power and Ground Pins
VDDC25[1]
VDDC25[2]
VDDC25[3]
VDDC25[4]
VDDC25[5]
VDDC25[6]
VDDC25[7]
VDDC25[8]
Power G1
H3
J1
L1
H15
K15
M13
J16
Core Power (VDDC25[1:8]). The VDDC25[1:8] pins should be connected to
a well decoupled +2.5V DC power supply.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
30
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Pin Name
Type
VSSC25[1]
VSSC25[2]
VSSC25[3]
VSSC25[4]
VSSC25[5]
VSSC25[6]
VSSC25[7]
Ground G2
H1
J3
L3
G13
K16
L15
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Pin No. Function
Core Ground (VSSC25[1:7]). The VSSC25[1:7] pins should be connected
to GND. The 16 thermal balls should also be connected to GND.
G7
G8
G9
G10
H7
H8
H9
H10
J7
J8
J9
J10
K7
K8
K9
K10
VDDQ33[1]
VDDQ33[2]
Power H2
K14
Quiet Power (VDDQ33[1:2]). The VDDQ33[1:2] pins should be connected
to a well decoupled +3.3V DC power supply.
VSSQ33[1]
VSSQ33[2]
Ground G4
K13
Quiet Ground (VSSQ33[1:2]). The VSSQ33[1:2] pins should be connected
to GND.
VDD33[1]
VDD33[2]
VDD33[3]
VDD33[4]
VDD33[5]
VDD33[6]
Power C3
D4
K4
N2
G16
N14
Switching Power (VDD33[1:6]). The VDD33[1:6] pins should be connected
to a well decoupled +3.3V DC power supply.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
31
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Pin Name
Type
VSS33[1]
VSS33[2]
VSS33[3]
VSS33[4]
VSS33[5]
VSS33[6]
VSS33[7]
VSS33[8]
VSS33[9]
Ground B2
D1
J2
R2
F14
L13
P14
M2
C14
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Pin No. Function
Switching Ground (VSS33[1:9]). The VSS33[1:9] pins should be
connected to GND.
NOTES ON PIN DESCRIPTIONS:
1. All COMET-QUAD inputs and bi-directionals present minimum capacitive loading.
2. All COMET-QUAD inputs and bi-directionals, when configured as inputs, tolerate TTL logic
levels.
3. All COMET-QUAD outputs and bi-directionals have at least 2 mA drive capability. The data
bus outputs, D[7:0], the INTB output, and the BRCLK[1:4] and BTCLK[1:4] outputs has 4 mA
drive capability. The transmit analog outputs (TXTIP and TXRING) have built-in short circuit
current limiting.
4. Inputs RSTB, ALE, TMS, TDI and TRSTB have internal pull-up resistors.
5. Input PIO has an internal pull-down resistor.
6. All unused inputs should be connected to GROUND.
7. It is recommended that the VSS33 and VSSC25 pins be connected to a common GROUND
Plane.
8. The 3.3 Volt power pins (i.e., TAVD1, TAVD2, TAVD3, CAVD, RAVD1, RAVD2, QAVD, VDD33,
and VDDQ33) will be collectively referred to as VDDall33 in this document.
9. Power to VDDall33 should be applied before power to the VDDC25 pins is applied. Similarly,
power to the VDDC25 pins should be removed before power to VDDall33 is removed.
10. The VDDall33 voltage level should not be allowed to drop below the VDDC25 voltage level.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
32
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
9
9.1
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
FUNCTIONAL DESCRIPTION
Quadrants
The COMET-QUAD’s four E1/T1 transceivers/framers operate independently and can be
configured to operate uniquely. The COMET-QUAD transceiver/framers (or quadrants) do share a
common XCLK crystal clock input and internal clock synthesizer; hence a single CSU
Configuration register is present and all quadrants share a common E1/T1B mode register bit.
When an H-MVIP interface is enabled, the interface interacts with all four quadrants, and hence
some common settings are required.
9.2
Receive Interface
The analog receive interface is configurable to operate in both E1 and T1 short-haul and long-haul
applications. Short-haul T1 is defined as transmission over less than 655 ft of cable. Short-haul
E1 is defined as transmission on any cable that attenuates the signal by less than 6 dB.
For long-haul signals, unequalized long- or short-haul bipolar alternate mark inversion (AMI)
signals are received as the differential voltage between the RXTIP and RXRING inputs. The
COMET-QUAD typically accepts unequalized signals that are attenuated for both T1 and E1
signals and are non-linearly distorted by typical cables.
For short-haul, the slicing threshold is set to a fraction of the input signal’s peak amplitude, and
adapts to changes in this amplitude. The slicing threshold is programmable, but is typically 67%
and 50% for DSX-1 and E1 applications, respectively. Abnormally low input signals are detected
when the input level is below a programmable threshold, which is typically 140 mV for E1 and
105 mV for T1.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
33
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Figure 5
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- External Analog Interface Circuits
TXTIP1
TXTIP2
TV REF
TXRING1
TXRING2
A TB
RXTIP
RXRING
One of Four
T1 or E1 Transceiver / Framers
Figure 5 gives the recommended external protection circuitry for designs required to meet the
major surge immunity and electrical safety standards including FCC Part 68, UL1950, and
Bellcore TR-NWT-001089. Standards compliance testing of this circuitry has not completed as of
the date of publication of this document.
For systems not requiring phantom feed or inter-building line protection, the Bi-directional
Transient Surge Suppressors (Z1-Z4), their associated ground connection and the center tap of
the transformer can be removed from the circuit.
See Table 1 for the descriptions of components for Figure 5. See Table 2 for the descriptions of
values for the transformer turns ratio, n, Rt1 and Rt2 for Figure 5.
Note that the crowbar devices (Z1 – Z4) are not required if the transformer’s isolation rating is not
exceeded.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
34
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Table 1:
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- External Component Descriptions
Component
Description
Part #
Source
LC01-6
Semtech
Surge Protector Diode Array
SRDA3.3-4
Semtech
Z1 – Z4
Bi-directional Transient Surge Suppressors
SGT27B13
Harris
T1 & T2
Generally 1:2.42CT Transformers (see
Table 2)
50436 (single)
T1137 (dual)
TG23-1505NS
(single)
TG23-1505N1
(dual)
Midcom
Pulse
Halo
Rt1 & Rt2
Typically 12.7Ω ±1% Resistors (see Table
2)
Rterm
18.2Ω ±1% Resistor for T1 & 120Ω E1
13Ω ±1% Resistor for 75Ω E1
(assuming a 1:2.42 transformer)
C0 & C1
4.7µF±10% Capacitors
F1 – F4
1 Amp, 600V Fuses
Rf1 – Rf4
2Ω ±1%, 2W, Resistors
TVS1 & TVS2
D1
Table 2 :
6V Bi-directional Transient Voltage
Suppressor Diode
Halo
- Termination Resistors, Transformer Ratios and TRL
Case
n
Rt1
Rt2
Typical TRL
SH T1: Zo=100Ω
1:2.42
12.7Ω ±1%
12.7Ω ±1%
14.1dB
SH E1: Zo=120Ω
1:2.42
12.7Ω ±1%
12.7Ω ±1%
19.4dB
SH E1: Zo=75Ω
1
SH E1: Zo=75Ω
1:2.42
1
1:2.42
12.7Ω ±1%
8.06Ω ±1%
12.7Ω ±1%
8.06Ω ±1%
9.6dB
18.8dB
LH T1 LBO=0dB: Zo=100Ω
1:2.42
12.7Ω ±1%
12.7Ω ±1%
14.1dB
LH T1 LBO=-7.5dB: Zo=100Ω
1:2.42
12.7Ω ±1%
12.7Ω ±1%
14.1dB
LH T1 LBO=-15dB: Zo=100Ω
1:2.42
12.7Ω ±1%
12.7Ω ±1%
14.1dB
LH T1 LBO=-22.5dB:
Zo=100Ω
1:2.42
12.7Ω ±1%
12.7Ω ±1%
14.1dB
Notes:
1) Headroom power is about 30% higher in this case.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
35
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
9.3
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Clock and Data Recovery (CDRC)
The Clock and Data Recovery function is provided by the Clock and Data Recovery (CDRC)
block. The CDRC provides clock and PCM data recovery, B8ZS and HDB3 decoding, line code
violation detection, and loss of signal detection. It recovers the clock from the incoming RZ data
pulses using a digital phase-locked-loop and reconstructs the NRZ data. Loss of signal is
indicated after a programmable threshold of consecutive bit periods of the absence of pulses on
both the positive and negative line pulse inputs and is cleared after the occurrence of a single line
pulse. An alternate loss of signal indication is provided which is cleared upon meeting an 1-in-8
pulse density criteria for T1 and a 1-in-4 pulse density criteria for E1. If enabled, a microprocessor
interrupt is generated when a loss of signal is detected and when the signal returns. A line code
violation is defined as a bipolar violation (BPV) for AMI-coded signals, is defined as a BPV that is
not part of a zero substitution code for B8ZS-coded signals, and is defined as a bipolar violation of
the same polarity as the last bipolar violation for HDB3-coded signals.
In T1 mode, the input jitter tolerance of the COMET-QUAD complies with the Bellcore Document
TA-TSY-000170 and with the AT&T specification TR62411, as shown in Figure 6. The tolerance is
measured with a QRSS sequence (220-1 with 14 zero restriction). The CDRC block provides two
algorithms for clock recovery that result in differing jitter tolerance characteristics. The first
algorithm (when the ALGSEL register bit is logic 0) provides good low frequency jitter tolerance,
but the high frequency tolerance is close to the TR62411 limit. The second algorithm (when
ALGSEL is logic 1) provides much better high frequency jitter tolerance at the expense of the low
frequency tolerance; the low frequency tolerance of the second algorithm is approximately 80%
that of the first algorithm.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
36
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Figure 6:
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- T1 Jitter Tolerance
10
Acceptable Range
Sine W ave
Jitter
Am plitude
P. to P. (UI)
Log Scale
1.0
Bellcore Spec.
0.3
AT&T Spec.
0.2
0.1
0.1
0.30 0.31
1.0
10
100
Sine W ave Jitter Frequency (kHz) Log Scale
For E1 applications, the input jitter tolerance complies with the ITU-T Recommendation G.823
"The Control of Jitter and Wander Within Digital Networks Which are Based on the 2048 kbit/s
Hierarchy." Figure 7 illustrates this specification and the performance of the phase-locked loop
when the ALGSEL register bit is logic 0.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
37
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Figure 7:
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- Compliance with ITU-T Specification G.823 for E1 Input Jitter
DPLL TOLERANCE
WITH AMI ENCODED
15
2 -1 PRBS
10
SINEWAVE
JITTER
AMPLITUDE
P. TO P. (UI)
LOG SCALE
DPLL TOLERANCE
WITH HDB3 ENCODED
15
2 -1 PRBS
IN SPEC
REGION
1.5
1
REC. G823
JITTER
TOLERANCE
SPECIFICATION
0.2
0.1
10
3
2.4
10
4
1.8
10
5
SINEWAVE JITTER FREQUENCY, Hz - LOG SCALE
9.4
Receive Jitter Attenuator (RJAT)
The Receive Jitter Attenuator (RJAT) digital PLL attenuates the jitter present on the
RXTIP/RXRING inputs. The attenuation is only performed when the RJATBYP register bit is a
logic 0.
The jitter characteristics of the Receive Jitter Attenuator (RJAT) are the same as the Transmit
Jitter Attenuator (TJAT).
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
38
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
9.5
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
T1 Inband Loopback Code Detector (IBCD)
The T1 Inband Loopback Code Detection function is provided by the IBCD block. This block
detects the presence of either of two programmable INBAND LOOPBACK ACTIVATE and
DEACTIVATE code sequences in either framed or unframed data streams. Each INBAND
LOOPBACK code sequence is defined as the repetition of the programmed code in the PCM
stream for at least 5.1 seconds. The code sequence detection and timing is compatible with the
specifications defined in T1.403-1993, TA-TSY-000312, and TR-TSY-000303. LOOPBACK
ACTIVATE and DEACTIVATE code indication is provided through internal register bits. An
interrupt is generated to indicate when either code status has changed.
9.6
T1 Pulse Density Violation Detector (PDVD)
The Pulse Density Violation Detection function is provided by the PDVD block. The block detects
pulse density violations of the requirement that there be N ones in each and every time window of
8(N+1) data bits (where N can equal 1 through 23). The PDVD also detects periods of 16
consecutive zeros in the incoming data. Pulse density violation detection is provided through an
internal register bit. An interrupt is generated to signal a 16 consecutive zero event, and/or a
change of state on the pulse density violation indication.
9.7
T1 Framer (T1-FRMR)
The T1 framing function is provided by the T1-FRMR block. This block searches for the framing
bit position in the backplane receive stream. It works in conjunction with the FRAM block to
search for the framing bit pattern in the standard superframe (SF), or extended superframe (ESF)
framing formats. When searching for frame, the FRMR simultaneously examines each of the 193
(SF) or each of the 772 (ESF) framing bit candidates. The FRAM block is addressed and
controlled by the FRMR while frame synchronization is acquired.
The time required to acquire frame alignment to an error-free backplane receive stream,
containing randomly distributed channel data (i.e. each bit in the channel data has a 50%
probability of being 1 or 0), is dependent upon the framing format. For SF format, the T1-FRMR
block will determine frame alignment within 4.4 ms 99 times out of 100. For ESF format, the T1FRMR will determine frame alignment within 15 ms 99 times out of 100.
Once the T1-FRMR has found frame, the backplane receive data is continuously monitored for
framing bit errors, bit error events (a framing bit error in SF or a CRC-6 error in ESF), and
severely errored framing events. The T1-FRMR also detects out of frame, based on a selectable
ratio of framing bit errors.
The T1-FRMR can also be disabled to allow reception of unframed data.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
39
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
9.8
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
E1 Framer (E1-FRMR)
The E1 framing function is provided by the E1-FRMR block. The E1-FRMR block searches for
basic frame alignment, CRC multiframe alignment, and channel associated signaling (CAS)
multiframe alignment in the incoming recovered PCM stream.
Once the E1-FRMR has found basic (or FAS) frame alignment, the incoming PCM data stream is
continuously monitored for FAS/NFAS framing bit errors. Framing bit errors are accumulated in
the framing bit error counter contained in the PMON block. Once the E1-FRMR has found CRC
multiframe alignment, the PCM data stream is continuously monitored for CRC multiframe
alignment pattern errors, and CRC-4 errors. CRC-4 errors are accumulated in the CRC error
counter of the PMON block. Once the E1-FRMR has found CAS multiframe alignment, the PCM
data is continuously monitored for CAS multiframe alignment pattern errors. The E1-FRMR also
detects and indicates loss of basic frame, loss of CRC multiframe, and loss of CAS multiframe,
based on user-selectable criteria. The reframe operation can be initiated by software (via the
E1-FRMR Frame Alignment Options register), by excessive CRC errors, or when CRC multiframe
alignment is found by the offline framer. The E1-FRMR also identifies the position of the frame,
the CAS multiframe, and the CRC multiframe.
The E1-FRMR extracts the contents of the International bits (from both the FAS frames and the
NFAS frames), the National bits, and the Extra bits (from timeslot 16 of frame 0 of the CAS
multiframe), and stores them in the E1-FRMR International/National Bits register and the
E1-FRMR Extra Bits register. Moreover, the E1-FRMR also extracts submultiframe-aligned 4-bit
codewords from each of the National bit positions Sa4 to Sa8, and stores them in microprocessoraccessible registers that are updated every CRC submultiframe.
The E1-FRMR identifies the raw bit values for the Remote (or distant frame) Alarm (bit 3 in
timeslot 0 of NFAS frames) and the Remote Signaling Multiframe (or distant multiframe) Alarm (bit
6 of timeslot 16 of frame 0 of the CAS multiframe) via the E1-FRMR International/National Bits
Register, and the E1-FRMR Extra Bits Register respectively. Access is also provided to the
"debounced" remote alarm and remote signaling multiframe alarm bits which are set when the
corresponding signals have been a logic 1 for 2 or 3 consecutive occurrences, as per
Recommendation O.162. Detection of AIS and timeslot 16 AIS are provided. AIS is also
integrated, and an AIS Alarm is indicated if the AIS condition has persisted for at least 100 ms.
The out of frame (OOF=1) condition is also integrated, indicating a Red Alarm if the OOF
condition has persisted for at least 100 ms.
An interrupt may be generated to signal a change in the state of any status bits (OOF, OOSMF,
OOCMF, AIS or RED), and to signal when any event (RAI, RMAI, AISD, TS16AISD, COFA, FER,
SMFER, CMFER, CRCE or FEBE) has occurred. Additionally, interrupts may be generated every
frame, CRC submultiframe, CRC multiframe or signaling multiframe.
Basic Frame Alignment Procedure
The E1-FRMR searches for basic frame alignment using the algorithm defined in ITU-T
Recommendation G.706 sections 4.1.2 and 4.2.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
40
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
The algorithm finds frame alignment by using the following sequence:
1. Search for the presence of the correct 7-bit FAS (‘0011011’);
2. Check that the FAS is absent in the following frame by verifying that bit 2 of the assumed nonframe alignment sequence (NFAS) TS 0 byte is a logic 1;
3. Check that the correct 7-bit FAS is present in the assumed TS 0 byte of the next frame.
If either of the conditions in steps 2 or 3 are not met, a new search for frame alignment is initiated
in the bit immediately following the second 7-bit FAS sequence check. This "hold-off" is done to
ensure that new frame alignment searches are done in the next bit position, modulo 512. This
facilitates the discovery of the correct frame alignment, even in the presence of fixed timeslot data
imitating the FAS.
These algorithms provide robust framing operation even in the presence of random bit errors:
framing with algorithm #1 or #2 provides a 99.98% probability of finding frame alignment within
1 ms in the presence of 10-3 bit error rate and no mimic patterns.
Once frame alignment is found, the block sets the OOF indication low, indicates a change of
frame alignment (if it occurred), and monitors the frame alignment signal, indicating errors
occurring in the 7-bit FAS pattern and in bit 2 of NFAS frames, and indicating the debounced value
of the Remote Alarm bit (bit 3 of NFAS frames). Using debounce, the Remote Alarm bit has
<0.00001% probability of being falsely indicated in the presence of a 10-3 bit error rate. The block
declares loss of frame alignment if 3 consecutive FAS's have been received in error or,
additionally, if bit 2 of NFAS frames has been in error for 3 consecutive occasions. In the
presence of a random 10-3 bit error rate the frame loss criteria provides a mean time to falsely
lose frame alignment of >12 minutes.
The E1-FRMR can be forced to initiate a basic frame search at any time when any of the following
conditions are met:
•
the software re-frame bit in the E1-FRMR Frame Alignment Options register goes to logic 1;
•
the CRC Frame Find Block is unable to find CRC multiframe alignment; or
•
the CRC Frame Find Block accumulates excessive CRC evaluation errors (≥ 915 CRC errors
in 1 second) and is enabled to force a re-frame under that condition.
CRC Multiframe Alignment Procedure
The E1-FRMR searches for CRC multiframe alignment by observing whether the International bits
(bit 1 of TS 0) of NFAS frames follow the CRC multiframe alignment pattern. Multiframe
alignment is declared if at least two valid CRC multiframe alignment signals are observed within
8 ms, with the time separating two alignment signals being a multiple of 2 ms
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
41
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Once CRC multiframe alignment is found, the OOCMFV register bit is set to logic 0, and the
E1-FRMR monitors the multiframe alignment signal, indicating errors occurring in the 6-bit MFAS
pattern, errors occurring in the received CRC and the value of the FEBE bits (bit 1 of frames 13
and 15 of the multiframe). The E1-FRMR declares loss of CRC multiframe alignment if basic
frame alignment is lost. However, once CRC multiframe alignment is found, it cannot be lost due
to errors in the 6-bit MFAS pattern.
Under the CRC-to-non-CRC interworking algorithm, if the E1-FRMR can achieve basic frame
alignment with respect to the incoming PCM data stream, but is unable to achieve CRC-4
multiframe alignment within the subsequent 400 ms, the distant end is assumed to be a non CRC4 interface. The details of this algorithm are illustrated in the state diagram in Figure 8.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
42
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Figure 8:
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- CRC Multiframe Alignment Algorithm
O ut of Fram e
3 consecutiv e FAS or NF AS
errors; m anual refram e; or
excessiv e C RC errors
FAS_Find_1_Par
FAS_Find_1
NFAS
not found
next fram e
FAS
found
FAS
found
NFAS_Find
NFAS_Find_Par
NFAS
found
next fram e
FAS
not found
next fram e
NFAS
found
next fram e
8m s expire
Start 400m s tim er
and 8m s tim er
BFA
CRC MFA
CRC to CRC
Interworking
FAS
not found
next fram e
FAS_Find_2_Par
FAS_Find_2
FAS
found
next fram e
NFAS
not found
next fram e
FAS
found
next fram e
8m s expire and
NOT(400m s expire)
Reset BF A to
m ost recently
found alignm ent
Start 8m s tim er
BFA_Par
CRCMFA_Par
CR CMFA_Par
(Optional setting)
400m s
expire
CRC to non-CRC
Interworking
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
43
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Table 3:
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- E1-FRMR Framing States
State
FAS_Find_1
NFAS_Find
FAS_Find_2
BFA
CRC to CRC Interworking
FAS_Find_1_Par
NFAS_Find_Par
FAS_Find_2_Par
BFA_Par
CRC to non-CRC Interworking
Out of Frame
Yes
Yes
Yes
No
No
No
No
No
No
No
Out of Offline Frame
No
No
No
No
No
Yes
Yes
Yes
No
No
The states of the primary basic framer and the parallel/offline framer in the E1-FRMR block at
each stage of the CRC multiframe alignment algorithm are shown in Table 3.
From an out of frame state, the E1-FRMR attempts to find basic frame alignment in accordance
with the FAS/NFAS/FAS G.706 Basic Frame Alignment procedure outlined above. Upon achieving
basic frame alignment, a 400 ms timer is started, as well as an 8 ms timer. If two CRC multiframe
alignment signals separated by a multiple of 2 ms are observed before the 8 ms timer has
expired, CRC multiframe alignment is declared.
If the 8 ms timer expires without achieving multiframe alignment, a new offline search for basic
frame alignment is initiated. This search is performed in accordance with the Basic Frame
Alignment procedure outlined above. However, this search does not immediately change the
actual basic frame alignment of the system (i.e., PCM data continues to be processed in
accordance with the first basic frame alignment found after an out of frame state while this frame
alignment search occurs as a parallel operation).
When a new basic frame alignment is found by this offline search, the 8 ms timer is restarted. If
two CRC multiframe alignment signals separated by a multiple of 2 ms are observed before the
8 ms timer has expired, CRC multiframe alignment is declared and the basic frame alignment is
set accordingly (i.e., the basic frame alignment is set to correspond to the frame alignment found
by the parallel offline search, which is also the basic frame alignment corresponding to the newly
found CRC multiframe alignment).
Subsequent expirations of the 8 ms timer will likewise reinitiate a new search for basic frame
alignment. If, however, the 400 ms timer expires at any time during this procedure, the E1-FRMR
stops searching for CRC multiframe alignment and declares CRC-to-non-CRC interworking. In
this mode, the E1-FRMR may be optionally set to either halt searching for CRC multiframe
altogether, or may continue searching for CRC multiframe alignment using the established basic
frame alignment. In either case, no further adjustments are made to the basic frame alignment,
and no offline searches for basic frame alignment occur once CRC-to-non-CRC interworking is
declared: it is assumed that the established basic frame alignment at this point is correct.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
44
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
AIS Detection
When an unframed all-ones receive data stream is received, an AIS defect is indicated by setting
the AISD bit of the E1-FRMR Maintenance/Alarm Status register to logic 1 when fewer than three
zero bits are received in 512 consecutive bits or, optionally, in each of two consecutive periods of
512 bits. The AISD bit is reset to logic 0 when three or more zeros in 512 consecutive bits or in
each of two consecutive periods of 512 bits. Finding frame alignment will also cause the AISD bit
to be set to logic 0.
Signaling Frame Alignment
Once the basic frame alignment has been found, the E1-FRMR searches for Channel Associated
Signaling (CAS) multiframe alignment using the following G.732 compliant algorithm: signaling
multiframe alignment is declared when at least one non-zero timeslot 16 bit is observed to
precede a timeslot 16 containing the correct CAS alignment pattern, namely four zeros (“0000”) in
the first four bit positions of timeslot 16.
Once signaling multiframe alignment has been found, the E1-FRMR sets the OOSMFV bit of the
E1-FRMR Framing Status register to logic 0, and monitors the signaling multiframe alignment
signal, indicating errors occurring in the 4-bit pattern, and indicating the debounced value of the
Remote Signaling Multiframe Alarm bit (bit 6 of timeslot 16 of frame 0 of the multiframe). Using
debounce, the Remote Signaling Multiframe Alarm bit has < 0.00001% probability of being falsely
indicated in the presence of a 10-3 bit error rate.
This E1-FRMR also indicates the reception of TS 16 AIS when timeslot 16 has been received with
three or fewer zeros in each of two consecutive multiframe periods. The TS16AIS signal is
cleared when each of two consecutive signaling multiframe periods contain four or more zeros OR
when the signaling multiframe signal is found.
The block declares loss of CAS multiframe alignment if two consecutive CAS multiframe
alignment signals have been received in error, or additionally, if all the bits in timeslot 16 are
logic 0 for 1 or 2 (selectable) CAS multiframes. Loss of CAS multiframe alignment is also
declared if basic frame alignment has been lost.
National Bit Extraction
The E1-FRMR extracts and assembles the submultiframe-aligned National bit codewords
Sa4[1:4], Sa5[1:4], Sa6[1:4], Sa7[1:4] and Sa8[1:4]. The corresponding register values are
updated upon generation of the CRC submultiframe interrupt.
This E1-FRMR also detects the V5.2 link ID signal, which is detected when 2 out of 3 Sa7 bits are
zeros. Upon reception of this Link ID signal, the V52LINKV bit of the E1-FRMR Framing Status
register is set to logic 1. This bit is cleared to logic 0 when 2 out of 3 Sa7 bits are ones.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
45
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Alarm Integration
The OOF and the AIS defects are integrated, verifying that each condition has persisted for
104 ms (± 6 ms) before indicating the alarm condition. The alarm is removed when the condition
has been absent for 104 ms (± 6 ms).
The AIS alarm algorithm accumulates the occurrences of AISD (AIS detection). The E1-FRMR
counts the occurrences of AISD over a 4 ms interval and indicates a valid AIS is present when 13
or more AISD indications (of a possible 16) have been received. Each interval with a valid AIS
presence indication increments an interval counter which declares AIS Alarm when 25 valid
intervals have been accumulated. An interval with no valid AIS presence indication decrements
the interval counter. The AIS Alarm declaration is removed when the counter reaches 0. This
algorithm provides a 99.8% probability of declaring an AIS Alarm within 104 ms in the presence of
a 10-3 mean bit error rate.
The Red alarm algorithm monitors occurrences of OOF over a 4 ms interval, indicating a valid
OOF interval when one or more OOF indications occurred during the interval, and indicating a
valid in frame (INF) interval when no OOF indication occurred for the entire interval. Each interval
with a valid OOF indication increments an interval counter which declares Red Alarm when 25
valid intervals have been accumulated. An interval with valid INF indication decrements the
interval counter; the Red Alarm declaration is removed when the counter reaches 0. This
algorithm biases OOF occurrences, leading to declaration of Red alarm when intermittent loss of
frame alignment occurs.
The E1-FRMR can also be disabled to allow reception of unframed data.
9.9
Receive Elastic Store (RX-ELST)
The Elastic Store (ELST) synchronizes backplane receive frames to the backplane receive clock
and frame pulse (BRCLK[x], BRFP[x]) in the Clock Slave backplane receive modes or to the
common backplane receive H-MVIP clock and frame pulse (CMV8MCLK, CMVFP, CMVFPC) in
H-MVIP modes. The frame data is buffered in a two frame circular data buffer. Input data is
written to the buffer using a write pointer and output data is read from the buffer using a read
pointer.
When the elastic store is being used, if the average frequency of the incoming data is greater than
the average frequency of the backplane clock, the write pointer will catch up to the read pointer
and the buffer will be filled. Under this condition a controlled slip will occur when the read pointer
crosses the next frame boundary. The subsequent backplane receive frame is deleted.
If the average frequency of the incoming data is less than the average frequency of the backplane
clock, the read pointer will catch up to the write pointer and the buffer will be empty. Under this
condition a controlled slip will occur when the read pointer crosses the next frame boundary. The
previous backplane receive frame is repeated.
A slip operation is always performed on a frame boundary.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
46
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
When the backplane receive timing is recovered from the receive data the elastic store can be
bypassed to eliminate the one frame delay. In this configuration (the Clock Master backplane
receive modes), the elastic store is used to synchronize the backplane receive frames to the
transmit line clock so that per-DS0 loopbacks may be enabled.
To allow for the extraction of signaling information in the data channels, superframe identification
is also passed through the ELST.
For payload conditioning, the ELST may optionally insert a programmable idle code into all
channels when the framer is out of frame synchronization. This code is set to all 1’s when the
ELST is reset.
9.10 Signaling Extractor (SIGX)
The Signaling Extraction (SIGX) block provides channel associated signaling (CAS) extraction
from an E1 signaling multi-frame or from ESF or SF T1 formats. It selectively debounces the bits,
and serializes the results onto the BRSIG[x] or CASBRD outputs. Debouncing is performed on
individual signaling bits. This BRSIG[x] (CASBRD) output is channel aligned with BRPCM[x]
(MVBRD) output, and the signaling bits are repeated for the entire multiframe/superframe,
allowing downstream logic to reinsert signaling into any frame, as determined by system timing.
The signaling data stream contains the A,B,C,D bits in the lower 4 channel bit locations (bits 5, 6,
7 and 8) in T1 ESF or E1 framing formats; in T1 SF format the A and B bits are repeated in
locations C and D (i.e. the signaling stream contains the bits ABAB for each channel).
The SIGX block contains three superframes worth of signal buffering to ensure that there is a
greater than 95% probability that the signaling bits are frozen in the correct state for a 50% ones
density out of frame condition, as specified in TR-TSY-000170 and BELL PUB 43801. With
signaling debounce enabled, the per-channel signaling state must be in the same state for 2
superframes before appearing on the serial output stream.
The SIGX block provides one superframe or signaling-multiframe of signal freezing on the
occurrence of slips. When a slip event occurs, the SIGX freezes the output signaling for the entire
superframe in which the slip occurred; the signaling is unfrozen when the next slip-free
superframe occurs.
The SIGX also provides control over timeslot signaling bit fixing, data inversion and signaling
debounce on a per-timeslot basis.
The SIGX block also provides an interrupt to indicate a change of signaling state on a per channel
basis.
9.11 Performance Monitor Counters (T1/E1-PMON)
The Performance Monitor Counters function is provided by the PMON block. The block
accumulates CRC error events, Frame Synchronization bit error events, and Out Of Frame
events, or optionally, Change of Frame Alignment (COFA) events with saturating counters over
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
47
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
consecutive intervals as defined by the period of the supplied transfer clock signal (typically 1
second). When the transfer clock signal is applied, the PMON transfers the counter values into
holding registers and resets the counters to begin accumulating events for the interval. The
counters are reset in such a manner that error events occurring during the reset are not missed.
If the holding registers are not read between successive transfer clocks, an OVR overrun register
bit is asserted.
Generation of the transfer clock within a quadrant is performed by writing to any counter register
location within the quadrant or by writing to the Revision/Chip ID/Quadrant PMON Update register.
The holding register addresses are contiguous to facilitate faster polling operations.
9.12 T1 Automatic Performance Report Generation (APRM)
In compliance with the ANSI T1.231, T1.403 and T1.408 standards, a performance report is
generated each second for T1 ESF applications. The report conforms to the HDLC protocol and
is inserted into the ESF facility data link.
The performance report can only be transmitted if the TDPR is configured to insert the ESF
Facility Data Link and the PREN bit of the TDPR Configuration register is logic 1. The
performance report takes precedence over incompletely written packets, but it does not pre-empt
packets already being transmitted.
See the Operation section for details on the performance report encoding.
9.13 T1 Alarm Integrator (ALMI)
The T1 Alarm Integration function is provided by the ALMI block. This block detects the presence
of Yellow, Red, and AIS Carrier Fail Alarms (CFA) in SF, or ESF formats. The alarm detection and
integration is compatible with the specifications defined in ANSI T1.403 and TR-TSY-000191.
The ALMI block declares the presence of Yellow alarm when the Yellow pattern has been received
for 425 ms (± 50 ms); the Yellow alarm is removed when the Yellow pattern has been absent for
425 ms (± 50 ms). The presence of Red alarm is declared when an out of frame condition has
been present for 2.55 sec (± 40 ms); the Red alarm is removed when the out of frame condition
has been absent for 16.6 sec (± 500 ms). The presence of AIS alarm is declared when an out of
frame condition and all-ones in the PCM data stream have been present for 1.5 sec (±100 ms);
the AIS alarm is removed when the AIS condition has been absent for 16.8 sec (±500 ms).
CFA alarm detection algorithms operate in the presence of a 10-3 bit error rate.
The ALMI also indicates the presence or absence of the Yellow, Red, and AIS alarm signal
conditions over 40 ms, 40 ms, and 60 ms intervals, respectively, allowing an external
microprocessor to integrate the alarm conditions via software with any user-specific algorithms.
Alarm indication is provided through internal register bits.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
48
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
9.14 HDLC Receiver (RDLC)
The RDLC is a microprocessor peripheral used to receive HDLC frames on the T1 4kHz ESF
facility data link, the E1 Sa-bit data link, or in any arbitrary timeslot (T1 or E1).
The RDLC detects the change from flag characters to the first byte of data, removes stuffed zeros
on the incoming data stream, receives packet data, and calculates the CRC-CCITT frame check
sequence (FCS).
In the address matching mode, only those packets whose first data byte matches one of two
programmable bytes or the universal address (all ones) are stored in the FIFO. The two least
significant bits of the address comparison can be masked for LAPD SAPI matching.
Received data is placed into a 128-level FIFO buffer. An interrupt is generated when a
programmable number of bytes are stored in the FIFO buffer. Other sources of interrupt are
detection of the terminating flag sequence, abort sequence, or FIFO buffer overrun.
The Status Register contains bits that indicate the overrun or empty FIFO status, the interrupt
status, and the occurrence of first flag or end of message bytes written into the FIFO. The Status
Register also indicates the abort, flag, and end of message status of the data just read from the
FIFO. On end of message, the Status Register indicates the FCS status and if the packet
contained a non-integer number of bytes.
9.15 Bit Oriented Code Detector (RBOC)
The Bit Oriented Code detection function is provided by the RBOC block. This block detects the
presence of 63 of the possible 64 bit oriented codes transmitted in the T1 Facility Data Link
Th
channel in ESF framing format, as defined in ANSI T1.403 and in TR-TSY-000194. The 64 code
(111111) is similar to the HDLC flag sequence and is used by the RBOC to indicate no valid code
received.
Bit oriented codes are received on the Facility Data Link channel as a 16-bit sequence consisting
of 8 ones, a zero, 6 code bits, and a trailing zero (111111110xxxxxx0). BOCs are validated when
repeated at least 10 times. The RBOC can be enabled to declare a received code valid if it has
been observed for 8 out of 10 times or for 4 out of 5 times, as specified by the AVC bit in the
RBOC Configuration/Interrupt Enable register. The RBOC declares that the code is removed if two
code sequences containing code values different from the detected code are received in a moving
window of ten code periods.
Valid BOC are indicated through the RBOC Interrupt Status register. The BOC bits are set to all
ones (111111) if no valid code has been detected. An interrupt is generated to signal when a
detected code has been validated, or optionally, when a valid code goes away (i.e. the BOC bits
go to all ones).
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
49
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
9.16 Receive Per-Channel Serial Controller (RPSC)
The RPSC allows data and signaling trunk conditioning to be applied on the backplane receive
stream on a per-channel basis. It also allows per-channel control of data inversion, the extraction
of clock and data on BRCLK[x] and BRPCM[x] (when the Clock Master: Nx64Kbit/s mode is
active), and the detection or generation of pseudo-random patterns. The RPSC operates on the
data after its passage through ELST, so that data and signaling conditioning may overwrite the
ELST trouble code.
9.17 Pseudo Random Binary Sequence Generation and Detection (PRBS)
The Pseudo Random Binary Sequence Generator/Detector (PRBS) block is a software selectable
11
15
20
PRBS generator and checker for 2 -1, 2 -1 or 2 -1 PRBS polynomials for use in the T1 and E1
links. PRBS patterns may be generated in either the transmit or receive directions, and detected
in the opposite direction.
The PRBS block can perform an auto synchronization to the expected PRBS pattern and
accumulates the total number of bit errors in two 24-bit counters. The error count accumulates
over the interval defined by to the Quadrant PMON Update register. When an accumulation is
forced, the holding register is updated, and the counter reset to begin accumulating for the next
interval. The counter is reset in such a way that no events are missed. The data is then available
in the Error Count registers until the next accumulation.
9.18 Backplane Receive System Interface (BRIF)
The Backplane Receive System Interface (BRIF) block provides system side serial clock and data
access as well as H-MVIP access for up to 4 T1 or E1 receive streams. There are several
master and slave clock modes for serial clock and data system side access to the T1 and E1
streams. When enabled for 8.192 Mbit/s H-MVIP, there are three separate signals for data and
signaling. Information on programming the Backplane Receive System Interface can be found in
the Operation section.
Three Clock Master modes provide a serial clock and data backplane receive interface with
clocking provided by COMET-QUAD: Clock Master: Full T1/E1, Clock Master: Nx64Kbit/s, Clock
Master: Clear Channel. Three Clock slave modes provide a serial clock and data backplane
receive mode, an H-MVIP mode, and a mixed clock-and-data/H-MVIP mode. All Clock Slave
modes accept externally sourced clocking. The modes are Clock Slave: Full T1/E1, Clock Slave:
Full T1/E1 with CCS H-MVIP, and Clock Slave: H-MVIP.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
50
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Figure 9:
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- Receive Clock Master: Full T1/E1
BRPCM[x], BRFP[x], BRSIG[x]
Timed to BRCLK[x ]
BRPCM[1:4]
BRFP[1:4]
BRSIG[1:4]
BRIF
Backplane
Receive
System
Interface
RECEIVER
FRAM
Framer:
Slip Buffer RAM
FRMR
Framer:
Frame Alignment,
Alarm Extraction
RJAT
Digital Jitter
Attenuator
Receive Data[1:4]
Receive CLK[1:4]
BRCLK[1:4]
In Receive Clock Master: Full T1/E1 mode, the elastic store is bypassed and the backplane
receive clock (BRCLK[x]) is, optionally, a jitter attenuated version of the 1.544 MHz or 2.048 MHz
receive clock. The backplane receive data appears on BRPCM[x], the backplane receive
signaling appears on BRSIG[x], and the backplane receive frame alignment is indicated by
BRFP[x]. In this mode, T1 or E1 data passes through the COMET-QUAD unchanged during out
of frame conditions, similar to an offline framer system. When the COMET-QUAD is the clock
master in the backplane receive direction, the receive elastic store is used to buffer between the
backplane receive and backplane transmit clocks to facilitate per-DS0 loopback.
Figure 10:
- Receive Clock Master: Nx64Kbit/s
BRPCM[x], BRFP[x],
BRSIG[x] Timed to
gapped BRCLK[x]
BRPCM[1:4]
BRFP[1:4]
BRSIG[1:4]
BRCLK[1:4]
BRIF
Backplane
Receive
System
Interface
FRAM
Framer:
Slip Buffer RAM
FRMR
Framer:
Frame Alignment,
Alarm Extraction
RECEIVER
RJAT
Digital Jitter
Attenuator
Receive Data[1:4]
Receive CLK[1:4]
In Receive Clock Master: Nx64Kbit/s mode, BRCLK[x] is a gapped version of the optionally jitter
attenuated 1.544 MHz or 2.048 MHz receive clock. BRCLK[x] is gapped on a per channel basis
so that a subset of the 24 channels in the T1 frame or 32 channels in an E1 frame is extracted on
BRPCM[x]. BRFP[x] indicates frame alignment but, in T1 mode, has no clock since it is gapped
during the framing bit positions. Channel extraction is controlled by the RPSC block. The framing
bit position is always gapped in T1 mode, so the number of BRCLK[x] pulses is controllable from 0
to 192 pulses per T1 frame or 0 to 256 pulses per E1 frame on a per-DS0 basis. In this mode, T1
or E1 streams pass through the COMET-QUAD unchanged during out of frame conditions. The
parity functions are not usable in this mode. When the COMET-QUAD is the clock master in the
backplane receive direction, the elastic store is used to buffer between the backplane receive and
backplane transmit clocks to facilitate per-DS0 loopback.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
51
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Figure 11:
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- Receive Clock Master: Clear Channel
RECEIVER
BRPCM[x]
Timed to gapped
BRCLK[x ]
BRPCM[1:4]
BRCLK[1:4]
BRIF
Backplane
Receive
System
Interface
RJAT
Digital Jitter
Attenuator
Receive Data[1:4]
Receive CLK[1:4]
In Receive Clock Master: Clear Channel mode, the elastic store is bypassed and the backplane
receive clock (BRCLK[x]) is optionally a jitter attenuated version of the 1.544 MHz or 2.048 MHz
receive clock. The backplane receive data appears on BRPCM[x] with no frame alignment
indication.
Figure 12:
- Receive Clock Slave: Full T1/E1
ELST
Elastic
Store
BRCLK[1:4]
BRIF
Backplane
Receive
System
Interface
BRFP[1:4]
BRPCM[1:4]
BRSIG[1:4]
RECEIVER
FRAM
Framer:
Slip Buffer RAM
RJAT
Digital Jitter
Attenuator
FRMR
Framer:
Frame Alignment,
Alarm Extraction
Receive Data[1:4]
Receive CLK[1:4]
BRPCM[x], BRSIG[x ],
Timed to BRCLK[x]
In Receive Clock Slave: Full T1/E1 mode, the elastic store is enabled to permit the input
BRCLK[x] to specify the backplane receive-side timing. The backplane receive data on
BRPCM[x] and signaling BRSIG[x] are bit aligned to the 1.544 MHz or 2.048 MHz backplane
receive clock (BRCLK[x]) and are frame aligned to the backplane receive frame pulse (BRFP[x]).
BRSIG[x] contains the signaling state (ABCD or ABAB) in the lower four bits of each channel.
Figure 13:
- Receive Clock Slave: H-MVIP
ELST
Elastic
Store
CMV8MCLK
CMVFPC
CMVFPB
MVBRD
CASBRD
BRIF
Backplane
Receive
System
Interface
RECEIVER
FRAM
Framer:
Slip Buffer RAM
FRMR
Framer:
Frame Alignment,
Alarm Extraction
RJAT
Digital Jitter
Attenuator
Receive Data[1:4]
Receive CLK[1:4]
Outputs Timed
to CMV 8MCLK
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
52
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
When Receive Clock Slave: H-MVIP mode is enabled a 8.192 Mbit/s H-MVIP backplane transmit
interface multiplexes up to 128 channels from 4 T1s or E1s, up to 128 channel associated
signaling (CAS) channels from 4 T1s or E1s and common channel signaling from up to 4 T1s or
E1s. The H-MVIP interface uses common clocks, CMV8MCLK and CMVFPC, and frame pulse,
CMVFPB, for synchronization.
Using the H-MVIP interface forces the T1 or E1 receiver to operate in synchronous mode,
meaning that elastic stores are used.
The H-MVIP backplane receive data pins are multiplexed with serial data outputs to provide HMVIP access to 128 data channels.
The CASBRD H-MVIP signal provides access to the Channel Associated Signaling (CAS) for all of
the 128 data channels. The CAS is time division multiplexed exactly the same way as the data
channels and is synchronized with the H-MVIP data channels. Over a T1 or E1 multi-frame the
four CAS bits per channel are repeated with each data byte. Four stuff bits are used to pad each
CAS nibble (ABCD bits) out to a full byte in parallel with each data byte.
Figure 14:
- Receive Clock Slave: Full T1/E1 with CCS H-MVIP
BRPCM[x], BRSIG[x],
Timed to BRCLK[x]
ELST
Elastic
Store
BRCLK[1:4]
BRFP[1:4]
BRPCM[1:4]
BRSIG[1:4]
CMV8MCLK
RECEIVER
FRAM
Framer:
Slip Buffer RAM
FRMR
Framer:
Frame Alignment,
Alarm Extraction
BRIF
Backplane
Receive
System
Interface
RJAT
Digital Jitter
Attenuator
Receive Data[1:4]
Receive CLK[1:4]
CMVFPC
CMVFPB
CCSBRD
CCSBRD Timed
to CMV 8MCLK
CCS ELST
Elastic
Store
In Receive Clock Slave: Full T1/E1 with CCS H-MVIP mode, the elastic store is enabled to permit
the input BRCLK[x] to specify the backplane receive-side timing. The backplane receive data on
BRPCM[x] and signaling BRSIG[x] are bit aligned to the 1.544 MHz or 2.048 MHz backplane
receive clock (BRCLK[x]) and are frame aligned to the backplane receive frame pulse (BRFP[x]).
BRSIG[x] contains the signaling state (ABCD or ABAB) in the lower four bits of each channel.
The H-MVIP interface (CMV8MCLK, CMVFPC, CMVFPB, and CCSBRD) extracts Common
th
Channel Signaling (CCS) from the 24 DS0 in T1 mode and up to 3 timeslots (15, 16, 31) in E1
mode. The H-MVIP interface uses common clocks, CMV8MCLK and CMVFPC, and frame pulse,
CMVFPB, for synchronization.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
53
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
BRCLK[x] may optionally be configured as clock master. This is represented with the above figure
but with BRCLK[x] being driven by the COMET-QUAD rather than being an input.
When CCS H-MVIP is enabled, BRCLK[1:4] must be configured to run at 2.048 MHz.
9.19 Backplane Transmit System Interface (BTIF)
The Backplane Transmit System Interface (BTIF) block provides system side serial clock and data
access as well as H-MVIP access for up to 4 T1 or E1 transmit streams. There are several master
and slave clocking modes for serial clock and data system side access to the T1 and E1 streams.
When enabled for 8.192 Mbit/s H-MVIP there are three separate signals for data and signaling.
Information on programming the Backplane Transmit System Interface for various modes can be
found in the Operation section.
Three Clock Master modes provide a serial clock and data backplane transmit interface with per
link clocking provided by COMET-QUAD: Clock Master: Full T1/E1, Clock Master: Nx64Kbit/s and
Clock Master: Clear Channel. Four Clock slave modes provide two serial clock and data
backplane transmit modes, a mixed clock-and-data/H-MVIP mode, and a pure H-MVIP mode all
with externally sourced clocking: Clock Slave: Full T1/E1, Clock Slave: Full T1/E1 with CCS HMVIP, Clock Slave: Clear Channel and Clock Slave: H-MVIP.
In Clock Master modes the transmit clock can be sourced from either the common transmit clock,
CTCLK, the received clock for that link, or one of the two recovered clocks.
Figure 15:
- Transmit Clock Master: Full T1/E1
CTCLK
BTPCM[1:4]
BTSIG[1:4]
BTFP[1:4]
BTCLK[1:4]
BTPCM[x], BTSIG[x],
BTP[x]Timed to
BTCLK[x]
Receive CLK[1:4]
BTIF
Backplane
Transmit
System
Interface
T1-XBAS/E1-TRAN
BasicTransmitter:
Frame Generation,
Alarm Insertion,
Signaling Insertion,
Trunk Conditioning
Line Coding
TJAT
Digital PLL
Transmit CLK[1:4]
Transmit Data[1:4]
TRANSMITTER
In Transmit Clock Master: Full T1/E1 mode, the backplane transmit clock (BTCLK[x]) is a jitter
attenuated version of the 1.544 MHz or 2.048 MHz receive clock. BTCLK[x] is pulsed for each bit
in the 193 bit T1 frame or for each bit in the 256 bit E1 frame. The backplane transmit data is
sampled from BTPCM[x], the backplane transmit signaling is sampled from BRSIG[x], and the
backplane transmit frame alignment is indicated by BTFP[x].
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
54
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Figure 16:
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- Transmit Clock Master: Nx64Kbit/s
CTCLK
BTPCM[1:4]
BTSIG[1:4]
BTFP[1:4]
BTCLK[1:4]
Receive CLK[1:4]
BTIF
Backplane
Transmit
System
Interface
T1-XBAS/E1-TRAN
BasicTransmitter:
Frame Generation,
Alarm Insertion,
Signaling Insertion,
Trunk Conditioning
Line Coding
TJAT
Digital PLL
Transmit CLK[1:4]
Transmit Data[1:4]
TRANSMITTER
BTPCM[x], BTSIG[x],
BTFP[x] Timed to
gapped BTCLK[x]
In Transmit Clock Master: Nx64Kbit/s mode, BTCLK[x] is gapped on a per-DS0 basis so that a
subset of the 24 channels in a T1 frame or 32 timeslots in an E1 frame are inserted on BTPCM[x].
BTFP[x] indicates frame alignment but, in T1 mode, has no clock since it is gapped during the
framing bit positions. Channel insertion is controlled by the IDLE_CHAN bits in the TPSC block’s
Backplane Transmit Control Bytes. The framing bit position is always gapped, so the number of
BTCLK[x] pulses is controllable from 0 to 192 pulses per T1 frame or 0 to 256 pulses per E1
frame on a per-DS0 basis. The parity functions are not usable in Nx64Kbit/s mode.
Figure 17:
- Transmit Clock Master: Clear Channel
CTCLK
Receive CLK[1:4]
BTPCM[1:4]
TJAT
Digital PLL
BTIF
Backplane
Transmit
System
Interface
BTCLK[1:4]
BTPCM[x] Timed
to BTCLK[x]
Transmit CLK[1:4]
Transmit Data[1:4]
TRANSMITTER
Transmit Clock Master: Clear Channel mode has no frame alignment therefore no frame
alignment is indicated to the upstream device. BTCLK[x] is a continuous clock at 1.544 Mbit/s for
T1 links or 2.048 Mbit/s for E1 links.
Figure 18:
- Transmit Clock Slave: Full T1/E1
TRANSMITTER
BTCLK[1:4]
BTFP[1:4]
BTSIG[1:4]
BTPCM[1:4]
BTIF
Backplane
Transmit
System
Interface
T1-XBAS/E1-TRAN
BasicTransmitter:
Frame Generation,
Alarm Insertion,
Signaling Insertion,
Trunk Conditioning
Line Coding
TJAT
Digital PLL
TJAT
FIFO
Transmit CLK[1:4]
Transmit Data[1:4]
BTPCM[x], BTSIG[x]
Timed to BTCLK[x]
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
55
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
In Transmit Clock Slave: Full T1/E1 mode, the backplane transmit interface is clocked by the
backplane transmit clock (BTCLK[x]). The transmitter is either frame-aligned or superframealigned to the backplane transmit frame pulse (BTFP[x]). BTFP[x] is configurable to indicate the
frame alignment or the superframe alignment of BTPCM[x]. BTSIG[x] contain the signaling data to
be inserted into Transmit Data[x], with the four least significant bits of each channel on BTSIG[x]
representing the signaling state (ABCD or ABAB). BTCLK[x] can be enabled to be either a 1.544
MHz clock for T1 links or a 2.048 MHz clock for T1 and E1 links.
Figure 19:
- Transmit Clock Slave: Clear Channel
BTPCM[x] Timed
to BTCLK[x]
BTCLK[1:4]
BTPCM[1:4]
TRANSMITTER
TJAT
Digital PLL
BTIF
Backplane
Transmit
System
Interface
TJAT
FIFO
Transmit CLK[1:4]
Transmit Data[1:4]
In Transmit Clock Slave: Clear Channel mode, the backplane transmit interface is clocked by the
externally provided backplane transmit clock (BTCLK[x]). BTCLK[x] must be a 1.544 MHz clock
for T1 links or a 2.048 MHz clock for E1 links. The Transmit Clock[x] is a jitter attenuated version
of BTCLK[x].
Figure 20:
- Transmit Clock Slave: H-MVIP
TRANSMITTER
CMV8MCLK
CMVFPC
CMVFPB
MVBTD
CCSBTD
CASBTD
BTIF
Backplane
Transmit
System
Interface
T1-XBAS/E1-TRAN
BasicTransmitter:
Frame Generation,
Alarm Insertion,
Signaling Insertion,
Trunk Conditioning
Line Coding
TJAT
Digital PLL
TJAT
FIFO
Transmit CLK[1:4]
Transmit Data[1:4]
Inputs Timed
to CMV8MCLK
When Transmit Clock Slave: H-MVIP mode is enabled, a 8.192 Mbit/s H-MVIP backplane transmit
interface multiplexes up to 128 channels from 4 T1’s or E1’s, up to 128 Channel Associated
Signaling (CAS) channels from 4 T1’s or E1’s and Common Channel Signaling (CCS) from up to
4 T1’s or E1’s. The H-MVIP interface uses common clocks, CMV8MCLK and CMVFPC, and
frame pulse, CMVFPB, for synchronization.
The H-MVIP data signal, MVBTD, provides H-MVIP access to 128 data channels.
A separate H-MVIP signal, CASBTD, provides access to the Channel Associated Signaling (CAS)
for 128 channels. The CAS H-MVIP signal is time division multiplexed exactly the same way as
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
56
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
the data channels and should be synchronized with the H-MVIP data channels. Over a T1 or E1
multi-frame the four CAS bits per channel are repeated with each data byte. Four stuff bits are
used to pad each CAS nibble (ABCD bits) out to a full byte in parallel with each data byte.
The third H-MVIP signal, CCSBTD, is used to time division multiplex the Common Channel
Signaling (CCS) for all 4 T1’s and E1’s plus V5.1 and V5.2 channels in E1 mode.
Figure 21:
- Transmit Clock Slave: Full T1/E1 with CCS H-MVIP
TRANSMITTER
BTPCM[x], BTSIG[x]
Timed to BTCLK[x]
BTCLK[1:4]
BTFP[1:4]
BTSIG[1:4]
BTPCM[1:4]
BTIF
Backplane
Transmit
System
Interface
T1-XBAS/E1-TRAN
BasicTransmitter:
Frame Generation,
Alarm Insertion,
Signaling Insertion,
Trunk Conditioning
Line Coding
TJAT
Digital PLL
TJAT
FIFO
Transmit CLK[1:4]
Transmit Data[1:4]
CMV8MCLK
CMVFPC
CMVFPB
CCS ELST
Elastic
Store
CCSBTD
CCSBTDTimed
to CMV8MCLK
Transmit Clock Slave: Full T1/E1 with CCS H-MVIP mode is the same as Transmit Clock Slave:
Full T1/E1 mode except that Common Channel Signaling (CCS) is inserted into the transmit
stream via an H-MVIP interface. The CCSBTD H-MVIP signal is used to time division multiplex
the Common Channel Signaling (CCS) for all 4 T1’s and E1’s plus V5.1 and V5.2 channels in E1
mode. The H-MVIP interface use common clocks, CMV8MCLK and CMVFPC, and frame pulse,
CMVFPB, for synchronization.
BTCLK[x] may optionally be configured as clock master. This is represented with the above figure
but with BTCLK[x] being driven by the COMET-QUAD rather than being an input.
9.20 Transmit Per-Channel Serial Controller (TPSC)
The Transmit Per-Channel Serial Controller allows data and signaling trunk conditioning or idle
code to be applied on the transmit DS-1 stream on a per-channel basis. It also allows per-channel
control of zero code suppression, data inversion, channel loopback (from the backplane receive
stream), channel insertion, and the detection or generation of pseudo-random or repetitive
patterns.
The TPSC interfaces directly to the E1-TRAN and T1-XBAS block and provides serial streams for
signaling control, idle code data and backplane transmit data control.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
57
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
9.21 Transmit Elastic Store (TX-ELST)
The Transmit Elastic Store (TX-ELST) provides the ability to decouple the line timing from the
backplane timing. The TX-ELST is required whenever the backplane and lineside clocks are not
traceable to a common source.
When the elastic store is being used, if the average frequency of the backplane data is greater
than the average frequency of the line clock, the buffer will fill. Under this condition a controlled
slip will occur upon the next frame boundary. The following frame of PCM data will be deleted.
If the average frequency of the backplane data is less than the average frequency of the line
clock, the buffer will empty. Under this condition a controlled slip will occur upon the next frame
boundary. The last frame will be repeated.
A slip operation is always performed on a frame boundary. The TX-ELST is upstream of the
frame overhead insertion; therefore, frame slips do not corrupt the frame alignment signal.
When the line timing is derived from CTCLK or BTCLK is an output, the elastic store is bypassed
to eliminate the one frame delay.
9.22 T1 Basic Transmitter (T1-XBAS)
The T1 Basic Transmitter (T1-XBAS) block generates the 1.544 Mbit/s T1 data stream according
to SF or ESF frame formats.
In concert with the Transmit Per-Channel Serial Controller (TPSC), the T1-XBAS block, provides
per-channel control of idle code substitution, data inversion (either all 8 bits, sign bit magnitude or
magnitude only), and zero code suppression. Three types of zero code suppression (GTE, Bell
and "jammed bit 8") are supported and selected on a per-channel basis to provide minimum ones
density control. An internal signaling control stream provides per-channel control of robbed bit
signaling and selection of the signaling source. All channels can be forced into a trunk
conditioning state (idle code substitution and signaling conditioning) by use of the Master Trunk
Conditioning bit in the Configuration Register.
A data link is provided for ESF mode. The data link sources include bit oriented codes and HDLC
messages. Support is provided for the transmission of framed or unframed Inband Code
sequences and transmission of AIS or Yellow alarm signals for all formats.
The transmitter can be disabled for framing via the disable bit in the Transmit Functions Enable
register. When transmitting ESF formatted data, the framing bit, datalink bit, or the CRC-6 bit from
the backplane transmit stream can be by-passed to the output PCM stream. Finally, the
transmitter can be by-passed completely to provide an unframed operating mode.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
58
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
9.23 E1 Transmitter (E1-TRAN)
The E1 Transmitter (E1-TRAN) generates a 2048 kbit/s data stream according to ITU-T
recommendations, providing individual enables for frame generation, CRC multiframe generation,
and channel associated signaling (CAS) multiframe generation.
In concert with Transmit Per-Channel Serial Controller (TPSC), the E1-TRAN block provides pertimeslot control of idle code substitution, data inversion, digital milliwatt substitution, selection of
the signaling source and CAS data. All timeslots can be forced into a trunk conditioning state (idle
code substitution and signaling substitution) by use of the master trunk conditioning bit in the
Configuration Register.
Common Channel Signaling (CCS) is supported in timeslot 16 through the Transmit Channel
Insertion (TXCI) block. Support is provided for the transmission of AIS and TS16 AIS, and the
transmission of remote alarm (RAI) and remote multiframe alarm signals.
The National Use bits (Sa-bits) can be sourced from the E1-TRAN National Bits Codeword
registers as 4-bit codewords aligned to the submultiframe. Alternatively, the Sa-bits may
individually carry data links sourced from the internal HDLC controller, or may be passed
transparently from the BTPCM[x] input.
9.24 T1 Inband Loopback Code Generator (XIBC)
The T1 Inband Loopback Code Generator (XIBC) block generates a stream of inband loopback
codes (IBC) to be inserted into a T1 data stream. The IBC stream consists of continuous
repetitions of a specific code and can be either framed or unframed. When the XIBC is enabled
to generate framed IBC, the framing bit overwrites the inband code pattern. The contents of the
code and its length are programmable from 3 to 8 bits. The XIBC interfaces directly to the T1XBAS Basic Transmitter block.
9.25 Pulse Density Enforcer (XPDE)
The Pulse Density Enforcer function is provided by the XPDE block. Pulse density enforcement is
enabled by a register bit within the XPDE.
This block monitors the digital output of the transmitter and detects when the stream is about to
violate the ANSI T1.403 12.5% pulse density rule over a moving 192-bit window. If a density
violation is detected, the block can be enabled to insert a logic 1 into the digital stream to ensure
the resultant output no longer violates the pulse density requirement. When the XPDE is disabled
from inserting logic 1s, the digital stream from the transmitter is passed through unaltered.
9.26 T1 Signaling Aligner (SIGA)
When enabled, the Signaling Aligner is positioned in the backplane transmit path before the T1XBAS. Its purpose is to ensure that, if the signaling on BTSIG[x] is changed in the middle of a
superframe, the T1-XBAS completes transmitting the signalling bits (the A,B,C, and D bits in ESF
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
59
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
mode, the A and B bits in SF mode) for the current superframe before switching to the new
values. This permits signaling integrity to be preserved independent of the superframe alignment
of the T1-XBAS or the signaling data source.
9.27 Bit Oriented Code Generator (XBOC)
The Bit Oriented Code Generator function is provided by the XBOC block. This block transmits
63 of the possible 64 bit oriented codes in the Facility Data Link (FDL) channel in ESF framing
format, as defined in ANSI T1.403-1989. The 64th code (111111) is similar to the HDLC Flag
sequence and is used in the XBOC to disable transmission of any bit oriented codes. When
transmission is disabled the FDL channel is set to all ones.
Bit oriented codes are transmitted on the T1 Facility Data Link channel as a 16-bit sequence
consisting of 8 ones, a zero, 6 code bits, and a trailing zero (111111110xxxxxx0) which is repeated
as long as the code is not 111111. When driving the T1 facility data link the transmitted bit
oriented codes have priority over any data transmitted except for ESF Yellow Alarm. The code to
be transmitted is programmed by writing to the XBOC code registers when it is held until the last
code has been transmitted at least 10 times. An interrupt or polling mechanism is used to
determine when the most recent code written the XBOC register is being transmitted and a new
code can be accepted.
9.28 HDLC Transmitter (TDPR)
The HDLC Transmitter (TDPR) provides a serial data link in the T1 4 kHz ESF facility data link, E1
Sa-bit data link, or in any arbitrary timeslot (T1 or E1). The TDPR is used under microprocessor
control to transmit HDLC data frames. It performs all of the data serialization, CRC generation,
zero-bit stuffing, as well as flag, and abort sequence insertion. Upon completion of the message,
a CRC-CCITT frame check sequence (FCS) may be appended, followed by flags. If the TDPR
transmit data FIFO underflows, an abort sequence is automatically transmitted.
When enabled, the TDPR continuously transmits the flag sequence (01111110) until data is ready
to be transmitted. Data bytes to be transmitted are written into the Transmit Data Register. The
TDPR performs a parallel-to-serial conversion of each data byte before transmitting it.
The default procedure provides automatic transmission of data once a complete packet is written.
All complete packets of data will be transmitted. After the last data byte of a packet, the CRC
word (if CRC insertion has been enabled) and a flag, or just a flag (if CRC insertion has not been
enabled) is transmitted. The TDPR then returns to the transmission of flag characters until the
next packet is available for transmission. While working in this mode, the user must only be
careful to avoid overfilling the FIFO; underruns cannot occur unless the packet is greater than 128
bytes long. The TDPR will force transmission if the FIFO is filled up regardless of whether or not
the packet has been completely written into the FIFO.
The second procedure transmits data only when the FIFO depth has reached a user configured
upper threshold. The TDPR will continue to transmit data until the FIFO depth has fallen below
the upper threshold and the transmission of the last packet with data above the upper threshold
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
60
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
has completed. In this mode, the user must be careful to avoid overruns and underruns. An
interrupt can be generated once the FIFO depth has fallen below a user configured lower
threshold as an indicator for the user to write more data.
Interrupts can also be generated if the FIFO underflows while transmitting a packet, when the
FIFO falls below a lower threshold, when the FIFO is full, or if the FIFO is overrun.
If there are more than five consecutive ones in the raw transmit data or in the CRC data, a zero is
stuffed into the serial data output. This prevents the unintentional transmission of flag or abort
sequences.
Abort characters can be continuously transmitted at any time by setting a control bit. During
packet transmission, an underrun situation can occur if data is not written to the TDPR Transmit
Data register before the previous byte has been depleted. In this case, an abort sequence is
transmitted, and the controlling processor is notified via the UDRI interrupt.
Before enabling TDPR transmission, the XBOC must first be disabled by programming the XBOC
Code register to an all-ones code.
9.29 Transmit Jitter Attenuator (TJAT)
The Transmit Jitter Attenuation function is provided by a digital phase lock loop and 80-bit deep
FIFO. The TJAT receives jittery, dual-rail data in NRZ format on two separate inputs, which allows
bipolar violations to pass through the block uncorrected. The incoming data streams are stored in
a FIFO timed to the transmit clock (either CTCLK or the recovered clock). The respective input
data emerges from the FIFO timed to the jitter attenuated clock (Transmit clock) referenced to
either CTCLK, BTCLK[x], or the recovered clock.
The jitter attenuator generates the jitter-free 1.544 MHz or 2.048 MHz Transmit clock output
transmit clock by adjusting Transmit clock's phase in 1/96 UI increments to minimize the phase
difference between the generated Transmit clock and input data clock to TJAT (either CTCLK or
the recovered clock). Jitter fluctuations in the phase of the input data clock are attenuated by the
phase-locked loop within TJAT so that the frequency of Transmit clock is equal to the average
frequency of the input data clock. For T1 applications, to best fit the jitter attenuation transfer
function recommended by TR 62411, phase fluctuations with a jitter frequency above 5.7 Hz are
attenuated by 6 dB per octave of jitter frequency. Wandering phase fluctuations with frequencies
below 5.7 Hz are tracked by the generated Transmit clock. In E1 applications, the corner
frequency is 7.6 Hz. To provide a smooth flow of data out of TJAT, Transmit clock is used to read
data out of the FIFO.
If the FIFO read pointer (timed to Transmit clock) comes within one bit of the write pointer (timed
to the input data clock, CTCLK or RSYNC), TJAT will track the jitter of the input clock. This
permits the phase jitter to pass through unattenuated, inhibiting the loss of data.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
61
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Jitter Characteristics
The TJAT Block provides excellent jitter tolerance and jitter attenuation while generating minimal
residual jitter. It can accommodate up to 61 UIpp of input jitter at jitter frequencies above 5.7 Hz
(7.6 Hz for E1). For jitter frequencies below 5.7 Hz (7.6 Hz for E1), more correctly called wander,
the tolerance increases 20 dB per decade. In most applications the TJAT Block will limit jitter
tolerance at lower jitter frequencies only. For high frequency jitter, above 10 kHz for example,
other factors such as clock and data recovery circuitry may limit jitter tolerance and must be
considered. For low frequency wander, below 10 Hz for example, other factors such as slip buffer
hysteresis may limit wander tolerance and must be considered. The TJAT block meets the
stringent low frequency jitter tolerance requirements of AT&T TR 62411 and thus allows
compliance with this standard and the other less stringent jitter tolerance standards cited in the
references.
The corner frequency in the jitter transfer response can be altered through programming.
TJAT exhibits negligible jitter gain for jitter frequencies below 5.7 Hz (7.6 Hz for E1), and
attenuates jitter at frequencies above 5.7 Hz (7.6 Hz for E1) by 20 dB per decade. In most
applications, the TJAT block will determine jitter attenuation for higher jitter frequencies only.
Wander, below 10 Hz for example, will essentially be passed unattenuated through TJAT. Jitter,
above 10 Hz for example, will be attenuated as specified, however, outgoing jitter may be
dominated by the generated residual jitter in cases where incoming jitter is insignificant. This
generated residual jitter is directly related to the use of a 1/96 UI phase adjustment quantum.
TJAT meets the jitter attenuation requirements of AT&T TR 62411. The block allows the implied
jitter attenuation requirements for a TE or NT1 given in ANSI Standard T1.408, and the implied
jitter attenuation requirements for a type II customer interface given in ANSI T1.403 to be met.
Jitter Tolerance
Jitter tolerance is the maximum input phase jitter at a given jitter frequency that a device can
accept without exceeding its linear operating range, or corrupting data. For TJAT, the input jitter
tolerance is 61 Unit Intervals peak-to-peak (UIpp) with a worst case frequency offset of 354 Hz. It
is 80 UIpp with no frequency offset. The frequency offset is the difference between the frequency
of XCLK and that of the input data clock.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
62
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Figure 22:
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- TJAT Jitter Tolerance
100
JAT
MIN.TOLER
ANCE
28
JITTER
AMPLITUDE,
UI pp
10
1.0
61
acceptable
0.4
unacceptable
0.1
0.01
1
10
100
1k
10k
100k
JITTER FREQUENCY, Hz
The accuracy of the XCLK frequency and that of the TJAT PLL reference input clock used to
generate the jitter-free Transmit clock output have an effect on the minimum jitter tolerance.
Given that the TJAT PLL reference clock accuracy can be ±200 Hz and that the XCLK input
accuracy can be ±100 ppm, the minimum jitter tolerance for various differences between the
frequency of PLL reference clock and XCLK are shown in Figure 23.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
63
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Figure 23:
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- TJAT Minimum Jitter Tolerance vs. XCLK Accuracy
70
68
66
65
JAT MIN.
JITTER
TOLERANCE, 60
UI pp
61
55
MAX. FREQUENCY
100
OFFSET
XCLK ACCURACY
200
250
0
32
300
354
100
Hz
,± ppm
Jitter Transfer
For T1 applications, the output jitter for jitter frequencies from 0 to 5.7 Hz (7.6 Hz for E1) is no
more than 0.1 dB greater than the input jitter, excluding residual jitter. Jitter frequencies above
5.7 Hz (7.6 Hz for E1) are attenuated at a level of 6 dB per octave, as shown in Figure 24. The
figure is valid for the case where the N1 = 2FH in the TJAT Jitter Attenuator Divider N1 Control
register and N2 = 2FH in the TJAT Divider N2 Control register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
64
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Figure 24:
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- TJAT Jitter Transfer
0
-10
62411
max
62411
min
JITTER -20
GAIN
dB
-30
43802
max
JAT
response
-40
-50
1
5.7
10
100
1k
10k
JITTER FREQUENCY
Hz
T1
In the non-attenuating mode, when the FIFO is within one UI of overrunning or under running, the
tracking range is 1.48 MHz to 1.608 MHz.
The guaranteed linear operating range for the jittered input clock is 1.544 MHz ± 200 Hz with
worst case jitter (61 UIpp), and maximum system clock frequency offset (± 100 ppm). The
nominal range is 1.544 MHz ± 963 Hz with no jitter or system clock frequency offset.
E1
In the non-attenuating mode, when the FIFO is within one UI of overrunning or under running, the
tracking range is 2.13 MHz to 1.97 MHz.
The guaranteed linear operating range for the jittered input clock is 2.048 MHz ± 300 Hz with
worst case jitter (61 UIpp), and maximum system clock frequency offset (± 100 ppm). The
nominal range is 2.048 MHz ± 1277 Hz with no jitter or system clock frequency offset.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
65
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Jitter Generation
In the absence of input jitter, the output jitter shall be less than 0.025 UIpp. This complies with the
AT&T TR 62411 requirement of less than 0.025 UIpp of jitter generation.
9.30 Line Transmitter
The line transmitter generates Alternate Mark Inversion (AMI) transmit pulses suitable for use in
the DSX-1 (short haul T1), short haul E1, long haul T1 and long haul E1 environments. The
voltage pulses are produced by applying a current to a known termination (termination resistor
plus line impedance). The use of current (instead of a voltage driver) simplifies transmit Input
Return Loss (IRL), transmit short circuit protection (none needed) and transmit tri-stating.
The output pulse shape is synthesized digitally with current digital-to-analog (DAC) converters,
which produce 24 samples per symbol. The current DAC’s produce differential bipolar outputs
that directly drive the TXTIP1[x], TXTIP2[x] TXRING1[x], and TXRING2[x] pins. The current
output is applied to a terminating resistor and line-coupling transformer in a differential manner,
which when viewed from the line side of the transformer produce the output pulses at the required
levels and insures a small positive to negative pulse imbalance.
The pulse shape is user programmable. For T1 short haul, the cable length between the COMETQUAD and the cross-connect (where the pulse template specifications are given) greatly affects
the resulting pulse shapes. Hence, the data applied to the converter must account for different
cable lengths. For CEPT E1 applications the pulse template is specified at the transmitter, thus
only one setting is required. For T1 long haul with a LBO of 7.5 dB the previous bits effect what
the transmitter must drive to compensate for inter-symbol interference; for LBO’s of 15 dB or
22.5 dB the previous 3 or 4 bits effect what the transmitter must send out.
Refer to the Operation section for details on creating the synthesized pulse shape.
9.31 Timing Options (TOPS)
The Timing Options block provides a means of selecting the source of the internal input clock to
the TJAT block, and the reference clock for the TJAT digital PLL.
9.32 JTAG Test Access Port
The JTAG Test Access Port block provides JTAG support for boundary scan. The standard JTAG
EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST instructions are supported.
9.33 Microprocessor Interface
The Microprocessor Interface Block provides normal and test mode registers, the interrupt logic,
and the logic required to connect to the Microprocessor Interface. The normal mode registers are
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
66
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
required for normal operation, and test mode registers are used to enhance the testability of the
COMET-QUAD.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
67
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
10
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
NORMAL MODE REGISTER DESCRIPTION
Normal mode registers are used to configure and monitor the operation of the COMET-QUAD.
The Register Memory Map in Table 4 below shows where the normal mode registers are
accessed. The registers are organized so that backward software compatibility with existing PMC
devices is optimized. The COMET-QUAD contains 1 set of master configuration, H-MVIP, and
CSU registers and 4 sets of T1/E1 Framer registers. Where only 1 set is present, the registers
apply to the entire device. Where 4 sets are present, the registers apply to a single quadrant of
the COMET-QUAD. By convention, where 4 sets of registers are present, address space 000H –
0FFH applies to quadrant #1, 100H – 1FFH applies to quadrant #2, 200H – 2FFH applies to
quadrant #3, and 300H – 3FFH applies to quadrant #4.
On reset the COMET-QUAD defaults to T1 mode. For proper operation some register
configuration is expected. System side access defaults to the serial clock and data signals. By
default interrupts will not be enabled, and automatic alarm generation is disabled.
Notes on Normal Mode Register Bits:
1. Writing values into unused register bits has no effect. Reading back unused bits can produce
either a logic 1 or a logic 0; hence, unused register bits should be masked off by software
when read.
2. All configuration bits that can be written into can also be read back. This allows the processor
controlling the COMET-QUAD to determine the programming state of the chip.
3. Writeable normal mode register bits are cleared to zero upon reset unless otherwise noted.
4. Writing into read-only normal mode register bit locations does not affect COMET-QUAD
operation unless otherwise noted.
5. Certain register bits are reserved. These bits are associated with functions that are unused in
this application. To ensure that the COMET-QUAD operates as intended, reserved register
bits must only be written with their default values unless otherwise stated. Similarly, writing to
reserved registers should be avoided unless otherwise stated.
10.1 Normal Mode Register Memory Map
Table 4 - Normal Mode Register Memory Map
Addr
Addr
Addr
Addr
Register
000H
100H
200H
300H
Global Configuration
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
68
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Addr
Addr
Addr
Addr
Register
001H
101H
201H
301H
Clock Monitor
002H
102H
202H
302H
Receive Options
003H
103H
203H
303H
Receive Line Interface Configuration
004H
104H
204H
304H
Transmit Line Interface Configuration
005H
105H
205H
305H
Transmit Framing and Bypass Options
006H
106H
206H
306H
Transmit Timing Options
007H
107H
207H
307H
Interrupt Source #1
008H
108H
208H
308H
Interrupt Source #2
009H
109H
209H
309H
Interrupt Source #3
00AH
10AH
20AH
30AH
Master Diagnostics
00BH
Master Test
10BH
20BH
30BH
Reserved
00CH
10CH
20CH
30CH
Reserved
00DH
10DH
20DH
30DH
Revision/Chip ID/Quadrant PMON Update
00EH
Reset
10EH
20EH
30EH
Reserved
00FH
10FH
20FH
30FH
PRBS Positioning/Control and HDLC Control
010H
110H
210H
310H
CDRC Configuration
011H
111H
211H
311H
CDRC Interrupt Enable
012H
112H
212H
312H
CDRC Interrupt Status
013H
113H
213H
313H
CDRC Alternate Loss of Signal
014H
114H
214H
314H
RJAT Interrupt Status
015H
115H
215H
315H
RJAT Reference Clock Divisor (N1) Control
016H
116H
216H
316H
RJAT Output Clock Divisor (N2) Control
017H
017H
217H
317H
RJAT Configuration
018H
118H
218H
318H
TJAT Interrupt Status
019H
119H
219H
319H
TJAT Reference Clock Divisor (N1) Control
01AH
11AH
21AH
31AH
TJAT Output Clock Divisor (N2) Control
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
69
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Addr
Addr
Addr
Addr
Register
01BH
11BH
21BH
31BH
TJAT Configuration
01CH
11CH
21CH
31CH
RX-ELST Configuration
01DH
11DH
21DH
31DH
RX-ELST Interrupt Enable/Status
01EH
11EH
21EH
31EH
RX-ELST Idle Code
01FH
11FH
21FH
31FH
RX-ELST Reserved
020H
120H
220H
320H
TX-ELST Configuration
021H
121H
221H
321H
TX-ELST Interrupt Enable/Status
022H023H
122H123H
222H223H
322H323H
TX-ELST Reserved
024H027H
124H127H
224H227H
324H327H
Reserved
028H
128H
228H
328H
RXCE Receive Data Link Control
029H
129H
229H
329H
RXCE Receive Data Link Bit Select
02AH02FH
12AH12FH
22AH22FH
032AH
-32FH
RXCE Reserved
030H
130H
230H
330H
BRIF Receive Backplane Configuration
031H
131H
231H
331H
BRIF Receive Backplane Frame Pulse Configuration
032H
132H
232H
332H
BRIF Receive Backplane Parity/F-Bit Configuration
033H
133H
233H
333H
BRIF Receive Backplane Timeslot Offset
034H
134H
234H
334H
BRIF Receive Backplane Bit Offset
035H037H
135H137H
235H237H
335H337H
BRIF Receive Backplane Reserved
038H
138H
238H
338H
TXCI Transmit Data Link Control
039H
139H
239H
339H
TXCI Transmit Data Link Bit Select
03AH03FH
13AH13FH
23AH23FH
033AH
-33FH
TXCI Reserved
040H
140H
240H
340H
BTIF Transmit Backplane Configuration
041H
141H
241H
341H
BTIF Transmit Backplane Frame Pulse Configuration
042H
142H
242H
342H
BTIF Transmit Backplane Parity Configuration and Status
043H
143H
243H
343H
BTIF Transmit Backplane Timeslot Offset
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
70
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Addr
Addr
Addr
Addr
Register
044H
144H
244H
344H
BTIF Transmit Backplane Bit Offset Register
045H047H
145H147H
245H247H
345H347H
BTIF Transmit Backplane Reserved
048H
148H
248H
348H
T1-FRMR Configuration
049H
149H
249H
349H
T1-FRMR Interrupt Enable
04AH
14AH
24AH
34AH
T1-FRMR Interrupt Status
04BH
14BH
24BH
34BH
Reserved
04CH
14CH
24CH
34CH
IBCD Configuration
04DH
14DH
24DH
34DH
IBCD Interrupt Enable/Status
04EH
14EH
24EH
34EH
IBCD Activate Code
04FH
14FH
24FH
34FH
IBCD Deactivate Code
050H
150H
250H
350H
SIGX Configuration/Change of Signaling State
051H
151H
251H
351H
SIGX µP Access Status/Change of Signaling State
052H
152H
252H
352H
SIGX Channel Indirect Address/Control/ Change of Signaling
State
053H
153H
253H
353H
SIGX Channel Indirect Data Buffer/Change of Signaling
State
054H
154H
254H
354H
T1 XBAS Configuration
055H
155H
255H
355H
T1 XBAS Alarm Transmit
056H
156H
256H
356H
T1 XIBC Control
057H
157H
257H
357H
T1 XIBC Loopback Code
058H
158H
258H
358H
PMON Interrupt Enable/Status
059H
159H
259H
359H
PMON Framing Bit Error Count
05AH
15AH
25AH
35AH
PMON OOF/COFA/Far End Block Error Count (LSB)
05BH
15BH
25BH
35BH
PMON OOF/COFA/Far End Block Error Count (MSB)
05CH
15CH
25CH
35CH
PMON Bit Error/CRCE Count (LSB)
05DH
15DH
25DH
35DH
PMON Bit Error/CRCE Count (MSB)
05EH
15EH
25EH
35EH
PMON LCV Count (LSB)
05FH
15FH
25FH
35FH
PMON LCV Count (MSB)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
71
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Addr
Addr
Addr
Addr
Register
060H
160H
260H
360H
T1 ALMI Configuration
061H
161H
261H
361H
T1 ALMI Interrupt Enable
062H
162H
262H
362H
T1 ALMI Interrupt Status
063H
163H
263H
363H
T1 ALMI Alarm Detection Status
064H
164H
264H
364H
T1 PDVD Reserved
065H
165H
265H
365H
T1 PDVD Interrupt Enable/Status
066H
166H
266H
366H
T1 XBOC Control
067H
167H
267H
367H
T1 XBOC Code
068H
168H
268H
368H
T1 XPDE Reserved
069H
169H
269H
369H
T1 XPDE Interrupt Enable/Status
06AH
16AH
26AH
36AH
T1 RBOC Enable
06BH
16BH
26BH
36BH
T1 RBOC Code Status
06CH
16CH
26CH
36CH
TPSC Configuration
06DH
16DH
26DH
36DH
TPSC µP Access Status
06EH
16EH
26EH
36EH
TPSC Channel Indirect Address/Control
06FH
16FH
26FH
36FH
TPSC Channel Indirect Data Buffer
070H
170H
270H
370H
RPSC Configuration
071H
171H
271H
371H
RPSC µP Access Status
072H
172H
272H
372H
RPSC Channel Indirect Address/Control
073H
173H
273H
373H
RPSC Channel Indirect Data Buffer
074H077H
174H177H
274H277H
374H377H
Reserved
078H
178H
278H
378H
T1 APRM Configuration/Control
079H
179H
279H
379H
T1 APRM Reserved
07AH
17AH
27AH
37AH
T1 APRM Interrupt Status
07BH
17BH
27BH
37BH
T1 APRM One Second Content Octet 2
07CH
17CH
27CH
37CH
T1 APRM One Second Content Octet 3
07DH
17DH
27DH
37DH
T1 APRM One Second Content Octet 4
07EH
17EH
27EH
37EH
T1 APRM One Second Content MSB (Octet 5)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
72
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Addr
Addr
Addr
Addr
Register
07FH
17FH
27FH
37FH
T1 APRM One Second Content LSB (Octet 6)
080H
180H
280H
380H
E1-TRAN Configuration
081H
181H
281H
381H
E1-TRAN Transmit Alarm/Diagnostic Control
082H
182H
282H
382H
E1-TRAN International Control
083H
183H
283H
383H
E1-TRAN Extra Bits Control
084H
184H
284H
384H
E1-TRAN Interrupt Enable
085H
185H
285H
385H
E1-TRAN Interrupt Status
086H
186H
286H
386H
E1-TRAN National Bit Codeword Select
087H
187H
287H
387H
E1-TRAN National Bit Codeword
088H08BH
188H18BH
288H28BH
388H38BH
Reserved
08CH08DH
18CH18DH
28CH28DH
38CH38DH
T1-FRMR Reserved
08EH08FH
18EH18FH
28EH28FH
38EH38FH
Reserved
090H
190H
290H
390H
E1-FRMR Frame Alignment Options
091H
191H
291H
391H
E1-FRMR Maintenance Mode Options
092H
192H
292H
392H
E1-FRMR Framing Status Interrupt Enable
093H
193H
293H
393H
E1-FRMR Maintenance/Alarm Status Interrupt Enable
094H
194H
294H
394H
E1-FRMR Framing Status Interrupt Indication
095H
195H
295H
395H
E1-FRMR Maintenance/Alarm Status Interrupt Indication
096H
196H
296H
396H
E1-FRMR Framing Status
097H
197H
297H
397H
E1-FRMR Maintenance/Alarm Status
098H
198H
298H
398H
E1-FRMR International/National Bits
099H
199H
299H
399H
E1-FRMR CRC Error Count - LSB
09AH
19AH
29AH
39AH
E1-FRMR CRC Error Count - MSB
09BH
19BH
29BH
39BH
E1-FRMR National Bit Codeword Interrupt Enables
09CH
19CH
29CH
39CH
E1-FRMR National Bit Codeword Interrupts
09DH
19DH
29DH
39DH
E1-FRMR National Bit Codewords
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
73
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Addr
Addr
Addr
Addr
Register
09EH
19EH
29EH
39EH
E1-FRMR Frame Pulse/Alarm Interrupt Enables
09FH
19FH
29FH
39FH
E1-FRMR Frame Pulse/Alarm Interrupt
0A0H0A7H
1A0H1A7H
2A0H2A7H
3A0H3A7H
Reserved
0A8H
1A8H
2A8H
3A8H
TDPR Configuration
0A9H
1A9H
2A9H
3A9H
TDPR Upper Transmit Threshold
0AAH
1AAH
2AAH
3AAH
TDPR Lower Transmit Threshold
0ABH
1ABH
2ABH
3ABH
TDPR Interrupt Enable
0ACH
1ACH
2ACH
3ACH
TDPR Interrupt Status/UDR Clear
0ADH
1ADH
2ADH
3ADH
TDPR Transmit Data
0AEH0AFH
0AEH1AFH
2AEH2AFH
3AEH3AFH
Reserved
0B0H
1B0H
2B0H
3B0H
RX-ELST CCS Configuration
0B1H
1B1H
2B1H
3B1H
RX-ELST CCS Interrupt Enable/Status
0B2H
1B2H
2B2H
3B2H
RX-ELST CCS Idle Code
0B3H
1B3H
2B3H
3B3H
RX-ELST CCS Reserved
0B4H
1B4H
2B4H
3B4H
TX-ELST CCS Configuration
0B5H
1B5H
2B5H
3B5H
TX-ELST CCS Interrupt Enable/Status
0B6H0B7H
1B6H1B7H
2B6H2B7H
3B6H3B7H
TX-ELST CCS Reserved
0B8H
Receive H-MVIP/CCS Enable
1B8H
2B8H
3B8H
Reserved
0B9H
1B9H
2B9H
3B9H
Transmit H-MVIP/CCS Enable and Configuration
0BAH
1BAH
2BAH
3BAH
Reserved
0BBH
RSYNC Select
1BBH
2BBH
3BBH
0BCH
0BDH0BFH
Reserved
COMET-QUAD Master Interrupt Source
1BCH
2BCH
3BCH
Reserved
1BDH1BFH
2BDH2BFH
3BDH3BFH
Reserved
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
74
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Addr
Addr
Addr
Addr
Register
0C0H
1C0H
2C0H
3C0H
RDLC Configuration
0C1H
1C1H
2C1H
3C1H
RDLC Interrupt Control
0C2H
1C2H
2C2H
3C2H
RDLC Status
0C3H
1C3H
2C3H
3C3H
RDLC Data
0C4H
1C4H
2C4H
3C4H
RDLC Primary Address Match
0C5H
1C5H
2C5H
3C5H
RDLC Secondary Address Match
0C6H0D5H
1C6H1D5H
2C6H2D5H
3C6H3D5H
Reserved
0D6H
CSU Configuration
1D6H
2D6H
3D6H
0D7H
Reserved
CSU Reserved
1D7H
2D7H
3D7H
Reserved
0D8H
1D8H
2D8H
3D8H
RLPS Equalization Indirect Data Register
0D9H
1D9H
2D9H
3D9H
RLPS Equalization Indirect Data Register
0DAH
1DAH
2DAH
3DAH
RLPS Equalization Indirect Data Register
0DBH
1DBH
2DBH
3DBH
RLPS Equalization Indirect Data Register
0DCH
1DCH
2DCH
3DCH
RLPS Equalizer Loop Voltage Reference
0DDH0DFH
1DDH1DFH
2DDH2DFH
3DDH3DFH
RLPS Reserved
0E0H
1E0H
2E0H
3E0H
PRBS Generator/Checker Control
0E1H
1E1H
2E1H
3E1H
PRBS Checker Interrupt Enable/Status
0E2H
1E2H
2E2H
3E2H
PRBS Pattern Select
0E3H
1E3H
2E3H
3E3H
PRBS Reserved
0E4H
1E4H
2E4H
3E4H
PRBS Error Count #1
0E5H
1E5H
2E5H
3E5H
PRBS Error Count #2
0E6H
1E6H
2E6H
3E6H
PRBS Error Count #3
0E7H0EFH
1E7H1EFH
2E7H2EFH
3E7H3EFH
Reserved
0F0H
1F0H
2F0H
3F0H
XLPG Line Driver Configuration
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
75
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Addr
Addr
Addr
Addr
Register
0F1H
1F1H
2F1H
3F1H
Reserved
0F2H
1F2H
2F2H
3F2H
XLPG Pulse Waveform Storage Write Address
0F3H
1F3H
2F3H
3F3H
XLPG Pulse Waveform Storage Data
0F4H
1F4H
2F4H
3F4H
XLPG Configuration #1
0F5H
1F5H
2F5H
3F5H
XLPG Configuration #2
0F6H
1F6H
2F6H
3F6H
XLPG Initialization
0F7H
1F7H
2F7H
3F7H
XLPG Reserved
0F8H
1F8H
2F8H
3F8H
RLPS Configuration and Status
0F9H
1F9H
2F9H
3F9H
RLPS ALOS Detection/Clearance Threshold
0FAH
1FAH
2FAH
3FAH
RLPS ALOS Detection Period
0FBH
1FBH
2FBH
3FBH
RLPS ALOS Clearance Period
0FCH
1FCH
2FCH
3FCH
RLPS Equalization Indirect Address
0FDH
1FDH
2FDH
3FDH
RLPS Equalization Read/WriteB Select
0FEH
1FEH
2FEH
3FEH
RLPS Equalizer Loop Status and Control
0FFH
1FFH
2FFH
3FFH
RLPS Equalizer Configuration
400H-7FFH
Reserved for Test
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
76
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 000H, 100H, 200H, 300H: Global Configuration
Bit
Type
Function
Default
Bit 7
R/W
PIO_OE
0
Bit 6
R/W
PIO
0
Bit 5
R/W
IBCD_IDLE
0
Bit 4
R/W
RSYNC_ALOSB
0
Bit 3
R/W
OOSMFAIS
0
Bit 2
R/W
TRKEN
0
Bit 1
R/W
RXMTKC
0
Bit 0
R/W
E1/T1B
0
PIO_OE:
The programmable I/O output enable, PIO_OE, bit controls the PIO pin. When PIO_OE is
logic 1, the PIO pin is configured as an output and driven by the COMET-QUAD. When
PIO_OE is logic 0, the PIO pin is configured as an input. Upon reset, the PIO pin is
configured as an input.
PIO_OE is only defined for Register 000H. In Registers 100H, 200H, and 300H the bit is
unused, and the Default value is ‘X’.
PIO:
The programmable I/O, PIO, bit controls/reflects the state of the PIO pin. When the PIO pin is
configured as an output, the PIO bit controls the state of the PIO pin. When the PIO pin is
configured as an input, the PIO bit reflects the state of the PIO pin. Upon reset, the PIO pin is
an input.
PIO is only defined for Register 000H. In Registers 100H, 200H, and 300H the bit is unused,
and the Default value is ‘X’.
OOSMFAIS:
In E1 mode, this bit controls the quadrant receive backplane signaling trunk conditioning in an
out of signaling multiframe condition. If OOSMFAIS is set to a logic 0, an OOSMF indication
from the E1-FRMR does not affect the BRSIG[x] or CASBRD output of the quadrant. When
OOSMFAIS is a logic 1, an OOSMF indication from the E1-FRMR will cause the BRSIG[x] or
CASBRD output of the quadrant to be set to all 1's.
RSYNC_ALOSB:
The RSYNC_ALOSB bit controls the source of the loss of signal condition used to control the
behaviour of the receive reference presented on the RSYNC. If RSYNC_ALOSB is a logic 0,
analog loss of signal is used. If RSYNC_ALOSB is a logic 1, digital loss of signal is used.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
77
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
When the COMET-QUAD quadrant is in a loss of signal state, the RSYNC output is derived
from XCLK. When the COMET-QUAD quadrant is not in a loss of signal state, the RSYNC
output is derived from the receive recovered clock of the selected quadrant.
The quadrant becoming the source of RSYNC is configured in the RSYNC Select register.
IBCD_IDLE:
When the IBCD_IDLE bit is set to logic 1, the data to the inband code detector (IBCD) block is
gapped during the framing bit. This allows the IBCD to be used to detect an idle code that is
inserted only in the payload of the receive DS1 PCM stream. The IBCD must still be
programmed to detect the desired pattern, and otherwise operates unchanged. The
IBCD_IDLE bit is only valid in T1 mode.
TRKEN:
The TRKEN bit enables quadrant receive trunk conditioning upon an out of frame condition. If
TRKEN is logic 1, the contents of the RX-ELST Idle Code register are inserted into all data
timeslots (including TS0 and TS16) of BRPCM[x] or MVBRD of the quadrant if the framer is
out-of-basic frame (i.e. the OOF status bit is logic 1). The TRKEN bit only has effect if
RXELSTBYP bit is logic 0. If TRKEN is a logic 0, receive trunk conditioning can still be
performed on a per-timeslot basis via the RPSC Data Trunk Conditioning and Signaling Trunk
Conditioning registers.
RXMTKC:
The RXMTKC bit allows quadrant trunk conditioning to be applied to the received data and
signaling streams, BRPCM[x] or MVBRD, and BRSIG[x] or CASBRD, of the quadrant. When
RXMTKC is set to logic 1, the data on BRPCM[x] or MVBRD for each channel of the quadrant
is replaced with the data contained in the data trunk conditioning registers within RPSC;
similarly, the signaling on BRSIG[x] or CASBRD for each channel of the quadrant is replaced
with the signaling contained in the signaling trunk conditioning registers. When RXMTKC is
set to logic 0, the data and signaling streams are modified on a per-channel basis in
accordance with the control bits contained in the per-channel control registers within the
RPSC.
E1/T1B:
The global E1/T1B bit selects the operating mode of all four of the COMET-QUAD quadrants.
If E1/T1B is logic 1, the 2.048 Mbit/s E1 mode is selected for all four quadrants. If E1/T1B is
logic 0, the 1.544 Mbit/s T1 mode is selected for all four quadrants.
E1/T1B is only defined for Register 000H. In Registers 100H, 200H, and 300H the bit is
unused, and the Default value is ‘X’.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
78
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 001H, 101H, 201H, 301H: Clock Monitor
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
R
XCLKA
X
Bit 3
R
BTCLKA
X
Bit 2
R
CTCLKA
X
Bit 1
R
BRCLKA
X
Unused
X
Bit 0
When a monitored clock signal makes a low to high transition, the corresponding register bit is set
high. The bit will remain high until this register is read, at which point all the bits in this register are
cleared. A lack of transitions is indicated by the corresponding register bit reading low. This
register should be read at periodic intervals to detect clock failures.
XCLKA:
The XCLK active (XCLKA) bit detects for low to high transitions on the XCLK input. XCLKA is
set high on a rising edge of XCLK, and is set low when this register is read.
Note: XCLKA is only defined for register 301H, although it applies to the XCLK source used by
four quadrants. In Registers 001H, 101H, and 201H, the bit is unused and the Default value is
‘X’.
BTCLKA:
The BTCLK active (BTCLKA) bit detects low to high transitions on the BTCLK input. BTCLKA
is set high on a rising edge of BTCLK, and is set low when this register is read.
CTCLKA:
The CTCLK active (CTCLKA) bit detects low to high transitions on the CTCLK input.
CTCLKA is set high on a rising edge of CTCLK, and is set low when this register is read.
BRCLKA:
The BRCLK active (BRCLKA) bit detects low to high transitions on the BRCLK input.
BRCLKA is set high on a rising edge of BRCLK, and is set low when this register is read.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
79
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 002H, 102H, 202H, 302H: Receive Options
Bit
Type
Function
Default
Bit 7
R/W
RJATBYP
1
Bit 6
R/W
UNF
0
Bit 5
R/W
RXELSTBYP
0
Bit 4
R/W
RSYNC_MEM
0
Bit 3
R/W
RSYNCSEL
0
Bit 2
R/W
WORDERR
0
Bit 1
R/W
CNTNFAS
0
Bit 0
R/W
CCOFA
0
This register allows software to configure the receive functions of each framer.
RJATBYP:
The RJATBYP bit disables jitter attenuation in the receive direction. When receive jitter
attenuation is not being used, setting RJATBYP to logic 1 will reduce the latency through the
receiver section by typically 40 bits. When RJATBYP is set to logic 0, the quadrant’s
BRCLK[x] output (if BRCLK[x] is configured to be an output by setting the CMODE bit of the
BRIF Configuration register to logic 0), is jitter attenuated. When the RJAT is bypassed, the
quadrant’s BRCLK[x] is not jitter attenuated. The RSYNC output is jitter attenuated by the
RJAT, regardless of the state of RJATBYP.
Note: In T1 mode, when the framer is enabled (i.e., the UNF bit in the Receive Options
register is logic 0), this bit must be programmed to logic 0.
UNF:
The UNF bit allows the framer to operate with unframed DS-1 or E1 data. When UNF is set
to logic 1, the framer is disabled (both the T1-FRMR and E1-FRMR are held reset) and the
recovered data passes through the receiver section of the framer without frame or channel
alignment. While UNF is set to logic 1, the Alarm Integrator continues to operate and detects
and integrates AIS alarm. When UNF is set to logic 0, the framer operates normally,
searching for frame alignment on the incoming data.
When UNF is a logic 1, the BRFP[x] pin (if configured as an output) is held low.
RXELSTBYP:
The RXELSTBYP bit allows the Receive Elastic Store (RX-ELST) to be bypassed, eliminating
the one frame delay incurred through the RX-ELST. When set to logic 1, the received data
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
80
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
and clock inputs to RX-ELST are internally routed directly to the RX-ELST output. If
RXELSTBYP is logic 1, the CMODE bit of the BRIF Configuration register must be logic 0 and
the FPMODE bit of the BRIF Frame Pulse Configuration register must be logic 0.
In Receive Clock Slave: H-MVIP mode, RXELSTBYP must be programmed to logic 0.
RSYNC_MEM:
The RSYNC_MEM bit controls the quadrant’s RSYNC output under a loss of signal condition
(as determined by the RSYNC_ALOSB register bit). When RSYNC_MEM is a logic 1, the
quadrant’s RSYNC output is held high during a loss of signal condition. When RSYNC_MEM
is a logic 0, the quadrant’s RSYNC output is derived from XCLK during a loss of signal
condition.
RSYNCSEL:
The RSYNCSEL bit selects the frequency of the receive reference presented on the
quadrant’s RSYNC output. If RSYNCSEL is a logic 1, the quadrant’s RSYNC will be an 8 kHz
clock. If RSYNCSEL is a logic 0, the quadrant’s RSYNC will be an 1.544 MHz (T1) or
2.048 MHz (E1) clock.
WORDERR:
In E1 mode, the WORDERR bit determines how frame alignment signal (FAS) errors are
reported. When WORDERR is logic 1, one or more errors in the seven bit FAS word results
in a single framing error count. When WORDERR is logic 0, each error in a FAS word results
in a single framing error count.
CNTNFAS:
In E1 mode, when the CNTNFAS bit is a logic 1, a zero in bit 2 of timeslot 0 of non-frame
alignment signal (NFAS) frames results in an increment of the framing error count. If
WORDERR is also a logic 1, the word is defined as the eight bits consisting of the seven-bit
FAS pattern and bit 2 of timeslot 0 of the next NFAS frame. When the CNTNFAS bit is a
logic 0, only errors in the FAS affect the framing error count.
CCOFA
The CCOFA bit determines whether the PMON counts Change-Of-Frame Alignment (COFA)
events or out of frame (OOF) events. When CCOFA is set to logic 1, COFA events are
counted by PMON. When CCOFA is set to logic 0, OOF events are counted by PMON. The
CCOFA bit is only valid in T1 mode.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
81
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 003H, 103H, 203H, 303H: Receive Line Interface Configuration
Bit
Type
Function
Default
Bit 7
R/W
AUTOYELLOW
0
Bit 6
R/W
AUTORED
0
Bit 5
R/W
AUTOOOF
0
Bit 4
R/W
AUTOAIS
0
Bit 3
R/W
Reserved
0
Bit 2
R/W
BPV
0
Bit 1
R/W
Reserved
0
Bit 0
R/W
Reserved
0
Reserved:
These bits must be a logic 0 for normal operation.
AUTOYELLOW:
In T1 mode, when the AUTOYELLOW bit is set to logic 1, whenever the alarm integrator
declares a Red alarm in the receive direction, Yellow alarm will be transmitted to the far end.
When AUTOYELLOW is set to logic 0, Yellow alarm will only be transmitted when the XYEL
bit is set in the T1-XBAS Alarm Transmit Register. Note that the Red alarm is not deasserted
on detection of AIS.
In E1 mode, when the AUTOYELLOW bit is set to logic 1, the RAI bit in the transmit stream is
set to a logic 1 for the duration of a loss of frame alignment or AIS. The G706ANNBRAI bit of
the Transmit Framing and Bypass Options register optionally also allows for the transmission
of RAI when CRC-to-non-CRC interworking has been established. When AUTOYELLOW is
set to logic 0, RAI will only be transmitted when the RAI bit is set in the E1-TRAN Transmit
Alarm/Diagnostic Control register.
AUTORED:
The AUTORED bit allows quadrant trunk conditioning to be applied to the receive data and
signaling streams, BRPCM[x] or MVBRD, and BRSIG[x] or CASBRD, immediately upon
declaration of Red carrier failure alarm. When AUTORED is set to logic 1, the data on
BRPCM[x] or MVBRD for each channel of the quadrant is replaced with the data contained in
the Data Trunk Conditioning registers within RPSC and the signaling on BRSIG[x] or
CASBRD for each channel of the quadrant is replaced with the signaling contained in the
Signaling Trunk Conditioning registers within the RPSC while Red CFA is declared. When
AUTORED is set to logic 0, the receive data and signaling is not automatically conditioned
when Red CFA is declared.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
82
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
AUTOOOF:
The AUTOOOF bit allows quadrant trunk conditioning to be applied to the receive data
stream, BRPCM[x] or MVBRD of the quadrant, immediately upon declaration of out of frame
(OOF). When AUTOOOF is set to logic 1, while OOF is declared, the data on BRPCM[x] or
MVBRD for each channel of the quadrant is replaced with the data contained in the data trunk
conditioning registers within RPSC. When AUTOOOF is set to logic 0, the receive data
stream, BRPCM[x] or MVBRD of the quadrant, is not automatically conditioned by RPSC
when OOF is declared. However, if the RX-ELST is not bypassed, the RX-ELST trouble code
will still be inserted in channel data while OOF is declared if the TRKEN register bit is logic 1.
RPSC data and signaling trunk conditioning overwrites the RX-ELST trouble code.
AUTOAIS:
If the AUTOAIS bit is logic 1, AIS is inserted in the receive path and the channel associated
signaling is frozen for the duration of a loss of signal condition. (The loss of signal criteria is
configured via the LOS[1:0] bits of the CDRC Configuration register.) If AUTOAIS is logic 0,
AIS may be inserted manually via the RAIS register bit.
BPV:
In T1 mode, the BPV bit enables only bipolar violations to indicate line code violations and be
accumulated in the PMON LCV Count Registers. When BPV is set to logic 1, BPVs (which
are not part of a valid B8ZS signature if B8ZS line coding is used) generate an LCV indication
and increment the PMON LCV counter. When BPV is set to logic 0, both BPVs (which are not
part of a valid B8ZS signature if B8ZS line coding is used) and excessive zeros (EXZ)
generate an LCV indication and increment the PMON LCV counter. Excessive zeros is a
sequence of zeros greater than fifteen bits long for an AMI-coded signal and greater than
seven bits long for a B8ZS-coded signal.
In E1 mode, the BPV bit enables only bipolar violations to indicate line code violations and be
accumulated in the PMON LCV Count registers. (The O162 bit in the CDRC Configuration
register provides two E1 LCV definitions.) When BPV is set to logic 1, BPVs (which are not
part of a valid HDB3 signature if HDB3 line coding is used) generate an LCV indication and
increment the PMON LCV counter. When BPV is set to logic 0, both BPVs (which are not part
of a valid HDB3 signature if HDB3 line coding is used) and excessive zeros (EXZ) generate
an LCV indication and increment the PMON LCV counter. Excessive zeros is a sequence of
zeros greater than four bits long.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
83
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 004H, 104H, 204H, 304H: Transmit Line Interface Configuration
Bit
Type
Function
Default
Bit 7
R/W
TJATBYP
0
Bit 6
R/W
TAISEN
0
Bit 5
R/W
TAUXP
0
Bit 4
R/W
Reserved
0
Bit 3
R/W
Reserved
0
Unused
X
Reserved
0
Unused
X
Bit 2
Bit 1
Bit 0
R/W
Reserved:
These bits must be a logic 0 for normal operation.
TJATBYP:
The TJATBYP bit enables the transmit jitter attenuator's FIFO to be removed from the
transmit data path. When transmit jitter attenuation is not being used, setting TJATBYP to
logic 1 will reduce the latency through the transmitter section by typically 40 bits. Since the
transmit jitter attenuator’s PLL is never bypassed, the PLLREF[1:0] bits of the Transmit Timing
Options register must be configured to reference the transmit line clock regardless of the
value of the TJATBYP bit.
TAISEN:
The TAISEN bit enables the interface to generate an unframed all-ones AIS alarm on the
TXTIP[x] and TXRING[x]. When TAISEN is set to logic 1 the bipolar TXTIP[x] and TXRING[x]
outputs are forced to pulse alternately, creating an all-ones signal. The transition to
transmitting AIS on the TXTIP[x] and TXRING[x] outputs is done in such a way as to not
introduce any bipolar violations.
The diagnostic loopback point is upstream of this AIS insertion point.
TAUXP:
The TAUXP bit enables the interface to generate an unframed alternating zeros and ones (i.e.
010101...) auxiliary pattern (AUXP) on the TXTIP[x] and TXRING[x]. When TAUXP is set to
logic 1 the bipolar TXTIP[x] and TXRING[x] outputs are forced to pulse alternately every other
cycle. The transition to transmitting AUXP on the TXTIP[x] and TXRING[x] outputs is done in
such a way as to not introduce any bipolar violations.
The diagnostic loopback point is upstream of this AUXP insertion point.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
84
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 005H, 105H, 205H, 305H : Transmit Framing and Bypass Options
Bit
Type
Function
Default
Bit 7
R/W
PATHCRC
0
Bit 6
R/W
G706ANNBRAI
0
Bit 5
R/W
SIGAEN
0
Bit 4
R/W
OOCMFE0
0
Bit 3
R/W
FDIS
0
Bit 2
R/W
FBITBYP
0
Bit 1
R/W
CRCBYP
0
Bit 0
R/W
FDLBYP
0
This register allows software to configure the bypass and framing options of the transmitter, the
use of the Signaling Alignment block, and controls the quadrant transmit framing disable.
PATHCRC:
This bit only has effect in E1 mode.
When in E1 mode, the PATHCRC bit allows upstream block errors to be preserved in the
transmit CRC bits. If PATHCRC is a logic 1, the CRC-4 bits are modified to reflect any bit
values in BTPCM[x], MVBTD or CCSBTD of the quadrant which have changed prior to
transmission. When PATHCRC is set to logic 0, a new CRC-4 value overwrites the incoming
CRC-4 word. For the PATHCRC bit to be effective, the FPTYP bit of the Transmit Backplane
Frame Pulse Configuration register must be a logic 1; otherwise, the identification of the
incoming CRC-4 bits would be impossible. The PATHCRC bit only takes effect if the GENCRC
bit of the E1-TRAN Configuration register is a logic 1 and either the INDIS or FDIS bit in the
same register are set to logic 1.
G706ANNBRAI:
When in E1 mode, the G.706 Annex B RAI bit, G706ANNBRAI, selects between two modes of
operation concerning the transmission of RAI when the quadrant is out of CRC-4 multiframe.
When G706ANNBRAI is logic 1, the behaviour of RAI follows Annex B of G.706, i.e., RAI is
transmitted only when out of basic frame, not when CRC-4-to-non-CRC-4 interworking is
declared, nor when the offline framer is out of frame. When G706ANNBRAI is logic 0, the
behaviour of RAI follows ETSI standards, i.e., RAI is transmitted when out of basic frame,
when CRC-4-to-non-CRC-4 interworking is declared, and when the offline framer is out of
frame.
This bit only has effect in E1 mode.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
85
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
SIGAEN:
The SIGAEN bit enables the operation of the signaling aligner (SIGA) to ensure superframe
alignment of signaling bits between the backplane and the transmit DS-1 stream. When set
to logic 1, the SIGA is inserted into the signaling bit data path before the T1-XBAS. When the
signaling aligner is used, the backplane frame alignment indication must also be changed to
indicate superframe alignment for the transmit backplane. When SIGAEN is set to logic 0,
the SIGA is removed from the circuit. It is recommended that SIGAEN be set to logic 1 in T1
mode.
This bit has no effect in E1 mode.
OOCMFE0:
When in E1 mode, the OOCMFE0 bit selects between two modes of operation concerning the
transmission of E-bits when the quadrant is out of CRC-4 multiframe. When OOCMFE0 is
logic 0, the quadrant transmits ones for the E-bits while out of CRC-4 multiframe. When
OOCMFE0 is logic 1, the quadrant transmits zeroes for the E-bits while out of CRC-4
multiframe. The option to transmit zeroes as E-bits while out of CRC-4 multiframe is provided
to allow compliance with the CRC-4 to non-CRC-4 interworking procedure in Annex B of
G.706.
This bit only has effect in E1 mode.
FDIS:
The FDIS bit allows the framing generation through the transmitter to be disabled and the
transmit data to pass through the transmitter unchanged. When FDIS is set to logic 1, the
transmitter is disabled from generating framing. When FDIS is set to logic 0, the transmitter is
enabled to generate and insert the framing into the transmit data.
FBITBYP:
The FBITBYP bit allows the frame synchronization bit in the input data stream, BTPCM[x] or
MVBTD of the quadrant, to bypass the generation through the T1-XBAS and be re-inserted
into the appropriate position in the digital output stream. When FBITBYP is set to logic 1, the
input frame synchronization bit is re-inserted into the transmit output data stream. When
FBITBYP is set to logic 0, the T1-XBAS is allowed to generate the output frame
synchronization bits.
This bit must be set to logic 0 when not in T1 ESF mode.
CRCBYP:
In T1 mode, when the CRCBYP bit is a logic 1, the framing bit corresponding to the CRC-6 bit
position in the input data stream, BTPCM[x] or MVBTD of the quadrant, passes transparently
to the transmit output data stream. When CRCBYP is set to logic 0, the T1-XBAS is allowed
to generate the output CRC-6 bits.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
86
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
This bit must be set to logic 0 when not in T1 ESF mode.
FDLBYP:
In T1 mode, when the FDLBYP bit is a logic 1, the framing bit corresponding to the facility
data link bit position in the input data stream, BTPCM[x] or MVBTD of the quadrant, passes
transparently to the transmit output data stream. When FDLBYP is set to logic 0, the T1XBAS is allowed to generate the output facility data link.
This bit must be set to logic 0 when not in T1 ESF mode.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
87
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 006H, 106H, 206H, 306H: Transmit Timing Options
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
R/W
OCLKSEL1
0
Bit 4
R/W
OCLKSEL0
0
Bit 3
R/W
PLLREF1
0
Bit 2
R/W
PLLREF0
0
Unused
X
TXELSTBYP
1
Bit 1
Bit 0
R/W
This register allows software to configure the options of the transmit timing section.
TXELSTBYP:
The TXELSTBYP bit allows the Transmit Elastic Store (TX-ELST) to be bypassed, eliminating
the one frame delay incurred through the TX-ELST. When set to logic 1, the received data
and clock inputs to TX-ELST are internally routed directly to the TX-ELST outputs.
OCLKSEL1, OCLKSEL0:
The OCLKSEL[1:0] bits select the source of the Transmit Jitter Attenuator FIFO output clock
signal.
Table 5 - TJAT FIFO Output Clock Source
OCLKSEL1
OCLKSEL0
Source of FIFO Output Clock
0
0
The TJAT FIFO output clock is driven with the internal jitterattenuated 1.544 MHz or 2.048 MHz clock.
0
1
The TJAT FIFO output clock is driven with the CTCLK input
clock. In this mode, PLLREF[1:0] must be programmed to
‘b11.
1
X
The TJAT FIFO output clock is driven with the FIFO input
clock. In this mode the jitter attenuation is disabled and the
input clock must be jitter-free. In this mode, PLLREF[1:0]
must be programmed to ‘b00.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
88
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
PLLREF1, PLLREF0:
The PLLREF[1:0] bits select the source of the Transmit Jitter Attenuator phase locked loop
reference signal as follows:
Table 6 - TJAT PLL Source
PLLREF1
PLLREF0
Source of PLL Reference
0
0
TJAT FIFO input clock (either the conditioned BTCLK[x] or
CMV8MCLK or the Receive recovered clock, as selected by
LINELB, assuming the TX-ELST is bypassed)
0
1
Conditioned input BTCLK[x] or CMV8MCLK (assuming the TXELST is bypassed)
1
0
Receive recovered clock
1
1
CTCLK input
If the THMVIPEN bit of the Transmit H-MVIP/CCS Enable and Configuration register is logic 0
and BTCLK[x] is configured as an output (CMODE bit of the Transmit Backplane
Configuration register is a logic 0), only the recovered clock or the CTCLK input should be
selected, or else the timing becomes self-referential and unpredictable.
The following table illustrates the required bit settings for these various clock sources to affect the
transmitted data:
Table 7 - Transmit Timing Options Summary
Input Transmit Data
Bit Settings
Effect on Output Transmit Data
Synchronous to BTCLK[x] input when
OCLKSEL1=0
Jitter attenuated. Transmit clock is a smooth 1.544 MHz
THMVIPEN=0, or synchronous to
CMV8MCLK when THMVIPEN=1.
Transmit Backplane Configuration
register CMODE =1.
OCLKSEL0=0
PLLREF1=0
PLLREF0=X
or 2.048 MHz.
Transmit line clock referenced to BTCLK[x] input when
THMVIPEN=0, or CMV8MCLK when THMVIPEN=1.
TX-ELST bypassed.
LINELB=0
TXELSTBYP=1
Synchronous to BTCLK[x] output.
OCLKSEL1=0
Transmit Backplane Configuration
OCLKSEL0=0
register CMODE =0.
PLLREF1=1
PLLREF0=0
Jitter attenuated looptiming. Transmit line clock is a
smooth 1.544 MHz or 2.048 MHz.
Loop timed to the Receive recovered clock. TX-ELST
bypassed.
LINELB=0
TXELSTBYP=1
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
89
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Input Transmit Data
Bit Settings
Effect on Output Transmit Data
Synchronous to BTCLK[x] input when
OCLKSEL1=0
Jitter attenuated looptiming. Transmit line clock is a
THMVIPEN=0, or synchronous to
CMV8MCLK when THMVIPEN=1.
Transmit Backplane Configuration
register CMODE =1.
OCLKSEL0=0
PLLREF1=1
PLLREF0=0
smooth 1.544 MHz or 2.048 MHz.
Loop timed to the Receive recovered clock. TX-ELST
allows BTCLK[x] or CMV8MCLK to be plesiochronous.
LINELB=0
TXELSTBYP=0
Synchronous to BTCLK[x] output.
OCLKSEL1=0
Transmit Backplane Configuration
OCLKSEL0=0
register CMODE =0.
PLLREF1=1
Jitter attenuated. Transmit clock is a smooth 1.544 MHz
or 2.048 MHz. Transmit line clock and BTCLK[x]
referenced to CTCLK input. TX-ELST bypassed.
PLLREF0=1
LINELB=0
TXELSTBYP=1
Synchronous to BTCLK[x] input when
THMVIPEN=0, or synchronous to
CMV8MCLK when THMVIPEN=1.
Transmit Backplane Configuration
register CMODE =1.
OCLKSEL1=0
OCLKSEL0=0
PLLREF1=1
Jitter attenuated. Transmit line clock is a smooth
1.544 MHz or 2.048 MHz. Transmit line clock referenced
to CTCLK input. TX-ELST allows BTCLK[x] or
CMV8MCLK to be plesiochronous.
PLLREF0=1
LINELB=0
TXELSTBYP=0
Synchronous to BTCLK[x] input when
THMVIPEN=0, or synchronous to
CMV8MCLK when THMVIPEN=1.
Transmit Backplane Configuration
OCLKSEL1=1
OCLKSEL0=X
PLLREF1=0
register CMODE =1. If BTCLK[x] is
PLLREF0=0
2.048 MHz or if THMVIPEN=1, then
LINELB=0
COMET-QUAD must be in E1 mode.
Synchronous to BTCLK[x] output.
Transmit Backplane Configuration
register CMODE =0.
No jitter attenuation. Transmit line clock is equivalent to
BTCLK[x] or frequency divided CMV8MCLK. TX-ELST
bypassed.
TXELSTBYP=1
OCLKSEL1=0
OCLKSEL0=1
PLLREF1=1
No jitter attenuation. Transmit line clock is equal to
CTCLK (useful for higher rate MUX applications). The
BTCLK[x] output is referenced to CTCLK. TX-ELST
bypassed.
PLLREF0=1
LINELB=0
TXELSTBYP=1
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
90
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Input Transmit Data
Bit Settings
Effect on Output Transmit Data
Synchronous to BTCLK[x] input when
OCLKSEL1=0
No jitter attenuation. Transmit line clock is equal to
THMVIPEN=0, or synchronous to
CMV8MCLK when THMVIPEN=1.
Transmit Backplane Configuration
CTCLK (useful for higher rate MUX applications). TX-
OCLKSEL0=1
ELST allows BTCLK[x] or CMV8MCLK to be
PLLREF1=1
plesiochronous.
PLLREF0=1
register CMODE =1.
LINELB=0
TXELSTBYP=0
Transmit data ignored. Receive data
is looped back.
OCLKSEL1=0
Line loopback with jitter attenuation.
OCLKSEL0=0
PLLREF1=0
PLLREF0=0
LINELB=1
TXELSTBYP=X
TJATBYP=0
Upon reset of the COMET-QUAD, these bits are cleared to zero, selecting jitter attenuation with
Transmit line clock referenced to the backplane transmit clock, BTCLK[x]. Figure 25 illustrates
the various bit setting options, with the reset condition highlighted. Note that THMVIPEN is a bit in
Transmit H-MVIP/CCS Enable and Configuration register and CMODE is a bit in the BTIF
Configuration register. PLLREF[1:0] must be configured such that the internal 24x clock
references the Transmit line clock.
Figure 25
- Transmit Timing Options
1
TXELSTBY P
1
TJA TBY P
Transmit data
0
0
MVBTD
1
BTPCM
0
Transmit line clock
(also becomes BTCLK
output w hen CMODE=0)
TX
ELST
0
CMV8MCLK
1
BTCLK (input)
0
Possible
freq. division
and gapping
1
TXELSTBY P
FIFO input
data clock
0
1
TJAT
FIFO
OCLKSEL1
0
FIFO output
data clock
LINELB
1
THMVIPEN
OCLKSEL0
1
Notes:
00
01
Data indicated with
dashed lines; clocks
indicated with solid lines
TJAT
PLL
PLLREF[1:0]
Receive recovered clock
CTCLK
0
"Jitter-free" line rate clock
(1.544MHz or 2.048MHz)
Internal 24x clock
10
11
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
91
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 007H, 107, 207H, 307H: Interrupt Source #1
Bit
Type
Function
Default
Bit 7
R
PMON
X
Bit 6
R
PRBS
X
Bit 5
R
FRMR
X
Bit 4
R
SIGX
X
Bit 3
R
APRM
X
Bit 2
R
TJAT
X
Bit 1
R
RJAT
X
Bit 0
R
CDRC
X
This register allows software to determine the block which produced the interrupt on the INTB
output pin. A logic 1 indicates an interrupt was produced from the block.
Reading this register does not remove the interrupt indication; the corresponding block's interrupt
status register must be read to remove the interrupt indication.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
92
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 008H, 108H, 208H, 308H: Interrupt Source #2
Bit
Type
Function
Default
Bit 7
R
RX-ELST
X
Bit 6
R
RX-ELST CCS
X
Bit 5
R
Unused
X
Bit 4
R
RDLC
X
Bit 3
R
TX-ELST
X
Bit 2
R
TX-ELST CCS
X
Bit 1
R
XBOC
X
Bit 0
R
TDPR
X
This register allows software to determine the block that produced the interrupt on the INTB
output pin. A logic 1 indicates an interrupt was produced from the block.
Reading this register does not remove the interrupt indication; the corresponding block's interrupt
status register must be read to remove the interrupt indication.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
93
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 009H, 109H, 209H, 309H: Interrupt Source #3
Bit
Type
Function
Default
Bit 7
R
IBCD
X
Bit 6
R
PDVD
X
Bit 5
R
RBOC
X
Bit 4
R
XPDE
X
Bit 3
R
ALMI
X
Bit 2
R
TRAN
X
Bit 1
R
RLPS
X
Bit 0
R
BTIF
X
This register allows software to determine the block that produced the interrupt on the INTB
output pin. A logic 1 indicates an interrupt was produced from the block.
Reading this register does not remove the interrupt indication; the corresponding block's interrupt
status register must be read to remove the interrupt indication.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
94
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 00AH, 10AH, 20AH, 30AH: Master Diagnostics
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
R/W
PAYLB
0
Bit 4
R/W
LINELB
0
Bit 3
R/W
RAIS
0
Bit 2
R/W
DDLB
0
Bit 1
R/W
TXMFP
0
Bit 0
R/W
Reserved
0
PAYLB:
The PAYLB bit selects the payload loopback mode, where the received data output from the
RX-ELST is internally connected to the transmit data input of the transmitter. The data read
out of RX-ELST is timed to the transmitter clock, and the transmit frame alignment is used to
synchronize the output frame alignment of RX-ELST. The transmit frame alignment is either
arbitrary (when the TX-ELST is used) or is specified by the BTFP[x] input (when the TX-ELST
is bypassed). During payload loopback, the data on BRPCM[x] is only valid when the
quadrant is configured as a BRCLK[x] master, BRFP[x] master and the RX-ELST is bypassed.
When the RX-ELST is not bypassed, the BRPCM[x] or MVBRD output for the quadrant is
forced to all-ones. During payload loopback in Receive Clock Slave: Full T1/E1 with CCS HMVIP mode, the data on CCSBRD remains valid. When PAYLB is set to logic 1, the payload
loopback mode is enabled. When PAYLB is set to logic 0, the loopback mode is disabled. In
T1 mode, if the TDPR is configured to send performance reports from the T1-APRM, this bit
requires two updating cycles before being included in the performance report. Only one of
PAYLB, LINELB, and DDLB can be enabled at any one time.
LINELB:
The LINELB bit selects the line loopback mode, where the recovered data are internally
directed to the digital inputs of the transmit jitter attenuator. The data sent to the TJAT is the
recovered data from the output of the CDRC block. When LINELB is set to logic 1, the line
loopback mode is enabled. When LINELB is set to logic 0, the line loopback mode is
disabled. Note that when line loopback is enabled, to correctly attenuate the jitter on the
receive clock, the contents of the TJAT Reference Clock Divisor and Output Clock Divisor
registers should be programmed to 2FH in T1 or FFH in E1 and the Transmit Timing Options
register should be cleared to all zeros. Only one of PAYLB, LINELB, and DDLB can be
enabled at any one time.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
95
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
RAIS:
When a logic 1, the RAIS bit forces all ones into the BRPCM[x] or MVBRD data stream of the
quadrant. The BRSIG[x] or CASBRD data stream of the quadrant will freeze at the current
valid signaling. This capability is provided to indicate the unavailability of the line when line
loopback is active. The CCSBRD stream of the quadrant is unaffected by RAIS.
DDLB:
The DDLB bit selects the diagnostic digital loopback mode, where the quadrant is configured
to internally direct the output of the TJAT to the inputs of the receiver section. The dual-rail
RZ outputs of the TJAT are directed to the dual-rail inputs of the CDRC. When DDLB is set to
logic 1, the diagnostic digital loopback mode is enabled. When DDLB is set to logic 0, the
diagnostic digital loopback mode is disabled. Only one of PAYLB, LINELB, and DDLB can be
enabled at any one time.
TXMFP:
In T1 mode, the TXMFP bit introduces a mimic framing pattern in the digital output of the
basic transmitter by forcing a copy of the current framing bit into bit location 1 of the frame,
thereby creating a mimic pattern in the bit position immediately following the correct framing
bit. When TXMFP is set to logic 1, the mimic framing pattern is generated. When TXMFP is
set to logic 0, no mimic pattern is generated.
Reserved:
This bit must be a logic 0 for normal operation.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
96
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 00BH: Master Test
Bit
Type
Function
Default
Bit 7
W
Reserved
0
Bit 6
W
Reserved
0
Bit 5
W
Reserved
0
Bit 4
W
Reserved
0
Bit 3
W
Reserved
0
Bit 2
W
Reserved
0
Bit 1
W
HIZDATA
0
Bit 0
R/W
HIZIO
0
Reserved:
These bits must remain logic 0 for normal operation.
HIZIO, HIZDATA:
The HIZIO and HIZDATA bits control the tri-state modes of the COMET-QUAD. While the
HIZIO bit is a logic 1, all output pins of the COMET-QUAD except TDO and the data bus are
held in a high-impedance state. The microprocessor interface is still active. While the
HIZDATA bit is a logic 1, the data bus is held in a high-impedance state which inhibits
microprocessor read cycles.
Note: A software reset of the COMET-QUAD does not affect the state of these bits.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
97
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 00DH, 10DH, 20DH, 30DH: Revision/Chip ID/Quadrant PMON Update
Bit
Type
Function
Default
Bit 7
R
TYPE[2]
0
Bit 6
R
TYPE[1]
1
Bit 5
R
TYPE[0]
0
Bit 4
R
ID[4]
0
Bit 3
R
ID[3]
0
Bit 2
R
ID[2]
0
Bit 1
R
ID[1]
1
Bit 0
R
ID[0]
0
The version identification bits, ID[4:0], are set to a fixed value representing the version
number of the COMET-QUAD. The chip identification bits, TYPE[2:0], are set to “010”
representing the COMET-QUAD. The TYPE[2:0] and ID[4:0] bits are only defined for Register
00DH. In Registers 10DH, 20DH, and 30DH, the bits are undefined and the Default value is
‘X’.
Writing any value to this register causes all performance monitor counters in the quadrant to
be updated simultaneously.
To update performance counters in quadrant #1, write to address 00DH.
To update performance counters in quadrant #2, write to address 10DH.
To update performance counters in quadrant #3, write to address 20DH.
To update performance counters in quadrant #4, write to address 30DH.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
98
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 00EH: Reset
Bit
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
Unused
X
Bit 1
Unused
X
RESET
0
Bit 0
Type
R/W
RESET:
The RESET bit implements a software reset. If the RESET bit is a logic 1, the COMET-QUAD
is held in reset. This bit is not self-clearing; therefore, a logic 0 must be written to bring the
COMET-QUAD out of reset. Holding the COMET-QUAD in a reset state effectively puts it into
a low-power, stand-by mode. A hardware reset clears the RESET bit, thus deasserting the
software reset.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
99
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 00FH, 10FH, 20FH, 30FH: PRBS Positioning/Control and HDLC Control
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
R/W
HDLC_DIS
0
Bit 4
R/W
Nx56K_GEN
0
Bit 3
R/W
Nx56K_DET
0
Bit 2
R/W
RXPATGEN
0
Bit 1
R/W
UNF_GEN
0
Bit 0
R/W
UNF_DET
0
This register modifies the way in which the PRBS generator/checker is used by the TPSC and
RPSC.
HDLC_DIS:
The HDLC_DIS bit, when set to logic 1, is used to disable the clock to the TDPR and RDLC,
putting them into a low power, stand-by mode. When the HDLC_DIS bit is set to logic 0, the
clock to the TDPR and RDLC is enabled.
Nx56K_GEN:
The Nx56K_GEN bit is active when the RPSC or TPSC is used to insert PRBS into selected
channels of the transmit or receive stream. When the Nx56Kbit/s generation bit is set to
logic 1, the pattern is only inserted in the first 7 bits of the selected channels, and gapped on
the eighth bit. This is particularly useful when using the jammed-bit-8 zero code suppression
in the transmit direction, for instance when sending a Nx56Kbit/s fractional T1/E1 loopback
sequence. This bit has no effect when UNF_GEN is set to logic 1.
Nx56K_DET:
The Nx56K_DET bit is active when the RPSC or TPSC is used to detect PRBS in selected
channels of the transmit or receive stream. When the Nx56Kbit/s detection bit is set to logic 1,
the pattern generator only looks at the first 7 bits of the selected channels, and gaps out the
eighth bit. This is particularly useful when searching for fractional T1 loopback codes in an
Nx56Kbit/s fractional T1 signal. This bit has no effect when UNF_DET is set to logic 1.
RXPATGEN:
The Receive Pattern Generate, RXPATGEN, bit controls the location of the PRBS
generator/detector. When RXPATGEN is set to logic 1, the PRBS generator is inserted in the
receive path and the PRBS checker is inserted in the transmit path. Timeslots from the
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
100
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
receive line may be overwritten with generated PRBS patterns before appearing on the
receive system interface, and timeslots from the transmit system interface may be checked
for the generated pattern before appearing on the transmit line. When RXPATGEN is set to
logic 0, the PRBS detector is inserted in the receive path and the PRBS generator is inserted
in the transmit path. Timeslots from the transmit system interface may be overwritten with
generated PRBS patterns before appearing on the transmit line, and timeslots from the
receive line may be checked for the generated pattern before appearing on the receive
system interface.
UNF_GEN
When the Unframed Pattern Generation bit, UNF_GEN, is set to logic 1, the PRBS Generator
will overwrite all 193 bits/256 bits in every frame in the direction specified by the RXPATGEN
bit. If the generator is enabled in the transmit path, unless signaling and/or framing is
disabled, the transmitter will still overwrite the signaling bit positions and/or the framing bit
position. Similarly, if pattern generation is enabled in the receive direction, the pattern will
overwrite the framing bit positions. The UNF_GEN bit overrides any per-timeslot pattern
generation specified in the TPSC or RPSC. When RXPATGEN = 0, UNF_GEN also overrides
idle code insertion and data inversion in the transmit direction, just like the TEST bit in the
TPSC.
UNF_DET
When the Unframed Pattern Detection bit, UNF_DET, is set to logic 1, the PRBS Checker will
search for the pattern in all 193 bits/256 bits of the transmit or receive stream, depending on
the setting of RXPATGEN. The UNF_DET bit overrides any per-timeslot pattern detection
specified in the TPSC or RPSC.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
101
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 010H, 110H, 210H, 310H: CDRC Configuration
Bit
Type
Function
Default
Bit 7
R/W
AMI
0
Bit 6
R/W
LOS[1]
0
Bit 5
R/W
LOS[0]
0
Bit 4
R/W
Reserved
0
Bit 3
R/W
Reserved
0
Bit 2
R/W
ALGSEL
0
Bit 1
R/W
O162
0
Bit 0
R/W
Reserved
0
Reserved:
These bits must be a logic 0 for normal operation.
O162:
If the AMI bit is logic 0 in E1 mode, the Recommendation O.162 compatibility select bit (O162)
allows selection between two line code violation definitions:
If O162 is a logic 0, a line code violation is indicated if the serial stream does not match the
verbatim HDB3 definition given in Recommendation G.703. A bipolar violation that is not part
of an HDB3 signature or a bipolar violation in an HDB3 signature that is the same polarity as
the last bipolar violation results in a line code violation indication.
If O162 is a logic 1, a line code violation is indicated if a bipolar violation is of the same
polarity as the last bipolar violation, as per Recommendation O.162.
The O162 bit has no effect in T1 mode.
ALGSEL:
The Algorithm Select (ALGSEL) bit specifies the algorithm used by the DPLL for clock and
data recovery. The choice of algorithm determines the high frequency input jitter tolerance of
the CDRC. When ALGSEL is set to logic 1, the CDRC jitter tolerance is increased to
approach 0.5 UIpp for jitter frequencies above 20 kHz. When ALGSEL is set to logic 0, the
jitter tolerance is increased for frequencies below 20 kHz (i.e. the tolerance is improved by
20% over that of ALGSEL=1 at these frequencies), but the tolerance approaches 0.4 UIpp at
the higher frequencies.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
102
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
AMI:
The alternate mark inversion (AMI) bit specifies the line coding of the incoming signal. A
logic 1 selects AMI line coding by disabling HDB3 decoding if E1 mode and B8ZS in T1 mode.
In E1 mode, a logic 0 selects HDB3 line decoding which entails substituting an HDB3
signature with four zeros. In T1 mode, a logic 0 selects B8ZS line decoding which entails
substituting an B8ZS signature with eight zeros.
LOS[1:0]:
The loss of signal threshold is set by the operating mode and the state of the AMI, LOS[1] and
LOS[0] bits:
Table 8 - Loss of Signal Thresholds
Mode
AMI
LOS[1]
LOS[0]
Threshold (PCM periods)
E1
0
0
0
10
T1
0
0
0
15
X
1
0
0
15
X
X
0
1
31
X
X
1
0
63
X
X
1
1
175
When the number of consecutive zeros on the incoming PCM line exceeds the programmed
threshold, the LOSV status bit is set. For example, if the threshold is set to 10, the 11th zero
causes the LOSV bit to be set. The LOSV bit clears when a pulse occurs.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
103
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 011H, 111H, 211H, 311H: CDRC Interrupt Control
Bit
Type
Function
Default
Bit 7
R/W
LCVE
0
Bit 6
R/W
LOSE
0
Bit 5
R/W
LCSDE
0
Bit 4
R/W
ZNDE
0
Bit 3
Unused
X
Bit 2
Unused
X
Bit 1
Unused
X
Bit 0
Unused
X
The bit positions LCVE, LOSE, LCSDE and ZNDE (bits 7 to 4) of this register are interrupt
enables to select which of the status events (Line Code Violation , Loss Of Signal, HDB3
signature, B8ZS signature or N Zeros), either singly or in combination, are enabled to generate an
interrupt on the microprocessor INTB pin when they are detected. A logic 1 bit in the
corresponding bit position enables the detection of these signals to generate an interrupt; a logic 0
bit in the corresponding bit position disables that signal from generating an interrupt.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
104
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 012H, 112H, 212H, 312H: CDRC Interrupt Status
Bit
Type
Function
Default
Bit 7
R
LCVI
X
Bit 6
R
LOSI
X
Bit 5
R
LCSDI
X
Bit 4
R
ZNDI
X
Bit 3
Unused
X
Bit 2
Unused
X
Bit 1
Unused
X
LOSV
X
Bit 0
R
The ZNDI, LCSDI, LOSI and LCVI (bits 4 to 7) of this register indicate which of the status events
have occurred since the last time this register was read. A logic 1 in any of these bit positions
indicates that the corresponding event was detected.
Bits ZNDI, LCSDI, LOSI and LCVI are cleared to logic 0 by reading this register.
LOSV:
The LOSV bit reflects the status of the LOS alarm.
ZNDI:
The consecutive zeros detection interrupt (ZNDI) indicates that N consecutive spaces have
occurred, where N is four for E1 and eight for T1. This bit can be used to detect an AMI
coded signal.
LCSDI:
The line code signature detection interrupt (LCSDI) indicates that a valid line code signature
has occurred. In T1 mode, the B8ZS signature is defined as 000+-0-+ if the previous impulse
is positive, or 000-+0+- if it is negative. In E1 mode, a valid HDB3 signature is defined as a
bipolar violation preceded by two zeros. This bit can be used to detect an HDB3 coded signal
in E1 mode and B8ZS coded signal in T1.
LOSI:
The LOSI bit is set to a logic 1 when the LOSV bit changes state.
LCVI:
The line code violation interrupt (LCVI) indicates a series of marks and spaces has occurred
in contradiction to the defined line code (AMI, B8ZS or HDB3).
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
105
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 013H, 113H, 213H, 313H: Alternate Loss of Signal Status
Bit
Type
Function
Default
Bit 7
R/W
ALTLOSE
0
Bit 6
R
ALTLOSI
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
Unused
X
Bit 1
Unused
X
ALTLOS
X
Bit 0
R
The alternate loss of signal status provides a more stringent criteria for the deassertion of the
alarm than the LOS indication in the CDRC Interrupt Status register.
ALTLOSE:
If the ALTLOSE bit is a logic 1, the INTB output is asserted low when the ALTLOS status bit
changes state.
ALTLOSI:
The ALTLOSI bit is set high when the ALTLOS status bit changes state. It is cleared when
this register is read.
ALTLOS:
The ALTLOS bit is asserted upon the absence of marks for the threshold of bit periods
specified by the LOS[1:0] register bits. The ALTLOS bit is deasserted only after pulse density
requirements have been met. In T1 mode, there must be N ones in each and every time
window of 8(N+1) data bits (where N can equal 1 through 23). In E1 mode, ALTLOS is
deasserted only after 255 bit periods during which no sequence of four zeros has been
received.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
106
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 014H, 114H, 214H, 314H: RJAT Interrupt Status
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
Unused
X
Bit 1
R
OVRI
X
Bit 0
R
UNDI
X
UNDI:
The UNDI bit is asserted when an attempt is made to read data from the receive FIFO when
the FIFO is already empty. When UNDI is a logic 1, an underrun event has occurred.
Reading this register will clear the UNDI bit to logic 0.
OVRI:
The OVRI bit is asserted when an attempt is made to write data into the receive FIFO when
the FIFO is already full. When OVRI is a logic 1, an overrun event has occurred. Reading
this register will clear the OVRI bit to logic 0.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
107
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 015H, 115H, 215H, 315H: RJAT Divider N1 Control
Bit
Type
Function
Default
Bit 7
R/W
N1[7]
0
Bit 6
R/W
N1[6]
0
Bit 5
R/W
N1[5]
1
Bit 4
R/W
N1[4]
0
Bit 3
R/W
N1[3]
1
Bit 2
R/W
N1[2]
1
Bit 1
R/W
N1[1]
1
Bit 0
R/W
N1[0]
1
This register contains an 8-bit binary number, N1, which is one less than the magnitude of the
reference clock divisor. The reference divisor magnitude, (N1+1), is the ratio between the
frequency of the recovered clock (or the transmit clock if a diagnostic loopback is enabled) and
the frequency at the phase discriminator input.
Writing to this register will reset the PLL. If the FIFORST bit of the RJAT Configuration register is
set high, a write to this register will reset both the PLL and FIFO.
The default value of N1 after a device reset is 47 = 2FH.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
108
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 016H, 116H, 216H, 316H: RJAT Divider N2 Control
Bit
Type
Function
Default
Bit 7
R/W
N2[7]
0
Bit 6
R/W
N2[6]
0
Bit 5
R/W
N2[5]
1
Bit 4
R/W
N2[4]
0
Bit 3
R/W
N2[3]
1
Bit 2
R/W
N2[2]
1
Bit 1
R/W
N2[1]
1
Bit 0
R/W
N2[0]
1
This register contains an 8-bit binary number, N2, which is one less than the magnitude of the
output clock divisor. The output clock divisor magnitude, (N2+1), is the ratio between the
frequency of the smooth output clock, BRCLK[x], and the frequency applied to the phase
discriminator input.
N2 must be programmed with a value of 15 = 0FH or greater for normal operation. With a value of
15 or greater, the PLL will schedule phase adjustments normally.
Writing to this register will reset the PLL. If the FIFORST bit of the RJAT Configuration register is
set high, a write to this register will reset both the PLL and FIFO.
The default value of N2 after a device reset is 47 = 2FH.
Recommendations
In general, the relationship N1 = N2 must always be true in order for the PLL to operate correctly.
Minimizing the values of N1 and N2 while keeping the above equation true minimizes intrinsic
jitter. However, the minimum valid value for N2 is 15 = 0FH.
In order to meet jitter transfer specifications for some modes, such as basic E1 operation, N1 and
N2 must be large in order to reduce the PLL transfer cutoff frequency. In general, for E1
operation, N2 is set to FFH to meet ETSI jitter transfer specifications.
For T1 mode, the recommended values are N1 = N2 = 2FH. For E1 mode, the recommended
values are N1 = N2 = FFH.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
109
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 017H, 117H, 217H, 317H: RJAT Configuration
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
R/W
CENT
0
Bit 3
R/W
UNDE
0
Bit 2
R/W
OVRE
0
Bit 1
R/W
FIFORST
0
Bit 0
R/W
LIMIT
1
CENT:
The CENT bit allows the FIFO to self-center its read pointer, maintaining the pointer at least
4 UI away from the FIFO being empty or full. When CENT is set to logic 1, the FIFO is
enabled to self-center for the next 384 transmit data bit period, and for the first 384 bit periods
following an overrun or underrun event. If an EMPTY or FULL alarm occurs during this 384 UI
period, the period will be extended by the number of UI that the EMPTY or FULL alarm
persists. During the EMPTY or FULL alarm conditions, data is lost. When CENT is set to
logic 0, the self-centering function is disabled, allowing the data to pass through uncorrupted
during EMPTY or FULL alarm conditions.
The recommended value of CENT is logic 1.
UNDE:
Setting the UNDE bit to logic 1 enables an underrun event to assert the INTB output low.
OVRE:
Setting the OVRE bit to logic 1 enables an overrun event to assert the INTB output low.
FIFORST
Setting the FIFORST bit allows the FIFO to reset when the PLL is reset by software. When
FIFORST is logic 1, writing to the PLL Divider Control Registers N1 and N2 will cause both the
PLL and FIFO to reset. When FIFORST is logic 0, writing to the Divider Control Registers N1
and N2 will cause only the PLL to reset.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
110
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
LIMIT:
Setting the LIMIT bit to logic 1 will limit the PLL jitter attenuation by enabling the FIFO to
increase or decrease the frequency of the smooth output clock whenever the FIFO is within
one UI of overflowing or underflowing. This limiting of jitter ensures that no data is lost during
high phase shift conditions. When LIMIT is set to logic 0, underflows and overflows may
occur.
The recommended value of LIMIT is logic 0.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
111
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 018H, 118H, 218H, 318H: TJAT Interrupt Status
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
Unused
X
Bit 1
R
OVRI
X
Bit 0
R
UNDI
X
UNDI:
The UNDI bit is asserted when an attempt is made to read data from the transmit FIFO when
the FIFO is already empty. When UNDI is a logic 1, an underrun event has occurred.
Reading this register will clear the UNDI bit to logic 0.
OVRI:
The OVRI bit is asserted when an attempt is made to write data into the transmit FIFO when
the FIFO is already full. When OVRI is a logic 1, an overrun event has occurred. Reading this
register will clear the OVRI bit to logic 0.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
112
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 019H, 119H, 219H, 319H: TJAT Jitter Attenuator Divider N1 Control
Bit
Type
Function
Default
Bit 7
R/W
N1[7]
0
Bit 6
R/W
N1[6]
0
Bit 5
R/W
N1[5]
1
Bit 4
R/W
N1[4]
0
Bit 3
R/W
N1[3]
1
Bit 2
R/W
N1[2]
1
Bit 1
R/W
N1[1]
1
Bit 0
R/W
N1[0]
1
This register contains an 8-bit binary number, N1, which is one less than the magnitude of the
reference clock divisor. The reference divisor magnitude, (N1+1), is the ratio between the
frequency of the reference clock (as selected by the PLLREF1 and PLLREF0 bits of the Transmit
Timing Options register) and the frequency at the phase discriminator input.
Writing to this register will reset the PLL. If the FIFORST bit of the TJAT Configuration register is
set high, a write to this register will reset both the PLL and FIFO.
The default value of N1 after a device reset is 47 = 2FH.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
113
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 01AH, 11AH, 21AH, 31AH: TJAT Divider N2 Control
Bit
Type
Function
Default
Bit 7
R/W
N2[7]
0
Bit 6
R/W
N2[6]
0
Bit 5
R/W
N2[5]
1
Bit 4
R/W
N2[4]
0
Bit 3
R/W
N2[3]
1
Bit 2
R/W
N2[2]
1
Bit 1
R/W
N2[1]
1
Bit 0
R/W
N2[0]
1
This register contains an 8-bit binary number, N2, which is one less than the magnitude of the
output clock divisor. The output clock divisor magnitude, (N2+1), is the ratio between the
frequency of the smooth output clock and the frequency applied to the phase discriminator input.
N2 must be programmed with a value of 15 = 0FH or greater for normal operation. With a value of
15 or greater, the PLL will schedule phase adjustments normally.
Writing to this register will reset the PLL. If the FIFORST bit of the TJAT Configuration register is
set high, a write to this register will reset both the PLL and FIFO.
The default value of N2 after a device reset is 47 = 2FH.
Recommendations
In general, the relationship Fref/(N1+1) = Fout/(N2+1) must always be true in order for the PLL to
operate correctly.
Minimizing the values of N1 and N2 while keeping the above equation true minimizes intrinsic
jitter. However, the minimum valid value for N2 is 15 = 0FH.
In order to meet jitter transfer specifications for some modes, such as basic E1 operation, N1 and
N2 must be large in order to reduce the PLL transfer cutoff frequency. In general, for E1
operation, N2 is set to FFH to meet ETSI jitter transfer specifications.
When dealing with extremely low frequency references, such as an 8kHz reference clock, the N1
and N2 should configured so that Fref/(N1+1) and Fout/(N2+1) are both 8kHz results. Thus, for an
8kHz reference, N1 is 00H.
The table below summarizes the recommended values for N1 and N2 for common modes of
operation.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
114
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
PLL Reference, as set by
register bits
PLLREF[1:0]
PLL Output
Frequency
N1[7:0]
N2[7:0]
1.544 MHz
1.544 MHz (T1)
2FH
2FH
2.048 MHz
2.048 MHz (E1)
FFH
FFH
2.048 MHz
1.544 MHz (T1)
FFH
C0H
1.544 MHz
2.048 MHz (E1)
C0H
FFH
nominal 1.544 MHz (derived
1
from gapped 2.048 MHz)
1.544 MHz (T1)
C0H
C0H
8 kHz
1.544 MHz (T1)
00H
C0H
16 kHz
1.544 MHz (T1)
01H
C0H
8 kHz
2.048 MHz (E1)
00H
FFH
16 kHz
2.048 MHz (E1)
01H
FFH
1
Nominal 1.544 MHz is derived from a gapped 2.048 MHz when (a) the THMVIPEN bit of register
0B9H is logic 1 and the divided CMV8MCLK is configured as the reference or when (b) the device
is in T1 mode, the BTIF’s RATE[1:0] bits are set to “01”, and BTCLK[x] is configured as the
reference.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
115
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 01BH, 11BH, 21BH, 31BH: TJAT Configuration
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
R/W
CENT
0
Bit 3
R/W
UNDE
0
Bit 2
R/W
OVRE
0
Bit 1
R/W
FIFORST
0
Bit 0
R/W
LIMIT
1
CENT:
The CENT bit allows the FIFO to self-center its read pointer, maintaining the pointer at least
4 UI away from the FIFO being empty or full. When CENT is set to logic 1, the FIFO is
enabled to self-center for the next 384 transmit data bit period, and for the first 384 bit periods
following an overrun or underrun event. If an EMPTY or FULL alarm occurs during this 384 UI
period, the period will be extended by the number of UI that the EMPTY or FULL alarm
persists. During the EMPTY or FULL alarm conditions, data is lost. When CENT is set to
logic 0, the self-centering function is disabled, allowing the data to pass through uncorrupted
during EMPTY or FULL alarm conditions.
The recommended value of CENT is logic 1.
UNDE:
Setting the UNDE bit to logic 1 enables an underrun event to assert the INTB output low.
OVRE:
Setting the OVRE bit to logic 1 enables an overrun event to assert the INTB output low.
FIFORST
Setting the FIFORST bit allows the FIFO to reset when the PLL is reset by software. When
FIFORST is logic 1, writing to the PLL Divider Control Registers N1 and N2 will cause both the
PLL and FIFO to reset. When FIFORST is logic 0, writing to the Divider Control Registers N1
and N2 will cause only the PLL to reset.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
116
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
LIMIT:
Setting the LIMIT bit to logic 1 will limit the PLL jitter attenuation by enabling the FIFO to
increase or decrease the frequency of the smooth output clock whenever the FIFO is within
one UI of overflowing or underflowing. This limiting of jitter ensures that no data is lost during
high phase shift conditions. When LIMIT is set to logic 0, underflows and overflows may
occur.
The recommended value of LIMIT is logic 0.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
117
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 01CH, 11CH, 21CH, 31CH: RX-ELST Configuration
Bit
Type
Function
Default
Bit 7
R/W
Reserved
0
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
Unused
X
Bit 1
R/W
IR
1
Bit 0
R/W
OR
1
Reserved:
This bit must be a logic 0 for normal operation.
IR:
The IR bit selects the input frame format. The IR bit must be set to logic 1 for E1 mode; it
must be logic 0 for T1 mode.
OR:
The OR bit selects the output frame format. The OR bit must be set to logic 1 for E1 mode; it
must be logic 0 for T1 mode.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
118
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 01DH, 11DH, 21DH, 31DH: RX-ELST Interrupt Enable/Status
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
R/W
SLIPE
0
Bit 1
R
SLIPD
X
Bit 0
R
SLIPI
X
SLIPE:
The SLIPE bit position is an interrupt enable that when set, enables the INTB output to assert
low when a slip occurs. When the block is reset the SLIPE bit position is cleared and interrupt
generation is disabled.
SLIPD:
The SLIPD bit indicates the direction of the last slip. If the SLIPD bit is a logic 1 then the last
slip was due to the frame buffer becoming full; a frame was deleted. If the SLIPD bit is a
logic 0 then the last slip was due to the frame buffer becoming empty; a frame was duplicated.
SLIPI:
The SLIPI bit is set if a slip occurred since the last read of this register. The SLIPI bit is
cleared upon reading this register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
119
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 01EH, 11EH, 21EH, 31EH: RX-ELST Idle Code
Bit
Type
Function
Default
Bit 7
R/W
D7
1
Bit 6
R/W
D6
1
Bit 5
R/W
D5
1
Bit 4
R/W
D4
1
Bit 3
R/W
D3
1
Bit 2
R/W
D2
1
Bit 1
R/W
D1
1
Bit 0
R/W
D0
1
The contents of this register replace the timeslot data in the BRPCM serial data stream when the
framer is out of frame and the TRKEN bit in the Receive Options register is a logic 1. Since the
transmission of all ones timeslot data is a common requirement, this register is set to all ones on
a reset condition. D7 is the first to be transmitted.
The writing of the idle code pattern is asynchronous with respect to the output data clock. One
timeslot of idle code data will be corrupted if the register is written to when the framer is out of
frame.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
120
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 020H, 120H, 220H, 320H: TX-ELST Configuration
Bit
Type
Function
Default
Bit 7
R/W
Reserved
0
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
Unused
X
Bit 1
R/W
IR
1
Bit 0
R/W
OR
1
Reserved:
This bit must be logic 0 for normal operation.
IR:
The IR bit selects the input frame format. The IR bit must be set to logic 1 for E1 mode; it
must be logic 0 for T1 mode.
OR:
The OR bit selects the output frame format. The OR bit must be set to logic 1 for E1 mode; it
must be logic 0 for T1 mode.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
121
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 021H, 121H, 221H, 321H: TX-ELST Interrupt Enable/Status
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
R/W
SLIPE
0
Bit 1
R
SLIPD
X
Bit 0
R
SLIPI
X
SLIPE:
The SLIPE bit position is an interrupt enable that when set, enables the INTB output to assert
low when a slip occurs. When the block is reset the SLIPE bit position is cleared and interrupt
generation is disabled.
SLIPD:
The SLIPD bit indicates the direction of the last slip. If the SLIPD bit is a logic 1 then the last
slip was due to the frame buffer becoming full; a frame was deleted. If the SLIPD bit is a
logic 0 then the last slip was due to the frame buffer becoming empty; a frame was duplicated.
SLIPI:
The SLIPI bit is set if a slip occurred since the last read of this register. The SLIPI bit is
cleared upon reading this register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
122
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 028H, 128H, 228H, 328H: RXCE Receive Data Link Control
Bit
Type
Function
Default
Bit 7
R/W
DL_EVEN
0
Bit 6
R/W
DL_ODD
0
Bit 5
R/W
T1_DL_EN
1
Bit 4
R/W
DL_TS[4]
0
Bit 3
R/W
DL_TS[3]
0
Bit 2
R/W
DL_TS[2]
0
Bit 1
R/W
DL_TS[1]
0
Bit 0
R/W
DL_TS[0]
0
This register, along with the RXCE Data Link Bit Select register, controls the extraction of the data
link terminated by RDLC. Refer to the "Using the Internal HDLC Receivers" description in the
Operation section for details on terminating HDLC frames.
DL_EVEN:
The data link even select (DL_EVEN) bit controls whether or not the first data link is extracted
from the even frames of the receive data stream. If DL_EVEN is a logic 0, the data link is not
extracted from the even frames. If DL_EVEN is a logic 1, the data link is extracted from the
even frames. In E1 mode, the frames in an E1 CRC-4 multiframe are considered to be
numbered from 0 to 15; in T1 mode, the frames in a superframe are considered to be
numbered from 1 to 12 (or 1 to 24 in an extended superframe).
DL_ODD:
The data link odd select (DL_ODD) bit controls whether or not the first data link is extracted
from the odd frames of the receive data stream. If DL_ODD is a logic 0, the data link is not
extracted from the odd frames. If DL_ODD is a logic 1, the data link is extracted from the odd
frames.
T1_DL_EN:
The T1 data link enable bit allows the termination of the ESF or T1DM data links when in T1
mode. If T1_DL_EN is a logic 1, the ESF, FMS1 and FMS0 bits of the T1-FRMR
Configuration register determine the bit locations from which the data link is extracted. When
the T1_DL_EN bit is a logic 1, the DL_EVEN and DL_ODD bits must both be set to logic 0.
This bit must be set to logic 0 when in E1 mode.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
123
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
DL_TS[4:0]:
The data link timeslot (DL_TS[4:0]) bits gives a binary representation of the timeslot/channel
from which the data link is to be extracted. Note that T1 channels 1 to 24 are mapped to
values 0 to 23. The DL_TS[4:0] bits have no effect when DL_EVEN and DL_ODD are both a
logic 0.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
124
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 029H, 129H, 229H, 329H: RXCE Receive Data Link Bit Select
Bit
Type
Function
Default
Bit 7
R/W
DL_BIT[7]
0
Bit 6
R/W
DL_BIT[6]
0
Bit 5
R/W
DL_BIT[5]
0
Bit 4
R/W
DL_BIT[4]
0
Bit 3
R/W
DL_BIT[3]
0
Bit 2
R/W
DL_BIT[2]
0
Bit 1
R/W
DL_BIT[1]
0
Bit 0
R/W
DL_BIT[0]
0
DL_BIT[7:0]:
The data link bit select (DL_BIT[7:0]) bits controls which bits of the timeslot/channel are to be
extracted and passed to RDLC. If DL_BIT[x] is a logic 1, that bit is extracted as part of the
data link. To extract the data link from the entire timeslot, all eight DL_BIT[x] bits must be set
to a logic 1. DL_BIT[7] corresponds to the most significant bit (bit 1, the first bit received) of
the timeslot and DL_BIT[0] corresponds to the least significant bit (bit 8, the last bit received)
of the timeslot. The DL_BIT[7:0] bits have no effect when the DL_EVEN and DL_ODD bits of
the RXCE Data Link Control register are both logic 0.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
125
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 030H, 130H, 230H, 330H: BRIF Configuration
Bit
Type
Function
Default
Bit 7
R/W
NX64KBIT/S[1]
0
Bit 6
R/W
NX64KBIT/S[0]
0
Bit 5
R/W
CMODE
1
Bit 4
R/W
DE
1
Bit 3
R/W
FE
1
Bit 2
R/W
CMS
0
Bit 1
R/W
RATE[1]
0
Bit 0
R/W
RATE[0]
0
NX64KBIT/S[1:0]:
The NX64KBIT/S[1:0] bits determine the mode of operation when BRCLK[x] clock master
mode is selected, as shown in the following table. Note that these bits are ignored when clock
slave mode is selected.
Table 9 - Receive Backplane Nx64Kbit/s Mode Selection
NX64KBIT/S[1]
NX64KBIT/S[0]
Operation
0
0
Full Frame
0
1
Nx56Kbit/s
1
0
Nx64Kbit/s
1
1
Nx64Kbit/s with F-bit (only valid for E1 mode)
When in Full Frame mode, the entire frame (193 bits for T1 or 256 bits for E1) is presented and
the BRCLK[x] pulse train contains no gaps.
When in any of the Nx64Kbit/s modes (including the Nx56Kbit/s variant), only those timeslots with
their DTRKC bit cleared (logic 0) are clocked out the backplane. BRCLK[x] does not pulse during
those timeslots with their DTRKC bit set (logic 1). The DTRKC bits are located in the RPSC
Indirect Registers. When in T1 mode, the clock is always gapped during the framing bit position.
When the Nx56Kbit/s mode is selected, only the first 7 bits of the selected timeslots are presented
to the backplane and the 8th bit is gapped out. When the Nx64Kbit/s mode is selected, all 8 bits
of the selected timeslots are presented to the backplane.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
126
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
The Nx64Kbit/s with F-bit mode is intended to support ITU recommendation G.802 where
1.544 Mbit/s data is carried within a 2.048 Mbit/s data stream. This mode is only valid when the
E1/T1B register bit is a logic 1 (E1 mode is selected). The operation is the same as the
Nx64Kbit/s mode, except that the framing bit is presented during the first bit of timeslot 26. To
properly extract a G.802 formatted T1, the DTRKC bits must be set to logic 0 for timeslots 1
through 15 and 17 through 26, and the DTRKC bits must be set to logic 1 for timeslots 27 through
31.
CMODE:
The clock mode (CMODE) bit determines whether the BRCLK[x] pin is an input or output.
When CMODE is a logic 0, clock master mode is selected and the BRCLK[x] output is derived
from the integral clock synthesizer. Depending on the mode of operation, BRCLK[x] may
have a burst frequency of up to 2.048 MHz and may be gapped to support sub-rate
applications.
When CMODE is a logic 1, clock slave mode is selected and BRCLK[x] is an input.
In Receive Clock Slave: H-MVIP mode or when in T1 mode with RATE[1:0] = ’b01, CMODE
must be programmed to logic 1.
DE:
The data edge (DE) bit determines the edge of BRCLK[x] on which BRPCM[x] and BRSIG[x]
are generated. If DE is a logic 0, BRPCM[x] and BRSIG[x] are updated on the falling edge of
BRCLK[x]. If DE is a logic 1, BRPCM[x] and BRSIG[x] are updated on the rising edge of
BRCLK[x].
In Receive Clock Slave: H-MVIP mode, DE must be programmed to logic 0.
FE:
The framing edge (FE) bit determines the edge of BRCLK[x] on which the frame pulse
(BRFP[x]) pulse is sampled or updated. If FE is a logic 0, BRFP[x] is sampled or updated on
the falling edge of BRCLK[x]. If FE is a logic 1, BRFP[x] is sampled on the rising edge of
BRCLK[x]. In the case where FE is not equal to DE, BRFP[x] is sampled or updated one
clock edge before BRPCM[x] and BRSIG[x].
In Receive Clock Slave: H-MVIP mode, FE must be programmed to logic 1.
CMS:
When in Receive Clock Slave mode, the clock mode select (CMS) bit determines the
BRCLK[x] frequency multiple. If CMS is a logic 0, BRCLK[x] is at the backplane rate. If CMS
is a logic 1, BRCLK[x] is at twice the backplane rate.
In Receive Clock Slave: Full T1/E1 or Receive Clock Slave: Full T1/E1 with CCS H-MVIP
mode, CMS must be programmed to logic 0. In Receive Clock Slave: H-MVIP mode, CMS
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
127
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
must be programmed to logic 1. CMS has no effect when in Receive Clock Master mode and
should be set to logic 0.
RATE[1:0]:
The rate select (RATE[1:0]) bits determine the backplane data rate according to the following
table:
Table 10
- Receive Backplane Rate
RATE[1]
RATE[0]
Backplane Rate
0
0
1.544 Mbit/s
0
1
2.048 Mbit/s
1
0
Reserved
1
1
8.192 Mbit/s (H-MVIP)
When in Receive Clock Slave: H-MVIP mode and only in this mode, RATE[1:0] are to be
programmed to “11”. When in a Receive Clock Slave with CCS H-MVIP mode, RATE[1:0]
configures the backplane rate of BRPCM[x] and BRSIG[x]. When in T1 mode with a 2.048
Mbit/s (or faster) backplane rate, the BRIF must be in clock slave mode.
Note: The RATE[1:0] bits can only be set once after reset.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
128
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 031H, 131H, 231H, 331H: BRIF Frame Pulse Configuration
Bit
Type
Function
Default
Bit 7
R/W
MAP
0
Bit 6
R/W
FPINV
0
Bit 5
R/W
FPMODE
1
Bit 4
R/W
ALTFDL
0
Bit 3
R/W
ROHM
0
Bit 2
R/W
BRXSMFP
0
Bit 1
R/W
BRXCMFP
0
Bit 0
R/W
ALTBRFP
0
MAP:
The MAP bit determines the mapping of a 2.048 MHz backplane onto a 1.544 MHz line. This
bit is ignored when in E1 mode (E1/T1B register bit is logic 1), when the backplane rate is
1.544 Mbit/s (RATE[1:0] = 'b00), or when in clock master mode (CMODE = 'b0).
When MAP is a logic 0, every fourth timeslot is unused, starting with timeslot 0. Since the
framing bit is presented during bit 0 of timeslot 0, only bits 1 to 7 of timeslot 0 are unused.
When MAP is a logic 1, the first 24 timeslots (0 to 23) are used. The framing bit is sampled
during bit 7 of timeslot 31 and the rest of the frame (timeslots 24 to 30 and bits 0 to 6 of
timeslot 31) does not contain valid data.
MAP must be programmed to logic 0 when the Receive H-MVIP interface is enabled.
FPINV:
The frame pulse inversion (FPINV) bit determines whether BRFP[x] is inverted prior to
sampling or presentation. If FPINV is a logic 0, BRFP[x] is active high. If FPINV is a logic 1,
BRFP[x] is active low.
In Receive Clock Slave: H-MVIP mode, FPINV must be programmed to logic 0.
FPMODE:
The frame pulse mode (FPMODE) bit determines whether BRFP[x] is an input or an output.
When FPMODE is a logic 0, frame pulse master mode is selected, BRFP[x] is an output and
the ROHM, BRXSMFP, BRXCMFP and ALTBRFP bits determine what BRFP[x] connotes.
When FPMODE is a logic 1, frame pulse slave mode is selected and BRFP[x] is an input.
When configured as an input, BRFP[x] only has effect when the elastic store is in use
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
129
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
(RXELSTBYP is logic 0); otherwise, it is ignored.
In Receive Clock Slave: H-MVIP mode, FPMODE must be programmed to logic 1.
ALTFDL:
In T1 mode, the ALTFDL bit enables the framing bit position on the backplane PCM output to
contain a copy of the FDL bit. When ALTFDL is set to logic 1, each M-bit value in the ESFformatted stream is duplicated and replaces the subsequent CRC bit or F-bit in the output
signal stream on BRPCM[x]. When ALTFDL is set to logic 0, the output BRPCM[x] stream
contains the received M, CRC, or F bits in the framing bit position. Note that this function is
only valid for ESF-formatted streams; ALTFDL should be set to logic 0 when other framing
formats are being received.
This bit is ignored in E1 mode.
ALTBRFP:
The ALTBRFP bit suppresses every second output pulse on the backplane output BRFP[x].
When ALTBRFP is set to logic 1 and BRXCMFP and BRXSMP bits are both logic 0, the
output signal on BRFP[x] pulses every 386 bits or 512 bits, indicating the first bit of every
second frame. Under this condition, BRFP[x] indicates the Signaling Alignment bits (S1-S6)
for T1 SF, the data link bits for T1 ESF and the NFAS frames for E1. If the BRXCMFP or
BRXSMFP bit is logic 1 when ALTBRFP is logic 1, the output signal on BRFP[x] pulses every
24, 32 or 48 frames. In T1 mode, this latter setting (i.e. both ALTBRFP and BRXSMFP set to
logic 1) is useful for converting SF formatted data to ESF formatted data between two
COMET-QUAD devices. When ALTBRFP is set to logic 0, the output signal on BRFP[x]
pulses in accordance to the ROHM, BRXCMFP and BRXSMP bit settings.
ALTBRFP has no effect if the FPMODE bit or the ROHM bit is a logic 1.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
130
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
ROHM, BRXSMFP, BRXCMFP:
The ROHM, BRXSMFP and BRXCMFP bits select the output signal seen on the backplane
output BRFP[x]. These register bits only have effect if the FPMODE bit is a logic 0.
In T1 mode, only BRXSMFP has effect, the other two bits are ignored. When set to logic 1,
the BRFP[x] output pulses high during the first framing bit of the 12 frame SF or the 24 frame
ESF (depending on the framing format selected in the T1-FRMR ). When BRXSMFP is set to
logic 0, the BRFP[x] output pulses high during each framing bit (i.e. every 193 bits).
The following table summarizes the configurations for E1 mode:
Table 11
- E1 Receive Backplane Frame Pulse Configurations
ROHM
BRXSMFP
BRXCMFP
Result
0
0
0
Backplane receive frame pulse output:
BRFP[x] pulses high for 1 BRCLK[x] cycle during bit
1 of each 256-bit frame, indicating the frame
alignment of the BRPCM[x] data stream.
0
0
1
Backplane receive CRC multiframe output:
BRFP[x] pulses high for 1 BRCLK[x] cycle during bit
1 of frame 1 of every 16 frame CRC multiframe,
indicating the CRC multiframe alignment of the
BRPCM[x] data stream. (Even when CRC
multiframing is disabled, the BRFP[x] output
continues to indicate the position of bit 1 of the FAS
frame every 16th frame).
0
1
0
Backplane receive signaling multiframe output:
BRFP[x] pulses high for 1 BRCLK[x] cycle during bit
1 of frame 1 of the 16 frame signaling multiframe,
indicating the signaling multiframe alignment of the
BRPCM[x] data stream. (Even when signaling
multiframing is disabled, the BRFP[x] output
continues to indicate the position of bit 1 of every
16th frame.)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
131
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
ROHM
BRXSMFP
BRXCMFP
Result
0
1
1
Backplane receive composite multiframe output:
BRFP[x] goes high on the active BRCLK[x] edge
marking the beginning of bit 1 of frame 1 of every
16 frame signaling multiframe, indicating the
signaling multiframe alignment of the BRPCM[x]
data stream, and returns low on the active
BRCLK[x] edge marking the end of bit 1 of frame 1
of every 16 frame CRC multiframe, indicating the
CRC multiframe alignment of the BRPCM[x] data
stream. This mode allows both multiframe
alignments to be decoded externally from the single
BRFP[x] signal. Note that if the signaling and CRC
multiframe alignments are coincident, BRFP[x] will
pulse high for 1 BRCLK[x] cycle every 16 frames.
1
X
X
Backplane receive overhead output:
BRFP[x] is high for timeslot 0 and timeslot 16 of
each 256-bit frame, indicating the overhead of the
BRPCM[x] data stream.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
132
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 032H, 132H, 232H, 332H : BRIF Parity/F-bit Configuration
Bit
Type
Function
Default
Bit 7
R/W
RPTYP
0
Bit 6
R/W
RPTYE
0
Bit 5
R/W
FIXF
0
Bit 4
R/W
FIXPOL
0
Bit 3
R/W
PTY_EXTD
0
Unused
X
Bit 2
Bit 1
R/W
Reserved
0
Bit 0
R/W
TRI
0
This register provides control of data integrity checking on the BRPCM[x] and BRSIG[x] signals of
the receive backplane interface in T1 and E1 mode. (When in Receive Clock Slave: H-MVIP
mode, data integrity checking is performed on MVBRD and CASBRD on a per-quadrant basis.
Each of the four BRIF blocks checks parity over the data streams of its associated quadrant.) A
single parity bit in the first bit position of the frame (the F-bit if in T1 mode) represents parity over
the previous frame (including the undefined bit positions). If a 2.048 Mbit/s backplane rate or
Receive Clock Slave: H-MVIP mode is selected, the parity calculation is performed over all bit
positions, including the undefined positions. Signaling parity is similarly calculated over all bit
positions. Parity checking and generation is not supported when in Nx64Kbit/s mode or when
mapping a 1.544 Mbit/s signal onto a 2.048 Mbit/s backplane in the format where the first 24
timeslots are used, i.e., T1 mode, the RATE[1:0] bits in the BRIF Configuration register are “01”
and the MAP bit in the BRIF Frame Pulse Configuration register is logic 1.
RPTYP:
The receive parity type (RPTYP) bit sets even or odd parity in the receive streams. If RPTYP
is a logic 0, the expected parity value in the first bit position of the frame (the F-bit if in T1
mode) of BRPCM[x] or MVBRD for the quadrant and BRSIG[x] or CASBRD for the quadrant
is even, thus it is a one if the number of ones in the previous frame is odd. If RPTYP is a
logic 1, the expected parity value in the first bit position of the frame of BRPCM[x] or MVBRD
for the quadrant and BRSIG[x] or CASBRD for the quadrant is odd, thus it is a one if the
number of ones in the previous frame is even. RPTYP only has effect if RPRTYE is a logic 1.
RPRTYE:
The RPRTYE bit enables receive parity insertion. When set to logic 1, parity is inserted into
the first bit position of the frame for BRPCM[x] or MVBRD of the quadrant and BRSIG[x] or
CASBRD of the quadrant. When set to logic 0, the first bit position of the frame passes
through transparently.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
133
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
FIXF:
If the RPRTYE bit is a logic 0, a logic 1 in the FIXF bit forces the first bit of the frame for
BRPCM[x] or MVBRD of the quadrant to the polarity specified by the FIXPOL bit.
If RPRTYE is a logic 1, FIXF has no effect. If RPRTYE and FIXF are both logic 0, the first bit
of the frame passes from the line transparently.
FIXPOL:
This bit determines the logic level of the first bit of the frame for BRPCM[x] or MVBRD of the
quadrant when the FIXF bit is a logic 1 and the RPRTYE bit is a logic 0. If FIXPOL is a
logic 1, BRPCM[x] or MVBRD of the quadrant will be high in the first bit of the frame. If
FIXPOL is a logic 0, BRPCM[x] or MVBRD of the quadrant will be low in the first bit of the
frame.
PTY_EXTD:
The parity extend (PRY_EXTD) bit determines the scope of the parity calculation. When
PTY_EXTD is logic 1, the parity is calculated over the previous frame plus the previous parity
bit. When it is logic 0, the parity is calculated only over the previous frame.
Reserved
This bit must be logic 0 for normal operation.
TRI:
This is an engineering register bit. It must be programmed to logic 1 for valid data to be
expected on the MVBRD or CASBRD outputs. This bit can be either a 1 or a 0 when valid
data is not expected on these two outputs.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
134
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 033H, 133H, 233H, 333H: BRIF Timeslot Offset
Bit
Type
Bit 7
Function
Default
Unused
X
Bit 6
R/W
TSOFF[6]
0
Bit 5
R/W
TSOFF[5]
0
Bit 4
R/W
TSOFF[4]
0
Bit 3
R/W
TSOFF[3]
0
Bit 2
R/W
TSOFF[2]
0
Bit 1
R/W
TSOFF[1]
0
Bit 0
R/W
TSOFF[0]
0
TSOFF[6:0]:
The timeslot offset (TSOFF[6:0]) bits give a binary representation of the fixed byte offset
between the backplane receive frame pulse (BRFP[x]) and the start of the next frame on the
backplane receive data signal (BRPCM[x]). The seven bits can give an offset from 0 - 127
bytes.
When in Receive Clock Slave: Full T1/E1 with CCS H-MVIP mode, TSOFF[6:0] must all be
programmed to logic 0.
When in Receive Clock Slave: H-MVIP mode, the TSOFF[6:0] bits must be programmed as
follows:
Quadrant 1 (Register 033H): TSOFF[6:0] = “0000000”.
Quadrant 2 (Register 133H): TSOFF[6:0] = “0000001”.
Quadrant 3 (Register 233H): TSOFF[6:0] = “0000010”.
Quadrant 4 (Register 333H): TSOFF[6:0] = “0000011”.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
135
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 034H, 134H, 234H, 334H: BRIF Bit Offset
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
R/W
BOFF_EN
0
Bit 2
R/W
BOFF[2]
0
Bit 1
R/W
BOFF[1]
0
Bit 0
R/W
BOFF[0]
0
BOFF_EN:
The bit offset enable (BOFF_EN) bit is used to enable the bit offset bits. If BOFF_EN is a
logic 0, the bit offset is disabled and there is no bit offset between the frame pulse and the first
bit of the first timeslot. In this case, the BOFF[2:0] bits are ignored. If BOFF_EN is a logic 1,
the bit offset is enabled and the BOFF[2:0] bits operate as described below.
When a Receive H-MVIP interface is active, BOFF_EN must be programmed to logic 0.
BOFF[2:0]:
The bit offset (BOFF[2:0]) bits gives a binary representation of the fixed offset between the
backplane receive frame pulse (BRFP[x]) and the start of the first bit of the first timeslot. This
binary representation is then used to determine the BRCLK[x] edge, defined as CET (clock
edge transmit) on which the first bit of the first timeslot is sampled. For example, if CET is 4,
the data on BRPCM[x] and BRSIG[x] is sampled on the fourth clock edge after BRFP[x] is
sampled (see Figure 24). The following tables show the relationship between BOFF[2:0], FE,
DE and CER.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
136
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Table 12
FE
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- Receive Backplane Bit Offset for CMS = 0
DE
BOFF[2:0]
000
001
010
011
100
101
110
111
0
0
4
6
8
10
12
14
16
18
0
1
3
5
7
9
11
13
15
17
1
0
3
5
7
9
11
13
15
17
1
1
4
6
8
10
12
14
16
18
Table 13
FE
CET
- Receive Backplane Bit Offset for CMS = 1
DE
BOFF[2:0]
000
001
010
011
100
101
110
111
0
0
4
8
12
16
20
24
28
32
0
1
3
7
11
15
19
23
27
31
1
0
3
7
11
15
19
23
27
31
1
1
4
8
12
16
20
24
28
32
CET
The above tables are consistent with the convention established by the Concentration Highway
Interface (CHI) specification.
Note that in the case where FE is logic 0, DE is logic 1 and BRFP[x] is configured for a
superframe/multiframe mode, the maximum offset is one frame less two bits, rather than one
frame less one bit as in all other configurations. In this configuration, the maximum offset is 191
bits at 1.544 Mbit/s and 254 bits at 2.048 Mbit/s.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
137
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 038H, 138H, 238H, 338H: TXCI Transmit Data Link Control
Bit
Type
Function
Default
Bit 7
R/W
DL_EVEN
0
Bit 6
R/W
DL_ODD
0
Bit 5
R/W
T1_DL_EN
1
Bit 4
R/W
DL_TS[4]
0
Bit 3
R/W
DL_TS[3]
0
Bit 2
R/W
DL_TS[2]
0
Bit 1
R/W
DL_TS[1]
0
Bit 0
R/W
DL_TS[0]
0
This register, along with the TXCI Data Link Bit Select register, controls the insertion of the data
link generated by TDPR. Refer to the "Using the Internal HDLC Transmitters" description in the
Operation section for details on terminating HDLC frames.
DL_EVEN:
The data link even select (DL_EVEN) bit controls whether or not the first data link is inserted
into the even frames of the receive data stream. If DL_EVEN is a logic 0, the data link is not
inserted into the even frames. If DL_EVEN is a logic 1, the data link is inserted into the even
frames. In E1 mode, the frames in an E1 CRC-4 multiframe are considered to be numbered
from 0 to 15; in T1 mode, the frames in a superframe are considered to be numbered from 1
to 12 (or 1 to 24 in an extended superframe).
DL_ODD:
The data link odd select (DL_ODD) bit controls whether or not the first data link is inserted
into the odd frames of the receive data stream. If DL_ODD is a logic 0, the data link is not
inserted into the odd frames. If DL_ODD is a logic 1, the data link is inserted into the odd
frames.
T1_DL_EN:
The T1 data link enable bit allows the generation of the ESF or T1DM data links when in T1
mode. If T1_DL_EN is a logic 1, the ESF, FMS1 and FMS0 bits of the T1-FRMR
Configuration register determine the bit locations into which the data link is inserted. When
the T1_DL_EN bit is a logic 1, the DL_EVEN and DL_ODD bits must both be set to logic 0.
This bit must be set to logic 0 when in E1 mode.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
138
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
DL_TS[4:0]:
The data link timeslot (DL_TS[4:0]) bits gives a binary representation of the timeslot/channel
into which the data link is to be inserted. Note that T1 channels 1 to 24 are mapped to values
0 to 23. The DL_TS[4:0] bits have no effect when DL_EVEN and DL_ODD are both a logic 0.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
139
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 039H, 139H, 239H, 339H: TXCI Transmit Data Link Bit Select
Bit
Type
Function
Default
Bit 7
R/W
DL_BIT[7]
0
Bit 6
R/W
DL_BIT[6]
0
Bit 5
R/W
DL_BIT[5]
0
Bit 4
R/W
DL_BIT[4]
0
Bit 3
R/W
DL_BIT[3]
0
Bit 2
R/W
DL_BIT[2]
0
Bit 1
R/W
DL_BIT[1]
0
Bit 0
R/W
DL_BIT[0]
0
DL_BIT[7:0]:
The data link bit select (DL_BIT[7:0]) bits controls into which bits of the timeslot/channel data
from TDPR are to be inserted. If DL_BIT[x] is a logic 1, the data link is inserted into that bit.
To insert the data link into the entire timeslot, all eight DL_BIT[x] bits must be set to a logic 1.
DL_BIT[7] corresponds to the most significant bit (bit 1, the first bit transmitted) of the timeslot
and DL_BIT[0] corresponds to the least significant bit (bit 8, the last bit transmitted) of the
timeslot. The DL_BIT[7:0] bits have no effect when the DL_EVEN and DL_ODD bits of the
TXCI Data Link Control register are both logic 0.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
140
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 040H, 140H, 240H, 340H: BTIF Configuration
Bit
Type
Function
Default
Bit 7
R/W
NX64KBIT/S[1]
0
Bit 6
R/W
NX64KBIT/S[0]
0
Bit 5
R/W
CMODE
1
Bit 4
R/W
DE
1
Bit 3
R/W
FE
1
Bit 2
R/W
CMS
0
Bit 1
R/W
RATE[1]
0
Bit 0
R/W
RATE[0]
0
NX64KBIT/S[1:0]:
The NX64KBIT/S[1:0] bits determine the mode of operation when BTCLK clock master mode
is selected (CMODE logic 0), as shown in the following table. Note that these bits are ignored
when clock slave mode is selected (CMODE logic 1).
Table 14
- Transmit Backplane Nx64Kbit/s Mode Selection
NX64KBIT/S[1]
NX64KBIT/S[0]
Operation
0
0
Full Frame
0
1
Nx56Kbit/s
1
0
Nx64Kbit/s
1
1
Nx64Kbit/s with F-bit (only valid for E1 mode)
When in Full Frame mode, the entire frame (193 bits for T1 or 256 bits for E1) is sampled
from the backplane.
When in any of the Nx64Kbit/s modes (including the Nx56Kbit/s variant), only those timeslots
with their IDLE_CHAN bit cleared (logic 0) are sampled from the backplane. The other
timeslots, with their IDLE_CHAN bit set (logic 1), do not contain valid data and will be
overwritten with the per-DS0 idle code. The IDLE_CHAN bits are located in the TPSC Indirect
registers. When in T1 mode, the clock is always gapped during the framing bit position.
When the Nx56Kbit/s mode is selected, only the first 7 bits of the selected timeslots are
sampled from the backplane and the 8th bit is gapped out. When the Nx64Kbit/s mode is
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
141
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
selected, all 8 bits of the selected timeslots are sampled from the backplane.
The Nx64Kbit/s with F-bit mode is intended to support ITU recommendation G.802. This
mode is only valid when the E1/T1B register bit is a logic 1 (E1 mode is selected). The
operation is the same as the Nx64Kbit/s mode, except that the framing bit is sampled. The Fbit is always sampled during the first bit of timeslot 26. The remaining seven bits of timeslot
26 are not sampled. To properly insert a G.802 formatted T1, the IDLE_CHAN bits must be
set to logic 0 for timeslots 1 through 15 and 17 through 26, and the IDLE_CHAN bits must be
set to logic 1 for timeslots 27 through 31.
CMODE:
The clock mode (CMODE) bit determines whether the BTCLK[x] pin is an input or output.
When CMODE is a logic 0, clock master mode is selected and the BTCLK[x] output is derived
from the integral clock synthesizer. Depending on the mode of operation, BTCLK[x] may have
a burst frequency of up to 2.048 MHz and may be gapped to support sub-rate applications.
When CMODE is a logic 1, clock slave mode is selected and BTCLK[x] is an input.
In Transmit Clock Slave: H-MVIP mode or when in T1 mode with RATE[1:0] = ‘b01, CMODE
must be programmed to logic 1.
DE:
The data edge (DE) bit determines the edge of BTCLK[x] on which BTPCM[x] and BTSIG[x]
are sampled. If DE is a logic 0, BTPCM[x] and BTSIG[x] are sampled on the falling edge of
BTCLK[x]. If DE is a logic 1, BTPCM[x] and BTSIG[x] are sampled on the rising edge of
BTCLK[x].
In Transmit Clock Slave: H-MVIP mode, DE must be programmed to logic 1.
FE:
The framing edge (FE) bit determines the edge of BTCLK[x] on which the frame pulse
(BTFP[x]) is sampled or updated. If FE is a logic 0, BTFP[x] is sampled or updated on the
falling edge of BTCLK[x]. If FE is a logic 1, BTFP[x] is sampled or updated on the rising edge
of BTCLK[x]. In the case where FE is not equal to DE, BTFP[x] is sampled one clock edge or
updated three clock edges before BTPCM[x] and BTSIG[x] are sampled.
In Transmit Clock Slave: H-MVIP mode, FE must be programmed to logic 1.
CMS:
The clock mode select (CMS) bit determines the BTCLK[x] frequency multiple. If CMS is a
logic 0, BTCLK is at the backplane rate. If CMS is a logic 1, BTCLK[x] is at twice the
backplane rate. CMS must be programmed to logic 0 when CMODE=0.
In Transmit Clock Slave: H-MVIP mode, CMS must be programmed to logic 1.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
142
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
RATE[1:0]:
The rate select (RATE[1:0]) bits determine the backplane data rate according to the following
table:
Table 15
- Transmit Backplane Rate
RATE[1]
RATE[0]
Backplane Rate
0
0
1.544 Mbit/s
0
1
2.048 Mbit/s
1
0
Reserved
1
1
8.192 Mbit/s (H-MVIP)
When in Transmit Clock Slave: H-MVIP mode and only in this mode, RATE[1:0] are to be
programmed to “11”. When in a Transmit Clock Slave with CCS H-MVIP mode, RATE[1:0]
configures the backplane rate of BTPCM[x] and BTSIG[x]. When in T1 mode with a 2.048
Mbit/s (or faster) backplane rate, the BTIF must be in clock slave mode.
Note: The RATE[1:0] bits can only be set once after reset.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
143
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 041H, 141H, 241H, 341H: BTIF Frame Pulse Configuration
Bit
Type
Function
Default
Bit 7
R/W
MAP
0
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
R/W
FPINV
0
Bit 2
R/W
ESF_EN
0
Bit 1
R/W
FPTYP
0
Bit 0
R/W
FPMODE
1
MAP:
The MAP bit determines the mapping of a 2.048 MHz backplane onto a 1.544 MHz line. This
bit is ignored when in E1 mode (E1/T1B register bit is logic 1), when the backplane rate is
1.544 Mbit/s (RATE[1:0] = 'b00), or when in clock master mode (CMODE = 'b0).
When MAP is a logic 0, every fourth timeslot is unused, starting with timeslot 0. The framing
bit is sampled during bit 0 of timeslot 0, so that only bits 1 to 7 of timeslot 0 are ignored.
When MAP is a logic 1, the first 24 timeslots (0 to 23) are sampled. The framing bit is
sampled during bit 7 of timeslot 31 and the rest of the frame (timeslots 24 to 30 and bits 0 to 6
of timeslot 31) is ignored.
MAP must be programmed to logic 0 when a Transmit H-MVIP interface is enabled.
FPINV:
The frame pulse inversion (FPINV) bit determines whether BTFP[x] is inverted prior to
sampling. If FPINV is a logic 0, BTFP[x] is active high. If FPINV is a logic 1, BTFP[x] is active
low. Frame pulse inversion cannot be used when BTFP[x] is configured as an output
(FPMODE is a logic 0).
In Transmit Clock Slave: H-MVIP mode, FPINV must be programmed to logic 0.
ESF_EN:
The extended superframe enable (ESF_EN) bit determines which superframe alignment is
used when in T1 mode and FPTYP is a logic 1. When ESF_EN is a logic 0, superframe
alignment is chosen and BTFP[x] does pulse (FPMODE logic 0) or expects to be pulsed
(FPMODE logic 1) every 12 frames on the first frame bit of the superframe. When ESF_EN is
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
144
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
a logic 1, extended superframe alignment is chosen and BTFP[x] does pulse (FPMODE
logic 0) or expects to be pulsed (FPMODE logic 1) every 24 frames on the first frame bit of
the extended superframe.
This bit is ignored when in E1 mode or in T1 mode when FPTYP is a logic 0.
FPTYP:
The frame pulse type (FPTYP) bit determines the type of frame pulse on BTFP[x]. When
FPTYP is a logic 0, basic frame alignment is chosen and frame pulses occur every frame.
When FPTYP is a logic 1, multiframe alignment is chosen.
In T1 mode with multiframe alignment, BTFP[x] does pulse (FPMODE logic 0) or expects to
be pulsed (FPMODE logic 1) every 12 or 24 frames as determined by the ESF_EN bit.
In E1 mode, with multiframe alignment when FPMODE is a logic 0, as an output BTFP[x]
pulses once every 16 frames to indicate both CRC and signaling multiframe alignment. When
BTFP[x] is configured as an input, it must be brought high to mark bit 1 of frame 1 of every 16
frame signaling multiframe and brought low following bit 1 of frame 1 of every 16 frame CRC
multiframe.
To properly initialize the transmit HDLC controllers in basic frame alignment mode (FPTYP is
logic 0), multiframe alignment (FPTYP is logic 1) must be configured for at least one
multiframe (i.e., for at least one multiframe period in frame pulse master mode or for at least
one input frame pulse in frame pulse slave mode). After this initialization, the FPTYP can be
set to any desired value.
In Transmit Clock Slave: H-MVIP mode, FPTYP must be programmed to logic 0.
FPMODE:
The frame pulse mode (FPMODE) bit determines whether BTFP[x] is an input or an output.
When FPMODE is a logic 0, frame pulse master mode is selected and BTFP[x] is an output.
When FPMODE is a logic 1, frame pulse slave mode is selected and BTFP[x] is an input.
Frame pulse master mode cannot be used with transmit backplane clock rates greater than
2.048 MHz.
In Transmit Clock Slave: H-MVIP mode, FPMODE must be programmed to logic 1.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
145
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 042H, 142H, 242H, 342H: BTIF Parity Configuration and Status
Bit
Type
Function
Default
Bit 7
R/W
TPTYP
0
Bit 6
R/W
TPTYE
0
Bit 5
R
BTPCMI
X
Bit 4
R
BTSIGI
X
Bit 3
R/W
PTY_EXTD
0
Bit 2
Unused
X
Bit 1
Unused
X
Bit 0
Unused
X
This register provides control and status reporting of data integrity checking on the BTPCM[x] and
BTSIG[x] signals of the transmit backplane interface in T1 and E1 mode. (When in Transmit Clock
Slave: H-MVIP mode, data integrity checking is performed on MVBTD and CASBTD on a perquadrant basis. Each of the four BTIF blocks checks parity over the data streams of its associated
quadrant.) A single parity bit in the first bit position of the frame (the F-bit if in T1 mode) represents
parity over the previous frame (including the undefined bit positions). Parity checking and
generation is not supported when the Nx64Kbit/s mode is active. Parity checking and generation
is not supported when mapping a 1.544 Mbit/s signal onto a higher rate backplane in the format
where the first 24 timeslots are used, i.e., the RATE[1:0] bits in the BTIF Configuration register are
not set to “00” and the MAP bit in the BTIF Frame Pulse Configuration register is logic 1.
TPTYP:
The transmit parity type (TPTYP) bit sets even or odd parity in the transmit streams. If TPTYP
is a logic 0, the expected parity value in the first bit position of the frame of BTPCM[x] or
MVBTD of the quadrant and BTSIG[x] or CASBTD of the quadrant is even, thus it is expected
to be a one if the number of ones in the previous frame is odd. If TPTYP is a logic 1, the
expected parity value in the first bit position of the frame of BTPCM[x] or MVBTD of the
quadrant and BTSIG[x] or CASBTD of the quadrant is odd, thus it is expected to be a one if
the number of ones in the previous frame is even.
TPTYE:
The transmit parity enable (TPTYE) bit enables transmit parity interrupts. When TPTYE is a
logic 1, parity errors on the inputs BTPCM[x] or MVBTD of the quadrant and BTSIG[x] or
CASBTD of the quadrant are indicated by the BTPCMI and BTSIGI bits, respectively, and by
the assertion low of the INTB output. When TPTYE is a logic 0, parity errors are indicated by
the BTPCMI and BTSIGI bits but are not indicated on the INTB output.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
146
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
BTPCMI:
The transmit PCM data interrupt (BTPCMI) bit indicates if a parity error has been detected on
the stream for BTPCM[x] or MVBTD of the quadrant. BTPCMI is cleared when this register is
read.
BTSIGI:
The transmit signaling interrupt (BTSIGI) bit indicated if a parity error has been detected on
the stream for BTSIG[x] or CASBTD of the quadrant. BTSIGI is cleared when this register is
read.
PTY_EXTD:
The parity extend (PRY_EXTD) bit causes the parity to be calculated over the previous frame
plus the previous parity bit, instead of only the previous frame.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
147
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 043H, 143H, 243H, 343H: BTIF Timeslot Offset
Bit
Type
Bit 7
Function
Default
Unused
X
Bit 6
R/W
TSOFF[6]
0
Bit 5
R/W
TSOFF[5]
0
Bit 4
R/W
TSOFF[4]
0
Bit 3
R/W
TSOFF[3]
0
Bit 2
R/W
TSOFF[2]
0
Bit 1
R/W
TSOFF[1]
0
Bit 0
R/W
TSOFF[0]
0
TSOFF[6:0]:
The timeslot offset (TSOFF[6:0]) bits give a binary representation of the fixed byte offset
between the backplane transmit frame pulse (BTFP[x]) and the start of the next frame on the
backplane transmit data signal (BTPCM[x]). The seven bits can give an offset from 0 - 127
bytes.
When in Transmit Clock Slave: Full T1/E1 with CCS H-MVIP mode, TSOFF[6:0] must all be
programmed to logic 0.
When in Transmit Clock Slave: H-MVIP mode, the TSOFF[6:0] bits must be programmed as
follows:
Quadrant 1 (Register 043H): TSOFF[6:0] = “0000000”.
Quadrant 2 (Register 143H): TSOFF[6:0] = “0000001”.
Quadrant 3 (Register 243H): TSOFF[6:0] = “0000010”.
Quadrant 4 (Register 343H): TSOFF[6:0] = “0000011”.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
148
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 044H, 144H, 244H, 344H: BTIF Bit Offset
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
R/W
BOFF_EN
0
Bit 2
R/W
BOFF[2]
0
Bit 1
R/W
BOFF[1]
0
Bit 0
R/W
BOFF[0]
0
BOFF_EN:
The bit offset enable (BOFF_EN) bit is used to enable the bit offset bits. If BOFF_EN is a
logic 0, the bit offset is disabled and there is no bit offset between the frame pulse and the first
bit of the first timeslot. In this case, the BOFF[2:0] bits are ignored. If BOFF_EN is a logic 1,
the bit offset is enabled and the BOFF[2:0] bits operate as described below.
When a Transmit H-MVIP interface is active, BOFF_EN must be programmed to logic 0.
BOFF[2:0]:
The bit offset (BOFF[2:0]) bits gives a binary representation of the fixed offset between the
backplane transmit frame pulse (BTFP[x]) and the start of the first bit of the first timeslot. This
binary representation is then used to determine the BTCLK[x] edge, defined as CER (clock
edge receive) on which the first bit of the first timeslot is sampled. For example, if CER is 4,
the data on BTPCM[x] and BTSIG[x] is sampled on the fourth clock edge after BTFP[x] is
sampled (see Figure 24). The following tables show the relationship between BOFF[2:0], FE,
DE and CER.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
149
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Table 16
FE
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- Transmit Backplane Bit Offset for CMS = 0
DE
BOFF[2:0]
000
001
010
011
100
101
110
111
0
0
4
6
8
10
12
14
16
18
0
1
3
5
7
9
11
13
15
17
1
0
3
5
7
9
11
13
15
17
1
1
4
6
8
10
12
14
16
18
Table 17
FE
CER
- Transmit Backplane Bit Offset for CMS = 1
DE
BOFF[2:0]
000
001
010
011
100
101
110
111
0
0
6
10
14
18
22
26
30
34
0
1
7
11
15
19
23
27
31
35
1
0
7
11
15
19
23
27
31
35
1
1
6
10
14
18
22
26
30
34
CER
The above tables are consistent with the convention established by the Concentration Highway
Interface (CHI) specification.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
150
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 048H, 148H, 248H, 348H: T1-FRMR Configuration
Bit
Type
Function
Default
Bit 7
R/W
M2O[1]
0
Bit 6
R/W
M2O[0]
0
Bit 5
R/W
ESFFA
0
Bit 4
R/W
ESF
0
Bit 3
R/W
FMS1
0
Bit 2
R/W
FMS0
0
Bit 1
R/W
JPN
0
Unused
X
Bit 0
When the E1/T1B bit of the Global Configuration register is a logic 1 or the UNF bit of the Receive
Options register is a logic 1, this register is held reset.
This register selects the framing format and the frame loss criteria used by the T1-FRMR.
M2O[1:0]:
The M2O[1:0] bits select the ratio of errored to total framing bits before declaring out of frame
in SF, SLC®96 and ESF framing formats. A logic 00 selects 2 of 4 framing bits in error; a
logic 01 selects 2 of 5 bits in error; a logic 10 selects 2 of 6 bits in error. In T1DM framing
format, the ratio of errored to total framing bits before declaring out of frame is always 4 out of
12. A logic 11 in the M2O[1:0] bits is reserved and should not be used.
ESFFA:
The ESFFA bit selects one of two framing algorithms for ESF frame search in the presence of
mimic framing patterns in the incoming data. A logic 0 selects the ESF algorithm where the
FRMR does not declare in-frame while more than one framing bit candidate is following the
framing pattern in the incoming data. A logic 1 selects the ESF algorithm where a CRC-6
calculation is performed on each framing bit candidate, and is compared against the CRC bits
associated with the framing bit candidate to determine the most likely framing bit position.
ESF:
The ESF bit selects either extended superframe format or enables the Frame Mode Select
bits to select either standard superframe, T1DM, or SLC®96 framing formats. A logic 1 in the
ESF bit position selects ESF; a logic 0 bit enables FMS1 and FMS0 to select SF, T1DM, or
SLC®96.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
151
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
FMS1,FMS0:
The FMS1 and FMS0 bits select standard superframe, T1DM, or SLC®96 framing formats. A
logic 00 in these bits enable the SF framing format; a logic 01 or 11 in these bit positions
enable the T1DM framing format; a logic 10 in these bit positions enable the SLC®96 framing
format. When ESF is selected (ESF bit set to logic 1), the FMS1 and FMS0 bits select the
data rate and the source channel for the facility data link data. A logic 00 in these bits enables
the FRMR to receive FDL data at the full 4 kHz rate from every odd frame. When ESF is
selected, FMS1 and FMS0 settings other than logic 00 are reserved and should not be used.
The valid combinations of the ESF, FMS1, and FMS0 bits are summarized in the table below:
Table 18
- T1 Framing Modes
ESF
FMS1
FMS0
Mode
0
0
0
Select SF framing format
0
0
1
Select T1DM framing format
0
1
0
Select SLC®96 framing format
0
1
1
Select T1DM framing format
1
0
0
Select ESF framing format & 4 kHz FDL Data Rate
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
JPN:
The JPN bit enables Japanese variations of the standard framing formats. If the JPN bit is a
logic 1 and the ESF format is selected (ESF bit is logic 1), the T1-FRMR complies with TTC
JT-G704. If the JPN bit is a logic 1 and a non-ESF format is selected (ESF bit is logic 0), it is
th
assumed the 12 F-bit of the superframe carries a far end receive failure alarm. The alarm is
extracted and the framing is modified to be robust when the alarm is active.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
152
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 049H, 149H, 249H, 349H: T1-FRMR Interrupt Enable
Bit
Type
Bit 7
Function
Default
Unused
X
Bit 6
R/W
Reserved
0
Bit 5
R/W
COFAE
0
Bit 4
R/W
FERE
0
Bit 3
R/W
BEEE
0
Bit 2
R/W
SFEE
0
Bit 1
R/W
MFPE
0
Bit 0
R/W
INFRE
0
When the E1/T1B bit of the Global Configuration register is a logic 1 or the UNF bit of the Receive
Options register is a logic 1, this register is held reset.
This register selects which of the MFP, COFA, FER, BEE, SFE or INFR events generates an
interrupt on the microprocessor INTB pin when their state changes or their event condition is
detected.
Reserved:
The Reserved bit is used for production test purposes only. The Reserved bit must be logic 0
for normal operation.
COFAE:
The COFAE bit enables the generation of an interrupt when the frame find circuitry
determines that frame alignment has been achieved and that the new alignment differs from
the previous alignment. When COFAE is set to logic 1, the declaration of a change of frame
alignment is allowed to generate an interrupt. When COFAE is set to logic 0, a change in the
frame alignment does not generate an interrupt on the INTB pin.
FERE:
The FERE bit enables the generation of an interrupt when a framing bit error has been
detected. When FERE is set to logic 1, the detection of a framing bit error is allowed to
generate an interrupt. When FERE is set to logic 0, any error in the framing bits does not
generate an interrupt on the INTB pin.
BEEE:
The BEEE bit enables the generation of an interrupt when a bit error event has been detected.
A bit error event is defined as framing bit errors for SF formatted data, CRC-6 mismatch
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
153
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
errors for ESF formatted data, Ft bit errors for SLC®96 formatted data, and either framing bit
errors or sync word errors for T1DM formatted data. When BEEE is set to logic 1, the
detection of a bit error event is allowed to generate an interrupt. When BEEE is set to logic 0,
bit error events are disabled from generating an interrupt on the INTB pin.
SFEE:
The SFEE bit enables the generation of an interrupt when a severely errored framing event
has been detected. A severely errored framing event is defined as 2 or more framing bit
errors during the current superframe for SF, ESF, or SLC®96 formatted data, and 2 or more
framing bit errors or sync word errors during the current superframe for T1DM formatted data.
When SFEE is set to logic 1, the detection of a severely errored framing event is allowed to
generate an interrupt. When SFEE is set to logic 0, severely errored framing events are
disabled from generating an interrupt on the INTB pin.
MFPE:
The MFPE bit enables the generation of an interrupt when the frame find circuitry detects the
presence of framing bit mimics. The occurrence of a mimic is defined as more than one
framing bit candidate following the frame alignment pattern. When MFPE is set to logic 1, the
assertion or deassertion of the detection of a mimic is allowed to generate an interrupt. When
MFPE is set to logic 0, the detection of a mimic framing pattern is disabled from generating an
interrupt on the INTB pin.
INFRE:
The INFRE bit enables the generation of an interrupt when the frame find circuitry determines
that frame alignment has been achieved and that the framer is now "in-frame". When INFRE
is set to logic 1, the assertion or deassertion of the "in-frame" state is allowed to generate an
interrupt. When INFRE is set to logic 0, a change in the "in-frame" state is disabled from
generating an interrupt on the INTB pin.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
154
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 04AH, 14AH, 24AH, 34AH: T1-FRMR Interrupt Status
Bit
Type
Function
Default
Bit 7
R
COFAI
X
Bit 6
R
FERI
X
Bit 5
R
BEEI
X
Bit 4
R
SFEI
X
Bit 3
R
MFPI
X
Bit 2
R
INFRI
X
Bit 1
R
MFP
X
Bit 0
R
INFR
X
When the E1/T1B bit of the Global Configuration register is a logic 1 or the UNF bit of the Receive
Options register is a logic 1, this register is held reset.
This register indicates whether a change of frame alignment, a framing bit error, a bit error event,
or a severely errored framing event generated an interrupt. This register also indicates whether a
mimic framing pattern was detected or whether there was a change in the "in-frame" state of the
frame circuitry.
COFAI, FERI, BEEI, SFEI:
A logic 1 in the status bit positions COFAI, FERI, BEEI and SFEI indicate that the occurrence
of the corresponding event generated an interrupt; a logic 0 in the status bit positions COFAI,
FERI, BEEI, and SFEI indicate that the corresponding event did not generate an interrupt.
MFPI:
A logic 1 in the MFPI status bit position indicates that the assertion or deassertion of the
mimic detection indication has generated an interrupt; a logic 0 in the MFPI bit position
indicates that no change in the state of the mimic detection indication occurred.
INFRI:
A logic 1 in the INFRI status bit position indicates that a change in the "in-frame" state of the
frame alignment circuitry generated an interrupt; a logic 0 in the INFRI status bit position
indicates that no state change occurred.
MFP, INFR:
The bit position MFP and INFR indicate the current state of the mimic detection and of the
frame alignment circuitry.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
155
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
The interrupt and the status bit positions (COFAI, FERI, BEEI, SFEI, MFPI, and INFRI) are
cleared to logic 0 when this register is read.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
156
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 04CH, 14CH, 24CH, 34CH: IBCD Configuration
Bit
Type
Function
Default
Bit 7
R/W
Reserved
0
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
R/W
DSEL1
0
Bit 2
R/W
DSEL0
0
Bit 1
R/W
ASEL1
0
Bit 0
R/W
ASEL0
0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset.
This register provides the selection of the Activate and De-activate loopback code lengths (from 3
bits to 8 bits) as follows:
Table 19
- Loopback Code Configurations
DEACTIVATE Code
ACTIVATE Code
DSEL1
DSEL0
ASEL1
ASEL0
CODE LENGTH
0
0
0
0
5 bits
0
1
0
1
6 (or 3*) bits
1
0
1
0
7 bits
1
1
1
1
8 (or 4*) bits
Note:
3-bit and 4-bit code sequences can be accommodated by configuring the IBCD for 6 or 8 bits and
by programming two repetitions of the code sequence.
Reserved:
The Reserved bit must be logic 0 for normal operation.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
157
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 04DH, 14DH, 24DH, 34DH: IBCD Interrupt Enable/Status
Bit
Type
Function
Default
Bit 7
R
LBACP
X
Bit 6
R
LBDCP
X
Bit 5
R/W
LBAE
0
Bit 4
R/W
LBDE
0
Bit 3
R
LBAI
X
Bit 2
R
LBDI
X
Bit 1
R
LBA
X
Bit 0
R
LBD
X
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset.
LBACP, LBDCP:
The LBACP and LBDCP bits indicate when the corresponding loopback code is present
during a 39.8 ms interval.
LBAE:
The LBAE bit enables the assertion or deassertion of the inband Loopback Activate (LBA)
detect indication to generate an interrupt on the microprocessor INTB pin. When LBAE is set
to logic 1, any change in the state of the LBA detect indication generates an interrupt. When
LBAE is set to logic 0, no interrupt is generated by changes in the LBA detect state.
LBDE:
The LBDE bit enables the assertion or deassertion of the inband Loopback Deactivate (LBD)
detect indication to generate an interrupt on the microprocessor INTB pin. When LBDE is set
to logic 1, any change in the state of the LBD detect indication generates an interrupt. When
LBDE is set to logic 0, no interrupt is generated by changes in the LBD detect state.
LBAI, LBDI:
The LBAI and LBDI bits indicate which of the two expected loopback codes generated the
interrupt when their state changed. A logic 1 in these bit positions indicates that a state
change in that code has generated an interrupt; a logic 0 in these bit positions indicates that
no state change has occurred.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
158
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
LBA, LBD:
The LBA and LBD bits indicate the current state of the corresponding loopback code detect
indication. A logic 1 in these bit positions indicates the presence of that code has been
detected; a logic 0 in these bit positions indicates the absence of that code.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
159
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 04EH, 14EH, 24EH, 34EH: IBCD Activate Code
Bit
Type
Function
Default
Bit 7
R/W
ACT7
0
Bit 6
R/W
ACT6
0
Bit 5
R/W
ACT5
0
Bit 4
R/W
ACT4
0
Bit 3
R/W
ACT3
0
Bit 2
R/W
ACT2
0
Bit 1
R/W
ACT1
0
Bit 0
R/W
ACT0
0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset.
This 8-bit register selects the Activate code sequence that is to be detected. If the code sequence
length is less than 8 bits, the first 8 bits of several repetitions of the code sequence must be used
to fill the 8-bit register. For example, if code sequence is a repeating 00001, the first 8 bits of two
repetitions (0000100001) is programmed into the register, i.e.00001000. Note that bit ACT7
corresponds to the first code bit received.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
160
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 04FH, 14FH, 24FH, 34FH: IBCD Deactivate Code
Bit
Type
Function
Default
Bit 7
R/W
DACT7
0
Bit 6
R/W
DACT6
0
Bit 5
R/W
DACT5
0
Bit 4
R/W
DACT4
0
Bit 3
R/W
DACT3
0
Bit 2
R/W
DACT2
0
Bit 1
R/W
DACT1
0
Bit 0
R/W
DACT0
0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset.
This 8-bit register selects the Deactivate code sequence that is to be detected. If the code
sequence length is less than 8 bits, the first 8 bits of several repetitions of the code sequence
must be used to fill the 8-bit register. For example, if code sequence is a repeating 001, the first 8
bits of three repetitions (001001001) is programmed into the register, i.e.00100100. Note that bit
DACT7 corresponds to the first code bit received.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
161
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 050H, 150H, 250H, 350H: SIGX Configuration Register (COSS = 0)
Bit
Type
Function
Default
Bit 7
R/W
Reserved
0
Bit 6
R/W
COSS
0
Bit 5
R/W
SIGE
0
Bit 4
R/W
Reserved
0
Bit 3
R/W
Reserved
0
Bit 2
R/W
ESF
0
Bit 1
R/W
IND
0
Bit 0
R/W
PCCE
0
Reserved
These bits must be a logic 0 for normal operation.
COSS:
The COSS bit allows the channels to be polled to determine in which channel(s) the signaling
state has changed. When COSS is a logic 1, the SIGX register space is configured to allow
the change of signaling state event bits to be read. When COSS is a logic 0, the SIGX register
space is configured to allow indirect access to the configuration and signaling data for each of
the 24 T1 or 30 E1 channels.
SIGE:
The SIGE bit enables a change of signaling state in any one of the 24 channels (T1 mode) or
30 channels for (E1 mode ) to generate an interrupt on the INTB output.
When SIGE is set to logic 1, a change of signaling state in any channel generates an
interrupt. When SIGE is set to logic 0, the interrupt is disabled.
ESF:
The framing format in T1 mode is controlled by the ESF bit. A logic 1 in the ESF bit position
selects ESF; a logic 0 bit selects SF or T1DM. When in E1 mode, this bit is ignored.
IND:
The IND bit controls the microprocessor access type: either indirect or direct.
Note: Although the default of IND is logic 0, IND must be logic 1 for proper operation.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
162
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
PCCE:
The per-timeslot/per-channel configuration enable bit, PCCE, enables the configuration data
in the Per-Timeslot/Per-Channel registers to affect the BRSIG[x] or CASBRD and BRPCM[x]
or MVBRD data streams. (When in Receive Clock Slave: H-MVIP mode, only the
timeslots/channels of the quadrant are affected on the CASBRD or MVBRD streams.) A
logic 1 in the PCCE bit position enables the Per-Timeslot/Per-Channel Configuration Register
bits in the indirect registers 40H through 5FH to affect the signaling and data stream; when
PCCE is logic 0, all zeroes are used instead of the values written into the indirect registers
40H through 5FH to affect the signaling and data stream. The PCCE bit must not be set to
logic 1 until indirect registers 40H to 5FH have been initialized. Please refer to section 12.10
Using the Per-Channel Serial Controllers and SIGX for details.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
163
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 050H, 150H, 250H, 350H: SIGX Change of Signaling State Register (COSS = 1)
Bit
Type
Bit 7
Function
Default
Unused
X
Bit 6
R/W
COSS
0
Bit 5
R
COSS[30]
X
Bit 4
R
COSS[29]
X
Bit 3
R
COSS[28]
X
Bit 2
R
COSS[27]
X
Bit 1
R
COSS[26]
X
Bit 0
R
COSS[25]
X
COSS[30:25]:
The COSS[30:25] bits will be set to logic 1 if a change of signaling state occurs on the
corresponding E1 timeslot. COSS[30:25] are cleared after this register is read. COSS[30:25]
are valid only if the E1/T1B register bit is a logic 1. The COSS bit allows the timeslot to be
polled to determine in which timeslot(s) the signaling state has changed. When COSS is a
logic 1, the SIGX register space is configured to allow the change of signaling state event bits
to be read. When COSS is a logic 0, the SIGX register space is configured to allow indirect
access to the configuration and signaling data for each of the 24 T1 or 30 E1 channels.
COSS[25] through COSS[30] correspond to timeslots 26 through 31.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
164
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 051H, 151H, 251H, 351H: SIGX Timeslot Indirect Status (COSS = 0)
Bit
Type
Function
Default
R
BUSY
0
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
Unused
X
Bit 1
Unused
X
Bit 0
Unused
X
Bit 7
The Timeslot Indirect Status Register is provided at SIGX read/write address 1.
BUSY:
The BUSY bit is set to logic 1 while the timeslot data is being retrieved or while the
configuration data is being written. The bit is set to logic 0 when the read or write cycle has
been completed. The BUSY signal holds off a microprocessor read or write access until the
SIGX has completed the previous request. This register should be polled until the BUSY bit is
logic 0. The bits in this register are valid only when COSS = 0.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
165
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 051H, 151H, 251H, 351H: SIGX Change Of Signaling State Change (COSS=1)
Bit
Type
Function
Default
Bit 7
R
COSS[24]
X
Bit 6
R
COSS[23]
X
Bit 5
R
COSS[22]
X
Bit 4
R
COSS[21]
X
Bit 3
R
COSS[20]
X
Bit 2
R
COSS[19]
X
Bit 1
R
COSS[18]
X
Bit 0
R
COSS[17]
X
COSS[24:17]:
The COSS[24:17] bits will be set to logic 1 if a change of signaling state occurs on the
corresponding E1 timeslot OR T1 channel. COSS[24:17] are cleared after this register is
read.
In E1 mode, COSS[17] through COSS[24] correspond to timeslots 18 through 25.
For the purposes of signaling extraction, the T1 channels are indexed 1 through 24.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
166
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 052H, 152H, 252H, 352H: SIGX Timeslot Indirect Address/Control (COSS = 0)
Bit
Type
Function
Default
Bit 7
R/W
RWB
0
Bit 6
R/W
A[6]
0
Bit 5
R/W
A[5]
0
Bit 4
R/W
A[4]
0
Bit 3
R/W
A[3]
0
Bit 2
R/W
A[2]
0
Bit 1
R/W
A[1]
0
Bit 0
R/W
A[0]
0
If the SIGX is enabled for direct microprocessor access, writing to and reading from the Timeslot
Indirect Address Register will not generate any additional accesses.
A[6:0]:
If the SIGX is enabled for indirect microprocessor access, writing to the Timeslot Indirect
Address Register initiates a microprocessor access request to one of the registers in
segments 2 and 3. The desired register is addressed using the value written to bits A[6:0].
RWB:
The RWB bit indicates which operation is requested. If RWB is set to logic 1, a read is
requested. After the request has been issued, the Timeslot Indirect Status register should be
monitored to verify completion of the read. The desired register contents can then be found in
the Timeslot Indirect Data Register. If RWB is set to logic 0, a write is requested. Data to be
written to the microprocessor should first be placed in the Timeslot Indirect Data Register. For
both read and write operations, the BUSY bit in the Timeslot Indirect Status Register should
be monitored to ensure that the previous access has been completed.
Note: If the value written to A[6:0] addresses a segment 1 register, an access is not initiated.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
167
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 052H, 152H, 252H, 352H: SIGX Change of Signaling State Register (COSS = 1)
Bit
Type
Function
Default
Bit 7
R
COSS[16]
X
Bit 6
R
COSS[15]
X
Bit 5
R
COSS[14]
X
Bit 4
R
COSS[13]
X
Bit 3
R
COSS[12]
X
Bit 2
R
COSS[11]
X
Bit 1
R
COSS[10]
X
Bit 0
R
COSS[9]
X
COSS[16:9]:
The COSS[16:9] bits will be set to logic 1 if a change of signaling state occurs on the
corresponding E1 timeslot or T1 channel. COSS[16:9] are cleared after this register is read.
In E1 mode, COSS[9] through COSS[15] correspond to timeslots 9 through 15 and COSS[16]
corresponds to timeslot 17.
For the purposes of signaling extraction, the T1 channels are indexed 1 through 24.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
168
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 053H, 153H, 253H, 353H: SIGX Timeslot Indirect Data Buffer (COSS = 0)
Bit
Type
Function
Default
Bit 7
R/W
D[7]
X
Bit 6
R/W
D[6]
X
Bit 5
R/W
D[5]
X
Bit 4
R/W
D[4]
X
Bit 3
R/W
D[3]
X
Bit 2
R/W
D[2]
X
Bit 1
R/W
D[1]
X
Bit 0
R/W
D[0]
X
In the case of an indirect write, the Indirect Data Register holds the value that will be written to the
desired register when a write is initiated via the Timeslot Indirect Address Register. In the case of
an indirect read, the Indirect Data Register will hold the contents of the indirectly addressed
register, when the read has been completed. Please refer below to the per-timeslot register
descriptions for the expected bit formats.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
169
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 053H, 153H, 253H, 353H: SIGX Change of Signaling State (COSS = 1)
Bit
Type
Function
Default
Bit 7
R
COSS[8]
X
Bit 6
R
COSS[7]
X
Bit 5
R
COSS[6]
X
Bit 4
R
COSS[5]
X
Bit 3
R
COSS[4]
X
Bit 2
R
COSS[3]
X
Bit 1
R
COSS[2]
X
Bit 0
R
COSS[1]
X
COSS[8:1]:
The COSS[8:1] bits will be set to logic 1 if a change of signaling state occurs on the
corresponding E1 timeslot or T1 channel. COSS[8:1] are cleared after this register is read.
In E1 mode, COSS[1] through COSS[8] correspond to timeslots 1 through 8.
For the purposes of signaling extraction, the T1 channels are indexed 1 through 24.
SIGX Indirect Registers
The signaling and per-timeslot functions are allocated within the indirect registers as follows:
Table 20
- SIGX Indirect Register Map
Addr
Register
10H
Current Signaling Data Register for Ch 1 and 17
11H
Current Signaling Data Register for TS1 and 17/Ch 2 and 18
12H
Current Signaling Data Register for TS2 and 18/Ch 3 and 19
13H
Current Signaling Data Register for TS3 and 19/Ch 4 and 20
14H
Current Signaling Data Register for TS4 and 20/Ch 5 and 21
15H
Current Signaling Data Register for TS5 and 21/Ch 6 and 22
16H
Current Signaling Data Register for TS6 and 22/Ch 7 and 23
17H
Current Signaling Data Register for TS7 and 23/Ch 8 and 24
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
170
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Addr
Register
18H
Current Signaling Data Register for TS8 and 24/Ch 9
19H
Current Signaling Data Register for TS9 and 25/Ch 10
1AH
Current Signaling Data Register for TS10 and 26/Ch 11
1BH
Current Signaling Data Register for TS11 and 27/Ch 12
1CH
Current Signaling Data Register for TS12 and 28/Ch 13
1DH
Current Signaling Data Register for TS13 and 29/Ch 14
1EH
Current Signaling Data Register for TS14 and 30/Ch 15
1FH
Current Signaling Data Register for TS15 and 31/Ch 16
20H
Delayed Signaling Data Register for Ch 1
21H
Delayed Signaling Data Register for TS1/Ch 2
22H
Delayed Signaling Data Register for TS2/Ch 3
•
•
•
•
•
•
2FH
Delayed Signaling Data Register for TS15/Ch 16
30H
Delayed Signaling Data Register for Ch 17
31H
Delayed Signaling Data Register for TS17/Ch 18
•
•
•
•
•
•
37H
Delayed Signaling Data Register for TS23/Ch 24
38H
Delayed Signaling Data Register for TS24
•
•
•
•
•
•
3EH
Delayed Signaling Data Register for TS30
3FH
Delayed Signaling Data Register for TS31
40H
TS0/Ch 1 Configuration Data
41H
TS1/Ch 2 Configuration Data
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
171
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Addr
Register
•
•
•
•
•
•
57H
TS23/Ch 24 Configuration Data
58H
TS24 Configuration Data
•
•
•
•
•
•
5EH
TS 30 Configuration Data
5FH
TS 31 Configuration Data
Table 21
Bit
- SIGX Indirect Registers 10H - 1FH: Current Timeslot/Channel Signaling Data
Type
Function
Default
Bit 7
R
A TS/Ch ‘n’
X
Bit 6
R
B TS/Ch ‘n’
X
Bit 5
R
C TS/Ch ‘n’
X
Bit 4
R
D TS/Ch ‘n’
X
Bit 3
R
A TS/Ch ‘n+16’
X
Bit 2
R
B TS/Ch ‘n+16’
X
Bit 1
R
C TS/Ch ‘n+16’
X
Bit 0
R
D TS/Ch ‘n+16’
X
Timeslot (E1 mode) and Channel (T1 mode) signaling data can be read from the
Timeslot/Channel Signaling Data registers. In E1 mode, TS0 and TS16 do not contain valid data
and are not available for reading. The signaling data is termed “Current” here because it is
available in the same signaling multi-frame that the COSS[x] indication is available. Note that the
signaling data is stored in nibble format.
Table 22
Bit
Bit 7
- SIGX Indirect Registers 20H - 3FH: Delayed Timeslot/Channel Signaling Data
Type
Function
Default
Unused
X
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
172
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Bit
Type
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Function
Default
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
R
A TS/Ch ‘n’
X
Bit 2
R
B TS/Ch ‘n’
X
Bit 1
R
C TS/Ch ‘n’
X
Bit 0
R
D TS/Ch ‘n’
X
Timeslot (E1 mode) and Channel (T1 mode) signaling data can be read from the
Timeslot/Channel Signaling Data registers. Addresses 20H - 37H are valid in T1 mode.
Addresses 20H-3FH correspond to TS 0 - TS31. In E1 mode, TS0 and TS16 do not contain valid
data. The signaling data is termed “Delayed” here because it is not available until one full signaling
multi-frame after the COSS[x] indication is available.
Table 23
Bit
- Indirect Registers 40H - 5FH: Per-Timeslot Configuration
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
R/W
RINV[1]
X
Bit 2
R/W
RINV[0]/RFIX
X
Bit 1
R/W
RPOL
X
Bit 0
R/W
RDEBE
X
RINV[1:0] / RFIX:
In T1 mode, the RINV[1] and SIGNINV bit of the RPSC Data Control byte can be used to
invert data as shown in Table 24:
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
173
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Table 24
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- SIGX Per-Channel T1 Data Conditioning
RINV[1]
SIGNINV
Effect on PCM Channel Data
0
0
PCM Channel data is unchanged
1
0
All 8 bits of the received PCM channel data are inverted
0
1
Only the MSB of the received PCM channel data is inverted (SIGN bit
inversion)
1
1
All bits EXCEPT the MSB of the received PCM channel data is
inverted (Magnitude inversion)
In E1 mode, the RINV[1:0] bits select bits within the timeslot are inverted. The bit mapping is
as shown in Table 25.
Table 25
- SIGX Per-Channel E1 Data Conditioning
RINV[1]
RINV[0]
Effect on PCM Channel Data
0
0
do not invert
0
1
invert even bits (2,4,6,8)
1
0
invert odd bits (1,3,5,7)
1
1
invert all bits
Because of the distinct requirements for E1 and T1, the register bits have different definitions
in the two modes. In E1 mode bit 2 is defined as RINV[0]; whereas in T1 it is RFIX. RINV[1]
has a different effect for the two modes.
In T1 mode, RFIX controls whether the signaling bit (the least significant bit of the DS0
channel on BRPCM[x] or MVBRD of the quadrant during signaling frames) is fixed to the
polarity specified by the RPOL bit. A logic 1 in the RFIX position enables bit fixing; a logic 0 in
the RFIX position disables bit fixing. Note that the RPSC functions (inversion, digital milliwatt
code insertion, trunk conditioning, and PRBS detection or insertion) take place after bit fixing.
RPOL:
In T1 mode, the RPOL bit selects the logic level the signaling bit is fixed to when bit fixing is
enabled. When RPOL is a logic 1, the signaling is fixed to logic 1. When RPOL is a logic 0,
the signaling is fixed to logic 0.
RDEBE:
The RDEBE bit enables debouncing of timeslot/channel signaling bits. A logic 1 in this bit
position enables signaling debouncing while a logic 0 disables it. When debouncing is
selected, per-timeslot/per-channel signaling transitions are ignored until two consecutive,
equal values are sampled. Debouncing is performed on a per signaling bit basis.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
174
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Data inversion, data trunk conditioning, and digital milliwatt insertion are performed independently
of the received framing format. Digital milliwatt insertion takes precedence over data trunk
conditioning which, in turn, takes precedence over the various data inversions.
To enable the RINV[1], RINV[0]/RFIX, RPOL, RDEBE bits, the PCCE bit in the SIGX
Configuration Register must be set to logic 1.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
175
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 054H, 154H, 254H, 354H: T1-XBAS Configuration
Bit
Type
Function
Default
Bit 7
R/W
MTRK
0
Bit 6
R/W
JPN
0
Bit 5
R/W
B8ZS
0
Bit 4
R/W
ESF
0
Bit 3
R/W
FMS1
0
Bit 2
R/W
FMS0
0
Bit 1
R/W
ZCS1
0
Bit 0
R/W
ZCS0
0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset.
MTRK:
The MTRK bit forces trunk conditioning, idle code substitution and signaling conditioning, on
all channels when MTRK is a logic 1. This has the same effect as setting the IDLE_CHAN bit
in the PCM Control byte and the SIG0 bit in the SIGNALING Control byte for all channels.
JPN:
The JPN bit enables Japanese variations of the standard framing formats. If the JPN bit is a
logic 1 and the ESF format is selected (ESF bit is logic 1), the T1-XBAS complies with TTC
JT-G704. If the JPN bit is a logic 1 and the SF format is selected, the framing bit of frame 12
is forced to logic 1 when a Yellow alarm is declared. Otherwise, bit 2 in all of the channels is
forced to logic 0 to indicate Yellow alarm. Framing insertion must be enabled in order to
transmit the alternate SF Yellow alarm.
B8ZS:
The B8ZS bit enables B8ZS line coding when it is a logic 1. When the B8ZS bit is a logic 0,
AMI coding is used.
ESF, FMS1, FMS0:
The ESF bit selects either Extended Superframe format or enables the Frame Mode Select
bits (FMS) to select either regular superframe or T1DM framing formats. The mode is
encoded as follows:
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
176
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Table 26
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- T1 Framing Formats
ESF
FMS1
FMS0
MODE
0
0
0
SF framing format
0
0
1
T1DM framing format (R bit unaffected)
0
1
0
Reserved
0
1
1
T1DM framing format (FDL data replaces R bit)
1
0
0
ESF framing format - 4 kbit/s data link
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
ZCS[1:0]:
The ZCS[1:0] bits select the Zero Code Suppression format to be used. These register bits
are logically ORed with the value of the ZCS[1:0] register bits in the TPSC per-channel PCM
Control byte. The bits are encoded as follows:
Table 27
- T1 Zero Code Suppression Formats
ZCS1
ZCS0
Zero Code Suppression Format
0
0
None
0
1
GTE Zero Code Suppression (Bit 8 of an all zero channel byte is
replaced by a one, except in signaling frames where bit 7 is forced to a
one.)
1
0
DDS Zero Code Suppression (All zero data byte replaced with
"10011000")
1
1
Bell Zero Code Suppression (Bit 7 of an all zero channel byte is replaced
by a one.)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
177
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 055H, 155H, 255H, 355H: T1-XBAS Alarm Transmit
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
Unused
X
Bit 1
R/W
XYEL
0
Bit 0
R/W
XAIS
0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset.
This register controls the transmission of Yellow or AIS alarm.
XYEL
The XYEL bit enables the T1-XBAS to generate a Yellow alarm in the appropriate framing
format. When XYEL is set to logic 1, T1-XBAS is enabled to set bit 2 of each channel to
logic 0 for SF format, the Y-bit to logic 0 for T1DM format, and T1-XBAS is enabled to transmit
repetitions of 1111111100000000 (the Yellow Alarm BOC) on the FDL for ESF format. If the
JPN bit of the T1-XBAS Configuration register is a logic 1 and the SF format is selected, the
framing bit of frame 12 is forced to logic 1 when a Yellow alarm is enabled. When XYEL is set
to logic 0, T1-XBAS is disabled from generating the Yellow alarm.
XAIS:
The XAIS bit enables the T1-XBAS to generate an unframed all-ones AIS alarm. When XAIS
is set to logic 1, the T1-XBAS bipolar outputs are forced to pulse alternately, creating an allones signal. When XAIS is set to logic 0, the T1-XBAS bipolar outputs operate normally.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
178
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 056H, 156H, 256H, 356H: T1 XIBC Control
Bit
Type
Function
Default
Bit 7
R/W
EN
0
Bit 6
R/W
UF
0
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
Unused
X
Bit 1
R/W
CL1
0
Bit 0
R/W
CL0
0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset.
EN:
The EN bit controls whether the Inband Code is transmitted or not. A logic 1 in the EN bit
position enables transmission of inband codes; a logic 0 in the EN bit position disables inband
code transmission.
UF:
The UF bit controls whether the code is transmitted framed or unframed. A logic 1 in the UF
bit position selects unframed inband code transmission; a logic 0 in the UF bit position selects
framed inband code transmission. Note: the UF register bit controls the T1-XBAS directly and
is not qualified by the EN bit. When UF is set to logic 1, the T1-XBAS is disabled and no
framing is inserted regardless of the setting of EN. The UF bit should only be written to logic 1
when the EN bit is set, and should be cleared to logic 0 when the EN bit is cleared.
CL1, CL0:
The bit positions CL1 and CL0 of this register indicate the length of the inband loopback code
sequence, as follows:
Table 28
- Transmit In-band Code Length
CL1
CL0
Code Length
0
0
5
0
1
6
1
0
7
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
179
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
CL1
CL0
Code Length
1
1
8
Codes of 3 or 4 bits in length may be accommodated by treating them as half of a double-sized
code (i.e., a 3-bit code would use the 6-bit code length setting).
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
180
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 057H, 157H, 257H, 357H: T1 XIBC Loopback Code
Bit
Type
Function
Default
Bit 7
R/W
IBC7
X
Bit 6
R/W
IBC6
X
Bit 5
R/W
IBC5
X
Bit 4
R/W
IBC4
X
Bit 3
R/W
IBC3
X
Bit 2
R/W
IBC2
X
Bit 1
R/W
IBC1
X
Bit 0
R/W
IBC0
X
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset.
This register contains the inband loopback code pattern to be transmitted. The code is transmitted
most significant bit ( IBC7) first, followed by IBC6 and so on. The code, regardless of the length,
must be aligned with the MSB always in the IBC7 position (e.g., a 5-bit code would occupy the
IBC7 through IBC2 bit positions). To transmit a 3-bit or a 4-bit code pattern, the pattern must be
paired to form a double-sized code (i.e., the 3-bit code '011' would be written as the 6-bit code
'011011').
When the COMET-QUAD is reset, the contents of this register are not affected.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
181
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 058H, 158H, 258H, 358H: PMON Interrupt Enable/Status
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
R/W
INTE
0
Bit 1
R
XFER
0
Bit 0
R
OVR
0
This register contains status information indicating when counter data has been transferred into
the holding registers and indicating whether the holding registers have been overrun.
INTE:
The INTE bit controls the generation of a microprocessor interrupt when the transfer clock
has caused the counter values to be stored in the holding registers. A logic 1 bit in the INTE
position enables the generation of an interrupt via the INTB output; a logic 0 bit in the INTE
position disables the generation of an interrupt.
XFER:
The XFER bit indicates that a transfer of counter data has occurred. A logic 1 in this bit
position indicates that a latch request, initiated by writing to one of the counter register
locations or the Quadrant PMON Update register, was received and a transfer of the counter
values has occurred. A logic 0 indicates that no transfer has occurred. The XFER bit is
cleared (acknowledged) by reading this register.
OVR:
The OVR bit is the overrun status of the holding registers. A logic 1 in this bit position indicates
that a previous transfer (indicated by XFER being logic 1) has not been acknowledged before
the next transfer clock has been issued and that the contents of the holding registers have
been overwritten. A logic 0 indicates that no overrun has occurred. Reading this register clears
the OVR bit.
Registers 059-05FH, 159-15FH, 259-25FH, 359-35FH: Latching Performance Data
The Performance Data registers for a quadrant are updated as a group by writing to any of the
quadrant’s PMON count registers (addresses 059H-05FH, 159-15FH, 259-25FH, 359-35FH). A
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
182
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
write to one (and only one) of these locations loads performance data located in the PMON into
the internal holding registers. Alternatively, the Performance Data registers for the quadrant are
updated by writing to the Revision/Chip ID/Quadrant PMON Update register (addresses 00DH,
10DH, 20DH, 30DH). The data contained in the holding registers can then be subsequently read
by microprocessor accesses into the PMON count register address space. The latching of count
data, and subsequent resetting of the counters, is synchronized to the internal event timing so that
no events are missed.
The PMON is loaded with new performance data within 3.5 recovered clock periods of the latch
performance data register write. With nominal line rates, the PMON registers should not be polled
until 2.3 µsec have elapsed from the "latch performance data" register write.
When the COMET-QUAD is reset, the contents of the PMON count registers are unknown until
the first latching of performance data is performed.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
183
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 059H, 159H, 259H, 359H: PMON Framing Bit Error Count
Bit
Type
Bit 7
Function
Default
Unused
X
Bit 6
R
FER[6]
X
Bit 5
R
FER[5]
X
Bit 4
R
FER[4]
X
Bit 3
R
FER[3]
X
Bit 2
R
FER[2]
X
Bit 1
R
FER[1]
X
Bit 0
R
FER[0]
X
FER[6:0]:
The FER[6:0] bits indicate the number of framing bit error events that occurred during the
previous accumulation interval. The FER counts are suppressed when the framer has lost
frame alignment (OOF in the E1-FRMR Framing Status register is logic 1 or INFR in the
T1-FRMR Interrupt Status register is logic 0).
In T1 mode, a framing bit error is defined as an Fe-bit error in ESF, a framing bit error in SF,
an FT-bit error in SLC®96, or an F-bit error in T1DM.
In E1 mode, the count is either the number of FAS (frame alignment signal) bits (default) or
words in error. As an option, a zero in bit 2 of timeslot 0 of non-frame alignment signal
(NFAS) frames results in an increment of the framing error count. Refer to the Receive
Options register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
184
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 05AH, 15AH, 25AH, 35AH: PMON OOF/COFA/Far End Block Error Count LSB
Bit
Type
Function
Default
Bit 7
R
OOF/FEBE[7]
X
Bit 6
R
OOF/FEBE[6]
X
Bit 5
R
OOF/FEBE[5]
X
Bit 4
R
OOF/FEBE[4]
X
Bit 3
R
OOF/FEBE[3]
X
Bit 2
R
OOF/FEBE[2]
X
Bit 1
R
OOF/FEBE[1]
X
Bit 0
R
OOF/FEBE[0]
X
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
185
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 05BH, 15BH, 25BH, 35BH: PMON OOF/COFA/Far End Block Error Count MSB
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
Unused
X
Bit 1
R
OOF/FEBE[9]
X
Bit 0
R
OOF/FEBE[8]
X
OOF/FEBE[9:0]:
In T1 mode, the OOF[9:0] bits indicate the number Out Of Frame or Change Of Frame
Alignment events that occurred during the previous accumulation interval, as specified by the
CCOFA bit in the Receive Options register. If OOF's are being accumulated, the count is
incremented each time a severely errored framing event forces a reframe. IF COFA's are
being accumulated, the count is incremented if a new alignment differs from the previous
alignment.
In E1 mode, the FEBE[9:0] bits indicate the number of far end block error events that
occurred during the previous accumulation interval. The FEBE counts are suppressed when
the E1-FRMR has lost frame alignment (OOF in the FRMR Framing Status register is set).
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
186
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 05CH, 15CH, 25CH, 35CH: PMON Bit Error/CRC Error Count LSB
Bit
Type
Function
Default
Bit 7
R
BEE/CRCE[7]
X
Bit 6
R
BEE/CRCE[6]
X
Bit 5
R
BEE/CRCE[5]
X
Bit 4
R
BEE/CRCE[4]
X
Bit 3
R
BEE/CRCE[3]
X
Bit 2
R
BEE/CRCE[2]
X
Bit 1
R
BEE/CRCE[1]
X
Bit 0
R
BEE/CRCE[0]
X
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
187
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 05DH, 15DH, 25DH, 35DH: PMON Bit Error/CRC Error Count MSB
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
Unused
X
Bit 1
R
BEE/CRCE[9]
X
Bit 0
R
BEE/CRCE[8]
X
BEE/CRCE[9:0]:
In T1 mode, the BEE[9:0] bits contain the number of bit error events that occurred during the
previous accumulation interval. A bit error event is defined as a CRC-6 error in ESF, a
framing bit error in SF, an FT-bit error in SLC®96, and an F-bit or sync bit error (there can be
up to 7 bits in error per frame) in T1DM.
In E1 mode, the CRCE[9:0] bits indicate the number of CRC error events that occurred during
the previous accumulation interval. CRC error events are suppressed when the E1-FRMR is
out of CRC-4 multiframe alignment (OOCMF bit in the FRMR Framing Status register is set).
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
188
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 05EH, 15EH, 25EH, 35EH: PMON LCV Count (LSB)
Bit
Type
Function
Default
Bit 7
R
LCV[7]
X
Bit 6
R
LCV[6]
X
Bit 5
R
LCV[5]
X
Bit 4
R
LCV[4]
X
Bit 3
R
LCV[3]
X
Bit 2
R
LCV[2]
X
Bit 1
R
LCV[1]
X
Bit 0
R
LCV[0]
X
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
189
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 05FH, 15FH, 25FH, 35FH: PMON LCV Count (MSB)
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
R
LCV[12]
X
Bit 3
R
LCV[11]
X
Bit 2
R
LCV[10]
X
Bit 1
R
LCV[9]
X
Bit 0
R
LCV[8]
X
LCV[12:0]:
The LCV[12:0] bits indicate the number of LCV error events that occurred during the previous
accumulation interval. An LCV event is defined as the occurrence of a Bipolar Violation or
Excessive Zeros. The counting of Excessive Zeros can be disabled by the BPV bit of the
Receive Line Interface Configuration register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
190
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 060H, 160H, 260H, 360H: T1 ALMI Configuration
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
R/W
ESF
0
Bit 3
R/W
FMS1
0
Bit 2
R/W
FMS0
0
Bit 1
Unused
X
Bit 0
Unused
X
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset.
This register allows selection of the framing format and the data rate of the Facility Data Link in
ESF to allow operation of the CFA detection algorithms.
ESF:
The ESF bit selects either extended superframe format or enables the frame mode select bits
to select either regular superframe, T1DM, "alternate" T1DM, or SLC®96 framing formats. A
logic 1 in the ESF bit position selects ESF; a logic 0 bit enables FMS1 and FMS0 to select SF,
T1DM, "alternate" T1DM, or SLC®96.
FMS1,FMS0:
The FMS1 and FMS0 bits select standard superframe, T1DM, "alternate" T1DM, or SLC®96
framing formats. A logic 00 in these bits enable the SF framing format; a logic 01 in these bit
positions enable the T1DM framing format; and a logic 11 in these bit positions enable the
"alternate" T1DM framing format; a logic 10 in these positions enable SLC®96 framing format.
The "alternate" T1DM framing format configures the ALMI to process the Red alarm as if the
SF, SLC®96 or ESF framing format were selected; the Yellow alarm is still processed as
T1DM.
When ESF is selected (ESF bit set to logic 1), the FMS1 and FMS0 bits select the data rate
and the source channel for the Facility Data Link (FDL) data. A logic 00 in these bits enables
the ALMI to receive FDL data and validate the Yellow alarm at the full 4 kbit rate.
The valid combinations of the ESF, FMS1, and FMS0 bits are summarized in the table below:
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
191
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Table 29
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- T1 Framing Modes
ESF
FMS1
FMS0
Mode
0
0
0
Select Superframe framing format
0
0
1
Select T1DM framing format
0
1
0
Select SLC®96 framing format
0
1
1
Select "alternate" T1DM mode
1
0
0
Select ESF framing format & 4 kbit FDL Data Rate
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
192
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 061H, 161H, 261H, 361H: T1 ALMI Interrupt Enable
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
R/W
FASTD
0
Bit 3
R/W
Reserved
0
Bit 2
R/W
YELE
0
Bit 1
R/W
REDE
0
Bit 0
R/W
AISE
0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset.
This register selects which of the three CFA's can generate an interrupt when their logic state
changes and enables the "fast" deassertion mode of operation.
FASTD:
The FASTD bit enables the "fast" deassertion of Red and AIS alarms. When FASTD is set to
a logic 1, deassertion of Red alarm occurs within 120 ms of going in frame. Deassertion of
AIS alarm occurs within 180 ms of either detecting a 60 ms interval containing 127 or more
zeros, or going in frame. When FASTD is set to a logic 0, Red and AIS alarm deassertion
times remain as defined in the ALMI description.
Reserved:
The Reserved bit must be logic 0 for normal operation.
YELE, REDE, AISE:
A logic 1 in the enable bit positions (YELE, REDE, AISE) enables a state change in the
corresponding CFA to generate an interrupt; a logic 0 in the enable bit positions disables any
state changes to generate an interrupt. The enable bits are independent; any combination of
Yellow, Red, and AIS CFA's can be enabled to generate an interrupt.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
193
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 062H, 162H, 262H, 362H: T1 ALMI Interrupt Status
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
R
YELI
X
Bit 4
R
REDI
X
Bit 3
R
AISI
X
Bit 2
R
YEL
X
Bit 1
R
RED
X
Bit 0
R
AIS
X
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset.
This register indicates which of the three Carry Failure Alarms (CFA's) generated an interrupt
when their logic state changed in bit positions 5 through 3, and indicate the current state of each
CFA in bit positions 2 through 0. A logic 1 in the status positions (YELI, REDI, AISI) indicate that a
state change in the corresponding CFA has generated an interrupt; a logic 0 in the status positions
indicates that no state change has occurred. Both the status bit positions (bits 5 through 3) and
the interrupt generated because of the change in CFA state are cleared to logic 0 when the
register containing then is read.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
194
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 063H, 163H, 263H, 363H: T1 ALMI Alarm Detection Status
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
R
REDD
X
Bit 1
R
YELD
X
Bit 0
R
AISD
X
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset.
This register indicates the presence or absence of one or more OOF occurrences within the last
40 ms; the presence or absence of the Yellow alarm signal over the last 40 ms; and indicate the
presence or absence of the AIS alarm signal over the last 60 ms.
REDD:
When REDD is a logic 1, one or more out of frame events have occurred during the last
40 ms interval. When REDD is a logic 0, no out of frame events have occurred within the last
40 ms interval.
YELD:
When YELD is logic 1, a valid Yellow signal was present during the last 40 ms interval. When
YELD is logic 0, the Yellow signal was absent during the last 40 ms interval. For each framing
format, a valid Yellow signal is deemed to be present if:
•
bit 2 of each channel is not logic 0 for 16 or fewer times during the 40 ms interval
for the SF and SLC®96 framing formats;
•
the Y-bit is not logic 0 for 4 or fewer times during the 40 ms interval for T1DM
framing format;
•
the 16-bit Yellow bit oriented code is received error-free 8 or more times during
the interval for ESF framing format with a 4 kHz data link;
•
In a Japanese T1 mode, the 12 F-bit toggles between 1 and 0 signifying a
Japanese Yellow alarm
th
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
195
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
AISD:
When AISD is logic 1, a valid AIS signal was present during the last 60 ms interval. When
AISD is logic 0, the AIS signal was absent during the last 60 ms interval. A valid AIS signal is
deemed to be present during a 60 ms interval if the out of frame condition has persisted for
the entire interval and the received PCM data stream is not logic 0 for 126 or fewer times.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
196
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 065H, 165H, 265H, 365H: T1 PDVD Interrupt Enable/Status
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
R
PDV
X
Bit 3
R
Z16DI
X
Bit 2
R
PDVI
X
Bit 1
R/W
Z16DE
0
Bit 0
R/W
PDVE
0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset.
PDV:
The PDV bit indicates the current state of the pulse density violation indication. When PDV is
a logic 1, a violation of the pulse density rule exists. When PDV is a logic 0, no violation of the
pulse density rule exists. Note: the PDV indication persists for the duration of the pulse density
violation. At its minimum, PDV may be asserted for only 1 bit time, therefore, reading this bit
may not return a logic 1 even though a pulse density violation has occurred.
PDVI, Z16DI:
The PDVI and Z16DI bits identify the source of a generated interrupt. PDVI is a logic 1
whenever a change in the pulse density violation indication generated an interrupt. PDVI is
cleared to 0 when this register is read. Z16DI is a logic 1 whenever 16 consecutive zeros are
detected. Z16DI is cleared to 0 when this register is read. Note that the PDVI and Z16DI
interrupt indications operate regardless of whether interrupts are enabled or disabled.
Z16DE:
The Z16DE bit enables an interrupt to be generated on the microprocessor INTB pin when 16
consecutive zeros are detected. When Z16DE is set to logic 1, interrupt is generation is
enabled. When Z16DE is set to logic 0, interrupt generation is disabled.
PDVE:
The PDVE bit enables an interrupt to be generated on the microprocessor INTB pin when a
change in the pulse density is detected. When PDVE is set to logic 1, an interrupt is
generated whenever a pulse density violation occurs or when the pulse density ceases to
exist. When PDVE is set to logic 0, interrupt generation by pulse density violations is
disabled.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
197
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 066H, 166H, 266H, 366H: T1 XBOC Control
Bit
Type
Function
Default
Bit 7
R
BOCSMPI
X
Bit 6
R/W
BOCSMPE
0
Bit 5
R
RDY
X
Unused
X
Bit 4
Bit 3
R/W
RPT[3]
0
Bit 2
R/W
RPT[2]
0
Bit 1
R/W
RPT[1]
0
Bit 0
R/W
RPT[0]
0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset.
BOCSMPI:
The BOCSMPI bit is set high when the XBOC Code register and RPT[3:0] are sampled by the
XBOC, indicating that the Code Register is ready to be updated with a new BOC. BOCSMPI
will not change while a Control Register read is in process. Instead, BOCSMPI will hold its
initial value – its value at the start of a Control Register read cycle, when RDB falls – until the
Control Register read cycle is complete, when RDB rises. After RDB rises, BOCSMPI will be
cleared to 0 if it was logic 1 during the read, otherwise BOCSMPI will not be cleared.
BOCSMPE:
Setting BOCSMPE to logic 1 enables a hardware interrupt on the INTB output pin when
BOCSMPI is logic 1.
RDY:
The RDY bit is set high when the Code Register and RPT[3:0] are sampled by the XBOC,
indicating that the XBOC is ready to be updated with a new BOC. Whenever a new BOC is
written, RDY goes low, indicating that the BOC has not yet been accepted by the XBOC state
machine. Note that if the XBOC code register is written with a new value, causing RDY to fall,
and then written with its original value, RDY will rise immediately, indicating that the BOC has
been sampled previously.
RPT[3:0]:
These bits contain the 4 bit repeat count used to determine the number (RPT[3:0] + 1) of
consecutive, identical, 16-bit bit-oriented code patterns to be transmitted before sampling the
XBOC Code Register, and XBOC Control Register again. In the event that the Code Register
values do not change, the same bit oriented code pattern will be repeated continuously. The
RPT[3:0] bits can be changed at any time, and are sampled at the same time as the bit
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
198
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
oriented code patterns. To obtain the maximum BOC modification rate, RPT[3:0] should be
updated and stable within N*16 - 3 bit periods of the INTB interrupt pin going high, where N is
the number of times the BOC code is to be repeated.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
199
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 067H, 167H, 267H, 367H: T1 XBOC Code
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
R/W
BOC[5]
1
Bit 4
R/W
BOC[4]
1
Bit 3
R/W
BOC[3]
1
Bit 2
R/W
BOC[2]
1
Bit 1
R/W
BOC[1]
1
Bit 0
R/W
BOC[0]
1
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset.
BOC[5:0]:
BOC[5:0] enables the XBOC to generate a bit oriented code and selects the 6-bit code to be
transmitted.
When this register is written with any 6-bit code other than 111111, that code will be
transmitted repeatedly in the ESF Facility Data Link with the format
111111110[BOC0][BOC1][BOC2][BOC3][BOC4][BOC5]0, overwriting any HDLC packets
currently being transmitted. When the register is written with 111111, the XBOC is disabled. To
obtain the maximum BOC modification rate, BOC[5:0] should be updated and stable within
N*16 - 3 CLK cycles of the BOCSMPI bit going high, where N is the number of times the BOC
code is to be transmitted.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
200
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 069H, 169H, 269H, 369H: T1 XPDE Interrupt Enable/Status
Bit
Type
Function
Default
Bit 7
R/W
STUFE
0
Bit 6
R/W
STUFF
0
Bit 5
R
STUFI
X
Bit 4
R
PDV
X
Bit 3
R
Z16DI
X
Bit 2
R
PDVI
X
Bit 1
R/W
Z16DE
0
Bit 0
R/W
PDVE
0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset.
STUFE:
The STUFE bit enables the occurrence of pulse stuffing to generate an interrupt on INTB.
When STUFE is set to logic 1, an interrupt is generated on the occurrence of a bit stuff.
When STUFE is a logic 0, bit stuffing occurrences do not generate an interrupt on INTB.
STUFF:
The STUFF bit enables pulse stuffing to occur upon detection of a violation of the pulse
density rule. Bit stuffing is performed in such a way that the resulting data stream no longer
violates the pulse density rule. When STUFF is set to logic 1, bit stuffing is enabled and the
STUFI bit indicates the occurrence of bit stuffs. When STUFF is a logic 0, bit stuffing is
disabled and the PDVI bit indicates occurrences of pulse density violation. Also, when STUFF
is a logic 0, PCM data passes through XPDE unaltered.
STUFI:
The STUFI bit is valid when pulse stuffing is active. This bit indicates when a bit stuff occurred
to eliminate a pulse density violation and that an interrupt was generated due to the bit stuff (if
STUFE is logic 1). When pulse stuffing is active, PDVI remains logic 0, indicating that the
stuffing has removed the density violation. The STUFI bit is reset to logic 0 once this register
is read. If the STUFE bit is also logic 1, the interrupt is also cleared once this register is read.
PDV:
The PDV bit indicates the current state of the pulse density violation indication. When PDV is
a logic 1, a violation of the pulse density rule exists. When PDV is a logic 0, no violation of the
pulse density rule exists. Note: the PDV indication persists for the duration of the pulse density
violation. At its minimum, PDV may be asserted for only 1 bit time, therefore, reading this bit
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
201
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
may not return a logic 1 even though a pulse density violation has occurred. When the XPDE
is enabled for pulse stuffing, PDV remains logic 0.
PDVI, Z16DI:
The PDVI and Z16DI bits identify the source of a generated interrupt. PDVI is a logic 1
whenever a change in the pulse density violation indication generated an interrupt. PDVI is
cleared to 0 when this register is read. Z16DI is a logic 1 whenever 16 consecutive zeros are
detected. Z16DI is cleared to 0 when this register is read. Note that the PDVI and Z16DI
interrupt indications operate regardless of whether the corresponding interrupt enables are
enabled or disabled. When STUFF is set to logic 1, the PDVI and Z16DI bits are forced to
logic 0.
Z16DE:
The Z16DE bit enables an interrupt to be generated on the microprocessor INTB pin when 16
consecutive zeros are detected. When Z16DE is set to logic 1, interrupt is generation is
enabled. When Z16DE is set to logic 0, interrupt generation is disabled.
PDVE:
The PDVE bit enables an interrupt to be generated on the microprocessor INTB pin when a
change in the pulse density is detected. When PDVE is set to logic 1, an interrupt is
generated whenever a pulse density violation occurs or when the pulse density ceases to
exist (if STUFE is logic 0). When PDVE is set to logic 0, interrupt generation by pulse density
violations is disabled.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
202
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 06AH, 16AH, 26AH, 36AH: T1 RBOC Enable
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
R/W
IDLE
0
Bit 1
R/W
AVC
0
Bit 0
R/W
BOCE
0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset.
This register selects the validation criteria to be used in determining a valid bit oriented code
(BOC) and enables generation of an interrupt on a change in code status.
IDLE:
The IDLE bit position enables or disables the generation of an interrupt when there is a
transition from a validated BOC to idle code. A logic 1 in this bit position enables generation
of an interrupt; a logic 0 in this bit position disables interrupt generation.
AVC:
The AVC bit position selects the validation criteria used in determining a valid BOC. A logic 1
in the AVC bit position selects the "alternate" validation criterion of 4 out of 5 matching BOCs;
a logic 0 selects the 8 out of 10 matching BOC criterion.
BOCE:
The BOCE bit position enables or disables the generation of an interrupt on the
microprocessor INTB pin when a valid BOC is detected. A logic 1 in this bit position enables
generation of an interrupt; a logic 0 in this bit position disables interrupt generation.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
203
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 06BH, 16BH, 26BH, 36BH: T1 RBOC Code Status
Bit
Type
Function
Default
Bit 7
R
IDLEI
X
Bit 6
R
BOCI
X
Bit 5
R
BOC[5]
X
Bit 4
R
BOC[4]
X
Bit 3
R
BOC[3]
X
Bit 2
R
BOC[2]
X
Bit 1
R
BOC[1]
X
Bit 0
R
BOC[0]
X
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset.
BOC[5:0]:
The BOC[5:0] bits indicate the current state value of the received bit-oriented code.
IDLEI:
The IDLEI bit position indicates whether an interrupt was generated by the detection of the
transition from a valid BOC to idle code. A logic 1 in the IDLEI bit position indicates that a
transition from a valid BOC to idle code has generated an interrupt; a logic 0 in the IDLEI bit
position indicates that no transition from a valid BOC to idle code has been detected. IDLEI is
cleared to logic 0 when the register is read.
BOCI:
The BOCI bit position indicates whether an interrupt was generated by the detection of a valid
BOC. A logic 1 in the BOCI bit position indicates that a validated BOC code has generated an
interrupt; a logic 0 in the BOCI bit position indicates that no BOC has been detected. BOCI is
cleared to logic 0 when the register is read.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
204
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 06CH, 16CH, 26CH, 36CH: TPSC Configuration
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
R/W
Reserved
0
Bit 1
R/W
IND
0
Bit 0
R/W
PCCE
0
This register allows selection of the microprocessor read access type and output enable control
for the Transmit Per-channel Serial Controller.
Reserved:
The Reserved bit must be logic 0 for normal operation.
IND:
The IND bit controls the microprocessor access type: either indirect or direct. When the
COMET-QUAD is reset, the IND bit is set low, disabling the indirect access mode.
Note: Although the default of IND is logic 0, IND must be logic 1 for proper operation.
PCCE:
The PCCE bit enables the per-channel functions as programmed by the user into the TPSC
indirect register map. When the PCCE bit is set to a logic 1, each channel's PCM Control
byte, IDLE Code byte, and SIGNALING Control byte are passed on to the T1-XBAS as
programmed by the user. When the PCCE bit is set to logic 0, values of all zeros are taken
instead of the user programmed values for each channel's PCM Control byte, IDLE Code
byte, and SIGNALING Control byte. PCCE should not be programmed to logic 1 until after the
user has programmed each channel's PCM Control byte, IDLE Code byte, and SIGNALING
Control byte. Please refer to section 12.10 Using the Per-Channel Serial Controllers and SIGX
for details.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
205
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 06DH, 16DH, 26DH, 36DH: TPSC µP Access Status
Bit
Type
Function
Default
R
BUSY
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
Unused
X
Bit 1
Unused
X
Bit 0
Unused
X
Bit 7
The BUSY bit in the Status register is high while a µP access request is in progress. The BUSY
bit goes low timed to an internal high-speed clock rising edge after the access has been
completed. During normal operation, the Status Register should be polled until the BUSY bit goes
low before another µP access request is initiated. A µP access request is typically completed
within 640 ns.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
206
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 06EH, 16EH, 26EH, 36EH: TPSC Channel Indirect Address/Control
Bit
Type
Function
Default
Bit 7
R/W
R/WB
0
Bit 6
R/W
A6
0
Bit 5
R/W
A5
0
Bit 4
R/W
A4
0
Bit 3
R/W
A3
0
Bit 2
R/W
A2
0
Bit 1
R/W
A1
0
Bit 0
R/W
A0
0
This register allows the µP to access the internal TPSC registers addressed by the A[6:0] bits and
perform the operation specified by the R/WB bit. Writing to this register with a valid address and
R/WB bit initiates an internal µP access request cycle. The R/WB bit selects the operation to be
performed on the addressed register: when R/WB is set to a logic 1, a read from the internal
TPSC register is requested; when R/WB is set to a logic 0, a write to the internal TPSC register is
requested.
This register address is only valid when the IND bit of the TPSC Configuration register is logic 1.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
207
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 06FH, 16FH, 26FH, 36FH: TPSC Channel Indirect Data Buffer
Bit
Type
Function
Default
Bit 7
R/W
D7
0
Bit 6
R/W
D6
0
Bit 5
R/W
D5
0
Bit 4
R/W
D4
0
Bit 3
R/W
D3
0
Bit 2
R/W
D2
0
Bit 1
R/W
D1
0
Bit 0
R/W
D0
0
This register contains either the data to be written into the internal TPSC registers when a write
request is initiated or the data read from the internal TPSC registers when a read request has
completed. During normal operation, if data is to be written to the internal registers, the byte to be
written must be written into this Data register before the target register's address and R/WB=0 is
written into the Address/Control register, initiating the access. If data is to be read from the
internal registers, only the target register's address and R/WB=1 is written into the
Address/Control register, initiating the request. After 640 ns, this register will contain the requested
data byte.
The internal TPSC registers control the per-channel functions on the Transmit PCM data, provide
the per-channel Transmit IDLE Code, and provide the per-channel Transmit signaling control and
the alternate signaling bits. The functions are allocated within the registers as follows:
Table 30
- TPSC Indirect Register Map
Addr
Register
20H
PCM Data Control byte for Timeslot 0
21H
PCM Data Control byte for Channel 1/Timeslot 1
22H
PCM Data Control byte for Channel 2/Timeslot 2
•
•
•
•
37H
PCM Data Control byte for Channel 23/Timeslot 23
38H
PCM Data Control byte for Channel 24/Timeslot 24
39H
PCM Data Control byte for Timeslot 25
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
208
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Addr
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register
•
•
•
•
3EH
PCM Data Control byte for Timeslot 30
3FH
PCM Data Control byte for Timeslot 31
40H
IDLE Code byte for Timeslot 0
41H
IDLE Code byte for Channel 1/Timeslot 1
42H
IDLE Code byte for Channel 2/Timeslot 2
•
•
•
•
57H
IDLE Code byte for Channel 23/Timeslot 23
58H
IDLE Code byte for Channel 24/Timeslot 24
59H
IDLE Code byte for Timeslot 25
•
•
•
•
5EH
IDLE Code byte for Timeslot 30
5FH
IDLE Code byte for Timeslot 31
60H
E1 Control byte for Timeslot 0
61H
Signaling/E1 Control byte for Channel 1/Timeslot 1
62H
Signaling/E1 Control byte for Channel 2/Timeslot 2
•
•
•
•
77H
Signaling/E1 Control byte for Channel 23/Timeslot 23
78H
Signaling/E1 Control byte for Channel 24/Timeslot 24
79H
Signaling/E1 Control byte for Timeslot 25
•
•
•
•
7EH
Signaling/E1 Control byte for Timeslot 30
7FH
Signaling/E1 Control byte for Timeslot 31
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
209
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
The "Timeslot" designation refers to the E1 assignment. The "Channel" designation refers to the
T1 assignment.
The bits within each control byte are allocated as follows:
Table 31
- TPSC Indirect Registers 20H-3FH: PCM Data Control byte
Bit
Type
Function
Default
Bit 7
R/W
INVERT
X
Bit 6
R/W
IDLE_CHAN
X
Bit 5
R/W
DMW
X
Bit 4
R/W
SIGNINV
X
Bit 3
R/W
TEST
X
Bit 2
R/W
LOOP
X
Bit 1
R/W
ZCS0
X
Bit 0
R/W
ZCS1
X
INVERT:
When the INVERT bit is set to a logic 1, the BTPCM[x] or MVBTD data stream of the
quadrant is inverted for the duration of that channel.
The INVERT bit only has effect in T1 mode.
IDLE_CHAN:
When the IDLE_CHAN bit is set to a logic 1, data from the IDLE Code Byte replaces the
BTPCM[x] or MVBTD data stream of the quadrant for the duration of that channel. The
IDLE_CHAN bit controls insertion of the IDLE Code Byte only in T1 mode.
When the Nx64Kbit/s mode is active, IDLE_CHAN also controls the generation of BTCLK[x].
When IDLE_CHAN is a logic 0, data is inserted from the transmit backplane interface during
that channel, and eight clock pulses are generated on BTCLK[x]. When IDLE_CHAN is a
logic 1, an IDLE code byte is inserted, and BTCLK[x] is suppressed for the duration of that
channel.
SIGNINV:
When the SIGNINV bit is set to a logic 1, the most significant bit from BTPCM[x] or MVBTD
data stream of the quadrant is inverted for that channel.
The SIGNINV bit only has effect in T1 mode.
The INVERT and SIGNINV can be used to produce the following types of inversions:
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
210
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Table 32
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- TPSC Transmit Data Conditioning
INVERT
SIGNINV
Effect on PCM Channel Data
0
0
PCM Channel data is unchanged
1
0
All 8 bits of the PCM channel data are inverted
0
1
Only the MSB of the PCM channel data is inverted (SIGN bit
inversion)
1
1
All bits EXCEPT the MSB of the PCM channel data is inverted
(Magnitude inversion)
DMW:
When the DMW bit is set to a logic 1, the digital milliwatt pattern replaces the BTPCM[x] or
MVBTD data stream of the quadrant for the duration of that channel.
The DMW bit only has effect in T1 mode.
TEST:
When the TEST bit is set to a logic 1, channel data from the BTPCM[x] or MVBTD data
stream of the quadrant is either overwritten with a test pattern from the PRBS generator block
or is routed to the PRBS checker block and compared against an expected test pattern. The
RXPATGEN bit in the T1/E1 PRBS Positioning and HDLC Control register determines
whether the transmit data is overwritten or compared as shown in the following table:
Table 33
- Transmit Test Pattern Modes
TEST
RXPATGEN
Description
0
X
Channel data is not included in test pattern
1
1
Channel data is routed to PRBS Checker and compared against
expected test pattern
1
0
Channel data is overwritten with PRBS test pattern
All the channels that are routed to the PRBS generator/checker are concatenated and treated
as a continuous stream in which PRBS patterns are searched for. Similarly, all channels set
to be overwritten with PRBS test pattern data are treated such that if the channels are
subsequently extracted and concatenated, the PRBS appears in the concatenated stream.
PRBS generation/detection can be enabled to work on only the first 7 bits of a channel (for
Nx56Kbit/s fractional T1) using the Nx56K_DET and Nx56K_GEN bits in the T1/E1 PRBS
Positioning and HDLC Control register. The PRBS generator/checker can also be enabled to
work on the entire DS1, including framing bits, using the UNF_GEN and UNF_DET bits in the
PRBS Positioning/Control and HDLC Control register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
211
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
LOOP:
The LOOP bit enables the DS0 loopback. When the LOOP bit is set to a logic 1, transmit
data is overwritten with the corresponding channel data from the receive line. When the
Receive Elastic Store (RX-ELST) is bypassed, it is used to align the receive line data to the
transmit frame. When RX-ELST is enabled, however, it is unavailable to facilitate per-DS0
loopbacks.
Data inversion, idle, loopback and test pattern insertion/checking are performed independent of
the transmit framing format. DS0 loopback takes precedence over digital milliwatt pattern
insertion. Next in priority is test pattern insertion, which, in turn, takes precedence over idle code
insertion. Data inversion has the lowest priority. When test pattern checking is enabled, the
transmit data is compared before DS0 loopback, digital milliwatt pattern insertion, idle code
insertion or data inversion is performed. None of this prioritizing has any effect on the gapping of
BTCLK[x] in Nx64Kbit/s mode. That is, if both DS0 loopback and idle code insertion are enabled
for a given channel while in Nx64Kbit/s mode, the DS0 will be looped-back, will not be overwritten
with idle code, and BTCLK[x] will be gapped out for the duration of the channel. Similarly, none of
the prioritizing has any effect on the generation of test patterns from the PRBS generator, only on
the insertion of that pattern. Thus, if both DMW and TEST are set for a given DS0, and
RXPATGEN = 0, the test pattern from the PRBS generator will be overwritten with the digital
milliwatt code. This same rule also applies to test patterns inserted via the UNF_GEN bit in the
PRBS Positioning/Control register.
ZCS1, ZCS0:
The ZCS[1:0] bits select the zero code suppression used indicated in the below table. In T1
mode, these register bits are logically ORed with the value of the ZCS[1:0] register bits in the
T1-XBAS Configuration register.
Table 34
- Transmit Zero Code Suppression Formats
ZCS1
ZCS0
Description
0
0
No Zero Code Suppression
0
1
T1 mode: GTE Zero Code Suppression (Bit 8 of an all zero
channel byte is replaced by a one, except in signaling frames
where bit 7 is forced to a one.) E1 mode: Reserved.
1
0
T1 mode: DDS Zero Code Suppression (All zero data byte
replaced with "10011000"). E1 mode: “Jammed bit 8" - Every bit 8
is forced to a one. This may be used for 56 kbit/s data service.
1
1
T1 mode: Bell Zero Code Suppression (Bit 7 of an all zero channel
byte is replaced by a one.) E1 mode: Reserved.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
212
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
Table 35
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- TPSC Indirect Registers 40H-5FH: IDLE Code byte
Bit
Type
Function
Default
Bit 7
R/W
IDLE7
X
Bit 6
R/W
IDLE6
X
Bit 5
R/W
IDLE5
X
Bit 4
R/W
IDLE4
X
Bit 3
R/W
IDLE3
X
Bit 2
R/W
IDLE2
X
Bit 1
R/W
IDLE1
X
Bit 0
R/W
IDLE0
X
The contents of the IDLE Code byte register is substituted for the channel data on the BTPCM[x]
or MVBTD data stream of the quadrant when the IDLE_CHAN bit in the PCM Control Byte is set
to a logic 1 in T1 mode or when the SUBS bit of the E1 Control Byte is logic 1 and the DS[0] bit of
the E1 Control Byte is logic 0 in E1 mode. The IDLE Code is transmitted from MSB (IDLE7) to
LSB (IDLE0).
Table 36
- TPSC Indirect Registers 60H-7FH: Signaling/E1 Control byte
Bit
Type
Function
Default
Bit 7
R/W
SIGC[0]/SUBS
X
Bit 6
R/W
SIGC[1]/DS[0]
X
Bit 5
R/W
DS[1]
X
Bit 4
R/W
SIGSRC
X
Bit 3
R/W
A'
X
Bit 2
R/W
B'
X
Bit 1
R/W
C'
X
Bit 0
R/W
D'
X
The significance of the bits in these registers is dependent on whether the operating mode is T1
or E1.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
213
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
E1 Mode
SUBS, DS[1], and DS[0]:
The SUBS, DS[1], and DS[0] bits select one of the following data manipulations to be
performed on the timeslot:
Table 37
- Transmit Per-timeslot Data Manipulation
SUBS
DS[0]
DS[1]
Function on BTPCM[x] or MVBTD of the Quadrant
0
0
0
OFF - no change to PCM timeslot data
0
0
1
ADI - data inversion on timeslot bits 1, 3, 5, 7
0
1
0
ADI - data inversion on timeslot bits 2, 4, 6, 8
0
1
1
INV - data inversion on all timeslot bits
1
0
X
Data substitution on - IDLE code replaces PCM timeslot data
1
1
0
Data substitution on - A-Law digital pattern* replaces PCM
timeslot data.
1
1
1
Data substitution on - µ-Law digital pattern* replaces PCM
timeslot data.
*Note: The A-Law digital milliwatt pattern used is that defined in Recommendation G.711 for A-law:
Table 38
- A-Law Digital Milliwatt Pattern
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
0
0
1
1
0
1
0
0
0
0
1
0
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
0
0
0
0
1
1
0
1
0
0
0
0
1
1
0
1
1
0
1
0
0
*Note: The µ-Law digital milliwatt pattern used is that defined in Recommendation G.711 for µ-law:
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
214
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Table 39
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- µ-Law Digital Milliwatt Pattern
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
0
0
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
0
0
0
1
0
1
1
0
0
0
1
1
1
1
0
1
0
0
1
1
1
1
0
1
0
0
0
1
0
1
1
1
0
0
0
1
0
1
1
1
0
0
1
1
1
1
0
SIGSRC:
The SIGSRC bit is valid only if Channel Associated Signaling (CAS) is selected in the
E1-TRAN Configuration Register; otherwise, it is ignored. When valid, the SIGSRC bit selects
the source of the timeslot signaling bits: if SIGSRC is a logic 0, the signaling bits are taken
from the incoming BTSIG[x] stream in the format specified by the SIGEN and DLEN bits in the
E1-TRAN Configuration Register; if SIGSRC is a logic 1, the signaling bits are taken from the
A',B',C', and D' bit.
T1 Mode
Signaling insertion is controlled by the SIGC[1:0] bits. The source of the signaling bits is
determined by SIGC[0]: when SIGC[0] is set to a logic 1, signaling data is taken from the A', B', C',
and D' bits; when SIGC[0] is set to logic 0, signaling data is taken from the A,B,C, and D bit
locations on BTSIG[x] or CASBTD of the quadrant. Signaling insertion is controlled by SIGC[1]:
when SIGC[1] is set to a logic 1 and ESF or SF transmit format is selected, insertion of signaling
bits is enabled; when SIGC[1] is set to logic 0, the insertion of signaling bits is disabled. For the
SF format, the C' and D' or C and D bits from Signaling Control byte or BTSIG[x] or CASBTD of
the quadrant, respectively, are inserted into the A and B signaling bit positions of every second
superframe that is transmitted. It is assumed that C=A and D=B. The A',B',C', and D' bits do not
pass through the Signaling Aligner block. When signaling insertion via the A’,B’,C’, and D’ bits is
enabled, changing the signaling state by writing to the TPSC can cause the transmit stream to
briefly (for one superframe or extended superframe) carry a signaling state that is neither the new
or the old signaling state (e.g., may have the A bit from the new state but the B bit from the old
state).
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
215
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 070H, 170H, 270H, 370H: RPSC Configuration
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
R/W
Reserved
0
Bit 1
R/W
IND
0
Bit 0
R/W
PCCE
0
This register allows selection of the microprocessor read access type and output enable control
for the Receive Per-channel Serial Controller.
Reserved:
The Reserved bit must be logic 0 for normal operation.
IND:
The IND bit controls the microprocessor access type: either indirect or direct. When the
COMET-QUAD is reset, the IND bit is set low, disabling the indirect access mode.
Note: Although the default of IND is logic 0, IND must be logic 1 for proper operation.
PCCE:
The PCCE bit enables the per-channel functions as programmed by the user into the RPSC
indirect register map. When the PCCE bit is set to a logic 1, the user values programmed into
the Data Trunk Conditioning Code byte and Signaling Trunk Conditioning Code byte are used
to modify the received data and extracted signaling data streams (visible on BRPCM[x] or
MVBRD and BRSIG[x] or CASBRD, if selected) under direction of the value the user has
programmed into each channel's PCM Control byte. When the PCCE bit is set to logic 0,
values of all zeroes are taken instead of the user programmed values for each channel’s Data
Trunk Conditioning Code, Signaling Trunk Conditioning Code, and PCM Control byte to
modify the received data stream and extracted data streams. PCCE should not be
programmed to logic 1 until after the user has programmed each channel's Data Trunk
Conditioning Code byte, Signaling Trunk Conditioning Code byte, and PCM Control byte.
Please refer to section 12.10 Using the Per-Channel Serial Controllers and SIGX for details.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
216
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 071H, 171H, 271H, 371H: RPSC µP Access Status
Bit
Type
Function
Default
R
BUSY
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
Unused
X
Bit 1
Unused
X
Bit 0
Unused
X
Bit 7
The BUSY bit in the Status register is high while a µP access request is in progress. The BUSY
bit goes low timed to an internal high-speed clock rising edge after the access has been
completed. During normal operation, the Status Register should be polled until the BUSY bit goes
low before another µP access request is initiated. A µP access request is typically completed
within 640 ns.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
217
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 072H, 172H, 272H, 372H: RPSC Channel Indirect Address/Control
Bit
Type
Function
Default
Bit 7
R/W
R/WB
0
Bit 6
R/W
A6
0
Bit 5
R/W
A5
0
Bit 4
R/W
A4
0
Bit 3
R/W
A3
0
Bit 2
R/W
A2
0
Bit 1
R/W
A1
0
Bit 0
R/W
A0
0
This register allows the µP to access the internal RPSC registers addressed by the A[6:0] bits and
perform the operation specified by the R/WB bit. Writing to this register with a valid address and
R/WB bit initiates an internal µP access request cycle. The R/WB bit selects the operation to be
performed on the addressed register: when R/WB is set to a logic 1, a read from the internal
RPSC register is requested; when R/WB is set to a logic 0, an write to the internal RPSC register
is requested.
This register address is only valid when the IND bit of the RPSC Configuration register is logic 1.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
218
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 073H, 173H, 273H, 373H: RPSC Channel Indirect Data Buffer
Bit
Type
Function
Default
Bit 7
R/W
D7
0
Bit 6
R/W
D6
0
Bit 5
R/W
D5
0
Bit 4
R/W
D4
0
Bit 3
R/W
D3
0
Bit 2
R/W
D2
0
Bit 1
R/W
D1
0
Bit 0
R/W
D0
0
This register contains either the data to be written into the internal RPSC registers when a write
request is initiated or the data read from the internal RPSC registers when a read request has
completed. During normal operation, if data is to be written to the internal registers, the byte to be
written must be written into this Data register before the target register's address and R/WB=0 is
written into the Address/Control register, initiating the access. If data is to be read from the internal
registers, only the target register's address and R/WB=1 is written into the Address/Control
register, initiating the request. After 640 ns, this register will contain the requested data byte.
The internal RPSC registers control the per-channel functions on the Receive PCM data, provide
the per-channel Data Trunk Conditioning Code and provide the per-channel Signaling Trunk
Conditioning Code. The functions are allocated within the registers shown in Table 40:
Table 40
- RPSC Indirect Register Map
Addr
Register
20H
PCM Data Control byte for Timeslot 0
21H
PCM Data Control byte for Channel 1/Timeslot 1
22H
PCM Data Control byte for Channel 2/Timeslot 2
•
•
•
•
37H
PCM Data Control byte for Channel 23/Timeslot 23
38H
PCM Data Control byte for Channel 24/Timeslot 24
39H
PCM Data Control byte for Timeslot 25
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
219
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Addr
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register
•
•
•
•
3EH
PCM Data Control byte for Timeslot 30
3FH
PCM Data Control byte for Timeslot 31
40H
Data Trunk Conditioning byte for Timeslot 0
41H
Data Trunk Conditioning byte for Channel 1/Timeslot 1
42H
Data Trunk Conditioning byte for Channel 2/Timeslot 2
•
•
•
•
57H
Data Trunk Conditioning byte for Channel 23/Timeslot 23
58H
Data Trunk Conditioning byte for Channel 24/Timeslot 24
59H
Data Trunk Conditioning byte for Timeslot 25
•
•
•
•
5EH
Data Trunk Conditioning byte for Timeslot 30
5FH
Data Trunk Conditioning byte for Timeslot 31
61H
Signaling Trunk Conditioning byte for Channel 1/Timeslot 1
62H
Signaling Trunk Conditioning byte for Channel 2/Timeslot 2
•
•
•
•
77H
Signaling Trunk Conditioning byte for Channel 23/Timeslot 23
78H
Signaling Trunk Conditioning byte for Channel 24/Timeslot 24
79H
Signaling Trunk Conditioning byte for Timeslot 25
•
•
•
•
7EH
Signaling Trunk Conditioning byte for Timeslot 30
7FH
Signaling Trunk Conditioning byte for Timeslot 31
The "Timeslot" designation refers to the E1 assignment. The "Channel" designation refers to the
T1 assignment.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
220
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
The bits within each control byte are allocated as follows:
Table 41
- RPSC Indirect Registers 20H-3FH: PCM Data Control byte
Bit
Type
Function
Default
Bit 7
R/W
TEST
X
Bit 6
R/W
DTRKC
X
Bit 5
R/W
STRKC
X
Bit 4
R/W
DMW
X
Bit 3
R/W
DMWALAW
X
Bit 2
R/W
SIGNINV
X
Bit 1
Unused
X
Bit 0
Unused
X
TEST:
When the TEST bit is set to a logic 1, receive channel data is either overwritten with a test
pattern from the PRBS generator block or is routed to the PRBS checker block and compared
against an expected test pattern. The RXPATGEN bit in the Pattern Generator/Detector
Positioning/Control register determines whether the transmit data is overwritten or compared
as shown in the following table:
Table 42
TEST
- Receive Test Pattern Modes
RXPATGEN
Description
0
X
Channel data is not included in test pattern
1
0
Channel data is routed to the PRBS Checker and compared against
expected test pattern
1
1
Channel data is overwritten with the PRBS test pattern
All the channels that are routed to the PRBS Checker are concatenated and treated as a
continuous stream in which pseudorandom patterns are searched for. Similarly, all channels set
to be overwritten with the PRBS test pattern data are treated such that if the channels are
subsequently extracted and concatenated, the PRBS appears in the concatenated stream. PRBS
generation/detection can be enabled to work on only the first 7 bits of a channel (for Nx56Kbit/s
fractional T1) using the Nx56K_DET and Nx56K_GEN bits in the T1/E1 PRBS Positioning and
HDLC Control register. The PRBS generator/checker can also be enabled to work on the entire
DS1, including framing bits, using the UNF_GEN and UNF_DET bits in the Pattern
Generator/Detector Positioning/Control register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
221
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
DTRKC:
When the DTRKC bit is set to a logic 1, data from the Data Trunk Conditioning Code Byte
contained within the RPSC indirect registers replaces the BRPCM[x] or MVBRD output data
for the duration of that channel.
When the Receive Backplane Configuration register selects a Nx64Kbit/s mode, the DTRKC
bit also controls BRCLK[x] generation. If DTRKC is a logic 1, BRCLK[x] is held low for the
duration of the channel.
STRKC:
When the STRKC bit is set to a logic 1, data from the Signaling Trunk Conditioning Code Byte
contained within the RPSC indirect registers replaces the BRSIG[x] or CASBRD output data
for the duration of that channel.
DMW:
When the DMW bit is set to a logic 1, a digital milliwatt pattern replaces the BRPCM[x] or
MVBRD output data for the duration of that channel. The particular digital milliwatt pattern
used, A-law or u-law, is selected by the DMWALAW bit of this register.
DMWALAW:
When the DMWALAW bit is set to a logic 1, the digital milliwatt pattern replacing the
BRPCM[x] or MVBRD output data for the duration of that channel is the A-law pattern (see
Table 38). When the DMWALAW bit is set to a logic 0, the digital milliwatt pattern replacing
the BRPCM[x] or MVBRD output data for the duration of that channel is the µ-law pattern (see
Table 39).
SIGNINV:
When the SIGNINV bit is set to a logic 1, the most significant bit of the data output on the
BRPCM[x] or MVBRD pin is the inverse of the received data most significant bit for that
channel.
In T1 mode, the RINV[1] of the and SIGNINV bits can be used to invert data as shown in
Table 24:
Table 43
- RPSC Indirect Registers 40H-5FH: Data Trunk Conditioning Code byte
Bit
Type
Function
Default
Bit 7
R/W
DTRK7
X
Bit 6
R/W
DTRK6
X
Bit 5
R/W
DTRK5
X
Bit 4
R/W
DTRK4
X
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
222
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Bit
Type
Function
Default
Bit 3
R/W
DTRK3
X
Bit 2
R/W
DTRK2
X
Bit 1
R/W
DTRK1
X
Bit 0
R/W
DTRK0
X
The contents of the Data Trunk Conditioning Code byte register is substituted for the channel data
on BRPCM[x] or MVBRD when the DTRKC bit in the PCM Control Byte is set to a logic 1. The
Data Trunk Conditioning Code is transmitted from MSB (DTRK7) to LSB (DTRK0).
Table 44
Bit
- RPSC Indirect Registers 61H-7FH: Signaling Trunk Conditioning byte
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
R/W
A'
X
Bit 2
R/W
B'
X
Bit 1
R/W
C'
X
Bit 0
R/W
D'
X
The contents of the Signaling Trunk Conditioning Code byte register is substituted for the channel
signaling data on BRSIG[x] or CASBRD when the STRKC bit is set to a logic 1. The Signaling
Trunk Conditioning Code is placed in least significant nibble of the channel byte.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
223
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 078H, 178H, 278H, 378H: T1 APRM Configuration/Control
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
R/W
Reserved
0
Bit 4
R/W
Reserved
0
Bit 3
R/W
Reserved
0
Bit 2
R/W
CONT_CRC
0
Bit 1
R/W
INTE
0
Bit 0
R/W
AUTOUPDATE
0
Reserved:
These bits must be a logic 0 for normal operation.
AUTOUPDATE:
The AUTOUPDATE bit controls the automatic updating of the performance report on a per
second basis. If this bit is set to a logic 1, the Performance Report Messages are generated,
updated, and sent once a second. When AUTOUPDATE is set to a logic 0, the performance
report is not updated or sent.
INTE:
The INTE bit enables the interrupt output pin. When INTE is set to a logic 1, a logic 1 in the
INTR bit in the T1 APRM Interrupt Status register asserts the INTB output low. INTR is
disabled from generating interrupts when INTE is set to a logic 0.
CONT_CRC:
The CONT_CRC is the Continuous CRC bit. When set to logic 1, the SE and G6 bits in the
Performance Report are set to1 and G1, G2, G3, G4, G5 and FE are set to 0. When reset to
logic 0, the Gn (n = [1..5]), FE and SE bits are set according to the received CRC errors.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
224
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 07AH, 17AH, 27AH, 37AH: T1 APRM Interrupt Status
Bit
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
Unused
X
Bit 1
Unused
X
INTR
X
Bit 0
Type
R
INTR:
The interrupt (INTR) bit is set to logic 1 on one second boundaries, to signal that the one
second data is ready. If the INTE bit is a logic 1, the INTB output is asserted low when INTR
is logic 1. INTR is cleared when this register is read.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
225
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 07BH, 17BH, 27BH, 37BH: T1 APRM One Second Content Octet 2
Bit
Type
Function
Default
Bit 7
R/W
SAPI[5]
0
Bit 6
R/W
SAPI[4]
0
Bit 5
R/W
SAPI[3]
1
Bit 4
R/W
SAPI[2]
1
Bit 3
R/W
SAPI[1]
1
Bit 2
R/W
SAPI[0]
0
Bit 1
R/W
C/R
0
Bit 0
R/W
EA
0
SAPI[5:0]:
The SAPI[5:0] represent the service access point identifier bits. The value of SAPI[5:0] in the
performance report is constant i.e., SAPI = 14.
C/R:
The C/R bit is the Command/Response bit. The value of C/R from the CI is set to a logic 0
and the value of the C/R bit from the carrier is set to a logic 1.
EA:
The EA bit is the Extended Address bit in the second octet. The EA bit defaults to logic 0.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
226
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 07CH, 17CH, 27CH, 37CH: T1 APRM One Second Content Octet 3
Bit
Type
Function
Default
Bit 7
R/W
TEI[6]
0
Bit 6
R/W
TEI[5]
0
Bit 5
R/W
TEI[4]
0
Bit 4
R/W
TEI[3]
0
Bit 3
R/W
TEI[2]
0
Bit 2
R/W
TEI[1]
0
Bit 1
R/W
TEI[0]
0
Bit 0
R/W
EA
1
TEI[6:0]:
The TEI[6:0] bits represent the terminal endpoint identifier. The TEI[6:0] default to logic 0.
EA:
The EA bit is the Extended Address bit in the third octet. The EA bit defaults to logic 1.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
227
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 07DH, 17DH, 27DH, 37DH: T1 APRM One Second Content Octet 4
Bit
Type
Function
Default
Bit 7
R/W
CONTROL[7]
0
Bit 6
R/W
CONTROL[6]
0
Bit 5
R/W
CONTROL[5]
0
Bit 4
R/W
CONTROL[4]
0
Bit 3
R/W
CONTROL[3]
0
Bit 2
R/W
CONTROL[2]
0
Bit 1
R/W
CONTROL[1]
1
Bit 0
R/W
CONTROL[0]
1
CONTROL[7:0]:
This register set the value of the CONTROL field in the performance report and defaults to
"00000011". It is inserted into the fourth octet of the performance report.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
228
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 07EH, 17EH, 27EH, 37EH: T1 APRM One Second Content MSB (Octet 5)
Bit
Type
Function
Default
Bit 7
R
G3
X
Bit 6
R
LV
X
Bit 5
R
G4
X
Bit 4
R
U1
X
Bit 3
R
U2
X
Bit 2
R
G5
X
Bit 1
R
SL
X
Bit 0
R
G6
X
The contents of this register represent the values encoded in the latest performance report
transmitted. This register is updated coincident with the assertion of the INTR bit of the T1 APRM
Interrupt Status register.
G3:
This bit is set to a logic-1, if the number of CRC error events in a one second interval is
greater than 5 and less than or equal to 10 (i.e., 5 < CRC error events ≤ 10).
LV:
This bit is set to a logic 1, if the number of Line code violation events in a one second interval
is greater than or equal to 1 (i.e., LCV ≥ 1).
G4:
This bit is set to a logic 1, if the number of CRC error events in a one second interval is
greater than 10 and less than or equal to 100 (i.e., 10 <CRC error events ≤ 100).
U1,U2:
Under Study For Synchronization. The default value is set by the U1 and U2 bits in the T1
APRM configuration register (register 078H).
G5:
This bit is set to a logic 1 if, the number of CRC error events is greater than 100 and less than
or equal to 319 (i.e., 100 < CRC error events ≤ 319).
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
229
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
SL:
This bit is set to a logic 1 if, one or more controlled slip events occur in a one second interval
i.e. (SL ≥ 1).
G6:
This bit is set to a logic 1 if the number of CRC error events in a one second interval is greater
than or equal to 320 (i.e., CRC error events ≥ 320).
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
230
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 07FH, 17FH, 27FH, 37FH: T1 APRM One Second Content LSB (Octet 6)
Bit
Type
Function
Default
Bit 7
R
FE
X
Bit 6
R
SE
X
Bit 5
R
LB
X
Bit 4
R
G1
X
Bit 3
R
R
X
Bit 2
R
G2
X
Bit 1
R
Nm
X
Bit 0
R
NI
X
The contents of this register represent the values encoded in the latest performance report
transmitted. This register is updated coincident with the assertion of the INTR bit of the T1 APRM
Interrupt Status register.
FE:
This bit is set to a logic 1 if one or more Frame Synchronization Bit Error Event occurs in a 1
second window (SE =0). If more than one FE occurs in a 3 ms window, a SE is declared and
the FE bit is set to 0.
SE:
This bit is set to a logic 1 if, Severely Errored Framing Event ≥ 1 (FE =0). If more than one FE
occurs in a 3 ms window, a SE is declared and the FE bit is set to 0.
LB:
This bit is set to a logic 1 if the Payload Loopback is activated.
G1:
This bit is set to a logic 1 if the number of CRC error events in a one second interval is equal
to 1 (i.e., CRC error events =1).
R:
Reserved. The default value is set by the R bit in the T1 APRM configuration register (register
078H).
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
231
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
G2:
This bit is set to a logic 1 if the number of CRC error events in a one second interval is greater
than 1 and less than or equal to 5 (i.e., 1 <CRC error events ≤ 5).
NmNi:
One second Report Modulo 4 Counter. Every second, the value of NmNi is incremented by
one. Since it is a module 4 counter, it can assume any binary represented value between 0
and 3. The table below illustrates the relationship between the current value K of NmNi and
the time of the most recent report.
Table 45
- NmNi Settings
NmNi
K
Time
t (time of most recent report)
K-1
t-1
K-2
t-2
K-3
t-3
K
t-4
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
232
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 080H, 180H, 280H, 380H: E1-TRAN Configuration
Bit
Type
Function
Default
Bit 7
R/W
AMI
0
Bit 6
R/W
SIGEN
1
Bit 5
R/W
DLEN
1
Bit 4
R/W
GENCRC
0
Bit 3
R/W
FDIS
0
Bit 2
R/W
FEBEDIS
0
Bit 1
R/W
INDIS
0
Bit 0
R/W
XDIS
0
When the E1/T1B bit of the Global Configuration register is a logic 0, this register is held reset.
AMI:
The AMI bit enables AMI line coding when set to logic 1; when it is set to logic 0, the HDB3
line coding is enabled.
SIGEN, DLEN:
The SIGEN and DLEN bits select the signaling data source for Timeslot 16 (TS16) as follows:
Table 46
- E1 Signaling Insertion Mode
SIGEN
DLEN
MODE
0
0
Signaling insertion disabled. TS16 data is taken directly from the
CCSBTD input when the TCCSEN bit of the Transmit H-MVIP/CCS
Enable and Configuration register is logic 1. When TCCSEN is logic 0,
TS16 is taken directly from BTPCM[x] or MVBTD TS16.
0
1
Reserved.
1
0
Reserved.
1
1
CAS enabled. TS16 data is taken from either the BTSIG[x] or CASBTD
stream or from the TPSC SIGNALING/E1 Control byte as selected on a
per-timeslot basis via the SIGSRC bit. The format of the BTSIG[x] input
data stream is shown in the "Functional Timing" section.
When channel associated signaling (CAS) is enabled, the format of the input BTSIG[x] or
CASBTD stream is selected by the DLEN bit. A logic 1 in the DLEN bit position selects the
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
233
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
PMC compatible format in which the BTSIG[x] or CASBTD stream contains the signaling data
nibble in the lower four bits of the timeslot byte. A logic 0 in the DLEN bit position is reserved
and should not be used.
GENCRC:
The GENCRC bit enables generation of the CRC multiframe when set to logic 1. When
enabled, the E1-TRAN generates the CRC multiframe alignment signal, calculates and inserts
the CRC bits, and if enabled by FEBEDIS, inserts the FEBE indication in the spare bit
positions. The CRC bits transmitted during the first submultiframe (SMF) are indeterminate
th
and should be ignored. The CRC bits calculated during the transmission of the n SMF (SMF
n) are transmitted in the following SMF (SMF n+1). When GENCRC is set to logic 0, the CRC
generation is disabled. The CRC bits are then set to the logic value contained in the Si[1] bit
position in the International/National Bit Control Register and bit 1 of the NFAS frames are set
to the value of Si[0] bit if enabled by INDIS, or, if not enabled by INDIS, are taken directly from
BTPCM[x] or MVBTD. When BTPCM[x] or MVBTD or Si[1] are transmitted in lieu of the
calculated CRC bits, there is no delay of one SMF (i.e., the BTPCM[x] or MVBTD bits
received in SMF n are transmitted in the same SMF). The same applies when substituting
Si[1] in place of the calculated CRC bits.
FDIS:
The FDIS bit value controls the generation of the framing alignment signal. A logic 1 in the
FDIS bit position disables the generation of the framing pattern in TS0 and allows the
incoming data on BTPCM[x] or MVBTD to pass through the E1-TRAN transparently. A logic 0
in FDIS enables the generation of the framing pattern, replacing TS0 of frames 0, 2, 4, 6, 8,
10, 12 and 14 with the frame alignment signal, and if enabled by INDIS, replacing TS0 of
frames 1, 3, 5, 7, 9, 11, 13 and 15 with the contents of the International Bits Control Register.
When FDIS is a logic 1, framing is globally disabled and the values in control bits GENCRC,
FEBEDIS, INDIS, and XDIS are ignored.
Note that the above is true only if the AIS bit in the E1-TRAN Transmit Alarm/Diagnostic
Control register is a logic 0. If AIS is logic 1, the output bit stream becomes all-ones
unconditionally.
INDIS, GENCRC and FEBEDIS:
The INDIS bit controls the insertion of the International and National bits into TS0. When
INDIS is set to logic 0, the contents of the E1-TRAN International Bits Control register and the
National bits are inserted into TS0 (note that only the national bits that are enabled in the
E1-TRAN National Bits Codeword registers are inserted into TS0); when INDIS is a logic 1,
the contents of the E1-TRAN International Bits Control register and the E1-TRAN National bits
are ignored and the values for those bit positions in the output stream are taken directly from
the BTPCM[x] or MVBTD stream. When INDIS and FDIS are logic 0, the bit values used for
the International and National bits are dependent upon the values of the GENCRC and
FEBEDIS configuration bits, as shown in the following table:
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
234
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Table 47
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- E1 Timeslot 0 Bit 1 Insertion Control Summary
GENCRC
FEBEDIS
Source of International Bits
0
X
Bit position Si[1] in the International Bits Control register is used for
the International bit in the frame alignment signal (FAS) frames and
the Si[0] bit in the non-frame alignment signal (NFAS) frames if
INDIS is logic 0. BTPCM[x] or MVBTD replaces Si[1:0] if INDIS is
logic 1.
1
0
The calculated CRC bits are used for the International bit in the
FAS frames and the generated CRC multiframe alignment signal
and the FEBE bits are used for the International bit in the NFAS
frames.
1
1
The calculated CRC bits are used for the International bit in the
FAS frames and the generated CRC multiframe alignment signal is
used for the International bit in the NFAS frames, with the Si[1:0]
bits in the International Bits Control register used for the spare bits.
XDIS:
If FDIS is logic 0 and SIGEN is logic 1, the XDIS bit controls the insertion of the Extra bits in
TS16 of frame 0 of the signaling multiframe as follows. When XDIS is set to a logic 0, the
contents of the E1-TRAN Extra Bits Control Register are inserted into TS16, frame 0; when
XDIS is a logic 1, the contents of the register are ignored and the values for those bits
positions in the output stream are taken directly from the BTPCM[x] or MVBTD stream. That
is, when XDIS and FDIS are logic 0 and SIGEN is logic 1, the X1, X3 and X4 bit values from
the E1-TRAN Extra Bits Control Register are used for the Extra bits in TS16 of frame 0 of the
signaling multiframe.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
235
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 081H, 181H, 281H, 381H: E1-TRAN Transmit Alarm/Diagnostic Control
Bit
Type
Function
Default
Bit 7
R/W
MTRK
0
Bit 6
R/W
FPATINV
0
Bit 5
R/W
SPLRINV
0
Bit 4
R/W
SPATINV
0
Bit 3
R/W
RAI
0
Bit 2
R/W
YBIT
0
Bit 1
R/W
Reserved
0
Bit 0
R/W
AIS
0
When the E1/T1B bit of the Global Configuration register is a logic 0, this register is held reset.
MTRK:
The MTRK bit forces trunk conditioning (i.e., idle code substitution and signaling substitution)
when MTRK is a logic 1. This has the same effect as setting data substitution to IDLE code
on timeslots 1-15 and 17-31 (setting bits SUBS and DS[0] to binary 10 in timeslots 1-15 and
17-31) and sourcing the signaling data from the TPCS stream, if SIGEN is logic 1. When
SIGEN is logic 0, TS16 will be treated the same as timeslots 1-15 and 17-31 and will contain
data sourced from TIDL. TS0 data is determined by the control bits associated with it and is
independent of the value of MTRK.
FPATINV:
The FPATINV bit is a diagnostic control bit. When set to logic 1, FPATINV forces the frame
alignment signal (FAS) written into TS0 to be inverted (i.e., the correct FAS, 0011011, is
substituted with 1100100); when set to logic 0, the FAS is unchanged.
SPLRINV:
The SPLRINV bit is a diagnostic control bit. When set to logic 1, SPLRINV forces the "spoiler
bit" written into bit 2 of TS0 of NFAS frames to be inverted (i.e., the spoiler bit is forced to 0);
when set to logic 0, the spoiler bit is unchanged.
SPATINV:
The SPATINV bit is a diagnostic control bit. When set to logic 1, SPATINV forces the
signaling multiframe alignment signal written into bits 1-4 of TS16 of frame 0 of the signaling
multiframe to be inverted (i.e., the correct signaling multiframe alignment signal, 0000, is
substituted with 1111); when set to logic 0, the signaling multiframe alignment signal is
unchanged.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
236
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
RAI:
The RAI bit controls the transmission of the Remote Alarm Indication signal. A logic 1 in the
RAI bit position causes bit 3 of NFAS frames to be forced to logic 1; otherwise, bit 3 of NFAS
frames is a logic 0 unless the AUTOYELLOW register bit is set and a receive defect is
present.
YBIT:
The YBIT bit controls the transmission of the signaling multiframe Alarm Indication Signal. A
logic 1 in the YBIT bit position causes the Y-bit (bit 6) of TS16 of frame 0 of the signaling
multiframe to be forced to logic 1; otherwise, the Y-bit is a logic 0.
Reserved:
This bit must be set to a logic 0 for normal operation.
AIS:
The AIS bit controls the transmission of the Alarm Indication Signal (unframed all-ones). A
logic 1 in the AIS bit position forces the output streams to logic 1.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
237
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 082H, 182H, 282H, 382H: E1-TRAN International/National Control
Bit
Type
Function
Default
Bit 7
R/W
Si[1]
1
Bit 6
R/W
Si[0]
1
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
Unused
X
Bit 1
Unused
X
Bit 0
Unused
X
When the E1/T1B bit of the Global Configuration register is a logic 0, this register is held reset.
Si[1:0]:
The bits Si[1] and Si[0] correspond to the International bits. The Si[1] and Si[0] bits can be
programmed to any value and will be inserted into bit 1 of each FAS frame and NFAS frame,
respectively, when the block is configured for frame generation, INDIS is set to logic 0, and
CRC multiframe generation is disabled. When CRC multiframe generation is enabled, both
Si[1] and Si[0] are ignored if FEBE indication is enabled; if FEBEDIS is a logic 1 and INDIS =
0, the values programmed in the Si[1] and Si[0] bit positions are inserted into the spare bit
locations of frame 13 and frame 15, respectively, of the CRC multiframe. If both FEBEDIS
and INDIS are logic 1, data from BTPCM replaces the Si[0] and Si[1] bits in the CRC
multiframe.
The Si[1] and Si[0] bits should be programmed to a logic 1 when not being used to carry
information.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
238
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 083H, 183H, 283H, 383H: E1-TRAN Extra Bits Control
Bit
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
X[1]
1
Unused
X
Bit 3
Type
R/W
Bit 2
Bit 1
R/W
X[3]
1
Bit 0
R/W
X[4]
1
When the E1/T1B bit of the Global Configuration register is a logic 0, this register is held reset.
X[4:3,1]:
The X[1], X[3], and X[4] bits control the value programmed in the X[1], X[3], and X[4] bit
locations (bits 5,7, and 8) in TS16 of frame 0 of the signaling multiframe, when enabled by
XDIS. The X[1], X[3], and X[4] bits should be programmed to a logic 1 when not being used
to carry information.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
239
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 084H, 184H, 284H, 384H: E1-TRAN Interrupt Enable
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
R/W
SIGMFE
0
Bit 3
R/W
NFASE
0
Bit 2
R/W
MFE
0
Bit 1
R/W
SMFE
0
Bit 0
R/W
FRME
0
When the E1/T1B bit of the Global Configuration register is a logic 0, this register is held reset.
FRME:
When FRME is set to logic 1, the interrupt generated by the FRMI interrupt register is
propagated to the INTB output pin. When FRME is set to logic 0, the FRMI interrupt bit is
masked.
SMFE:
When SMFE is set to logic 1, the interrupt generated by the SMFI interrupt register is
propagated to the INTB output pin. When SMFE is set to logic 0, the SMFI interrupt bit is
masked.
MFE:
When MFE is set to logic 1, the interrupt generated by the MFI interrupt register is propagated
to the INTB output pin. When MFE is set to logic 0, the MFI interrupt bit is masked.
NFASE:
When NFASE is set to logic 1, the interrupt generated by the NFASI interrupt register is
propagated to the INTB output pin. When NFASE is set to logic 0, the NFASI interrupt bit is
masked.
SIGMFE:
When SIGMFE is set to logic 1, the interrupt generated by the SIGMFI interrupt register is
propagated to the INTB output pin. When SIGMFE is set to logic 0, the SIGMFI interrupt bit is
masked.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
240
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 085H, 185H, 285H, 385H: E1-TRAN Interrupt Status
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
R
SIGMFI
X
Bit 3
R
NFASI
X
Bit 2
R
MFI
X
Bit 1
R
SMFI
X
Bit 0
R
FRMI
X
When the E1/T1B bit of the Global Configuration register is a logic 0, this register is held reset.
FRMI:
The FRMI interrupt bit is set to logic 1 approximately on frame boundaries. The contents of
this register are cleared to logic 0 after the register is read.
SMFI:
The SMFI interrupt bit is set to logic 1 approximately on CRC-4 sub multiframe boundaries in
the transmit data stream. The contents of this register are cleared to logic 0 after the register
is read.
MFI:
The MFI interrupt bit is set to logic 1 approximately on CRC-4 multiframe boundaries in the
transmit data stream. The contents of this register are cleared to logic 0 after the register is
read.
NFASI:
The NFASI interrupt bit is set to logic 1 approximately on NFAS frame boundaries in the
transmit data stream. The contents of this register are cleared to logic 0 after the register is
read.
SIGMFI:
The SIGMFI interrupt bit is set to logic 1 approximately on signaling multiframe boundaries in
the transmit data stream. The contents of this register are cleared to logic 0 after the register
is read.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
241
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 086H, 186H, 286H, 386H: E1-TRAN National Bits Codeword Select
Bit
Type
Function
Default
Bit 7
R/W
SaSEL[2]
X
Bit 6
R/W
SaSEL[1]
X
Bit 5
R/W
SaSEL[0]
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
Unused
X
Bit 1
Unused
X
Bit 0
Unused
X
When the E1/T1B bit of the Global Configuration register is a logic 0, this register is held reset.
SaSEL[2:0]:
The SaSEL[2:0] bits select which National Bit codeword appears in the SaX[1:4] bits of the
E1-TRAN National Bits Codeword register. These bits map to the codeword selection as
follows:
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
242
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
Table 48
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- National Bits Codeword Select
SaSEL[2:0]
National Bit Codeword
000
Undefined
001
Undefined
010
Undefined
011
Sa4
100
Sa5
101
Sa6
110
Sa7
111
Sa8
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
243
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 087H, 187H, 287H, 387H: E1-TRAN National Bits Codeword
Bit
Type
Function
Default
Bit 7
R/W
SaX_EN[1]
0
Bit 6
R/W
SaX_EN[2]
0
Bit 5
R/W
SaX_EN[3]
0
Bit 4
R/W
SaX_EN[4]
0
Bit 3
R/W
SaX[1]
1
Bit 2
R/W
SaX[2]
1
Bit 1
R/W
SaX[3]
1
Bit 0
R/W
SaX[4]
1
When the E1/T1B bit of the Global Configuration register is a logic 0, this register is held reset.
Since this is an indirect register, the register values are not accessible until the SaSEL[2:0] bits of
the E1-TRAN National Bits Codeword Select register are set appropriately.
SaX[1:4]:
To aid in describing the SaX[1:4] bits, the format of the first timeslot of the frame within the
G.704 CRC-4 multiframe is shown below.
Table 49
- G.704 CRC-4 Multiframe
Sub-multiframe
Frame
(SMF)
number
0
2
3
0
0
C
2
1
A
0
0
0
C
3
1
A
0
0
1
C
4
1
A
0
0
0
C
1
1
A
0
0
1
C
2
1
A
0
0
1
C
3
1
A
0
0
1
A
14
E
C
4
0
0
15
E
1
A
2
3
4
5
6
7
8
9
10
II
1
C
1
0
1
I
Bits 1 to 8 of the first timeslot of the frame
11
12
13
4
1
S
1
S
1
S
1
S
1
S
1
S
1
S
1
S
a4
a4
a4
a4
a4
a4
a4
a4
5
1
S
1
S
1
S
1
S
1
S
1
S
1
S
1
S
a5
a5
a5
a5
a5
a5
a5
a5
6
0
S
0
S
0
S
0
S
0
S
0
S
0
S
0
S
a6
a6
a6
a6
a6
a6
a6
a6
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
7
1
S
1
S
1
S
1
S
1
S
1
S
1
S
1
S
a7
a7
a7
a7
a7
a7
a7
a7
8
1
S
1
S
1
S
1
S
1
S
1
S
1
S
1
S
a8
a8
a8
a8
a8
a8
a8
a8
244
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
The SaX[1:4] bits are used to program the values transmitted in the Sa4, Sa5, Sa6, Sa7, and
Sa8 bits for a given Sub-multiframe.
When SaSEL[2:0] = 011, Sa4 is selected for programming.
When SaSEL[2:0] = 100, Sa5 is selected for programming.
When SaSEL[2:0] = 101, Sa6 is selected for programming.
When SaSEL[2:0] = 110, Sa7 is selected for programming.
When SaSEL[2:0] = 111, Sa8 is selected for programming.
(The SaSEL[2:0] bits are located in the E1-TRAN National Codeword Select register.)
SaX[1:4] is latched internally and can be updated by the user every Sub-multiframe. For
example, if SaX[1:4] is written to during SMF I, the values written will appear in SMF II of the
same multiframe. If SaX[1:4] is written during SMF II of a multiframe, the values will appear in
SMF I of the next multiframe. Since the values written are latched internally, whatever is
written will not affect what appears in the current Sub-multiframe.
Note: when Sa8[1:4] has been selected by setting the SaSEL[2:0] = 111, the SaX[1:4] bits are
mapped in this register in the reverse order as the SaX[1:4] bits, where X = 4, 5, 6 or 7. That
is, Sa8[1] is mapped to bit 0 of this register, Sa8[2] is mapped to bit 1, Sa8[3] is mapped to
bit 2, and Sa8[4] is mapped to bit 3.
Example: Say that for Quadrant 1, the user wishes to program the Sa bits of Submultiframe I
as shown in Table 50 below.
Table 50
- Example Sa Bit Programming
Sub-multiframe
Frame
(SMF)
number
0
C
1
2
3
0
0
0
C
2
1
A
0
0
0
C
3
1
A
0
0
1
A
6
1
C
4
0
0
7
0
1
A
1
2
I
Bits 1 to 8 of the first timeslot of the frame
1
3
4
5
4
5
6
7
8
1
S =0
a4
1
S =1
a5
0
S =1
a6
1
S =1
a7
1
S =0
a8
1
S =1
a4
1
S =1
a5
0
S =1
a6
1
S =0
a7
1
S =1
a8
1
S =0
a4
1
S =1
a5
0
S =0
a6
1
S =1
a7
1
S =1
a8
1
S =1
a4
1
S =1
a5
0
S =1
a6
1
S =1
a7
1
S =1
a8
The desired values for SMF I are written during the SMF II prior to when the values are to be
transmitted. The writes are performed in advance so the values can be latched and available
for SMF I.
1. Write address 086H (i.e., SaSEL[2:0] bits) with a value of 60H to select Sa4.
2. Write address 087H (i.e., SaX_EN[1:4] and SaX[1:4] bits) with a value of F5H.
3. Write address 086H (i.e., SaSEL[2:0] bits) with a value of 80H to select Sa5.
4. Write address 087H (i.e., SaX_EN[1:4] and SaX[1:4] bits) with a value of FFH.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
245
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
5.
6.
7.
8.
9.
10.
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Write address 086H (i.e., SaSEL[2:0] bits) with a value of A0H to select Sa6.
Write address 087H (i.e., SaX_EN[1:4] and SaX[1:4] bits) with a value of FDH.
Write address 086H (i.e., SaSEL[2:0] bits) with a value of C0H to select Sa7.
Write address 087H (i.e., SaX_EN[1:4] and SaX[1:4] bits) with a value of FBH.
Write address 086H (i.e., SaSEL[2:0] bits) with a value of E0H to select Sa8.
Write address 087H (i.e., SaX_EN[1:4] and SaX[1:4] bits) with a value of FEH. (Note
that as per above, Sa8 is mapped in the reverse order.)
It is noted that all SaX_EN[1:4] bits in the above example are set to all ones to permit the
programmed Sa bits to appear in the transmitted stream.
SaX_EN[1:4]
Bits SaX_EN[1:4] enable the insertion of bits SaX[1:4] (where X = 4, 5, 6, 7, or 8) respectively.
If bits SaX_EN[1: 4] are set to logic 1, then the contents of bits SaX[1:4] are substituted into
the Sa bit locations of the Sub-multiframe. If any one or more of the SaX_EN[1:4] bits are set
to logic 0, the respective SaX[1:4] register bit is disabled and will not be written into the Submultiframe (i.e., the SaX bit that has been disabled will pass through transparently). The
SaX_EN bits are valid only when the INDIS bit in the E1-TRAN Configuration register is set to
logic 0.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
246
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 090H, 190H, 290H, 390H: E1-FRMR Frame Alignment Options
Bit
Type
Function
Default
Bit 7
R/W
CRCEN
1
Bit 6
R/W
CASDIS
0
Bit 5
R/W
C2NCIWCK
0
Unused
X
Bit 4
Bit 3
R/W
Reserved
0
Bit 2
R/W
REFR
0
Bit 1
R/W
REFCRCEN
1
Bit 0
R/W
REFRDIS
0
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive
Options register is a logic 1, this register is held reset.
This register selects the various framing formats and framing algorithms supported by the FRMR
block.
CRCEN:
The CRCEN bit enables the FRMR to frame to the CRC multiframe. When the CRCEN bit is
logic 1, the FRMR searches for CRC multiframe alignment and monitors for errors in the
alignment. A logic 0 in the CRCEN bit position disables searching for multiframe and
suppresses the OOCMF, CRCE, CMFER, FEBE, CFEBE, RAICCRC, C2NCIW and ICMFPI
FRMR status/interrupt bits, forcing them to logic 0.
CASDIS:
The CASDIS bit enables the FRMR to frame to the Channel Associated Signaling multiframe
when set to a logic 0. When CAS is enabled, the FRMR searches for signaling multiframe
alignment and monitors for errors in the alignment. A logic 1 in the CASDIS bit position
disables searching for multiframe and suppresses the OOSMF and the SMFER FRMR
outputs, forcing them to logic 0.
C2NCIWCK:
The C2NCIWCK bit enables the continuous checking for CRC multiframe in the CRC to nonCRC interworking mode of the E1-FRMR. If this bit is a logic 0, the E1-FRMR will cease
searching for CRC multiframe alignment in CRC to non-CRC interworking mode. If this bit is
a logic 1, the E1-FRMR will continue searching for CRC multiframe alignment, even if CRC to
non-CRC interworking has been declared.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
247
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Reserved:
The Reserved bit must be logic 0 for normal operation.
REFR:
A transition from logic 0 to logic 1 in the REFR bit position forces the re-synchronization to a
new frame alignment. The bit must be cleared to logic 0, then set to logic 1 again to generate
subsequent re-synchronizations.
REFCRCEN:
The REFCRCEN bit enables excessive CRC errors (≥ 915 errors in one second) to force a resynchronization to a new frame alignment. Setting the REFCRCEN bit position to logic 1
enables reframe due to excessive CRC errors; setting the REFCRCEN bit to logic 0 disables
CRC errors from causing a reframe.
REFRDIS:
The REFRDIS bit disables reframing under any error condition once frame alignment has
been found; reframing can be initiated by software via the REFR bit. A logic 1 in the REFRDIS
bit position causes the FRMR to remain "locked in frame" once initial frame alignment has
been found. A logic 0 allows reframing to occur based on the various error criteria (FER,
excessive CRC errors, etc.). Note that while the FRMR remains locked in frame due to
REFRDIS=1, a received AIS will not be detected since the FRMR must be out of frame to
detect AIS.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
248
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 091H, 191H, 291H, 391H: E1-FRMR Maintenance Mode Options
Bit
Type
Bit 7
Function
Default
Unused
X
Bit 6
R/W
BIT2C
1
Bit 5
R/W
SMFASC
0
Bit 4
R/W
TS16C
0
Bit 3
R/W
RAIC
0
Unused
X
Bit 2
Bit 1
R/W
AISC
0
Bit 0
R
EXCRCERR
X
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive
Options register is a logic 1, this register is held reset.
BIT2C:
The BIT2C bit enables the additional criterion that loss of frame is declared when bit 2 in
timeslot 0 of NFAS frames has been received in error on 3 consecutive occasions: a logic 1 in
the BIT2C position enables declaration of loss of frame alignment when bit 2 is received in
error; a logic 0 in BIT2C enables declaration of loss of frame alignment based on the absence
of FAS frames only.
SMFASC:
The SMFASC bit selects the criterion used to declare loss of signaling multiframe alignment
signal: a logic 0 in the SMFASC bit position enables declaration of loss of signaling multiframe
alignment when 2 consecutive multiframe alignment patterns have been received in error; a
logic 1 in the SMFASC bit position enables declaration of loss of signaling multiframe when 2
consecutive multiframe alignment patterns have been received in error or when timeslot 16
contains logic 0 in all bit positions for 1 or 2 multiframes based on the criterion selected by
TS16C.
TS16C:
The TS16C bit selects the criterion used to declare loss of signaling multiframe alignment
signal when enabled by the SMFASC: a logic 0 in the TS16C bit position enables declaration
of loss of signaling multiframe alignment when timeslot 16 contains logic 0 in all bit positions
for 1 multiframe; a logic 1 in the TS16C bit position enables declaration of loss of signaling
multiframe when timeslot 16 contains logic 0 in all bit positions for 2 consecutive signaling
multiframes.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
249
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
RAIC:
The RAIC bit selects the criterion used to declare a Remote Alarm Indication (RAI). If RAIC is
logic 0, the RAIV indication is asserted upon reception of any A=1 (bit 3 of NFAS frames) and
is deasserted upon reception of any A=0. If RAIC is logic 1, the RAIV indication is asserted if
A=1 is received on 4 or more consecutive occasions, and is cleared upon reception of any
A=0.
AISC :
The AISC bit selects the criterion used for determining AIS alarm indication. If AISC is logic 0,
AIS is declared if there is a loss of frame (LOF) indication and a 512-bit period is received with
less than 3 zeros. If AISC is a logic 1, AIS is declared if less than 3 zeros are detected in
each of 2 consecutive 512-bit periods and is cleared when 3 or more zeros are detected in
each of 2 consecutive 512-bit intervals.
EXCRCERR:
The EXCRCERR bit is an active high status bit indicating that excessive CRC evaluation
errors (i.e., ≥ 915 errors in one second) have occurred, thereby initiating a reframe if enabled
by the REFCRCEN bit of the E1-FRMR Frame Alignment Options register. The EXCRCERR
bit is reset to logic 0 after the register is read.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
250
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 092H, 1902H, 292H, 392H: E1-FRMR Framing Status Interrupt Enable
Bit
Type
Function
Default
Bit 7
R/W
C2NCIWE
0
Bit 6
R/W
OOFE
0
Bit 5
R/W
OOSMFE
0
Bit 4
R/W
OOCMFE
0
Bit 3
R/W
COFAE
0
Bit 2
R/W
FERE
0
Bit 1
R/W
SMFERE
0
Bit 0
R/W
CMFERE
0
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive
Options register is a logic 1, this register is held reset.
C2NCIWE, OOFE, OOSMFE and OOCMFE:
A logic one in bits C2NCIWE, OOFE, OOSMFE and OOCMFE enables the generation of an
interrupt on a change of state of C2NCIWV, OOFV, OOSMFV and OOCMFV bits respectively
of the E1-FRMR Framing Status register.
COFAE:
A logic one in the COFAE bit enables the generation of an interrupt when the position of the
frame alignment has changed.
FERE:
A logic one in the FERE bit enables the generation of an interrupt when an error has been
detected in the frame alignment signal.
SMFERE:
A logic one in the SMFERE bit enables the generation of an interrupt when an error has been
detected in the signaling multiframe alignment signal.
CMFERE:
A logic one in the CMFERE bit enables the generation of an interrupt when an error has been
detected in the CRC multiframe alignment signal.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
251
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 093H, 193H, 293H, 393H: E1-FRMR Maintenance/Alarm Status Interrupt Enable
Bit
Type
Function
Default
Bit 7
R/W
RAIE
0
Bit 6
R/W
RMAIE
0
Bit 5
R/W
AISDE
0
Bit 4
R/W
Reserved
0
Bit 3
R/W
REDE
0
Bit 2
R/W
AISE
0
Bit 1
R/W
FEBEE
0
Bit 0
R/W
CRCEE
0
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive
Options register is a logic 1, this register is held reset.
RAIE, RMAIE, AISDE, REDE and AISE:
A logic one in bits RAIE, RMAIE, AISDE, REDE or AISE enables the generation of an interrupt
on a change of state of the RAIV, RMAIV, AISD, RED and AIS bits respectively of the E1FRMR Maintenance/Alarm Status register.
Reserved:
This bit must be set to a logic 0 for normal operation.
FEBEE:
When the FEBEE bit is a logic one, an interrupt is generated when a logic zero is received in
the Si bits of frames 13 or 15.
CRCEE:
When the CRCEE bit is a logic one, an interrupt is generated when calculated CRC differs
from the received CRC remainder.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
252
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 094H, 194H, 294H, 394H: E1-FRMR Framing Status Interrupt Indication
Bit
Type
Function
Default
Bit 7
R
C2NCIWI
X
Bit 6
R
OOFI
X
Bit 5
R
OOSMFI
X
Bit 4
R
OOCMFI
X
Bit 3
R
COFAI
X
Bit 2
R
FERI
X
Bit 1
R
SMFERI
X
Bit 0
R
CMFERI
X
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive
Options register is a logic 1, this register is held reset.
A logic 1 in any bit position of this register indicates which framing status generated an interrupt by
changing state.
C2NCIWI, OOFI, OOSMFI, OOCMFI, and COFAI:
C2NCIWI, OOFI, OOSMFI, OOCMFI, and COFAI indicate when the corresponding status has
changed state from logic 0 to logic 1 or vice-versa.
FERI, SMFERI, CMFERI:
FERI, SMFERI, CMFERI indicate when a framing error, signaling multiframe error or CRC
multiframe error event has been detected; these bits will be set if one or more errors have
occurred since the last register read.
The interrupt indications within this register work independently from the interrupt enable bits,
allowing the microprocessor to poll the register to determine the state of the framer. The contents
of this register are cleared to logic 0 after the register is read; the interrupt is also cleared if it was
generated by any of the Framing Status outputs.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
253
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 095H, 195H, 295H, 395H: E1-FRMR Maintenance/Alarm Status Interrupt Indication
Bit
Type
Function
Default
Bit 7
R
RAII
X
Bit 6
R
RMAII
X
Bit 5
R
AISDI
X
Unused
X
Bit 4
Bit 3
R
REDI
X
Bit 2
R
AISI
X
Bit 1
R
FEBEI
X
Bit 0
R
CRCEI
X
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive
Options register is a logic 1, this register is held reset.
A logic 1 in any bit position of this register indicates which maintenance or alarm status generated
an interrupt by changing state.
RAII, RMAII, AISDI, REDI, and AISI:
RAII, RMAII, AISDI, REDI, and AISI indicate when the corresponding FRMR
Maintenance/Alarm Status register bit has changed state from logic 0 to logic 1 or vice-versa.
FEBEI:
The FEBEI bit becomes a logic one when a logic zero is received in the Si bits of frames 13 or
15.
CRCEI:
The CRCEI bit becomes a logic one when a calculated CRC differs from the received CRC
remainder.
The bits in this register are set by a single error event.
The interrupt indications within this register work independently from the interrupt enable bits,
allowing the microprocessor to poll the register to determine the state of the framer. The contents
of this register are cleared to logic 0 after the register is read; the interrupt is also cleared if it was
generated by one of the Maintenance/Alarm Status events.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
254
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 096H, 196H, 296H, 396H: E1-FRMR Framing Status
Bit
Type
Function
Default
Bit 7
R
C2NCIWV
X
Bit 6
R
OOFV
X
Bit 5
R
OOSMFV
X
Bit 4
R
OOCMFV
X
Bit 3
R
OOOFV
X
Bit 2
R
RAICCRCV
X
Bit 1
R
CFEBEV
X
Bit 0
R
V52LINKV
X
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive
Options register is a logic 1, this register is held reset.
Reading this register returns the current state value of the C2NCIW, OOF, OOSMF, OOCMF,
OOOF and RAICCRC FRMR framing statuses.
C2NCIWV:
The C2NCIWV bit is set to logic one while the FRMR is operating in CRC to non-CRC
interworking mode. The C2NCIWV bit goes to a logic zero once when the FRMR exits CRC
to non-CRC interworking mode.
OOFV:
The OOFV bit is a logic one when basic frame alignment has been lost. The OOFV bit goes
to a logic zero once frame alignment has been regained.
OOSMFV:
The OOSMFV bit is a logic one when the signaling multiframe alignment has been lost. The
OOSMFV bit becomes a logic zero once signaling multiframe has been regained.
OOCMFV:
The OOCMFV bit is a logic one when the CRC multiframe alignment has been lost. The
OOCMFV bit becomes a logic zero once CRC multiframe has been regained.
OOOFV:
This bit indicates the current state of the out of offline frame (OOOF) indicator. OOOFV is
asserted when the offline framer in the CRC multiframe find procedure is searching for frame
alignment.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
255
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
RAICCRCV:
This bit indicates the current state of the RAI and continuous CRC (RAICCRC) indicator.
RAICCRCV is asserted when the remote alarm (A bit) is set high and the CRC error (E bit) is
set low for a period of 10 ms.
CFEBEV:
This bit indicates the current state of the continuous FEBE (CFEBE) indicator. CFEBEV is
asserted when the CRC error (E bit) is set high on more than 990 occasions in each second
(out of 1000 possible occasions) for the last 5 consecutive seconds.
V52LINKV:
This bit indicates the current state of the V5.2 link (V52LINK) identification signal indicator.
V52LINKV is asserted if 2 out of the last 3 received Sa7 bits are a logic 0.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
256
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 097H, 197H, 297H, 397H: E1-FRMR Maintenance/Alarm Status
Bit
Type
Function
Default
Bit 7
R
RAIV
X
Bit 6
R
RMAIV
X
Bit 5
R
AISD
X
Unused
X
Bit 4
Bit 3
R
RED
X
Bit 2
R
AIS
X
Bit 1
Unused
X
Bit 0
Unused
X
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive
Options register is a logic 1, this register is held reset.
Reading this register returns the current state value of the RAI, RMAI, AISD, RED, and AIS
maintenance/alarm statuses.
RAIV:
The RAIV bit indicates the remote alarm indication (RAI) value. The RAIV bit is set to logic
one when the "A" bit (bit 3 in timeslot 0 of the non-frame alignment signal frame) has been
logic one for an interval specified by the RAIC bit in the E1-FRMR Maintenance Mode Options
register. When RACI is logic 1, RAIV is set when A=1 for 4 or more consecutive intervals, and
is cleared upon reception of any A=0. When RACI is logic 0, RAI is set upon reception of any
A=1, and is cleared upon reception of any A=0. The RAIV output is updated every two
frames.
RMAIV:
The RMAIV bit indicates the remote multiframe alarm indication (RMAI) value. The RMAIV bit
is set to logic one when the "Y" bit (bit 6 in timeslot 16 in frame 0 of the signaling multiframes)
has been a logic one for 3 consecutive signaling multiframes, and is cleared upon reception of
any Y=0. The RMAIV bit is updated every 16 frames.
AISD:
The AISD bit indicates the alarm indication signal (AIS) detect value. The AISD bit is set to
logic one when the incoming data stream has a low zero-bit density for an interval specified by
the AISC bit in the E1-FRMR Maintenance Mode Options register. When AISC is logic 0,
AISD is asserted when 512-bit periods have been received with 2 or fewer zeros. The
indication is cleared when a 512-bit period is received with 3 or more zeros. When AISC is
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
257
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
logic 1, AISD is asserted when two consecutive 512 bit periods have been received with 2 or
fewer zeros. The indication is cleared when 2 consecutive 512-bit periods are received, with
each period containing 3 or more zeros. The AISD bit is updated once every 512-bit period.
RED:
The RED bit is a logic one if an out of frame condition has persisted for 100 ms. The RED bit
returns to a logic zero when a out of frame condition has been absent for 100 ms.
AIS:
The AIS bit is a logic one when an out of frame all-ones condition has persisted for 100 ms.
The AIS bit returns to a logic zero when the AIS condition has been absent for 100 ms.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
258
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 098H, 198H, 298H, 398H: E1-FRMR Timeslot 0 International/National Bits
Bit
Type
Function
Default
Bit 7
R
Si[1]
X
Bit 6
R
Si[0]
X
Bit 5
R
A
X
Bit 4
R
Sa[4]
X
Bit 3
R
Sa[5]
X
Bit 2
R
Sa[6]
X
Bit 1
R
Sa[7]
X
Bit 0
R
Sa[8]
X
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive
Options register is a logic 1, this register is held reset.
This register returns the International and National bits from TS0 of incoming frames. The Si[1:0],
A and Sa[4:8] bits map to TS0 frames as shown in Table 51.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
259
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Table 51
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- Timeslot 0 Bit Position Allocation
Frame
1
2
3
4
5
6
7
8
FAS
Si[1]
0
0
1
1
0
1
1
NFAS
Si[0]
1
A
Sa[4]
Sa[5]
Sa[6]
Sa[7]
Sa[8]
Si [1]:
Reading the Si[1] bit returns the International bit in the last received FAS frame. This bit is
updated upon generation of the BRFPI interrupt on FAS frames.
Si[0]:
Reading the Si[0] bit returns the International bit in the last received NFAS frame. This bit is
updated upon generation of the BRFPI interrupt on NFAS frames.
A:
Reading the A bit position returns the Remote Alarm Indication (RAI) bit in the last received
NFAS frame. This bit is updated upon generation of the BRFPI interrupt on NFAS frames.
Sa[4:8]:
Reading these bits returns the National bit values in the last received NFAS frame. This bit is
updated upon generation of the BRFPI interrupt on NFAS frames.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
260
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 099H, 199H, 299H, 399H: E1-FRMR CRC Error Counter - LSB
Bit
Type
Function
Default
Bit 7
R
CRCERR[7]
X
Bit 6
R
CRCERR[6]
X
Bit 5
R
CRCERR [5]
X
Bit 4
R
CRCERR [4]
X
Bit 3
R
CRCERR [3]
X
Bit 2
R
CRCERR [2]
X
Bit 1
R
CRCERR [1]
X
Bit 0
R
CRCERR [0]
X
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive
Options register is a logic 1, this register is held reset.
CRCERR[7:0]:
The CRCERR[7:0] register bits contain the least significant byte of the 10-bit CRC error
counter value, which is updated every second.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
261
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 09AH, 19AH, 29AH, 39AH: E1-FRMR CRC Error Counter – MSB/Timeslot 16 Extra
Bits
Bit
Type
Function
Default
Bit 7
R
OVR
X
Bit 6
R
NEWDATA
X
Bit 5
R
X[3]
X
Bit 4
R
Y
X
Bit 3
R
X[1]
X
Bit 2
R
X[0]
X
Bit 1
R
CRCERR [9]
X
Bit 0
R
CRCERR [8]
X
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive
Options register is a logic 1, this register is held reset.
This register contains the most significant two bits of the 10-bit CRC error counter value, updated
every second.
NEWDATA:
The NEWDATA flag bit indicates that the CRCERR counter register contents have been
updated with a new count value accumulated over the last 1 second interval. It is set to
logic 1 when the CRC error counter data is transferred into the counter registers, and is reset
to logic 0 when this register is read. This bit can be polled to determine the 1 second timing
boundary used by the FRMR.
OVR:
The OVR flag bit indicates that the CRCERR counter register contents have not been read
within the last 1 second interval, and therefore have been over-written. It is set to logic 1 if
CRC error counter data is transferred into the counter registers before the previous data has
been read out, and is reset to logic 0 when this register is read.
X[3], Y, X[1], X[0]:
Reading these bits returns the value of the Extra bits (X[3] and X1:0]) and the Remote
Signaling Multiframe Alarm bit (Y) in Frame 0, Timeslot 16 of the last received signaling
multiframe. These bits are updated upon generation of the BRFPI interrupt on NFAS frames.
They map to timeslot 16 as shown in Table 52. Note that the contents of this register are not
updated while the E1-FRMR is out of frame.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
262
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Table 52
Bit
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- Signaling Multiframe Timeslot 16, Frame 0 Bit Positions
1
2
3
4
5
6
7
8
0
0
0
0
X[3]
Y
X[1]
X[0]
CRCERR[9:8]:
The CRCERR[9:8] register bits contain the two most significant bits of the 10-bit CRC error
counter value, which is updated every second.
This CRC error count is distinct from that of PMON because it is guaranteed to be an accurate
count of the number of CRC errors in one second; whereas, PMON relies on externally initiated
transfers which may not be one second apart.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
263
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 09BH, 19BH, 29BH, 39BH: E1-FRMR National Bit Codeword Interrupt Enables
Bit
Type
Function
Default
Bit 7
R/W
SaSEL[2]
0
Bit 6
R/W
SaSEL[1]
0
Bit 5
R/W
SaSEL[0]
0
Bit 4
R/W
Sa4E
0
Bit 3
R/W
Sa5E
0
Bit 2
R/W
Sa6E
0
Bit 1
R/W
Sa7E
0
Bit 0
R/W
Sa8E
0
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive
Options register is a logic 1, this register is held reset.
SaSEL[2:0]:
The SaSEL[2:0] bits selects which National Bit Codeword appears in the SaX[1:4] bits of the
National Bit Codeword register. These bits map to the codeword selection as shown in Table
53:
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
264
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Table 53
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- E1-FRMR Codeword Select
SaSEL[2:0]
National Bit Codeword
001
Undefined
010
Undefined
011
Undefined
100
Sa4
101
Sa5
110
Sa6
111
Sa7
000
Sa8
Sa4E, Sa5E, Sa6E, Sa7E, Sa8E:
The National Use interrupt enables allow changes in Sa code word values to generate an
interrupt. If SaXE is a logic 1, a logic 1 in the corresponding SaXI bit of the E1-FRMR
National Bit Codeword Interrupts register will result in the assertion low of the INTB output.
The interrupt enable should be logic 0 for any bit receiving a HDLC datalink.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
265
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 09CH, 19CH, 29CH, 39CH: E1-FRMR National Bit Codeword Interrupts
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
R
Sa4I
X
Bit 3
R
Sa5I
X
Bit 2
R
Sa6I
X
Bit 1
R
Sa7I
X
Bit 0
R
Sa8I
X
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive
Options register is a logic 1, this register is held reset.
Sa4I, Sa5I, Sa6I, Sa7I, Sa8I:
The National Use interrupt status bits indicate if the debounced version of the individual bits
has changed since the last time this register has been read. A logic 1 in one of the bit
positions indicates a new nibble codeword is available in the associated SaX[1:4] bits in the
National Bit Codeword registers, where N is 4 through 8. If the associated SaXE bit in the E1FRMR National Bit Interrupt Enables register is a logic 1, a logic 1 in the SaXI results in the
assertion of the INTB output.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
266
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 09DH, 19DH, 29DH, 39DH: E1-FRMR National Bit Codeword
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
R
SaX[1]
X
Bit 2
R
SaX[2]
X
Bit 1
R
SaX[3]
X
Bit 0
R
SaX[4]
X
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive
Options register is a logic 1, this register is held reset.
SaX[1:4]:
Reading these bits returns the SaX nibble code word extracted from the submultiframe, where
‘X’ corresponds to the National bit selected by the SaSEL[2:0] bits in the E1-FRMR National
Bit Codeword Interrupt Enables register. SaX[1] is from the first SaX bit of the submultiframe;
SaX[4] is from the last. A change in the codeword values sets the SaI[X] bit of the E1-FRMR
National Bits Codeword Interrupts register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
267
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 09EH, 19EH, 29EH, 39EH: E1-FRMR Frame Pulse/Alarm/V5.2 Link ID Interrupt
Enables
Bit
Type
Function
Default
Bit 7
R/W
OOOFE
0
Bit 6
R/W
RAICCRCE
0
Bit 5
R/W
CFEBEE
0
Bit 4
R/W
V52LINKE
0
Bit 3
R/W
BRFPE
0
Bit 2
R/W
ICSMFPE
0
Bit 1
R/W
ICMFPE
0
Bit 0
R/W
ISMFPE
0
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive
Options register is a logic 1, this register is held reset.
OOOFE:
A logic one in the OOOFE bit enables the generation of an interrupt when the out of offline
frame interrupt (OOOFI) is asserted.
RAICCRCE:
A logic one in the RAICCRCE bit enables the generation of an interrupt when a RAI and
Continuous CRC condition has been detected in the incoming data stream.
CFEBEE:
A logic one in the CFEBEE bit enables the generation of an interrupt when continuous FEBEs
have been detected in the incoming data stream.
V52LINKE:
A logic one in the V52LINKE bit enables the generation of an interrupt when a V5.2 link
identification has been detected in the Sa7 bits.
BRFPE:
The input frame pulse interrupt enable bit allows interrupts to be generated on each basic
frame pulse. If BRFPE is a logic 1, a logic 1 in the BRFPI bit of the Frame Pulse Interrupts
register will result in the assertion low of the INTB output.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
268
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
ICSMFPE:
The input frame pulse interrupt enable bit allows interrupts to be generated on each CRC
submultiframe pulse. If ICSMFPE is a logic 1, a logic 1 in the ICSMFPI bit of the Frame Pulse
Interrupts register will result in the assertion low of the INTB output.
ICMFPE:
The input frame pulse interrupt enable bit allows interrupts to be generated on each CRC
multiframe pulse. If ISMFPE is a logic 1, a logic 1 in the ISMFPI bit of the Frame Pulse
Interrupts register will result in the assertion low of the INTB output.
ISMFPE:
The input frame pulse interrupt enable bit allows interrupts to be generated on each signalling
multiframe pulse. If ISMFPE is a logic 1, a logic 1 in the ISMFPI bit of the Frame Pulse
Interrupts register will result in the assertion low of the INTB output.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
269
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 09FH, 19FH, 29FH, 39FH: E1-FRMR Frame Pulse/Alarm Interrupts
Bit
Type
Function
Default
Bit 7
R
OOOFI
X
Bit 6
R
RAICCRCI
X
Bit 5
R
CFEBEI
X
Bit 4
R
V52LINKI
X
Bit 3
R
BRFPI
X
Bit 2
R
ICSMFPI
X
Bit 1
R
ICMFPI
X
Bit 0
R
ISMFPI
X
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive
Options register is a logic 1, this register is held reset.
OOOFI:
The OOOFI bit indicates when the out of offline frame indicator (OOOFV) changes state.
RAICCRCI:
The RAICCRCI bit indicates when a RAI and Continuous CRC condition has been detected in
the incoming data stream. This interrupt is triggered when the remote alarm (A bit) is set high
and the CRC error (E bit) is set low for a period of 10 ms.
CFEBEI:
The CFEBEI bit indicates when continuous FEBEs have been detected in the incoming data
stream. This interrupt is triggered when the CRC error (E bit) is set high on more than 990
occasions in each second (out of 1000 possible occasions) for 5 consecutive seconds.
V52LINKI:
V52LINKI indicates when a V5.2 link identification signal has been detected or lost in the Sa7
bits. This bit will toggle any time the V52LINKV bit changes state.
BRFPI:
The input frame pulse interrupt status bit is asserted at timeslot 1, bit position 1 of the frame in
the incoming data stream.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
270
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
ICSMFPI:
The input CRC submultiframe alignment frame pulse interrupt status bit is asserted at timeslot
1, bit position 1 of frame 0 of the CRC submultiframe in the incoming data stream.
ICMFPI:
The input CRC multiframe alignment frame pulse interrupt status bit is asserted at timeslot 1,
bit position 1 of frame 0 of the CRC multiframe in the incoming data stream.
ISMFPI:
The input signaling multiframe alignment frame pulse interrupt status bit is asserted at
timeslot 17, bit position 1 of frame 0 of the signaling multiframe in the incoming data stream.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
271
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 0A8H, 1A8H, 2A8H, 3A8H: TDPR Configuration
Bit
Type
Function
Default
Bit 7
R/W
FLGSHARE
1
Bit 6
R/W
FIFOCLR
0
Bit 5
R/W
PREN
0
Unused
X
Bit 4
Bit 3
R/W
EOM
0
Bit 2
R/W
ABT
0
Bit 1
R/W
CRC
1
Bit 0
R/W
EN
0
EN:
The EN bit enables the TDPR functions. When EN is set to logic 1, the TDPR is enabled and
flag sequences are sent until data is written into the TDPR Transmit Data register. When the
EN bit is set to logic 0, the TDPR is disabled and overwrites the incoming backplane data with
an all 1's pattern.
CRC:
The CRC enable bit controls the generation of the CCITT_CRC frame check sequence
(FCS). Setting the CRC bit to logic 1 enables the CCITT-CRC generator and appends the 16bit FCS to the end of each message. When the CRC bit is set to logic 0, the FCS is not
appended to the end of the message. The CRC type used is the CCITT-CRC with generator
polynomial x16 + x12 + x5 + 1. The high order bit of the FCS word is transmitted first. CRC
FCS is also appended to the performance report data transmitted from the T1-APRM if CRC
is set to logic 1.
ABT:
The Abort (ABT) bit controls the sending of the 7 consecutive ones HDLC abort code. Setting
the ABT bit to a logic 1 causes the 11111110 code (the 0 is transmitted first) to be transmitted
after the last byte from the TDPR FIFO is transmitted. The FIFO is then reset. All data in the
FIFO will be lost. Aborts are continuously sent and the FIFO is held in reset until this bit is
reset to a logic 0. At least one Abort sequence will be sent when the ABT bit transitions from
logic 0 to logic 1. Note that T1-APRM performance report insertion takes precedence over the
ABT register bit. When a T1-APRM performance report frame is available, the TDPR will
transmit 2 flag sequences before, and 1 or 2 flag sequences (depending on the FLGSHARE
bit setting) after the performance report frame. If the ABT bit is still set, the TDPR will then
transmit the Abort sequence again.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
272
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
EOM:
The EOM bit indicates that the last byte of data written in the Transmit Data register is the end
of the present data packet. If the CRC bit is set then the 16-bit FCS word is appended to the
last data byte transmitted and a continuous stream of flags is generated. The EOM bit is
cleared upon a write to the TDPR Transmit Data register.
PREN:
The PREN bit enables performance reports from the T1-APRM to be transmitted. When
PREN is a logic 1, the message arbitrator circuit will insert the T1-APRM performance report
as soon as it is finished any packet whose transmission is already in progress and the
delimiting flags. When PREN is a logic 0, the message arbitrator circuit will ignore requests
from the T1-APRM.
FIFOCLR:
The FIFOCLR bit resets the TDPR FIFO. When set to logic 1, FIFOCLR will cause the TDPR
FIFO to be cleared. There is a maximum delay of one T1 or E1 clock cycle between the
setting of this register bit and the execution of the FIFO clear operation.
FLGSHARE:
The FLGSHARE bit configures the TDPR to share the opening and closing flags between
successive frames. If FLGSHARE is logic 1, the opening and closing flags between
successive frames are shared. If FLGSHARE is logic 0, separate closing and opening flags
are inserted between successive frames.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
273
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 0A9H, 1A9H, 2A9H, 3A9H: TDPR Upper Transmit Threshold
Bit
Type
Bit 7
Function
Default
Unused
X
Bit 6
R/W
UTHR[6]
1
Bit 5
R/W
UTHR[5]
0
Bit 4
R/W
UTHR[4]
0
Bit 3
R/W
UTHR[3]
0
Bit 2
R/W
UTHR[2]
0
Bit 1
R/W
UTHR[1]
0
Bit 0
R/W
UTHR[0]
0
UTHR[6:0]:
The UTHR[6:0] bits define the TDPR FIFO fill level which will automatically cause the bytes
stored in the TDPR FIFO to be transmitted. Once the fill level exceeds the UTHR[6:0] value,
transmission will begin. Transmission will not stop until the last complete packet is
transmitted and the TDPR FIFO fill level is below UTHR[6:0] + 1.
The value of UTHR[6:0] must always be greater than the value of LINT[6:0] unless both
values are equal to 00H.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
274
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 0AAH, 1AAH, 2AAH, 3AAH: TDPR Lower Interrupt Threshold
Bit
Type
Bit 7
Function
Default
Unused
X
Bit 6
R/W
LINT[6]
0
Bit 5
R/W
LINT[5]
0
Bit 4
R/W
LINT[4]
0
Bit 3
R/W
LINT[3]
0
Bit 2
R/W
LINT[2]
1
Bit 1
R/W
LINT[1]
1
Bit 0
R/W
LINT[0]
1
LINT[6:0]:
The LINT[6:0] bits define the TDPR FIFO fill level which causes an internal interrupt (LFILLI)
to be generated. Once the TDPR FIFO level decrements to empty or to a value less than
LINT[6:0], LFILLI and BLFILL will be set to logic 1. LFILLI will cause an interrupt on INTB if
LFILLE is set to logic 1.
The value of LINT[6:0] must always be less than the value of UTHR[6:0] unless both values
are equal to 00H.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
275
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 0ABH, 1ABH, 2ABH, 3ABH: TDPR Interrupt Enable
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
R/W
PRINTE
0
Bit 3
R/W
FULLE
0
Bit 2
R/W
OVRE
0
Bit 1
R/W
UDRE
0
Bit 0
R/W
LFILLE
0
LFILLE:
If LFILLE is a logic 1, a transition to logic 1 on LFILLI will generate an interrupt on INTB.
UDRE:
If UDRE is a logic 1, a transition to logic 1 on UDRI will generate an interrupt on INTB.
OVRE:
If OVRE is a logic 1, a transition to logic 1 on OVRI will generate an interrupt on INTB.
FULLE:
If FULLE is a logic 1, a transition to logic 1 on FULLI will generate an interrupt on INTB.
PRINTE:
If PRINTE is a logic 1, a transition to logic 1 on PRINTI will generate an interrupt on INTB.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
276
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 0ACH, 1ACH, 2ACH, 3ACH: TDPR Interrupt Status
Bit
Type
Bit 7
Function
Default
Unused
X
Bit 6
R
FULL
X
Bit 5
R
BLFILL
X
Bit 4
R
PRINTI
X
Bit 3
R
FULLI
X
Bit 2
R
OVRI
X
Bit 1
R
UDRI
X
Bit 0
R
LFILLI
X
Writing to this register will clear the underrun condition if it has occurred.
Consecutive writes to the TDPR Configuration and TDPR Transmit Data register and reads of the
TDPR Interrupt Status register should not occur at rates greater than that of Transmit clock.
LFILLI:
The LFILLI bit will transition to logic 1 when the TDPR FIFO level transitions to empty or falls
below the value of LINT[6:0] programmed in the TDPR Lower Interrupt Threshold register.
LFILLI will assert INTB if it is a logic 1 and LFILLE is programmed to logic 1. LFILLI is cleared
when this register is read.
UDRI:
The UDRI bit will transition to 1 when the TDPR FIFO underruns. That is, the TDPR was in
the process of transmitting a packet when it ran out of data to transmit. UDRI will assert INTB
if it is a logic 1 and UDRE is programmed to logic 1. UDRI is cleared when this register is
read.
OVRI:
The OVRI bit will transition to 1 when the TDPR FIFO overruns. That is, the TDPR FIFO was
already full when another data byte was written to the TDPR Transmit Data register. OVRI will
assert INTB if it is a logic 1 and OVRE is programmed to logic 1. OVRI is cleared when this
register is read.
FULLI:
The FULLI bit will transition to logic 1 when the TDPR FIFO is full. FULLI will assert INTB if it
is a logic 1 and FULLE is programmed to logic 1. FULLI is cleared when this register is read.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
277
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
PRINTI:
The PRINTI bit will transition to logic 1 when a performance report is ready to be transmitted
from the T1-APRM. PRINTI will assert INTB if it is a logic 1 and PRINTE is programmed to
logic 1. PRINTI is cleared when this register is read.
BLFILL:
The BLFILL bit is set to logic 1 if the current FIFO fill level is below the LINT[7:0] level or is
empty.
FULL:
The FULL bit reflects the current condition of the TDPR FIFO. If FULL is a logic 1, the TDPR
FIFO already contains 128-bytes of data and can accept no more.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
278
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 0ADH, 1ADH, 2ADH, 3ADH: TDPR Transmit Data
Bit
Type
Function
Default
Bit 7
R/W
TD[7]
X
Bit 6
R/W
TD[6]
X
Bit 5
R/W
TD[5]
X
Bit 4
R/W
TD[4]
X
Bit 3
R/W
TD[3]
X
Bit 2
R/W
TD[2]
X
Bit 1
R/W
TD[1]
X
Bit 0
R/W
TD[0]
X
Consecutive writes to the TDPR Configuration and TDPR Transmit Data register and reads of the
TDPR Interrupt Status register should not occur at rates greater than that of Transmit clock
TD[7:0]:
The TD[7:0] bits contain the data to be transmitted on the data link. Data written to this
register is serialized and transmitted (TD[0] is transmitted first).
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
279
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 0B0H, 1B0H, 2B0H, 3B0H: RX-ELST CCS Configuration
Bit
Type
Function
Default
Bit 7
R/W
Reserved
0
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
Unused
X
Bit 1
R/W
IR
1
Bit 0
R/W
OR
1
Reserved:
This bit must be logic 0 for normal operation.
IR:
This bit determines the input rate of the RX-ELST CCS. It must be set to logic 1 for E1 mode;
it must be set to logic 0 for T1 mode.
OR:
This bit must be logic 1 for normal operation.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
280
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 0B1H, 1B1H, 2B1H, 3B1H: RX-ELST CCS Interrupt Enable/Status
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
R/W
SLIPE
0
Bit 1
R
SLIPD
X
Bit 0
R
SLIPI
X
SLIPE:
The SLIPE bit position is an interrupt enable that when set, enables the INTB output to assert
low when a slip occurs. When the block is reset the SLIPE bit position is cleared and interrupt
generation is disabled.
SLIPD:
The SLIPD bit indicates the direction of the last slip. If the SLIPD bit is a logic 1 then the last
slip was due to the frame buffer becoming full; a frame was deleted. If the SLIPD bit is a
logic 0 then the last slip was due to the frame buffer becoming empty; a frame was duplicated.
SLIPI:
The SLIPI bit is set if a slip occurred since the last read of this register. The SLIPI bit is
cleared upon reading this register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
281
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 0B2H, 1B2H, 2B2H, 3B2H: RX-ELST CCS Idle Code
Bit
Type
Function
Default
Bit 7
R/W
D7
1
Bit 6
R/W
D6
1
Bit 5
R/W
D5
1
Bit 4
R/W
D4
1
Bit 3
R/W
D3
1
Bit 2
R/W
D2
1
Bit 1
R/W
D1
1
Bit 0
R/W
D0
1
The contents of this register replace the timeslot data in the CCSBRD serial data stream for the
associated quadrant when the framer is out of frame and the RCCSTRKEN bit in the Receive HMVIP/CCS Enable register is a logic 1. Since the transmission of all ones timeslot data is a
common requirement, this register is set to all ones on a reset condition. D7 is the first to be
transmitted.
The writing of the idle code pattern is asynchronous with respect to the output data clock. One
timeslot of idle code data will be corrupted if the register is written to when the framer is out of
frame.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
282
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 0B4H, 1B4H, 2B4H, 3B4H: TX-ELST CCS Configuration
Bit
Type
Function
Default
Bit 7
R/W
Reserved
0
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
Unused
X
Bit 1
R/W
IR
1
Bit 0
R/W
OR
1
Reserved:
This bit must be logic 0 for normal operation.
IR:
This bit must be logic 1 for normal operation.
OR:
This bit determines the output rate of the TX-ELST CCS. It must be set to logic 1 for E1
mode; it must be set to logic 0 for T1 mode.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
283
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 0B5H, 1B5H, 2B5H, 3B5H: TX-ELST CCS Interrupt Enable/Status
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
R/W
SLIPE
0
Bit 1
R
SLIPD
X
Bit 0
R
SLIPI
X
SLIPE:
The SLIPE bit position is an interrupt enable that when set, enables the INTB output to assert
low when a slip occurs. When the block is reset the SLIPE bit position is cleared and interrupt
generation is disabled.
SLIPD:
The SLIPD bit indicates the direction of the last slip. If the SLIPD bit is a logic 1 then the last
slip was due to the frame buffer becoming full; a frame was deleted. If the SLIPD bit is a
logic 0 then the last slip was due to the frame buffer becoming empty; a frame was duplicated.
SLIPI:
The SLIPI bit is set if a slip occurred since the last read of this register. The SLIPI bit is
cleared upon reading this register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
284
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 0B8H: Receive H-MVIP/CCS Enable
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
R/W
RCCSTRKEN
0
Bit 1
R/W
RCCSEN
0
Bit 0
R/W
RHMVIPEN
0
RHMVIPEN:
The Receive H-MVIP Enable bit, RHMVIPEN, configures the Receive stream for Clock Slave:
H-MVIP mode. When RHMVIPEN is a logic 1, the Receive stream is configured for Clock
Slave: H-MVIP mode and BRPCM[2:4] and BRSIG[1:4] are driven low. To enter Receive
Clock Slave: Full T1/E1 with CCS H-MVIP mode, RHMVIPEN is to be programmed to logic 0
and RCCSEN is to be programmed to logic 1.
See the Operation section for more information configuring the COMET-QUAD for the
Receive Clock Slave: H-MVIP mode of operation.
RCCSEN:
The Receive Common Channel Signaling Enable bit, RCCSEN, configures the Receive
stream for Common Channel Signaling (CCS) extraction. When RCCSEN is a logic 1, the
extracted CCS is presented on the CCSBRD pin. This bit is ignored when RHMVIPEN is a
logic 1. To enter Receive Clock Slave: Full T1/E1 with CCS H-MVIP mode, RCCSEN is to be
programmed to logic 1.
RCCSTRKEN:
The Receive Common Channel Signaling Trunk Conditioning Enable bit enables trunk
conditioning on the Receive Common Channel Signaling stream upon an out of frame
condition. If RCCSTRKEN is a logic 1, the contents of the RX-ELST CCS Idle Code register
are inserted into the CCSBRD timeslots corresponding to the quadrant reporting out-of-basic
frame (i.e., having its OOF status bit is logic 1). This bit only has an effect if RHMVIPEN is
logic 0 and RCCSEN is logic 1.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
285
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Receive Common Channel Signaling Trunk Conditioning is inserted downstream from the
payload loopback point and thus does not overwrite looped back payload.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
286
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 0B9H, 1B9H, 2B9H, 3B9H: Transmit H-MVIP/CCS Enable and Configuration
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
R/W
TCCS31
0
Bit 3
R/W
TCCS16
0
Bit 2
R/W
TCCS15
0
Bit 1
R/W
TCCSEN
0
Bit 0
R/W
THMVIPEN
0
THMVIPEN:
The Transmit H-MVIP Enable bit, THMVIPEN, enables the Transmit stream on all four
quadrants for Clock Slave: H-MVIP mode. When THMVIPEN is a logic 1, the Transmit stream
on all quadrants is configured for Clock Slave: H-MVIP mode. To enter Clock Slave: Full
T1/E1 with CCS H-MVIP mode, THMVIPEN is to be programmed to logic 0 and TCCSEN is to
be programmed to logic 1. THMVIPEN is only defined for Register 0B9H. In Registers 1B9H,
2B9H, and 3B9H, the bit is unused and the default value is ‘X’.
See the Operation section for more information on configuring the COMET-QUAD for the
Transmit Clock Slave: H-MVIP mode of operation.
TCCSEN:
The Transmit Common Channel Signaling Enable bit, TCCSEN, enables insertion of Common
Channel Signaling (CCS) into the transmit frame via the CCSBTD primary input pin. In T1
mode, the MAP bit of the BTIF Frame Pulse Configuration Register must be logic 0 and the
CCS should be presented on CCSBTD in timeslot 31. In E1 mode, CCS is inserted into zero
or more of timeslots 15, 16, and 31, as determined by the TCCS15, TCCS16, and TCCS31
register bits.
The CCSBTD pin’s CCS T1 and E1 timeslot formats are illustrated in Table 96 and Table 97
respectively.
TCCSEN is to be programmed to logic 1 in Transmit Clock Slave: Full T1/E1 with CCS HMVIP mode. TCCSEN can optionally be programmed to logic 1 in Transmit Clock Slave: HMVIP mode.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
287
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
TCCS15:
The Transmit Common Channel Signaling timeslot 15 bit enables the insertion of Common
Channel Signaling into timeslot 15 of the transmit E1 frame via the CCSBTD primary input
pin. This bit is ignored when TCCSEN is a logic 0 or when in T1 mode.
TCCS16:
The Transmit Common Channel Signaling timeslot 16 bit enables the insertion of Common
Channel Signaling into timeslot 16 of the transmit E1 frame via the CCSBTD primary input
pin. This bit is ignored when TCCSEN is a logic 0 or when in T1 mode.
In E1 mode, CCS is inserted upstream of the E1-TRAN. To avoid Timeslot 16 CCS from being
overwritten, program both the SIGEN and DLEN bits of the E1-TRAN Configuration register to
logic 0.
TCCS31:
The Transmit Common Channel Signaling timeslot 31 bit enables the insertion of Common
Channel Signaling into timeslot 31 of the transmit E1 frame via the CCSBTD primary input
pin. This bit is ignored when TCCSEN is a logic 0 or when in T1 mode.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
288
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 0BBH: RSYNC Select
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
Unused
X
Bit 1
R/W
RSYNC_SEL[1]
0
Bit 0
R/W
RSYNC_SEL[0]
0
RSYNC_SEL[1:0]:
The RSYNC Select register bits, RSYNC_SEL[1:0], select the source of the RSYNC COMETQUAD output.
When RSYNC_SEL[1:0] = “00”, quadrant #1 is selected as the source.
When RSYNC_SEL[1:0] = “01”, quadrant #2 is selected as the source.
When RSYNC_SEL[1:0] = “10”, quadrant #3 is selected as the source.
When RSYNC_SEL[1:0] = “11”, quadrant #4 is selected as the source.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
289
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 0BCH: COMET-QUAD Master Interrupt Source
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
R
QUAD[4]
X
Bit 2
R
QUAD[3]
X
Bit 1
R
QUAD[2]
X
Bit 0
R
QUAD[1]
X
QUAD[4:1]:
The QUAD[4:1] register bits allow software to determine the quadrant that produced the
interrupt on the INTB output pin. A logic 1 indicates an interrupt was produced from the
quadrant.
Reading this register does not remove the interrupt indication; within the corresponding
quadrant, the corresponding block’s interrupt status register must be read to remove the
interrupt indication.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
290
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Registers 0C0H, 1C0H, 2C0H, 3C0H: RDLC Configuration
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
R/W
Reserved
0
Bit 3
R/W
MEN
0
Bit 2
R/W
MM
0
Bit 1
R/W
TR
0
Bit 0
R/W
EN
0
EN:
The enable (EN) bit controls the overall operation of the RDLC. When EN is set to logic 1,
RDLC is enabled; when set to logic 0, RDLC is disabled. When the RDLC is disabled, the
FIFO buffer and interrupts are all cleared. When the RDLC is enabled, it will immediately
begin looking for flags.
TR:
Setting the terminate reception (TR) bit to logic 1 forces the RDLC to immediately terminate
the reception of the current data frame, empty the FIFO buffer, clear the interrupts, and begin
searching for a new flag sequence. The RDLC handles a terminate reception event in the
same manner as it would the toggling of the EN bit from logic 1 to logic 0 and back to logic 1.
Thus, the RDLC state machine will begin searching for flags. An interrupt will be generated
when the first flag is detected. The TR bit will reset itself to logic 0 after a rising and falling
edge have occurred on the CLK input, once the write strobe (CBI[9]) goes high. If the
Configuration Register is read after this time, the TR bit value returned will be logic 0.
MEN:
Setting the Match Enable (MEN) bit to logic 1 enables the detection and storage in the FIFO
of only those packets whose first data byte matches either of the bytes written to the Primary
or Secondary Match Address Registers, or the universal all ones address. When the MEN bit
is logic 0, all packets received are written into the FIFO.
MM:
Setting the Match Mask (MM) bit to logic 1 ignores the PA[1:0] bits of the Primary Address
Match Register, the SA[1:0] bits of the Secondary Address Match Register, and the two least
significant bits of the universal all ones address when performing the address comparison.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
291
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Reserved:
This bit must be set to logic 0 for normal operation.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
292
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Registers 0C1H, 1C1H, 2C1H, 3C1H: RDLC Interrupt Control
Bit
Type
Function
Default
Bit 7
R/W
INTE
0
Bit 6
R/W
INTC[6]
0
Bit 5
R/W
INTC[5]
0
Bit 4
R/W
INTC[4]
0
Bit 3
R/W
INTC[3]
0
Bit 2
R/W
INTC[2]
0
Bit 1
R/W
INTC[1]
0
Bit 0
R/W
INTC[0]
0
The contents of the Interrupt Control Register should only be changed when the EN bit in the
Configuration Register is logic 0. This prevents any erroneous interrupt generation.
INTC[6:0]:
These bits control the assertion of FIFO fill level set point interrupts. A value of 0 in INTC[6:0]
is interpreted as decimal 128.
INTE:
The Interrupt Enable bit (INTE) must be set to logic 1 to allow the internal interrupt status to
be propagated to the INTB output.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
293
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Registers 0C2H, 1C2H, 2C2H, 3C2H: RDLC Status
Bit
Type
Function
Default
Bit 7
R
FE
X
Bit 6
R
OVR
X
Bit 5
R
COLS
X
Bit 4
R
PKIN
X
Bit 3
R
PBS[2]
X
Bit 2
R
PBS[1]
X
Bit 1
R
PBS[0]
X
Bit 0
R
INTR
X
INTR:
The interrupt (INTR) bit is logic 1 if the RDLC has an active interrupt status. An RDLC
interrupt is generated
1) when the number of bytes specified by the INTC[6:0] bits of the RDLC Interrupt Control
register have been received on the data link and have been written into the FIFO,
2) immediately upon detection of a FIFO buffer overrun, as indicated by the OVR in this
register,
3) immediately upon writing the last byte of a packet into the FIFO,
4) immediately upon writing the last byte of an aborted packet, or
5) immediately upon detection of the transition from receiving all ones to flags, as indicated
by a “001” code in PBS[2:0].
If INTR is logic 1, follow the procedure described in section 12.5: Using the Internal HDLC
Receiver.
PBS[2:0]
The packet byte status (PBS[2:0]) bits indicate the status of the data last read from the FIFO.
The bits are encoded as follows:
Table 54
- Receive Packet Byte Status
PBS[2:0]
Significance
000
Data byte read from the FIFO is not special
001
The data byte read from the FIFO is the dummy byte that was written into the
FIFO when the first HDLC flag sequence (01111110) was detected. This
indicates that the data link became active.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
294
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
PBS[2:0]
Significance
010
The data byte read from the FIFO is the dummy byte that was written into the
FIFO when the HDLC abort sequence (01111111) was detected. This indicates
that the data link became inactive.
011
Reserved
100
The data byte read from the FIFO is the last byte of a normally terminated
packet with no CRC error and the packet received had an integer number of
bytes.
101
The data byte read from the FIFO must be discard because there was a noninteger number of bytes in the packet.
110
The data byte read from the FIFO is the last byte of a normally terminated
packet with a CRC error. The packet was received in error.
111
The data byte read from the FIFO is the last byte of a normally terminated
packet with a CRC error and a non-integer number of bytes. The packet was
received in error.
PKIN:
The Packet In (PKIN) bit is logic 1 when the last byte of a non-aborted packet is written into
the FIFO. The PKIN bit is cleared to logic 0 after the Status Register is read.
COLS:
The Change of Link Status (COLS) bit is set to logic 1 if the RDLC has detected the HDLC
flag sequence (01111110) or HDLC abort sequence (01111111) in the data. This indicates that
there has been a change in the data link status. The COLS bit is cleared to logic 0 by reading
this register or by clearing the EN bit in the Configuration Register. For each change in link
status, a byte is written into the FIFO. If the COLS bit is found to be logic 1 then the FIFO
must be read until empty. The status of the data link is determined by the PBS bits associated
with the data read from the FIFO.
OVR:
The overrun (OVR) bit is set to logic 1 when data is written over unread data in the FIFO
buffer. This bit is not reset to logic 0 until after the Status Register is read. While the OVR bit
is logic 1, the RDLC and FIFO buffer are held in the reset state, causing the COLS and PKIN
bits to be reset to logic 0.
FE:
The FIFO buffer empty (FE) bit is set to logic 1 when the last FIFO buffer entry is read. The
FE bit goes to logic 0 when the FIFO is loaded with new data.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
295
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Registers 0C3H, 1C3H, 2C3H, 3C3H: RDLC Data
Bit
Type
Function
Default
Bit 7
R
RD[7]
X
Bit 6
R
RD[6]
X
Bit 5
R
RD[5]
X
Bit 4
R
RD[4]
X
Bit 3
R
RD[3]
X
Bit 2
R
RD[2]
X
Bit 1
R
RD[1]
X
Bit 0
R
RD[0]
X
RD[0] corresponds to the first bit of the serial byte received on the DATA input.
This register is actually a 128-byte FIFO buffer. If data is available, the FE bit in the FIFO Input
Status Register is logic 0.
When an overrun is detected, an interrupt is generated and the FIFO buffer is held cleared until
the FIFO Input Status Register is read.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
296
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Registers 0C4H, 1C4H, 2C4H, 3C4H: RDLC Primary Address Match
Bit
Type
Function
Default
Bit 7
R/W
PA[7]
1
Bit 6
R/W
PA[6]
1
Bit 5
R/W
PA[5]
1
Bit 4
R/W
PA[4]
1
Bit 3
R/W
PA[3]
1
Bit 2
R/W
PA[2]
1
Bit 1
R/W
PA[1]
1
Bit 0
R/W
PA[0]
1
The first byte received after a flag character is compared against the contents of this register. If a
match occurs, the packet data, including the matching first byte, is written into the FIFO. PA[0]
corresponds to the first bit of the serial byte received on the DATA input. The MM bit in the
Configuration Register is used mask off PA[1:0] during the address comparison.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
297
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Registers 0C5H, 1C5H, 2C5H, 3C5H: RDLC Secondary Address Match
Bit
Type
Function
Default
Bit 7
R/W
SA[7]
1
Bit 6
R/W
SA[6]
1
Bit 5
R/W
SA[5]
1
Bit 4
R/W
SA[4]
1
Bit 3
R/W
SA[3]
1
Bit 2
R/W
SA[2]
1
Bit 1
R/W
SA[1]
1
Bit 0
R/W
SA[0]
1
The first byte received after a flag character is compared against the contents of this register. If a
match occurs, the packet data, including the matching first byte, is written into the FIFO. SA[0]
corresponds to the first bit of the serial byte received on the DATA input. The MM bit in the
Configuration Register is used mask off SA[1:0] during the address comparison.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
298
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 0D6H : CSU Configuration
Bit
Type
Function
Default
Bit 7
R/W
CSU_RESET
0
Bit 6
R/W
Reserved
0
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
R/W
MODE[2]
0
Bit 1
R/W
MODE[1]
0
Bit 0
R/W
MODE[0]
0
Reserved
This bit must be logic 0 for normal operation.
MODE[2:0]:
The MODE[2:0] selects the mode of the CSU. Table 55 indicates the required XCLK
frequency, and output frequencies for each mode.
Table 55
- Clock Synthesis Mode
MODE[2:0]
XCLK frequency
Transmit clock
frequency
000
2.048 MHz
2.048 MHz
001
1.544 MHz
1.544 MHz
01X
Reserved
Reserved
10X
Reserved
Reserved
110
Reserved
Reserved
111
2.048 MHz
1.544 MHz
CSU_RESET:
Setting the CSU_RESET bit to logic 1 causes the embedded CSU to be forced to a frequency
much lower than normal operation.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
299
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 0D8H, 1D8H, 2D8H, 3D8H: RLPS Equalization Indirect Data
Bit
Type
Function
Default
7
R/W
EQ_DATA[31]
0
6
R/W
EQ_DATA[30]
0
5
R/W
EQ_DATA[29]
0
4
R/W
EQ_DATA[28]
0
3
R/W
EQ_DATA[27]
0
2
R/W
EQ_DATA[26]
0
1
R/W
EQ_DATA[25]
0
0
R/W
EQ_DATA[24]
0
EQ_DATA[31:24]:
This register consists of 2-parts: read-only and write-only. Writing this register affects the most
significant byte of the input-data to the equalization RAM. Reading it returns the MSB of the
RAM location indexed by the RLPS Equalization Indirect Address register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
300
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 0D9H, 1D9H, 2D9H, 3D9H: RLPS Equalization Indirect Data
Bit
Type
Function
Default
7
R/W
EQ_DATA[23]
0
6
R/W
EQ_DATA[22]
0
5
R/W
EQ_DATA[21]
0
4
R/W
EQ_DATA[20]
0
3
R/W
EQ_DATA[19]
0
2
R/W
EQ_DATA[18]
0
1
R/W
EQ_DATA[17]
0
0
R/W
EQ_DATA[16]
0
EQ_DATA[23:16]:
This register consists of 2-parts: read-only and write-only. Writing this register affects the
second most significant byte of the input-data to the equalization RAM. Reading it returns the
second MSB of the RAM location indexed by the RLPS Equalization Indirect Address register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
301
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 0DAH, 1DAH, 2DAH, 3DAH: RLPS Equalization Indirect Data
Bit
Type
Function
Default
7
R/W
EQ_DATA[15]
0
6
R/W
EQ_DATA[14]
0
5
R/W
EQ_DATA[13]
0
4
R/W
EQ_DATA[12]
0
3
R/W
EQ_DATA[11]
0
2
R/W
EQ_DATA[10]
0
1
R/W
EQ_DATA[9]
0
0
R/W
EQ_DATA[8]
0
EQ_DATA[15:8]:
This register consists of 2-parts: read-only and write-only. Writing this register affects the
second least significant byte of the input-data to the equalization RAM. Reading it returns the
corresponding bits of the RAM location indexed by the RLPS Equalization Indirect Address
register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
302
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 0DBH, 1DBH, 2DBH, 3DBH: RLPS Equalization Indirect Data
Bit
Type
Function
Default
7
R/W
EQ_DATA[7]
0
6
R/W
EQ_DATA[6]
0
5
R/W
EQ_DATA[5]
0
4
R/W
EQ_DATA[4]
0
3
R/W
EQ_DATA[3]
0
2
R/W
EQ_DATA[2]
0
1
R/W
EQ_DATA[1]
0
0
R/W
EQ_DATA[0]
0
EQ_DATA[7:0]:
This register consists of 2-parts: read-only and write-only. Writing this register affects the least
significant byte of the input-data to the equalization RAM. Reading it returns the LSB of the
RAM location indexed by the RLPS Equalization Indirect Address register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
303
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 0DCH, 1DCH, 2DCH, 3DCH: RLPS Equalizer Voltage Reference
Bit
Type
Function
Default
7
Unused
X
6
Unused
X
5
R/W
EQ_VREF[5]
0
4
R/W
EQ_VREF[4]
0
3
R/W
EQ_VREF[3]
0
2
R/W
EQ_VREF[2]
0
1
R/W
EQ_VREF[1]
0
0
R/W
EQ_VREF[0]
0
EQ_VREF[5:0]:
This register sets the voltage reference of the analog receiver’s equalizer. For T1 mode, the
EQ_VREF[5:0] bits must be programmed to 2CH (‘b101100). For E1 mode, the
EQ_VREF[5:0] bits must be programmed to 3DH (‘b111101).
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
304
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 0E0H, 1E0H, 2E0H, 3E0H: PRBS Generator/Checker Control
Bit
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
QRSS
0
Unused
X
Bit 5
Type
R/W
Bit 4
Bit 3
R/W
TINV
0
Bit 2
R/W
RINV
0
Bit 1
R/W
AUTOSYNC
1
Bit 0
R/W
MANSYNC
0
QRSS:
The quasi-random signal source (QRSS) bit enables the zero suppression feature required
when generating a QRSS sequence. When QRSS is a logic 1, a one is forced in the Transmit
stream when the following 14 bit positions are all zeros. When QRSS is a logic 0, the zero
suppression feature is disabled. To generate the QRSS sequence as defined in AT&T 62411,
set the QRSS bit to logic 1 and the PATSEL[1:0] bits of the PRBS Pattern Select register to
‘b01.
TINV:
The TINV bit controls the logical inversion of the generated data stream. When TINV is a
logic 1, the data is inverted. When TINV is a logic 0, the data is not inverted.
RINV:
The RINV bit controls the logical inversion of the received stream before processing. When
RINV is a logic 1, the received data is inverted before being processed by the pattern detector.
When RINV is a logic 0, the data is not inverted
AUTOSYNC:
The AUTOSYNC bit enables the automatic resynchronization of the pattern detector. The
automatic resynchronization is activated when 10 or more bit errors are detected in a fixed 48bit window. When AUTOSYNC is a logic 1, the auto resync feature is enabled. When
AUTOSYNC is a logic 0, the auto sync feature is disabled, and pattern resynchronization is
accomplished using the MANSYNC bit.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
305
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
MANSYNC:
The MANSYNC bit is used to initiate a manual resynchronization of the pattern detector. A
low to high transition on MANSYNC initiates the resynchronization.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
306
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 0E1H, 1E1H, 2E1H, 3E1H: PRBS Checker Interrupt Enable/Status
Bit
Type
Function
Default
Bit 7
R/W
SYNCE
0
Bit 6
R/W
BEE
0
Bit 5
R/W
XFERE
0
Bit 4
R
SYNCV
X
Bit 3
R
SYNCI
X
Bit 2
R
BEI
X
Bit 1
R
XFERI
X
Bit 0
R
OVR
X
SYNCE:
The SYNCE bit enables the generation of an interrupt when the PRBS checker changes
synchronization state. When SYNCE is set to logic 1, the interrupt is enabled.
BEE:
The BEE bit enables the generation of an interrupt when a bit error is detected in the receive
data. When BEE is set to logic 1, the interrupt is enabled.
XFERE:
The XFERE bit enables the generation of an interrupt when an accumulation interval is
completed and new values are stored in the error counter holding registers. When XFERE is
set to logic 1, the interrupt is enabled.
SYNCV:
The SYNCV bit indicates the synchronization state of the PRBS checker. When SYNCV is a
logic 1 the PRBS checker is synchronized (the PRBS checker has observed at least 32
consecutive error free bit periods). When SYNCV is a logic 0, the PRBS checker is out of
sync (the PRBS checker has detected 6 or more bit errors in a 64 bit period window).
SYNCI:
The SYNCI bit indicates that the detector has changed synchronization state since the last
time this register was read. If SYNCI is logic 1, the pattern detector has gained or lost
synchronization at least once. SYNCI is set to logic 0 when this register is read.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
307
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
BEI:
The BEI bit indicates that one or more bit errors have been detected since the last time this
register was read. When BEI is set to logic 1, at least one bit error has been detected. BEI is
set to logic 0 when this register is read.
XFERI:
The XFERI bit indicates that a transfer of the error count has occurred. A logic 1 in this bit
position indicates that the error counter holding registers has been updated. This update is
initiated by writing to one of the PRBS Error Count register locations, or by writing to the
Quadrant PMON Update register. XFERI is set to logic 0 when this register is read.
OVR:
The OVR bit is the overrun status of the Error Count registers. A logic 1 in this bit position
indicates that a previous transfer (indicated by XFERI being logic 1) has not been
acknowledged before the next accumulation interval has occurred and that the contents of the
error counter holding registers have been overwritten. OVR is set to logic 0 when this register
is read.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
308
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 0E2H, 1E2H, 2E2H, 3E2H: PRBS Pattern Select
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
Unused
X
Bit 1
R/W
PATSEL[1]
0
Bit 0
R/W
PATSEL[0]
0
PATSEL[1:0]:
PATSEL[1:0] determines which of the three PRBS patterns are generated and checked for
errors.
PATSEL[1:0]
Pattern
00
2 -1
01
2 -1
10
2 -1
11
Reserved
15
20
11
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
309
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 0E4H, 1E4H, 2E4H, 3E4H: PRBS Error Count #1
Bit
Type
Function
Default
Bit 7
R
ERRCNT[7]
X
Bit 6
R
ERRCNT[6]
X
Bit 5
R
ERRCNT[5]
X
Bit 4
R
ERRCNT[4]
X
Bit 3
R
ERRCNT[3]
X
Bit 2
R
ERRCNT[2]
X
Bit 1
R
ERRCNT[1]
X
Bit 0
R
ERRCNT[0]
X
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
310
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 0E5H, 1E5H, 2E5H, 3E5H: PRBS Error Count #2
Bit
Type
Function
Default
Bit 7
R
ERRCNT[15]
X
Bit 6
R
ERRCNT[14]
X
Bit 5
R
ERRCNT[13]
X
Bit 4
R
ERRCNT[12]
X
Bit 3
R
ERRCNT[11]
X
Bit 2
R
ERRCNT[10]
X
Bit 1
R
ERRCNT[9]
X
Bit 0
R
ERRCNT[8]
X
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
311
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 0E6H, 1E6H, 2E6H, 3E6H: PRBS Error Count #3
Bit
Type
Function
Default
Bit 7
R
ERRCNT[23]
X
Bit 6
R
ERRCNT[22]
X
Bit 5
R
ERRCNT[21]
X
Bit 4
R
ERRCNT[20]
X
Bit 3
R
ERRCNT[19]
X
Bit 2
R
ERRCNT[18]
X
Bit 1
R
ERRCNT[17]
X
Bit 0
R
ERRCNT[16]
X
ERRCNT[23:0]:
ERRCNT[23:0] contain the error counter holding register. The value in this register represents
the number of bit errors that have been accumulated since the last accumulation interval, up
24
to a maximum (saturation) value of 2 -1. Note that bit errors are not accumulated while the
pattern detector is out of sync.
The Error Count registers for each individual PRBS generator/Checker are updated by writing
to any one of the Error count registers. Alternatively, the Error Count registers are updated
with all other quadrant counter registers by writing to the Revision/Chip ID/Quadrant PMON
Update register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
312
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 0F0H, 1F0H, 2F0H, 3F0H: XLPG Line Driver Configuration
Bit
Type
Function
Default
Bit 7
R/W
HIGHZ
1
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
R/W
SCALE[4]
0
Bit 3
R/W
SCALE[3]
0
Bit 2
R/W
SCALE[2]
0
Bit 1
R/W
SCALE[1]
0
Bit 0
R/W
SCALE[0]
0
HIGHZ:
The HIGHZ bit controls if the TXTIP[x] and TXRING[x] outputs are to be tri-stated or not.
When the HIGHZ bit is set to a logic 0, the outputs are enabled. When the HIGHZ bit is set to
a logic 1 then the outputs are put into high impedance. Setting HIGHZ to logic 1 has the same
effect as setting SCALE[4:0] to 00H.
SCALE[4:0]:
The SCALE[4:0] bits control the amplitude of the output waveform. A value of 0 (00H) tristates
the output while the maximum value of 21 (15H) sets the full scale current.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
313
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 0F2H, 1F2H, 2F2H, 3F2H: XLPG Pulse Waveform Storage Write Address
Bit
Type
Function
Default
Bit 7
R/W
SAMPLE[4]
0
Bit 6
R/W
SAMPLE[3]
0
Bit 5
R/W
SAMPLE[2]
0
Bit 4
R/W
SAMPLE[1]
0
Bit 3
R/W
SAMPLE[0]
0
Bit 2
R/W
UI[2]
0
Bit 1
R/W
UI[1]
0
Bit 0
R/W
UI[0]
0
This register is used to program the shape of analog pulses appearing on the TXTIP and TXRING
outputs. Each pulse period is comprised of 24 time samples, represented by the 24 rows in the
waveform table. Sample 0 is transmitted first, and sample 23 is transmitted last. A complete
waveform can consist of up to five Unit Intervals(UI), or bit periods. Refer to Section 12.7 for
complete details.
UI[2:0]:
The pulse waveform write address is composed of a unit interval selector and a sample
selector. The unit interval selector (UI[2:0]) selects which unit interval is being written for a
given sample. There are 5 unit intervals, numbered from 0 to 4. UI[2:0] can take the values
0H, 1H, 2H, 3H and 4H. The values 5H, 6H and 7H are undefined.
SAMPLE[4:0]:
The pulse waveform write address is composed of a unit interval selector and a sample
selector. The sample selector (SAMPLE[4:0]) selects which sample is being written for a
given unit interval. There are 24 samples, numbered from 0 to 23. SAMPLE[4:0] can thus
have any value from 00H to 17H. The values from 18H to 1FH are undefined.
See the Operation section for more details on setting up waveform templates.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
314
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 0F3H, 1F3H, 2F3H, 3F3H: XLPG Pulse Waveform Storage Data
Bit
Type
Bit 7
Function
Default
Unused
X
Bit 6
W
WDAT[6]
X
Bit 5
W
WDAT[5]
X
Bit 4
W
WDAT[4]
X
Bit 3
W
WDAT[3]
X
Bit 2
W
WDAT[2]
X
Bit 1
W
WDAT[1]
X
Bit 0
W
WDAT[0]
X
WDAT[6:0]:
This register allows software to program the contents of any one of the 120 internal waveform
template registers, addressed by the UI[2:0] and SAMPLE[4:0] bits in the Pulse Waveform
Storage Write Address register. When accessing the internal waveform storage registers, the
address of the desired register must first be written to the Indirect Address register (the XLPG
Pulse Waveform Storage Write Address register). Then, by writing the Indirect Data register
(the XLPG Pulse Waveform Storage Data register), the microprocessor can write the data to
the selected write address.
The value written to the internal pulse waveform storage registers is contained in the signed
WDAT[6:0] bits. A signed representation is used (by opposition to a two's complement
representation) to make the programming easier. WDAT[6] is the sign bit, WDAT[5] is the
most significant data bit and WDAT[0] is the least significant data bit. The data value thus can
range from -62 to +63 (-63 is not a valid value due to subsequent conversion into a two's
complement representation).
See the Operation section for more details on setting up custom waveform templates.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
315
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 0F4H, 1F4H, 2F4H, 3F4H: XLPG Configuration #1
Bit
Type
Function
Default
Bit 7
W
TNC[7]
X
Bit 6
W
TNC[6]
X
Bit 5
W
TNC[5]
X
Bit 4
W
TNC[4]
X
Bit 3
W
TNC[3]
X
Bit 2
W
TNC[2]
X
Bit 1
W
TNC[1]
X
Unused
X
Bit 0
TNC[7:1]:
The TNC[7:1] register bits are used to configure the COMET-QUAD transmitters after device
reset. Refer to the XLPG Initialization register for the correct initialization procedure.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
316
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 0F5H, 1F5H, 2F5H, 3F5H: XLPG Configuration #2
Bit
Type
Function
Default
Bit 7
W
TPC[7]
X
Bit 6
W
TPC[6]
X
Bit 5
W
TPC[5]
X
Bit 4
W
TPC[4]
X
Bit 3
W
TPC[3]
X
Bit 2
W
TPC[2]
X
Bit 1
W
TPC[1]
X
Unused
X
Bit 0
TPC[7:1]:
The TPC[7:1] register bits are used to configure the COMET-QUAD transmitters after device
reset. Refer to the XLPG Initialization register for the correct initialization procedure.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
317
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 0F6H, 1F6H, 2F6H, 3F6H: XLPG Initialization
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
R/W
PACT
0
Bit 1
R/W
NACT
0
Bit 0
R/W
FDSB
0
FDSB, NACT, PACT:
The XLPG Configuration registers are used to configure the COMET-QUAD transmitters. The
following four steps must be completed for each quadrant after device reset.
(1)
(2)
(3)
(4)
Write 06H to the XLPG Initialization register
Write 00H to the XLPG Configuration #1 register.
Write 00H to the XLPG Configuration #2 register.
Write 00H to the XLPG Initialization register.
After the sequence has been completed, the XLPG Initialization register bits must remain at
logic 0 until the next time the COMET-QUAD has been reset.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
318
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 0F8H, 1F8H, 2F8H, 3F8H: RLPS Configuration and Status
Bit
Type
Function
Default
Bit 7
R
ALOSI
X
Bit 6
R
ALOSV
X
Bit 5
R/W
ALOSE
0
Bit 4
R/W
SQUELCHE
0
Bit 3
R/W
Reserved
0
Bit 2
Unused
X
Bit 1
Unused
X
Reserved
1
Bit 0
R/W
Reserved:
The Reserved bits must remain at their default state for normal operation.
SQUELCHE:
The output data squelch enable (SQUELCHE) allows control of data squelching in response
to an analog LOS of signal condition. When SQUELCHE is set to logic 1, the recovered data
are forced to all-zeros if the ALOSV register bit is asserted. When SQUELCHE is set to
logic 0, squelching is disabled.
ALOSE:
The loss of signal interrupt enable bit (ALOSE) enables the generation of device level interrupt
on a change of Loss of Signal status. When ALOSE is a logic 1, an interrupt is generated by
asserting INTB low when there is a change of the ALOSV status. When ALOSE is set to
logic 0, interrupts are disabled.
ALOSV:
The loss of signal value bit (ALOSV) indicates the loss of signal alarm state.
ALOSI:
The loss of signal interrupt bit (ALOSI) is a logic 1 whenever the Loss of Signal indicator state
(ALOSV) changes. This bit is cleared when this register is read.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
319
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 0F9H, 1F9H, 2F9H, 3F9H: RLPS ALOS Detection/Clearance Threshold
Bit
Type
Bit 7
Function
Default
Unused
X
Bit 6
R/W
CLR_THR[2]
0
Bit 5
R/W
CLR_THR[1]
0
Bit 4
R/W
CLR_THR[0]
0
Unused
X
Bit 3
Bit 2
R/W
DET_THR[2]
0
Bit 1
R/W
DET_THR[1]
0
Bit 0
R/W
DET_THR[0]
0
Table 56
- ALOS Detection/Clearance Thresholds
THR
Signal level (dB)
9
000
001
010
14.5
20
011
100
101
22
25
30
110
111
31
35
Detection/
Clearance
Clearance
Detection and
Clearance
Detection and
Clearance
Detection
DET_THR[2:0]:
DET_THR[2:0] references one of the threshold settings in Table 56 as the ALOS detection
criteria. If the incoming signal level is less than or equal to that threshold for N consecutive
pulse period, (where N = 16 * the value stored in the RLPS ALOS Detection Period Register)
ALOS is declared and interrupt set. The DET_THR[2:0] bits must be programmed to the
same value as the CLR_THR[2:0] bits.
CLR_THR[2:0]:
CLR_THR[2:0] references one of the threshold settings listed in Table 56 as the ALOS
clearance criteria. ALOS is cleared when the incoming signal level is greater than or equal to
dB below nominal for N consecutive pulse intervals, where N = 16 * CLR_PER stored in the
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
320
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
RLPS ALOS Clearance Period Register. The CLR_THR[2:0] bits must be programmed to the
same value as the DET_THR[2:0] bits.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
321
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 0FAH, 1FAH, 2FAH, 3FAH: RLPS ALOS Detection Period
Bit
Type
Function
Default
Bit 7
R/W
DET_PER[7]
0
Bit 6
R/W
DET_PER[6]
0
Bit 5
R/W
DET_PER[5]
0
Bit 4
R/W
DET_PER[4]
0
Bit 3
R/W
DET_PER[3]
0
Bit 2
R/W
DET_PER[2]
0
Bit 1
R/W
DET_PER[1]
0
Bit 0
R/W
DET_PER[0]
1
DET_PER[7:0]:
This register specifies the time duration that the incoming signal level has to remain below the
detection threshold in order for the ALOS to be issued. This duration is equal to DET_PER *
16 number of pulse intervals, the resulting range is from 16 to 4080 and thus compliant with
all the presently available E1/T1 ALOS detection standards/ recommendations.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
322
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 0FBH, 1FBH, 2FBH, 3FBH: RLPS ALOS Clearance Period
Bit
Type
Function
Default
Bit 7
R/W
CLR_PER[7]
0
Bit 6
R/W
CLR_PER[6]
0
Bit 5
R/W
CLR_PER[5]
0
Bit 4
R/W
CLR_PER[4]
0
Bit 3
R/W
CLR_PER[3]
0
Bit 2
R/W
CLR_PER[2]
0
Bit 1
R/W
CLR_PER[1]
0
Bit 0
R/W
CLR_PER[0]
1
CLR_PER[7:0]:
This register specifies the time duration that the incoming signal level has to remain above the
clearance threshold in order for the ALOS to be cleared. This duration is equal to CLR_PER *
16 number of pulse intervals resulting in a range from 16 to 4080 and thus compliant with all
the presently available E1/T1 ALOS clearance standards/ recommendations.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
323
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 0FCH, 1FCH, 2FCH, 3FCH: RLPS Equalization Indirect Address
Bit
Type
Function
Default
Bit 7
R/W
EQ_ADDR[7]
0
Bit 6
R/W
EQ_ADDR[6]
0
Bit 5
R/W
EQ_ADDR[5]
0
Bit 4
R/W
EQ_ADDR[4]
0
Bit 3
R/W
EQ_ADDR[3]
0
Bit 2
R/W
EQ_ADDR[2]
0
Bit 1
R/W
EQ_ADDR[1]
0
Bit 0
R/W
EQ_ADDR[0]
0
EQ_ADDR [7:0]:
Writing to this register initiates an internal uP access request cycle to the RAM. Depending on
the setting of the RWB bit inside register 0FDH, a read or a write will be performed.
During a write cycle, the indirect data bits located in registers 0D8H to 0DBH (for Quadrant 1)
is written into the RAM. For a read request, the content of the addressed RAM location is
written into registers 0D8H to 0DBH (for Quadrant 1). This register should be the last register
to be written for a uP access. A waiting period of at least three line rate cycles is needed from
when this register is written until the next indirect data bits are written into any of the
respective quadrant’s RLPS Equalization Indirect Data registers (0D8H to 0DBH for quadrant
1, 1D8H to 1DBH for quadrant 2, 2D8H to 2DBH for quadrant 3, 3D8H to 3DBH for quadrant
4).
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
324
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 0FDH, 1FDH, 2FDH, 3FDH: RLPS Equalization Read/WriteB Select
Bit
Type
Function
Default
Bit 7
R/W
RWB
1
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
Unused
X
Bit 1
Unused
X
Bit 0
Unused
X
RWB:
This bit selects the operation to be performed on the RAM: when RWB is ‘1’, a read from the
equalization RAM is requested; when RWB is set to ‘0’, a write to the RAM is desired.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
325
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 0FEH, 1FEH, 2FEH, 3FEH: RLPS Equalizer Loop Status and Control
Bit
Type
Function
Default
Bit 7
R
LOCATION[7]
0
Bit 6
R
LOCATION[6]
0
Bit 5
R
LOCATION[5]
0
Bit 4
R
LOCATION[4]
0
Bit 3
R
LOCATION[3]
0
Bit 2
R
LOCATION[2]
0
Bit 1
R
LOCATION[1]
0
Bit 0
R
LOCATION[0]
0
LOCATION[7:0]:
The LOCATION[7:0] bits indicate the RAM address within the RLPS Equalizer RAM table
internally pointed to by the RLPS analog receiver. The value indicates the amount equalization
and amplification performed on the signal received on RXTIP and RXRING. Reading the value
of this register can aid in debugging of a system. A value of 00H would be typical for short
haul signal transmitted 0 feet. A value of FFH would be typical either for a long haul signal
transmitted over the maximum reach of the receiver or for the case where RXTIP and
RXRING are unconnected.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
326
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register 0FFH, 1FFH, 2FFH, 3FFH: RLPS Equalizer Configuration
Bit
Type
Function
Default
Bit 7
R/W
Reserved
0
Bit 6
R/W
Reserved
0
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
R/W
EQEN
0
Bit 2
R/W
Reserved
0
Bit 1
R/W
Reserved
1
Bit 0
R/W
Reserved
1
Reserved:
These bits must remain in their default state for normal operation.
EQEN:
The Equalizer Enable bit (EQEN) is used to enable the receiver.
Note: This bit defaults to logic 0 and must be set to logic 1 for normal operation.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
327
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
11
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
TEST FEATURES DESCRIPTION
Simultaneously asserting the CSB, RDB and WRB inputs causes all output pins and the data bus
to be held in a high-impedance state. This test feature may be used for board testing.
11.1 JTAG Test Port
The COMET-QUAD JTAG Test Access Port (TAP) allows access to the TAP controller and the 4
TAP registers: instruction, bypass, device identification and boundary scan. Using the TAP, device
input logic levels can be read, device outputs can be forced, the device can be identified and the
device scan path can be bypassed. For more details on the JTAG port, please refer to the
Operations section.
Instruction Register
Length - 3 bits
Instructions
Selected Register
Instruction Codes,
IR[2:0]
EXTEST
Boundary Scan
000
IDCODE
Identification
001
SAMPLE
Boundary Scan
010
BYPASS
Bypass
011
BYPASS
Bypass
100
STCTEST
Boundary Scan
101
BYPASS
Bypass
110
BYPASS
Bypass
111
Identification Register
Length - 32 bits
Version number – 2H for Rev C.
Part Number - 4354H
Manufacturer's identification code - 0CDH
Device Identification - 243540CDH for Rev C
Boundary Scan Register
Length - 114 bits
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
328
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Table 57
Pin/Enable
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- Boundary Scan Register
Scan
Cell Type
Register
Bit
Pin/Enable
Scan
Cell Type
Register
Bit
D_2_OEB
1
ENABLE1
BRFP[4]
58
IO_CELL
D[2]
2
IO_CELL
RSYNC_OEB
59
ENABLE2
1
D_1_OEB
3
ENABLE
D[1]
4
IO_CELL
RSYNC
60
OUT_CELL
PIO_OEB
61
ENABLE1
D_0_OEB
5
ENABLE1
PIO
62
IO_CELL
D[0]
6
IO_CELL
RES[7]
63
IN_CELL
A[0]
7
IN_CELL
RES[8]_OEB
64
ENABLE1
A[1]
8
IN_CELL
RES[8]
65
IO_CELL
A[2]
9
IN_CELL
BRFP_3_OEB
66
ENABLE1
A[3]
10
IN_CELL
BRFP[3]
67
IO_CELL
A[4]
11
IN_CELL
BRSIG_3_OEB
68
ENABLE2
A[5]
12
IN_CELL
BRSIG[3]
69
OUT_CELL
A[6]
13
IN_CELL
BRPCM_3_OEB
70
ENABLE2
A[7]
14
IN_CELL
BRPCM[3]
71
OUT_CELL
A[8]
15
IN_CELL
BRCLK_3_OEB
72
ENABLE1
A[9]
16
IN_CELL
BRCLK[3]
73
IO_CELL
A[10]
17
IN_CELL
RES[2]_OEB
74
ENABLE2
RDB
18
IN_CELL
RES[2]
75
OUT_CELL
WRB
19
IN_CELL
BTFP_3_OEB
76
ENABLE1
CSB
20
IN_CELL
BTFP[3]
77
IO_CELL
ALE
21
IN_CELL
BTSIG[3]
78
IN_CELL
RSTB
22
IN_CELL
BTPCM[3]
79
IN_CELL
INTB_OEB
23
ENABLE2
BTCLK_3_OEB
80
ENABLE1
INTB
24
OUT_CELL
BTCLK[3]
81
IO_CELL
MVBRD_CCSBRD_OEB
82
ENABLE2
MVBRD_CCSBRD
83
OUT_CELL
1
BRCLK_2_OEB
25
ENABLE
BRCLK[2]
26
IO_CELL
2
BRPCM_2_OEB
27
ENABLE
CCSBTD
84
IN_CELL
BRPCM[2]
28
OUT_CELL
MVBTD
85
IN_CELL
BRSIG_2_OEB
29
ENABLE2
CMV8MCLK
86
IN_CELL
BRSIG[2]
30
OUT_CELL
RES[4]_OEB
87
ENABLE2
1
BRFP_2_OEB
31
ENABLE
RES[4]
88
OUT_CELL
BRFP[2]
32
IO_CELL
BTFP_1_OEB
89
ENABLE1
BTCLK_2_OEB
33
ENABLE1
BTFP[1]
90
IO_CELL
BTCLK[2]
34
IO_CELL
BTSIG[1]
91
IN_CELL
BTFP_2_OEB
35
ENABLE1
CASBTD_BTPCM[1]
92
IN_CELL
BTFP[2]
36
IO_CELL
BTCLK_1_OEB
93
ENABLE1
BTPCM[2]
37
IN_CELL
BTCLK[1]
94
IO_CELL
XCLK
38
IN_CELL
CMVFPC
95
IN_CELL
BTSIG[2]
39
IN_CELL
CMVFPB
96
IN_CELL
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
329
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
RES[3]_OEB
40
ENABLE2
BRFP_1_OEB
97
ENABLE1
RES[3]
41
OUT_CELL
BRFP[1]
98
IO_CELL
BRSIG_1_OEB
99
ENABLE2
RES[1]_OEB
42
ENABLE
2
RES[1]
43
OUT_CELL
BRSIG[1]
100
OUT_CELL
CTCLK
44
IN_CELL
CASBRD_BRPCM_1_OE
101
ENABLE2
BTCLK_4_OEB
45
ENABLE1
CASBRD_BRPCM[1]
102
OUT_CELL
BTCLK[4]
46
IO_CELL
BRCLK_1_OEB
103
ENABLE1
BTPCM[4]
47
IN_CELL
BRCLK[1]
104
IO_CELL
BTSIG[4]
48
IN_CELL
D_7_OEB
105
ENABLE1
BTFP_4_OEB
49
ENABLE1
D[7]
106
IO_CELL
BTFP[4]
50
IO_CELL
D_6_OEB
107
ENABLE1
D[6]
108
IO_CELL
D_5_OEB
109
ENABLE1
B
1
BRCLK_4_OEB
51
ENABLE
BRCLK[4]
52
IO_CELL
BRPCM_4_OEB
53
ENABLE2
D[5]
110
IO_CELL
BRPCM[4]
54
OUT_CELL
D_4_OEB
111
ENABLE1
BRSIG_OEB
55
ENABLE2
D[4]
112
IO_CELL
BRSIG[4]
56
OUT_CELL
D_3_OEB
113
ENABLE1
BRFP_4_OEB
57
ENABLE1
D[3]
114
IO_CELL
Notes:
1. These OEB signals, when set low, will set the corresponding bidirectional signal to an output.
2. These OEB signals, when set high, will set the corresponding output to high impedance.
3. D_2_OEB is the first bit in the boundary scan chain scanned in and out. It is closest to TDO in
the scan chain.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
330
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
12
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
OPERATION
12.1 Configuring the COMET-QUAD from Reset
After the RSTB pin is driven low and the CSB pin is driven high concurrently, the COMET-QUAD
will default to the following settings:
Table 58
- Default Settings
Setting
Receiver Section
Transmitter Section
Framing Format
T1 SF
T1 SF
Line Code
B8ZS
AMI
Line interface
Pins RXTIP[x] and RXRING[x]
are uninitialized. The RLPS
Equalizer RAM table must be
programmed for normal
operation.
Pins TXTIP1[x], TXTIP2[x],
TXRING1[x], and TXRING2[x]
are held high impedance.
The EQEN bit in the RLPS
Equalizer Configuration
register defaults to logic 0 but
must be set to logic 1 for
normal operation.
The EQ_VREF[5:0] bits in the
RLPS Equalizer Voltage
Reference register (address
0DCH, 1DCH, 2DCH, and
3DCH) default to 00H but
must be programmed to 2CH
in T1 mode or 3DH in E1
mode for normal operation
System Backplane
Data Link
For normal operation, the
XLPG Configuration #1 and
#2 registers must be
initialized, the XLPG Transmit
Waveform Values must be
programmed, and the XLPG
SCALE[4:0] and HIGHZ
register bits must be
configured.
• 1.544 Mbit/s data rate
• 1.544 Mbit/s data rate
• BRPCM[x], BRSIG[x] active
• BTPCM[x] active
• BRFP[x] and BRCLK[x]
configured as inputs
• BTSIG[x] inactive
disabled
disabled
• BTFP[x] and BTCLK[x]
configured as inputs
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
331
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Setting
Receiver Section
Transmitter Section
Options
• RX-ELST not bypassed
• TX-ELST bypassed
• PMON accumulates OOFs
(not COFAs)
• Signaling alignment disabled
Timing Options
Not applicable
Jitter attenuation enabled, with
the transmit clock referenced
to BTCLK[x]
Diagnostics
All diagnostic modes disabled
All diagnostic modes disabled
• F, CRC, FDL bit bypass
disabled
To configure each quadrant of the COMET-QUAD for ESF framing format, after a reset, the
following registers should be written with the indicated values:
Table 59
- ESF Frame Format
Action
Addr
Data
Effect
Write CDRC Configuration Register
010H,
110H,
210H,
310H
00H
Select B8ZS line code for receiver
Write RX-ELST Configuration
Register
01CH,
11CH,
21CH,
31CH
00H
Select 193-bit frame format.
Write TX-ELST Configuration
Register
020H,
120H,
220H,
320H
00H
Select 193-bit frame format.
Write T1 XBAS Configuration
Register
054H,
154H,
254H,
354H
3XH
Select B8ZS, enable for ESF in
transmitter (bits defined by 'X'
determine the FDL data rate & Zero
Code suppression algorithm used)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
332
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Action
Addr
Data
Effect
Write T1 FRMR Configuration
Register
048H,
148H,
248H,
348H
1XH
or
Select ESF, 2 of 4 OOF threshold
5XH
or
9XH
Write RBOC Enable Register
Select ESF, 2 of 5 OOF threshold
Select ESF, 2 of 6 OOF threshold
(bits defined by 'X' determine the FDL
data rate, should be same as those
written to XBAS)
06AH,
16AH,
26AH,
36AH
00H
or
02H
Enable 8 out of 10 validation
Write ALMI Configuration Register
060H,
160H,
260H,
360H
1XH
Select ESF (bits defined by 'X'
determine the ESF Yellow data rate,
should be same as those written to T1
FRMR)
Write IBCD Configuration Register
04CH,
14CH,
24CH,
34CH
00H
Enable Inband Code detection
Write IBCD Activate Code Register
04EH,
14EH,
24EH,
34EH
08H
Program Loopback Activate Code
pattern
Write IBCD Deactivate Code Register
04FH,
14FH,
24FH,
34FH
44H
Program Loopback Deactivate Code
pattern
Write SIGX Configuration Register
050H,
150H,
250H,
350H
04H
Select ESF
Enable 4 out of 5 validation
To configure each quadrant of the COMET-QUAD for SF framing format, after a reset, the
following registers should be written with the indicated values:
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
333
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
Table 60
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- SF Frame Format
Action
Addr
Data
Effect
Write CDRC Configuration Register
010H,
110H,
210H,
310H
80H
Select AMI line code for receiver
Write RX-ELST Configuration
Register
01CH,
11CH,
21CH,
31CH
00H
Select 193-bit frame format.
Write TX-ELST Configuration
Register
020H,
120H,
220H,
320H
00H
Select 193-bit frame format.
Write T1 XBAS Configuration
Register
054H,
154H,
254H,
354H
00H
Select AMI, enable for SF in
transmitter
Write T1 FRMR Configuration
Register
048H,
148H,
248H,
348H
00H or
Select SF, 2 of 4 OOF threshold
40H or
Select SF, 2 of 5 OOF threshold
80H
Select SF, 2 of 6 OOF threshold
Write ALMI Configuration Register
060H,
160H,
260H,
360H
00H
Select SF
Write IBCD Configuration Register
04CH,
14CH,
24CH,
34CH
00H
Enable Inband Code detection
Write IBCD Activate Code Register
04EH,
14EH,
24EH,
34EH
08H
Program Loopback Activate Code
pattern
Write IBCD Deactivate Code
Register
04FH,
14FH,
24FH,
34FH
44H
Program Loopback Deactivate Code
pattern
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
334
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Action
Addr
Data
Effect
Write SIGX Configuration Register
050H,
150H,
250H,
350H
00H
Select SF
To configure each quadrant of the COMET-QUAD for T1DM framing format, after a reset, the
following registers should be written with the indicated values:
Table 61
- T1DM Frame Format
Action
Addr
Data
Effect
Write CDRC Configuration Register
010H,
110H,
210H,
310H
80H
Select AMI line code for receiver
Write RX-ELST Configuration
Register
01CH,
11CH,
21CH,
31CH
00H
Select 193-bit frame format.
Write TX-ELST Configuration
Register
020H,
120H,
220H,
320H
00H
Select 193-bit frame format.
Write T1 XBAS Configuration
Register
054H,
154H,
254H,
354H
04H or
0CH
Select AMI, enable for T1DM in
transmitter
Write T1 FRMR Configuration
Register
048H,
148H,
248H,
348H
04H
Select T1DM
Write ALMI Configuration Register
060H,
160H,
260H,
360H
04H or
Select T1DM with standard Red
integration
0CH
Select T1DM with alternate Red
integration
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
335
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Action
Addr
Data
Effect
Write IBCD Configuration Register
04CH,
14CH,
24CH,
34CH
00H
Enable Inband Code detection
Write IBCD Activate Code Register
04EH,
14EH,
24EH,
34EH
08H
Program Loopback Activate Code
pattern
Write IBCD Deactivate Code
Register
04FH,
14FH,
24FH,
34FH
44H
Program Loopback Deactivate Code
pattern
Write SIGX Configuration Register
050H,
150H,
250H,
350H
00H
Select T1DM
To configure each quadrant of the COMET-QUAD for E1 framing format, after a reset, the
following registers should be written with the indicated values:
Table 62
- E1 Frame Format
Action
Addr
Data
Effect
Write Global Configuration Register
000H
01H
Select E1 mode.
Write RXCE Receive Data Link 1
Control Register
028H,
128H,
228H,
328H
00H
Disable extraction of T1 data link for
HDLC receiver #1.
Write TXCI Transmit Data Link 1
Control Register
038H,
138H,
238H,
338H
00H
Disable insertion of T1 data link from
HDLC transmitter #1.
Write E1 TRAN Configuration
Register
080H,
180H,
280H,
380H
70H
Enable CRC multiframe generation
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
336
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Action
Addr
Data
Effect
Write E1 FRMR Frame Alignment
Options Register
090H,
190H,
290H,
390H
80H
Enable CRC multiframe search
algorithm
To access the Performance Monitor Registers of quadrant n+1, the following polling sequence
should be used (where n is either 0, 1, 2, or 3):
Table 63
- PMON Polling Sequence
Action
Addr
Offset
Data
Effect
Write PMON Framing Bit Error
Count Register
n59H
00H
Latch performance data into PMON
registers
Read Framing Bit Error Count
n59H
Read Framing bit error count
Read OOF/COFA/FEBE (LSB)
Count Register
n5AH
Read least significant byte out-offrame event count, change of frame
alignment event count if CCOFA bit in
COMET Receive Options Register is
set, or FEBE if E1
Read OOF/COFA/FEBE (MSB)
Count Register
n5BH
Read most significant byte out-offrame event count, change of frame
alignment event count if CCOFA bit in
COMET Receive Options Register is
set, or FEBE if E1
Read BEE/CRCE Count (LSB)
Register
n5CH
Read least significant byte of bit error
event or CRC error count
Read BEE/CRCE Count (MSB)
Register
n5DH
Read most significant byte of bit error
event or CRC error count
Read LCV Count (LSB) Register
n5EH
Read least significant byte of line
code violation count
Read LCV Count (MSB) Register
n5FH
Read most significant byte of line
code violation count
To configure each quadrant of the COMET-QUAD to utilize the internal HDLC transmitter and
receiver for processing the ESF facility data link, the following registers should be written with the
indicated values:
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
337
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
Table 64
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- ESF FDL Processing
Action
Addr
Data
Effect
Write RXCE Receive Data Link 1
Control Register
028H,
128H,
228H,
328H
20H
Select extraction of ESF Facility Data
Link for HDLC receiver #1.
(Quadrant must be set up for ESF
frame format.)
Write TXCI Transmit Data Link 1
Control Register
038H,
138H,
238H,
338H
20H
Select insertion of ESF Facility Data
Link from HDLC transmitter #1.
(Quadrant must be set up for ESF
frame format.)
12.2 Servicing Interrupts
The COMET-QUAD will assert INTB to logic 0 when a condition that is configured to produce an
interrupt occurs. To find which condition caused this interrupt to occur, the procedure outlined
below should be followed:
1. Read the bits of the COMET-QUAD Master Interrupt Source register (0BCH) to identify which
quadrants generated the interrupt. For example, a logic one read in the QUAD[2] bit of the
COMET-QUAD Master Interrupt Source register indicates that quadrant #2 produced the
interrupt.
2. Read the bits of the second level Interrupt Source registers to identify the block within the
quadrant generating the interrupt.
The Interrupt Source registers for quadrant #1 are 007H-009H.
The Interrupt Source registers for quadrant #2 are 107H-109H.
The Interrupt Source registers for quadrant #3 are 207H-209H.
The Interrupt Source registers for quadrant #4 are 307H-309H.
3. Read the third level Interrupt Source registers to identify the interrupt source.
4. Service the interrupt.
5. If the INTB pin is still logic 0, then there are still interrupts to be serviced. Otherwise, all
interrupts have been serviced. Wait for the next assertion of INTB
12.3 Using the Performance Monitoring Features
The PMON blocks are provided for performance monitoring purposes. The PMON blocks within
each T1/E1 Framer slice are used to monitor T1 or E1 performance primitives. The T1/E1 PMON
event counters are of sufficient length so that the probability of counter saturation over a one
second interval is very small (less than 0.001%).
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
338
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
An accumulation interval is initiated by writing to one of the PMON event counter register
addresses or by writing to the Revision/Chip ID/Quadrant PMON Update register. After initiating
an accumulation interval, 3.5 recovered clock periods must be allowed to elapse to permit the
PMON counter values to be properly transferred before the PMON registers may be read.
The odds of any one of the T1/E1 counters saturating during a one second sampling interval go
up as the bit error rate (BER) increases. At some point, the probability of counter saturation
reaches 50%. This point varies, depending upon the framing format and the type of event being
counted. The BER at which the probability of counter saturation reaches 50% is shown for
various counters in Table 65 for E1 mode, and in Table 66 for T1 mode.
Table 65:
- PMON Counter Saturation Limits (E1 mode)
Counter
BER
FER
4.0 X 10-3
CRCE
cannot saturate
FEBE
cannot saturate
Table 66:
- PMON Counter Saturation Limits (T1 mode)
Counter
Format
BER
FER
SF
1.6 x 10-3
ESF
6.4 x 10-2
SF
1.28 x 10-1
ESF
cannot saturate
CRCE
Below these 50% points, the relationship between the BER and the counter event count
(averaged over many one second samples) is essentially linear. Above the 50% point, the
relationship between BER and the average counter event count is highly non-linear due to the
likelihood of counter saturation. The following figures show this relationship for various counters
and framing formats. These graphs can be used to determine the BER, given the average event
count. In general, if the BER is above 10-3, the average counter event count cannot be used to
determine the BER without considering the statistical effect of occasional counter saturation.
Figure 26 illustrates the expected count values for a range of Bit Error Ratios in E1 mode.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
339
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Figure 26:
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- FER Count vs. BER (E1 mode)
Bit Error Rate (x 10 -3 )
9
8
Average Count Over
Many 1 Second Intervals
7
6
5
4
3
2
1
0
0
50
100
150
200
250
Framing Bit Error Count Per Second
Since the maximum number of CRC sub-multiframes that can occur in one second is 1000, the
10-bit FEBE and CRCE counters cannot saturate in one second. Despite this, there is not a linear
relationship between BER and CRC-4 block errors due to the nature of the CRC-4 calculation. At
BERs below 10-4, there tends to be no more than one bit error per sub-multiframe, so the number
of CRC-4 errors is generally equal to the number of bit errors, which is directly related to the BER.
However, at BERs above 10-4, each CRC-4 error is often due to more than one bit error. Thus,
the relationship between BER and CRCE count becomes non-linear above a 10-4 BER. This
must be taken into account when using CRC-4 counts to determine the BER. Since FEBEs are
indications of CRCEs at the far end, and are accumulated identically to CRCEs, the same
explanation holds for the FEBE event counter.
The bit error rate for E1 can be calculated from the one-second PMON CRCE count by the
following equation:
Bit Error Rate = 1 - 10
æ
8
æ
öö
ç log ç 1−
CRCE ÷ ÷
ç
è 8000
ø÷
ç
÷
8*256
çç
÷÷
è
ø
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
340
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Figure 27:
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- CRCE Count vs. BER (E1 mode)
1.00E-02
Bit Error Rate
1.00E-03
1.00E-04
1.00E-05
1.00E-06
1.00E-07
0
200
400
600
800
1000
1200
CRCE
Figure 28 illustrates the expected count values for a range of Bit Error Ratios in T1 mode.
Figure 28:
- FER Count vs. BER (T1 ESF mode)
Bit Error Rate (x 10 -2 )
9
Average Count Over
Many 1 Second Intervals
8
7
6
5
4
3
2
1
0
0
50
100
150
200
250
Framing Bit Error Count Per Second
Since the maximum number of ESF superframes that can occur in one second is 333, the 9-bit
BEE counter cannot saturate in one second in ESF framing format. Despite this, there is not a
linear relationship between BER and BEE count, due to the nature of the CRC-6 calculation. At
BERs below 10-4, there tends to be no more than one bit error per superframe, so the number of
CRC-6 errors is generally equal to the number of bit errors, which is directly related to the BER.
However, at BERs above 10-4, each CRC-6 error is often due to more than one bit error. Thus,
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
341
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
the relationship between BER and BEE count becomes non-linear above a 10-4 BER. This must
be taken into account when using ESF CRC-6 counts to determine the BER.
The bit error rate for T1 ESF can be calculated from the one-second PMON CRCE count by the
following equation:
Bit Error Rate = 1 - 10
Figure 29:
æ
24
æ
öö
ç log ç 1−
BEE ÷ ÷
ç
è 8000
ø÷
÷
ç
24*193
÷÷
çç
ø
è
- CRCE Count vs. BER (T1 ESF mode)
1.00E-02
Bit Error Rate
1.00E-03
1.00E-04
1.00E-05
1.00E-06
1.00E-07
0
50
100
150
200
250
300
350
CRCE
For T1 SF format, the CRCE and FER counts are identical, but the FER counter is smaller and
should be ignored.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
342
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Figure 30:
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- CRCE Count vs. BER (T1 SF mode)
Bit Error Rate (x 10-2 )
20
Average Count Over
Many 1 Second Intervals
18
16
14
12
10
8
6
4
2
0
0
200
400
600
800
1000
1200
Bit Error Event Count Per Second
12.4 Using the Internal HDLC Transmitter
It is important to note that access rate to the HDLC Transmitter (TDPR) registers is limited by the
rate of the XCLK crystal clock input. Consecutive accesses to the TDPR Configuration, TDPR
Interrupt Status/UDR Clear, and TDPR Transmit Data register should be accessed (with respect to
WRB rising edge and RDB falling edge) at a rate no faster than the XCLK clock rate. (In T1 mode
with a 2.048 MHz XCLK reference, accesses should be no faster than XCLK x 193/256.) This time
is used to sample the event, write the FIFO, and update the FIFO status. Instantaneous
variations in the XCLK clock frequency (e.g. jitter in XCLK) must be considered when determining
the procedure used to read and write the TDPR registers.
To properly initialize the transmit HDLC controllers in basic frame alignment mode (FPTYP is
logic 0), multiframe alignment (FPTYP is logic 1) must be configured for at least one multiframe
(i.e., for at least one multiframe period in frame pulse master mode or for at least one input frame
pulse in frame pulse slave mode). After this initialization, the FPTYP can be set to any desired
value.
Upon reset of the COMET-QUAD, the TDPR should be disabled by setting the EN bit in the TDPR
Configuration Register to logic 0 (default value). An HDLC all-ones idle signal will be sent while in
this state. The TDPR is enabled by first disabling the XBOC by programming the XBOC Code
register to an all-ones code and then setting the TDPR EN bit to logic 1. The FIFOCLR bit should
be set and then cleared to initialize the TDPR FIFO. The TDPR is now ready to transmit. To
indicate the timeslot and bits within the timeslot in which the HDLC message should be
transmitted, configure the TXCI Transmit Data Link Control and TXCI Transmit Data Link Bit
Select registers as desired.
To initialize the TDPR, the TDPR Configuration Register must be properly set. If FCS generation
is desired, the CRC bit should be set to logic 1. If the block is to be used in interrupt driven mode,
then interrupts should be enabled by setting the FULLE, OVRE, UDRE, and LFILLE bits in the
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
343
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
TDPR Interrupt Enable register to logic 1. The TDPR operating parameters in the TDPR Upper
Transmit Threshold and TDPR Lower Interrupt Threshold registers should be set to the desired
values. The TDPR Upper Transmit Threshold sets the value at which the TDPR automatically
begins the transmission of HDLC packets, even if no complete packets are in the FIFO.
Transmission will continue until the current packet is transmitted and the number of bytes in the
TDPR FIFO falls to, or below, this threshold level. The TDPR will always transmit all complete
HDLC packets (packets with EOM attached) in its FIFO. Finally, the TDPR can be enabled by
setting the EN bit to logic 1. If no message is sent after the EN bit is set to logic 1, continuous
flags will be sent.
The TDPR can be used in a polled or interrupt driven mode for the transfer of data. In the polled
mode the processor controlling the TDPR must periodically read the TDPR Interrupt Status
register to determine when to write to the TDPR Transmit Data register. In the interrupt driven
mode, the processor controlling the TDPR uses the INTB output, the COMET-QUAD Master
Interrupt Source register, the one of quadrant Interrupt Source #2 registers, and the TDPR
Interrupt Status registers to identify TDPR interrupts which determine when writes can or must be
done to the TDPR Transmit Data register.
Interrupt Driven Mode:
The TDPR automatically transmits a packet once it is completely written into the TDPR FIFO. The
TDPR also begins transmission of bytes once the FIFO level exceeds the programmable Upper
Transmit Threshold. The CRC bit can be set to logic 1 so that the FCS is generated and inserted
at the end of a packet. The TDPR Lower Interrupt Threshold should be set to such a value that
sufficient warning of an underrun is given. The FULLE, LFILLE, OVRE, and UDRE bits are all set
to logic 1 so an interrupt on INTB is generated upon detection of a FIFO full state, a FIFO depth
below the lower limit threshold, a FIFO overrun, or a FIFO underrun. The following procedure
should be followed to transmit HDLC packets:
1. Wait for a complete packet to be transmitted. Once data is available to be transmitted, then
go to step 2.
2. Write the data byte to the TDPR Transmit Data register.
3. If all bytes of the packet have been written to the Transmit Data register, then set the EOM bit
in the TDPR Configuration register to logic 1. Go to step 1.
4. If there are more bytes in the packet to be sent, then go to step 2.
While performing steps 1 to 4, the processor should monitor for interrupts generated by the
TDPR. When an interrupt is detected, the TDPR Interrupt Routine detailed in the following text
should be followed immediately.
The TDPR will force transmission of the packet information when the FIFO depth exceeds the
threshold programmed with the UTHR[6:0] bits in the TDPR Upper Transmit Threshold register.
Unless an error condition occurs, transmission will not stop until the last byte of all complete
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
344
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
packets is transmitted and the FIFO depth is at or below the threshold limit. The user should
watch the FULLI and LFILLI interrupts to prevent overruns and underruns.
TDPR Interrupt Routine:
Upon assertion of INTB, the source of the interrupt must first be identified by reading the COMETQUAD Master Interrupt Source register (0BCH) followed by reading the Interrupt Source #2
registers for the quadrants (008H, 108H, 208H, 308H). Once the source of the interrupt has been
identified as the TDPR in use, then the following procedure should be carried out:
1. Read the TDPR Interrupt Status register.
2. If UDRI=1, then the FIFO has underrun and the last packet transmitted has been corrupted
and needs to be retransmitted. When the UDRI bit transitions to logic 1, one Abort sequence
and continuous flags will be transmitted. The TDPR FIFO is held in reset state. To re-enable
the TDPR FIFO and to clear the underrun, the TDPR Interrupt Status/UDR Clear register
should be written with any value.
3. If OVRI=1, then the FIFO has overflowed. The packet of which the last byte written into the
FIFO belongs to, has been corrupted and must be retransmitted. Other packets in the FIFO
are not affected. Either a timer can be used to determine when sufficient bytes are available
in the FIFO or the user can wait until the LFILLI interrupt is set, indicating that the FIFO depth
is at the lower threshold limit.
If the FIFO overflows on the packet currently being transmitted (packet is greater than 128
bytes long), OVRI is set, an Abort signal is scheduled to be transmitted, the FIFO is emptied,
and then flags are continuously sent until there is data to be transmitted. The FIFO is held in
reset until a write to the TDPR Transmit Data register occurs. This write contains the first byte
of the next packet to be transmitted.
4. If FULLI=1 and FULL=1, then the TDPR FIFO is full and no further bytes can be written.
When in this state, either a timer can be used to determine when sufficient bytes are available
in the FIFO or the user can wait until the LFILLI interrupt is set, indicating that the FIFO depth
is at the lower threshold limit.
If FULLI=1 and FULL=0, then the TDPR FIFO had reached the FULL state earlier, but has
since emptied out some of its data bytes and now has space available in its FIFO for more
data.
5. If LFILLI=1 and BLFILL=1, then the TDPR FIFO depth is below its lower threshold limit. If
there is more data to transmit, then it should be written to the TDPR Transmit Data register
before an underrun occurs. If there is no more data to transmit, then an EOM should be set
at the end of the last packet byte. Flags will then be transmitted once the last packet has
been transmitted.
If LFILLI=1 and BLFILL=0, then the TDPR FIFO had fallen below the lower-threshold state
earlier, but has since been refilled to a level above the lower-threshold level. Note that the
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
345
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
value of UTHR[6:0] must always be greater than the value of LINT[6:0] unless both values are
equal to 00H.
Polling Mode:
The TDPR automatically transmits a packet once it is completely written into the TDPR FIFO. The
TDPR also begins transmission of bytes once the FIFO level exceeds the programmable Upper
Transmit Threshold. The CRC bit can be set to logic 1 so that the FCS is generated and inserted
at the end of a packet. The TDPR Lower Interrupt Threshold, LINT[6:0], should be set to such a
value that sufficient warning of an underrun is given. Note that the value of UTHR[6:0] must
always be greater than the value of LINT[6:0] unless both values are equal to 00H. The FULLE,
LFILLE, OVRE, and UDRE bits are all set to logic 0 since packet transmission is set to work with a
periodic polling procedure. The following procedure should be followed to transmit HDLC
packets:
1. Wait until data is available to be transmitted, then go to step 2.
2. Read the TDPR Interrupt Status register.
3. If FULL=1, then the TDPR FIFO is full and no further bytes can be written. Continue polling
the TDPR Interrupt Status register until either FULL=0 or BLFILL=1. Then, go to either step 4
or 5 depending on implementation preference.
4. If BLFILL=1, then the TDPR FIFO depth is below its lower threshold limit. Write the data into
the TDPR Transmit Data register. Go to step 6.
5. If FULL=0, then the TDPR FIFO has room for at least 1 more byte to be written. Write the
data into the TDPR Transmit Data register. Go to step 6.
6. If more data bytes are to be transmitted in the packet, then go to step 2.
If all bytes in the packet have been sent, then set the EOM bit in the TDPR Configuration register to logic
1. Go to step 1.
12.5 Using the Internal HDLC Receiver
It is important to note that the access rate to the HDLC Receiver (RDLC) registers is limited by the
rate of the XCLK crystal clock input. Consecutive accesses to the RDLC Status and RDLC Data
registers should be accessed (with respect to WRB rising edge and RDB falling edge) at a rate no
faster than 8/10 that of the XCLK clock rate. (In T1 mode with a 2.048 MHz XCLK reference,
accesses should be no faster than XCLK x (193 x 8)/2560.) This time is used by XCLK to sample
the event and update the FIFO status. Instantaneous variations in the XCLK clock frequency (e.g.
jitter in XCLK) must be considered when determining the procedure used to read RDLC registers.
On power up of the system, the RDLC should be disabled by setting the EN bit in the
Configuration Register to logic 0 (default state). The RDLC Interrupt Control register should then
be initialized to enable the INTB output and to select the FIFO buffer fill level at which an interrupt
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
346
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
will be generated. If the INTE bit is not set to logic 1, the RDLC Status register must be
continuously polled to check the interrupt status (INTR) bit.
After the RDLC Interrupt Control register has been written, the RDLC can be enabled at any time
by setting the EN bit in the RDLC Configuration register to logic 1. To indicate the timeslot and bits
within the timeslot in which the HDLC message should be received, configure the RXCE Receive
Data Link Control and RXCE Receive Data Link Bit Select registers as desired. When the RDLC
is enabled, it will assume the link status is idle (all ones) and immediately begin searching for
flags. When the first flag is found, an interrupt will be generated, and a dummy byte will be written
into the FIFO buffer. This is done to provide alignment of link up status with the data read from
the FIFO. When an abort character is received, another dummy byte and link down status is
written into the FIFO. This is done to provide alignment of link down status with the data read
from the FIFO. It is up to the controlling processor to check the COLS bit in the RDLC Status
register for a change in the link status. If the COLS bit is set to logic 1, the FIFO must be emptied
to determine the current link status. The first flag and abort status encoded in the PBS bits is
used to set and clear a Link Active software flag.
When the last byte of a properly terminated packet is received, an interrupt is generated. While
the RDLC Status register is being read the PKIN bit will be logic 1. This can be a signal to the
external processor to empty the bytes remaining in the FIFO or to just increment a number-ofpackets-received count and wait for the FIFO to fill to a programmable level. Once the RDLC
Status register is read, the PKIN bit is cleared to logic 0. If the RDLC Status register is read
immediately after the last packet byte is read from the FIFO, the PBS[2] bit will be logic 1 and the
CRC and non-integer byte status can be checked by reading the PBS[1:0] bits.
When the FIFO fill level is exceeded, an interrupt is generated. The FIFO must be emptied to
remove this source of interrupt.
The RDLC can be used in a polled or interrupt driven mode for the transfer of frame data. In the
polled mode, the processor controlling the RDLC must periodically read the RDLC Status register
to determine when to read the RDLC Data register. In the interrupt driven mode, the processor
controlling the RDLC uses the COMET-QUAD INTB output and the COMET-QUAD Master
Interrupt Source registers to determine when to read the RDLC Data register.
In the case of interrupt driven data transfer from the RDLC to the processor, the INTB output of
the COMET-QUAD is connected to the interrupt input of the processor. The processor interrupt
service routine verifies what block generated the interrupt by reading the COMET-QUAD Master
Interrupt Source register followed by one of the second level master interrupt source registers to
identify one of the 4 HDLC receivers as the interrupt source. Once it has identified that the RDLC
has generated the interrupt, it processes the data in the following order:
1. Read the RDLC Status register. The INTR bit should be logic 1.
2. If OVR = 1, then discard the last frame and go to step 1. Overrun causes a reset of FIFO
pointers. Any packets that may have been in the FIFO are lost.
3. If COLS = 1, then set the EMPTY FIFO software flag.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
347
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
4. If PKIN = 1, increment the PACKET COUNT. If the FIFO is desired to be emptied as soon as
a complete packet is received, set the EMPTY FIFO software flag. If the EMPTY FIFO
software flag is not set, FIFO emptying will delayed until the FIFO fill level is exceeded.
5. Read the RDLC Data register.
6. Read the RDLC Status register.
7. If OVR = 1, then discard last frame and go to step 1. Overrun causes a reset of FIFO
pointers. Any packets that may have been in the FIFO are lost.
8. If COLS = 1, then set the EMPTY FIFO software flag.
9. If PKIN = 1, increment the PACKET COUNT. If the FIFO is desired to be emptied as soon as
a complete packet is received, set the EMPTY FIFO software flag. If the EMPTY FIFO
software flag is not set, FIFO emptying will delayed until the FIFO fill level is exceeded.
10. Start the processing of FIFO data. Use the PBS[2:0] packet byte status bits to decide what is
to be done with the FIFO data.
If PBS[2:0] = 001, discard data byte read in step 5 and set the LINK ACTIVE software
flag.
If PBS[2:0] = 010, discard the data byte read in step 5 and clear the LINK ACTIVE
software flag.
If PBS[2:0] = 1XX, store the last byte of the packet, decrement the PACKET COUNT, and
check the PBS[1:0] bits for CRC or NVB errors before deciding whether or not to keep the
packet.
If PBS[2:0] = 000, store the packet data.
11. If FE = 0 and INTR = 1 or FE = 0 and EMPTY FIFO = 1, go to step 5 else clear the EMPTY
FIFO software flag and leave this interrupt service routine to wait for the next interrupt.
The link state is typically a local software variable. The link state is inactive if the RDLC is
receiving all ones or receiving bit-oriented codes which contain a sequence of eight ones. The
link state is active if the RDLC is receiving flags or data.
If the RDLC data transfer is operating in the polled mode, processor operation is exactly as shown
above for the interrupt driven mode, except that the entry to the service routine is from a timer,
rather than an interrupt.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
348
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Figure 31:
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- Typical Data Frame
BIT: 8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
0
FLAG
Address (high)
(low)
data bytes received
and transferred to
the FIFO Buffer
CONTROL
Frame Check
Sequence
0
1
1
1
1
1
1
0
FLAG
Bit 1 is the first serial bit to be received. When enabled, the primary, secondary and universal
addresses are compared with the high order packet address to determine a match.
Figure 32:
DATA
INT
- Example Multi-Packet Operational Sequence
FF F D D D D F D D D D D D D D DD A FF F F DD D D FF
1
2
3
4 5
6
7
FE
LA
F
A
D
INT
FE
LA
- flag sequence (01111110)
- abort sequence (01111111)
- packet data bytes
- active high interrupt output
- internal FIFO empty status
- state of the LINK ACTIVE software flag
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
349
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Figure 32 shows the timing of interrupts, the state of the FIFO, and the state of the Data Link
relative the input data sequence. The cause of each interrupt and the processing required at each
point is described in the following paragraphs. The actual interrupt signal, INTB, is active low and
will be the inverse of the INT signal shown in figure 16. Also in this example, the programmable
fill level set point is set at 8 bytes by writing this value into the INTC[6:0] bits of the RDLC Interrupt
Control register.
At points 1 and 5 the first flag after all ones or abort is detected. A dummy byte is written in the
FIFO, FE goes low, and an interrupt goes active. When the interrupt is detected by the processor
it reads the dummy byte, the FIFO becomes empty, and the interrupt is removed. The LINK
ACTIVE (LA) software flag is set to logic 1.
At points 2 and 6 the last byte of a packet is detected and the interrupt goes high. When the
interrupt is detected by the processor, it reads the data and status registers until the FIFO
becomes empty. The interrupt is removed as soon as the RDLC Status register is read, since the
FIFO fill level of 8 bytes has not been exceeded. It is possible to store many packets in the FIFO
and empty the FIFO when the FIFO fill level is exceeded. In either case the processor should use
this interrupt to count the number of packets written into the FIFO. The packet count or a
software time-out can be used as a signal to empty the FIFO.
At point 3 the FIFO fill level of 8 bytes is exceeded and interrupt goes high. When the interrupt is
detected by the processor it must read the data and status registers until the FIFO becomes
empty and the interrupt is removed.
At points 4 or 7 an abort character is detected, a dummy byte is written into the FIFO, and the
interrupt goes high. When the interrupt is detected by the processor it must read the data and
status registers until the FIFO becomes empty and the interrupt is removed. The LINK ACTIVE
software flag is cleared.
12.6 T1 Automatic Performance Report Format
Table 67:
Octet No.
1
2
3
4
5
6
7
8
9
10
11
- Performance Report Message Structure and Contents
Bit 8
G3
FE
G3
FE
G3
FE
G3
Bit 7
LV
SE
LV
SE
LV
SE
LV
Bit 6
Bit 5
Bit 4
FLAG
SAPI
TEI
CONTROL
G4
U1
U2
LB
G1
R
G4
U1
U2
LB
G1
R
G4
U1
U2
LB
G1
R
G4
U1
U2
Bit 3
G5
G2
G5
G2
G5
G2
G5
Bit 2
Bit 1
C/R
EA
EA
SL
Nm
SL
Nm
SL
Nm
SL
G6
NI
G6
NI
G6
NI
G6
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
350
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
12
13
14
15
FE
SE
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
LB
G1
R
G2
Nm
NI
FCS
FCS
FLAG
Notes:
1. The order of transmission of the bits is LSB (Bit 1) to MSB (Bit 8).
Table 68:
- Performance Report Message Structure Notes
Octet No.
Octet Contents
Interpretation
1
01111110
Opening LAPD Flag
2
00111000
From CI:
00111010
From carrier: SAPI=14,C/R=1,EA=0
3
00000001
TEI=0,EA=1
4
00000011
Unacknowledged Frame
5,6
Variable
Data for latest second (T')
7,8
Variable
Data for Previous Second(T'-1)
9,10
Variable
Data for earlier Second(T'-2)
11,12
Variable
Data for earlier Second(T'-3)
13,14
Variable
CRC16 Frame Check Sequence
15
01111110
Closing LAPD flag
Table 69:
SAPI=14, C/R=0, EA=0
- Performance Report Message Contents
Bit Value
Interpretation
G1=1
CRC ERROR EVENT =1
G2=1
1<CRC ERROR EVENT ≤5
G3=1
5<CRC ERROR EVENT ≤10
G4=1
10<CRC ERROR EVENT ≤100
G5=1
100<CRC ERROR EVENT ≤319
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
351
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
G6=1
CRC ERROR EVENT ≤ 320
SE=1
Severely Errored Framing Event ≥ 1(FE shall =0)
FE=1
Frame Synchronization Bit Error Event ≥1
(SE shall=0 )
LV=1
Line code violation event ≥ 1
SL=1
Slip Event ≥ 1
LB=1
Payload Loopback Activated
U1,U2=0
Under Study For Synchronization.
R=0
Reserved ( Default Value =0)
NmNI=00,01,10,11
One second Report Modulo 4 Counter
12.7 Using the Transmit Line Pulse Generator
The internal digital-to-analog pulse waveform registers, accessible via the microprocessor bus,
can be used to create a custom waveform. These 120 pulse waveform storage registers are
accessed indirectly through XLPG Pulse Waveform Storage Write Address and XLPG Pulse
Waveform Storage Data register. The values written into the pulse waveform storage registers
correspond to one of 127 quantized levels. 24 samples are output during every transmit clock
cycle.
The waveform being programmed must be done properly in order to meet the various T1 and E1
template specifications. The SCALE[4:0] bits of Line Driver Configuration Register bits are used
to obtain a proper output amplitude.
The following tables contain the waveform values to be programmed for different situations. Table
70 to Table 79 specify waveform values typically used for T1 long haul and short haul
transmission. Table 80 to Table 86 specify waveform values for compliance to the AT&T TR62411
ACCUNET T1.5 pulse template. This is particularly useful where compliance to the jitter
specification of TR62411 is desired. Table 87 and Table 88 specify waveform values for E1
transmission.
Each table describes a waveform that is composed of five columns, representing 5 Unit Intervals
(UIs), or bit periods. At any given time, UI#0 refers to the waveform generated in the current bit
period, UI#1 corresponds to the waveform generated during the previous bit period and UI#2 thru
UI#4 correspond to the waveforms generated in the three bit periods prior to UI#1. The five
columns are conditionally summed together to create the current waveform. Columns are not
added to the current sum if a pulse did not exist in the corresponding UI. This technique allows
each individual waveform to spread over multiple bit periods -- up to 5 bit periods. This is
particularly important in long-haul applications, where the waveform is shaped to concentrate its
energy in the low frequency spectrum, which results in the tails of the pulses being very long.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
352
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
From this perspective, the UI#0 represents the beginning portion of the current waveform, while
UI#1 thru UI#4 represent leftover portions (the "tails") of any preceding waveforms.
The T1 and E1 pulse templates for each quadrant may be programmed via the XLPG Pulse
Waveform Storage Write Address register (0F2H, 1F2H, 2F2H, 3F2H) where the sample number
(Ui#0 – UI#4) and the UI numbers are set and the data content for each quadrant is written to the
XLPG Pulse Waveform Storage Data register (0F3H, 1F3H, 2F3H, 3F3H).
The HIGHZ bit of the quadrant’s XLPG Line Driver Configuration register (0F0H, 1F0H, 2F0H,
3F0H) must be programmed to logic 0 to remove the high impedance state from the TXTIP1[x],
TXTIP2[x], TXRING1[x] and TXRING2[x] Transmit outputs.
Table 70
- T1.102 Transmit Waveform Values for T1 Long Haul (LBO 0 dB):
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
1
00
46
00
00
00
2
0A
45
00
00
00
3
20
43
00
00
00
4
32
41
00
00
00
5
3E
40
00
00
00
6
3D
40
00
00
00
7
3C
00
00
00
00
8
3B
00
00
00
00
9
3A
00
00
00
00
10
39
00
00
00
00
11
39
00
00
00
00
12
38
00
00
00
00
13
37
00
00
00
00
14
36
00
00
00
00
15
30
00
00
00
00
16
10
00
00
00
00
17
49
00
00
00
00
18
51
00
00
00
00
19
50
00
00
00
00
20
4E
00
00
00
00
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
353
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
21
4C
00
00
00
00
22
4A
00
00
00
00
23
48
00
00
00
00
24
47
00
00
00
00
Note: SCALE[4:0] programmed to 0CH.
Table 71
- T1.102 Transmit Waveform Values for T1 Long Haul (LBO 7.5 dB):
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
1
00
10
00
00
00
2
01
0E
00
00
00
3
02
0C
00
00
00
4
04
0A
00
00
00
5
08
08
00
00
00
6
0C
06
00
00
00
7
10
04
00
00
00
8
16
02
00
00
00
9
1A
01
00
00
00
10
1E
00
00
00
00
11
22
00
00
00
00
12
26
00
00
00
00
13
2A
00
00
00
00
14
2B
00
00
00
00
15
2C
00
00
00
00
16
2D
00
00
00
00
17
2C
00
00
00
00
18
28
00
00
00
00
19
24
00
00
00
00
20
20
00
00
00
00
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
354
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
21
1C
00
00
00
00
22
18
00
00
00
00
23
14
00
00
00
00
24
12
00
00
00
00
Note: SCALE[4:0] programmed to 08H.
Table 72
- T1.102 Transmit Waveform Values for T1 Long Haul (LBO 15 dB):
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
1
00
2A
09
01
00
2
00
28
08
01
00
3
00
26
08
01
00
4
00
24
07
01
00
5
01
22
07
01
00
6
02
20
06
01
00
7
04
1E
06
01
00
8
07
1C
05
00
00
9
0A
1B
05
00
00
10
0D
19
05
00
00
11
10
18
04
00
00
12
14
16
04
00
00
13
18
15
04
00
00
14
1B
13
03
00
00
15
1E
12
03
00
00
16
21
10
03
00
00
17
24
0F
03
00
00
18
27
0D
03
00
00
19
2A
0D
02
00
00
20
2D
0B
02
00
00
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
355
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
21
30
0B
02
00
00
22
30
0A
02
00
00
23
2E
0A
02
00
00
24
2C
09
02
00
00
Note: SCALE[4:0] programmed to 03H.
Table 73
- T1.102 Transmit Waveform Values for T1 Long Haul (LBO 22.5 dB):
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
1
00
1F
16
06
01
2
00
20
15
05
01
3
00
21
15
05
01
4
00
22
14
05
01
5
00
22
13
04
00
6
00
23
12
04
00
7
01
23
12
04
00
8
01
24
11
03
00
9
01
23
10
03
00
10
02
23
10
03
00
11
03
22
0F
03
00
12
05
22
0E
03
00
13
07
21
0E
02
00
14
09
20
0D
02
00
15
0B
1E
0C
02
00
16
0E
1D
0C
02
00
17
10
1B
0B
02
00
18
13
1B
0A
02
00
19
15
1A
0A
02
00
20
17
19
09
01
00
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
356
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
21
19
19
08
01
00
22
1B
18
08
01
00
23
1D
17
07
01
00
24
1E
17
06
01
00
Note: SCALE[4:0] programmed to 02H.
Table 74
- T1.102 Transmit Waveform Values for T1 Short Haul (0 - 110 ft.):
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
1
00
46
00
00
00
2
0A
45
00
00
00
3
20
43
00
00
00
4
3D
41
00
00
00
5
3D
40
00
00
00
6
3C
40
00
00
00
7
3C
00
00
00
00
8
3B
00
00
00
00
9
3A
00
00
00
00
10
39
00
00
00
00
11
39
00
00
00
00
12
38
00
00
00
00
13
37
00
00
00
00
14
36
00
00
00
00
15
30
00
00
00
00
16
10
00
00
00
00
17
58
00
00
00
00
18
53
00
00
00
00
19
50
00
00
00
00
20
4E
00
00
00
00
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
357
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
21
4C
00
00
00
00
22
4A
00
00
00
00
23
48
00
00
00
00
24
47
00
00
00
00
Note: SCALE[4:0] programmed to 0DH.
Table 75
- T1.102 Transmit Waveform Values for T1 Short Haul (110 – 220 ft.):
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
1
00
45
00
00
00
2
0A
44
00
00
00
3
33
42
00
00
00
4
33
41
00
00
00
5
33
40
00
00
00
6
33
40
00
00
00
7
30
00
00
00
00
8
2F
00
00
00
00
9
2E
00
00
00
00
10
2D
00
00
00
00
11
2C
00
00
00
00
12
2B
00
00
00
00
13
2A
00
00
00
00
14
29
00
00
00
00
15
19
00
00
00
00
16
5A
00
00
00
00
17
54
00
00
00
00
18
50
00
00
00
00
19
4E
00
00
00
00
20
4C
00
00
00
00
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
358
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
21
4B
00
00
00
00
22
48
00
00
00
00
23
48
00
00
00
00
24
47
00
00
00
00
Note: SCALE[4:0] programmed to 11H.
Table 76
- T1.102 Transmit Waveform Values for T1 Short Haul (220 – 330 ft.):
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
1
00
45
00
00
00
2
0A
44
00
00
00
3
36
43
00
00
00
4
36
41
00
00
00
5
34
40
00
00
00
6
34
40
00
00
00
7
30
00
00
00
00
8
2F
00
00
00
00
9
2E
00
00
00
00
10
2D
00
00
00
00
11
2C
00
00
00
00
12
2B
00
00
00
00
13
2A
00
00
00
00
14
29
00
00
00
00
15
23
00
00
00
00
16
4A
00
00
00
00
17
60
00
00
00
00
18
55
00
00
00
00
19
53
00
00
00
00
20
50
00
00
00
00
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
359
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
21
4E
00
00
00
00
22
4C
00
00
00
00
23
48
00
00
00
00
24
47
00
00
00
00
Note: SCALE[4:0] programmed to 12H.
Table 77
- T1.102 Transmit Waveform Values for T1 Short Haul (330 – 440 ft.):
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
1
00
46
00
00
00
2
0A
45
00
00
00
3
3A
43
00
00
00
4
3A
41
00
00
00
5
37
40
00
00
00
6
37
40
00
00
00
7
2F
00
00
00
00
8
2E
00
00
00
00
9
2D
00
00
00
00
10
2C
00
00
00
00
11
2B
00
00
00
00
12
2A
00
00
00
00
13
29
00
00
00
00
14
28
00
00
00
00
15
19
00
00
00
00
16
4A
00
00
00
00
17
64
00
00
00
00
18
57
00
00
00
00
19
53
00
00
00
00
20
4F
00
00
00
00
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
360
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
21
4C
00
00
00
00
22
4B
00
00
00
00
23
48
00
00
00
00
24
47
00
00
00
00
Note: SCALE[4:0] programmed to 13H.
Table 78
- T1.102 Transmit Waveform Values for T1 Short Haul (440 – 550 ft.):
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
1
00
46
00
00
00
2
0A
45
00
00
00
3
3E
43
00
00
00
4
3E
41
00
00
00
5
3E
40
00
00
00
6
30
40
00
00
00
7
30
00
00
00
00
8
2B
00
00
00
00
9
2A
00
00
00
00
10
29
00
00
00
00
11
28
00
00
00
00
12
27
00
00
00
00
13
26
00
00
00
00
14
24
00
00
00
00
15
19
00
00
00
00
16
4A
00
00
00
00
17
78
00
00
00
00
18
57
00
00
00
00
19
53
00
00
00
00
20
4F
00
00
00
00
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
361
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
21
4C
00
00
00
00
22
4B
00
00
00
00
23
48
00
00
00
00
24
47
00
00
00
00
Note: SCALE[4:0] programmed to 15H.
Table 79
- T1.102 Transmit Waveform Values for T1 Short Haul (550 – 660 ft.):
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
1
00
46
00
00
00
2
0A
45
00
00
00
3
3F
43
00
00
00
4
3F
41
00
00
00
5
3F
40
00
00
00
6
3F
40
00
00
00
7
2E
00
00
00
00
8
2E
00
00
00
00
9
2A
00
00
00
00
10
29
00
00
00
00
11
28
00
00
00
00
12
27
00
00
00
00
13
26
00
00
00
00
14
25
00
00
00
00
15
24
00
00
00
00
16
4A
00
00
00
00
17
7F
00
00
00
00
18
63
00
00
00
00
19
53
00
00
00
00
20
51
00
00
00
00
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
362
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
21
4C
00
00
00
00
22
4B
00
00
00
00
23
48
00
00
00
00
24
47
00
00
00
00
Note: SCALE[4:0] programmed to 15H.
Table 80
- TR62411 Transmit Waveform Values for T1 Long Haul (LBO 0 dB):
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
1
00
00
00
00
00
2
0A
00
00
00
00
3
20
00
00
00
00
4
32
00
00
00
00
5
3E
00
00
00
00
6
3D
00
00
00
00
7
3C
00
00
00
00
8
3B
00
00
00
00
9
3A
00
00
00
00
10
39
00
00
00
00
11
39
00
00
00
00
12
38
00
00
00
00
13
37
00
00
00
00
14
36
00
00
00
00
15
30
00
00
00
00
16
10
00
00
00
00
17
4F
00
00
00
00
18
4C
00
00
00
00
19
4A
00
00
00
00
20
46
00
00
00
00
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
363
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
21
44
00
00
00
00
22
42
00
00
00
00
23
00
00
00
00
00
24
00
00
00
00
00
Note: SCALE[4:0] programmed to 0CH.
Table 81
- TR62411 Transmit Waveform Values for T1 Short Haul (0 - 110 ft.):
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
1
00
00
00
00
00
2
0A
00
00
00
00
3
20
00
00
00
00
4
3D
00
00
00
00
5
3D
00
00
00
00
6
3C
00
00
00
00
7
3C
00
00
00
00
8
3B
00
00
00
00
9
3A
00
00
00
00
10
39
00
00
00
00
11
39
00
00
00
00
12
38
00
00
00
00
13
37
00
00
00
00
14
36
00
00
00
00
15
30
00
00
00
00
16
10
00
00
00
00
17
4C
00
00
00
00
18
4A
00
00
00
00
19
48
00
00
00
00
20
46
00
00
00
00
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
364
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
21
44
00
00
00
00
22
42
00
00
00
00
23
00
00
00
00
00
24
00
00
00
00
00
Note: SCALE[4:0] programmed to 0DH.
Table 82
- TR62411 Transmit Waveform Values for T1 Short Haul (110 – 220 ft.):
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
1
00
00
00
00
00
2
0A
00
00
00
00
3
33
00
00
00
00
4
33
00
00
00
00
5
33
00
00
00
00
6
33
00
00
00
00
7
30
00
00
00
00
8
2F
00
00
00
00
9
2E
00
00
00
00
10
2D
00
00
00
00
11
2C
00
00
00
00
12
2B
00
00
00
00
13
2A
00
00
00
00
14
29
00
00
00
00
15
19
00
00
00
00
16
5A
00
00
00
00
17
54
00
00
00
00
18
50
00
00
00
00
19
48
00
00
00
00
20
46
00
00
00
00
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
365
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
21
44
00
00
00
00
22
42
00
00
00
00
23
00
00
00
00
00
24
00
00
00
00
00
Note: SCALE[4:0] programmed to 11H.
Table 83
- TR62411 Transmit Waveform Values for T1 Short Haul (220 – 330 ft.):
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
1
00
00
00
00
00
2
0A
00
00
00
00
3
36
00
00
00
00
4
36
00
00
00
00
5
34
00
00
00
00
6
34
00
00
00
00
7
30
00
00
00
00
8
2F
00
00
00
00
9
2E
00
00
00
00
10
2D
00
00
00
00
11
2C
00
00
00
00
12
2B
00
00
00
00
13
2A
00
00
00
00
14
29
00
00
00
00
15
23
00
00
00
00
16
4A
00
00
00
00
17
60
00
00
00
00
18
55
00
00
00
00
19
48
00
00
00
00
20
46
00
00
00
00
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
366
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
21
44
00
00
00
00
22
42
00
00
00
00
23
00
00
00
00
00
24
00
00
00
00
00
Note: SCALE[4:0] programmed to 12H.
Table 84
- TR62411 Transmit Waveform Values for T1 Short Haul (330 – 440 ft.):
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
1
00
00
00
00
00
2
0A
00
00
00
00
3
3A
00
00
00
00
4
3A
00
00
00
00
5
37
00
00
00
00
6
37
00
00
00
00
7
2F
00
00
00
00
8
2E
00
00
00
00
9
2D
00
00
00
00
10
2C
00
00
00
00
11
2B
00
00
00
00
12
2A
00
00
00
00
13
29
00
00
00
00
14
28
00
00
00
00
15
19
00
00
00
00
16
4A
00
00
00
00
17
64
00
00
00
00
18
57
00
00
00
00
19
48
00
00
00
00
20
46
00
00
00
00
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
367
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
21
44
00
00
00
00
22
42
00
00
00
00
23
00
00
00
00
00
24
00
00
00
00
00
Note: SCALE[4:0] programmed to 13H.
Table 85
- TR62411 Transmit Waveform Values for T1 Short Haul (440 – 550 ft.):
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
1
00
00
00
00
00
2
0A
00
00
00
00
3
3E
00
00
00
00
4
3E
00
00
00
00
5
3E
00
00
00
00
6
30
00
00
00
00
7
30
00
00
00
00
8
2B
00
00
00
00
9
2A
00
00
00
00
10
29
00
00
00
00
11
28
00
00
00
00
12
27
00
00
00
00
13
26
00
00
00
00
14
24
00
00
00
00
15
19
00
00
00
00
16
4A
00
00
00
00
17
78
00
00
00
00
18
57
00
00
00
00
19
4A
00
00
00
00
20
46
00
00
00
00
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
368
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
21
44
00
00
00
00
22
42
00
00
00
00
23
00
00
00
00
00
24
00
00
00
00
00
Note: SCALE[4:0] programmed to 15H.
Table 86
- TR62411 Transmit Waveform Values for T1 Short Haul (550 – 660 ft.):
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
1
00
00
00
00
00
2
0A
00
00
00
00
3
3F
00
00
00
00
4
3F
00
00
00
00
5
3F
00
00
00
00
6
3F
00
00
00
00
7
2E
00
00
00
00
8
2E
00
00
00
00
9
2A
00
00
00
00
10
29
00
00
00
00
11
28
00
00
00
00
12
27
00
00
00
00
13
26
00
00
00
00
14
25
00
00
00
00
15
24
00
00
00
00
16
4A
00
00
00
00
17
7F
00
00
00
00
18
63
00
00
00
00
19
5F
00
00
00
00
20
50
00
00
00
00
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
369
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
21
49
00
00
00
00
22
44
00
00
00
00
23
42
00
00
00
00
24
00
00
00
00
00
Note: SCALE[4:0] programmed to 15H.
Table 87
- Transmit Waveform Values for E1 120 Ohm:
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
1
00
00
00
00
00
2
00
00
00
00
00
3
0A
00
00
00
00
4
3F
00
00
00
00
5
3F
00
00
00
00
6
39
00
00
00
00
7
38
00
00
00
00
8
36
00
00
00
00
9
36
00
00
00
00
10
35
00
00
00
00
11
35
00
00
00
00
12
35
00
00
00
00
13
35
00
00
00
00
14
35
00
00
00
00
15
2D
00
00
00
00
16
00
00
00
00
00
17
00
00
00
00
00
18
00
00
00
00
00
19
00
00
00
00
00
20
00
00
00
00
00
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
370
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
21
00
00
00
00
00
22
00
00
00
00
00
23
00
00
00
00
00
24
00
00
00
00
00
Note: SCALE[4:0] programmed to 0CH.
Table 88
- Transmit Waveform Values for E1 75 Ohm:
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
1
00
00
00
00
00
2
00
00
00
00
00
3
0A
00
00
00
00
4
3E
00
00
00
00
5
3E
00
00
00
00
6
3E
00
00
00
00
7
3C
00
00
00
00
8
3C
00
00
00
00
9
3A
00
00
00
00
10
3A
00
00
00
00
11
3A
00
00
00
00
12
3A
00
00
00
00
13
3A
00
00
00
00
14
3A
00
00
00
00
15
35
00
00
00
00
16
00
00
00
00
00
17
00
00
00
00
00
18
00
00
00
00
00
19
00
00
00
00
00
20
00
00
00
00
00
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
371
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
21
00
00
00
00
00
22
00
00
00
00
00
23
00
00
00
00
00
24
00
00
00
00
00
Note: SCALE[4:0] programmed to 0CH.
12.8 Using the Line Receiver
The line receivers must be properly initialized for normal operation. Initialization consists of a three
step procedure.
Step 1 – Line Receiver Configuration
The following registers should be configured to the desired mode of operation for each quadrant:
Table 89
- Line Receiver Configuration Registers
Register Address
Register Description
nF8H
RLPS Configuration and Status
nF9H
RLPS ALOS Detection / Clearance Threshold
nFAH
RLPS ALOS Detection Period
nFBH
RLPS ALOS Clearance Time
nFFH
RLPS Equalizer Configuration
nDCH
RLPS Equalizer Voltage Reference
Note: n = 0,1,2,3 where n = 0 denotes quadrant 1
Note: The following registers must be modified for normal operation.
•
RLPS Equalizer Configuration: EQEN must be set to 1.
•
RLPS Equalizer Voltage Reference: EQ_VREF[5:0] must be set to 2CH (T1 mode) or
3DH (E1 mode)
Step 2 – Equalizer RAM Table Programming
The line receiver utilizes “Equalizer RAM Tables” to recover signals that have been attenuated by
a length of cable. Two tables are included in this document for T1/J1 and E1 operation. Table 92
is used for T1/J1 and Table 93 is used for E1.
The line receiver equalizer RAM contents are programmed via indirect register accesses to the
following registers.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
372
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Table 90
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- Line Receiver RAM Programming Registers
Register Address
Register Description
nD8H
RLPS Equalizer Indirect Data[31:24]
nD9H
RLPS Equalizer Indirect Data[23:16]
nDAH
RLPS Equalizer Indirect Data[15:8]
nDBH
RLPS Equalizer Indirect Data[7:0]
nFDH
RLPS Equalization RAM Read/WriteB Select
nFCH
RLPS Equalization Indirect Address
Note: n = 0,1,2,3 where n = 0 denotes quadrant 1
A typical programming sequence follows. This programming sequence is repeated for each of the
256 Equalizer RAM Addresses.
1. Write the “Contents” of the Equalizer RAM table to the corresponding RLPS Indirect Data
register.
WRITE nD8H
<Content[31:24] of the Equalizer RAM table>
WRITE nD9H
<Content[23:16] of the Equalizer RAM table>
WRITE nDAH
<Content[15:8] of the Equalizer RAM table>
WRITE nDBH
<Content[7:0] of the Equalizer RAM table>
2. Identify this operation as an indirect write using the RLPS RAM Read/WriteB Select
register. (00H corresponds to a write.)
WRITE nFDH 00H
3. Perform the write operation using the RLPS Equalization Indirect Address register.
WRITE nFCH
<RAM Address of the Equalizer RAM table >
4. Pause and then repeat the sequence for the following table entry.
PAUSE
<wait 3 line rate clock cycles>
Step 3 – Line Receiver Optimizations
In order to ensure optimal receiver sensitivity under all operating conditions, the code sequence in
Table 91 below must be executed after programming or reprogramming the RLPS Equalization
RAM table as discussed in Step 2 above. All data entries in the below table are writes to the
identified register address.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
373
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
Table 91
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- Sequence to follow RLPS RAM programming
Step
Data Value
Register Address
Binary
Hex
1
00000000
00H
4D7H
2
00000000
00H
4F1H
3
00000000
00H
5F1H
4
00000000
00H
6F1H
5
00000000
00H
7F1H
6
00000000
00H
4F9H
7
00000000
00H
5F9H
8
00000000
00H
6F9H
9
00000000
00H
7F9H
10
00000100
04H
4F9H
11
00001001
09H
4FBH
12
00100000
20H
00BH
Wait 1 ms
13
14
00000000
00H
4F9H
15
00000000
00H
00BH
16
00000100
04H
5F9H
17
00001001
09H
5FBH
18
00100000
20H
00BH
Wait 1 ms
19
20
00000000
00H
5F9H
21
00000000
00H
00BH
22
00000100
04H
6F9H
23
00001001
09H
6FBH
24
00100000
20H
00BH
Wait 1 ms
25
26
00000000
00H
6F9H
27
00000000
00H
00BH
28
00000100
04H
7F9H
29
00001001
09H
7FBH
30
00100000
20H
00BH
Wait 1 ms
31
32
00000000
00H
7F9H
33
00000000
00H
00BH
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
374
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Table 92
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- RLPS Equalizer RAM Table (T1 mode)
RAM
Address
Content
(MSB..LSB)
RAM
Address
Content
(MSB..LSB)
0D
1D
2D
3D
4D
5D
6D
7D
8D
9D
10D
11D
12D
13D
14D
15D
16D
17D
18D
19D
20D
21D
22D
23D
24D
25D
26D
27D
28D
29D
30D
31D
32D
33D
34D
35D
36D
37D
38D
03 FE 18 40
03 FE 18 40
03 F6 18 40
03 F6 18 40
03 EE 18 40
03 EE 18 40
03 E6 18 40
03 E6 18 40
03 DE 18 40
0B DE 18 40
0B D6 18 40
0B D6 18 40
0B CE 18 40
0B CE 18 40
0B C6 18 40
0B C6 18 40
0B BE 18 40
0B BE 18 40
0B B6 18 40
0B B6 18 40
0B AE 18 40
0B AE 18 40
13 AE 18 40
13 AE 18 40
13 A6 18 40
13 A6 28 40
13 A6 28 40
13 A6 28 40
1B A6 28 40
1B A6 28 40
1B 9E 28 40
1B 9E 38 40
1B 9E 38 40
1B 9E 38 40
23 96 38 40
23 96 38 40
23 96 38 40
23 96 48 40
23 96 48 40
128D
129D
130D
131D
132D
133D
134D
135D
136D
137D
138D
139D
140D
141D
142D
143D
144D
145D
146D
147D
148D
149D
150D
151D
152D
153D
154D
155D
156D
157D
158D
159D
160D
161D
162D
163D
164D
165D
166D
86 4C D1 C0
86 4C D1 C0
86 4C D1 C0
8E 4C B2 40
8E 4C B2 40
8E 4C B2 40
8E 4C B2 40
8E 4C B2 40
8E 4C B2 40
96 4C C2 40
96 4C C2 40
96 4C C2 40
9E 4C D2 40
9E 4C D2 40
9E 4C D2 40
A6 4C D2 40
A6 4C D2 40
A6 4C D2 40
A6 4C E2 40
A6 4C E2 40
A6 4C E2 40
A6 4C F2 40
A6 4C F2 40
A6 4C F2 40
A6 4C F2 40
A6 4C F2 40
A6 4C F2 40
B6 4C E2 C0
B6 4C E2 C0
B6 4C E2 C0
BE 4C F2 C0
BE 4C F2 C0
BE 4C F2 C0
BE 4D 02 C0
BE 4D 02 C0
BE 4D 02 C0
BE 4D 12 C0
BE 4D 12 C0
BE 4D 12 C0
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
375
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
39D
40D
41D
42D
43D
44D
45D
46D
47D
48D
49D
50D
51D
52D
53D
54D
55D
56D
57D
58D
59D
60D
61D
62D
63D
64D
65D
66D
67D
68D
69D
70D
71D
72D
73D
74D
75D
76D
77D
78D
79D
80D
81D
23 96 48 40
23 96 58 40
23 96 58 40
23 96 58 40
2B 96 38 C0
2B 96 38 C0
2B 96 38 C0
33 8E 38 C0
33 8E 38 C0
33 8E 38 C0
37 8E 48 C0
37 8E 48 C0
37 86 48 C0
37 86 48 C0
37 86 58 C0
37 86 58 C0
3F 86 54 C0
3F 86 54 C0
3F 7E 54 C0
47 7E 54 C0
47 7E 54 C0
47 76 54 C0
47 76 64 C0
47 76 64 C0
47 76 64 C0
47 76 74 C0
47 76 74 C0
47 76 74 C0
47 76 74 C0
47 76 74 C0
47 76 74 C0
4F 76 65 40
4F 76 65 40
4F 76 65 40
57 76 75 40
57 76 75 40
5F 6E 75 40
5F 6E 75 40
67 6E 85 40
67 6E 85 40
67 6E 85 40
67 6E 95 40
67 6E 95 40
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
167D
168D
169D
170D
171D
172D
173D
174D
175D
176D
177D
178D
179D
180D
181D
182D
183D
184D
185D
186D
187D
188D
189D
190D
191D
192D
193D
194D
195D
196D
197D
198D
199D
200D
201D
202D
203D
204D
205D
206D
207D
208D
209D
C6 4D 12 C0
C6 4D 12 C0
C6 4D 12 C0
C6 4D 12 C0
C6 4D 12 C0
C6 4D 12 C0
CE 4D 22 C0
CE 4D 22 C0
CE 4D 22 C0
CE 4D 22 C0
CE 4D 22 C0
CE 4D 22 C0
CE 4D 22 C0
CE 4D 22 C0
CE 4D 22 C0
CE 4D 32 C0
CE 4D 32 C0
CE 4D 32 C0
CD 4D 22 C0
CD 4D 22 C0
CD 4D 22 C0
D5 4C E3 40
D5 4C E3 40
D5 4C F3 40
D5 4C F3 40
D5 4D 03 40
D5 4D 03 40
D5 4D 13 40
D5 4D 13 40
D5 4D 23 40
D5 4D 23 40
D5 4D 33 40
D5 4D 33 40
DD 45 13 40
DD 45 13 40
DD 45 13 40
DD 45 23 40
DD 45 23 40
DD 45 23 40
DD 45 33 40
DD 45 33 40
DD 45 33 40
E5 3D 23 40
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
376
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
82D
83D
84D
85D
86D
87D
88D
89D
90D
91D
92D
93D
94D
95D
96D
97D
98D
99D
100D
101D
102D
103D
104D
105D
106D
107D
108D
109D
110D
111D
112D
113D
114D
115D
116D
117D
118D
119D
120D
121D
122D
123D
124D
67 6E 95 40
67 66 95 40
67 66 95 40
67 66 A5 40
67 66 A5 40
67 5E 95 40
67 5E 95 40
77 5E 75 C0
77 5E 75 C0
77 5E 85 C0
77 5E 85 C0
77 5E 95 C0
77 5E 95 C0
77 5E A5 C0
77 5E A5 C0
77 5E B5 C0
7F 5E B5 C0
7F 5E C5 C0
7F 5E C5 C0
7F 5C A9 C0
7F 5C A9 C0
7F 5C A9 C0
7F 5C B9 C0
7F 5C B9 C0
7F 5C B9 C0
7F 5C A5 C0
7F 5C A5 C0
7F 5C A5 C0
7F 5C B5 C0
7F 54 A5 C0
7F 54 B5 C0
7F 54 C5 C0
7F 54 C5 C0
7F 54 C5 C0
7F 54 B1 C0
7F 54 B1 C0
7F 54 B1 C0
7F 54 B1 C0
7F 54 B1 C0
86 54 D1 C0
86 54 D1 C0
86 54 D1 C0
86 54 D1 C0
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
210D
211D
212D
213D
214D
215D
216D
217D
218D
219D
220D
221D
222D
223D
224D
225D
226D
227D
228D
229D
230D
231D
232D
233D
234D
235D
236D
237D
238D
239D
240D
241D
242D
243D
244D
245D
246D
247D
248D
249D
250D
251D
252D
E5 3D 23 40
E5 3D 23 40
E5 3D 33 40
E5 3D 33 40
E5 3D 33 40
E5 3D 43 40
E5 3D 43 40
E5 3D 43 40
E5 3D 53 40
E5 3D 53 40
E5 3D 53 40
EC 35 23 40
EC 35 33 40
EC 35 33 40
EC 35 43 40
EC 35 43 40
EC 35 43 40
EC 35 53 40
EC 35 53 40
EC 35 53 40
EC 35 63 40
EC 35 63 40
EC 35 63 40
EC 35 73 40
EC 35 73 40
EC 35 73 40
EC 2D 53 40
EC 2D 53 40
EC 2D 53 40
F4 2D 23 C0
F4 2D 23 C0
F4 2D 33 C0
FC 2D 33 C0
FC 2D 43 C0
FC 2D 43 C0
FC 25 43 C0
FC 25 43 C0
FC 25 43 C0
FC 25 43 C0
FC 1D 43 C0
FC 1D 43 C0
FC 1D 43 C0
FC 1D 43 C0
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
377
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
125D
126D
127D
Table 93
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
86 54 D1 C0
86 4C C1 C0
86 4C C1 C0
253D
254D
255D
FC 15 43 C0
FC 15 43 C0
FC 15 43 C0
- RLPS Equalizer RAM Table (E1 mode)
RAM
Address
Content
(MSB..LSB)
RAM
Address
Content
(MSB..LSB)
0D
1D
2D
3D
4D
5D
6D
7D
8D
9D
10D
11D
12D
13D
14D
15D
16D
17D
18D
19D
20D
21D
22D
23D
24D
25D
26D
27D
28D
29D
30D
31D
32D
33D
34D
35D
0F D6 1C 2C
0F D6 1C 2C
0F D6 2C 2C
0F D6 2C 2C
0F D6 3C 2C
0F D6 3C 2C
0F CE 3C 2C
0F CE 3C 2C
0F CE 3C 2C
17 CE 3C 2C
17 CE 3C 2C
17 CE 4C 2C
17 CE 4C 2C
17 CE 4C 2C
17 CE 4C 2C
17 CE 4C 2C
17 CE 4C 2C
1F C6 4C 2C
1F C6 4C 2C
1F C6 4C 2C
1F C6 4C 2C
1F C6 4C 2C
1F C6 5C 2C
1F C6 5C 2C
1F C6 5C 2C
1F C6 5C 2C
27 C6 5C 2C
27 C6 5C 2C
27 C6 7C 32
27 C6 8C 32
27 C6 9C 32
27 C6 AC 32
27 C6 BC 32
27 C6 CC 32
2F C6 DC 32
2F C6 EC 32
128D
129D
130D
131D
132D
133D
134D
135D
136D
137D
138D
139D
140D
141D
142D
143D
144D
145D
146D
147D
148D
149D
150D
151D
152D
153D
154D
155D
156D
157D
158D
159D
160D
161D
162D
163D
87 73 05 AC
86 72 F6 2C
86 72 F6 2C
86 72 F6 2C
86 72 F6 2C
86 72 F6 2C
8E 72 F6 2C
8E 72 F6 2C
8E 6A F6 2C
8E 6A F6 2C
8E 6A F6 2C
8E 6B 06 2C
8E 6B 06 2C
8E 6B 06 2C
8E 6B 06 2C
96 6B 06 2C
96 6B 06 AC
95 6B 06 AC
95 6B 06 AC
95 63 06 AC
95 63 06 AC
95 63 06 AC
95 63 16 AC
9D 63 16 AC
9D 63 16 AC
9D 63 16 AC
9D 63 16 AC
9D 63 16 AC
9D 5B 16 AC
9D 5B 16 AC
9D 5B 26 AC
A5 5B 26 AC
A5 5A F7 2C
A5 5A F7 2C
A5 5B 07 2C
A5 5B 07 2C
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
378
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
36D
37D
38D
39D
40D
41D
42D
43D
44D
45D
46D
47D
48D
49D
50D
51D
52D
53D
54D
55D
56D
57D
58D
59D
60D
61D
62D
63D
64D
65D
66D
67D
68D
69D
70D
71D
72D
73D
74D
75D
76D
77D
78D
ISSUE 6
2F C7 0C 32
2F C7 2C 32
2F BC 68 32
2F BC 68 2C
2F BC 68 2C
2F B4 68 2C
37 B4 68 2C
37 B4 78 2C
37 B4 78 2C
37 B4 78 2C
37 B4 78 2C
37 B4 78 2C
37 B4 78 2C
37 AC 78 2C
37 AC 78 2C
3F AC 78 2C
3F AC 78 2C
3F AC 78 2C
3F AC 78 2C
3F AC 78 2C
3F AC 78 2C
3F AC 78 2C
3F AC 78 2C
47 AC 78 2C
47 AC 88 2C
47 AC 88 2C
47 AC 98 2C
47 AC 98 2C
47 AC 68 AC
47 AC 68 AC
47 AC 78 AC
4F AC 78 AC
4F A4 88 AC
4F A4 88 AC
4F A4 98 AC
4F 9C 98 AC
4F 9C 98 AC
4F 9C 98 AC
4F 9C 98 AC
4F 9C A8 AC
57 9C A8 AC
57 9C A8 AC
57 9C A8 AC
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
164D
165D
166D
167D
168D
169D
170D
171D
172D
173D
174D
175D
176D
177D
178D
179D
180D
181D
182D
183D
184D
185D
186D
187D
188D
189D
190D
191D
192D
193D
194D
195D
196D
197D
198D
199D
200D
201D
202D
203D
204D
205D
206D
A5 5B 17 2C
A5 5B 17 2C
A5 5B 27 2C
A5 5B 27 2C
AD 5B 27 2C
AD 53 27 2C
AD 53 27 2C
AD 53 37 2C
AD 53 37 2C
AD 53 37 2C
AD 53 37 2C
AD 53 37 2C
B5 53 37 2C
B5 53 33 2C
B5 53 33 2C
B5 53 33 2C
B5 53 43 2C
B5 53 43 2C
B5 53 43 2C
B5 49 03 2C
BD 49 03 2C
BD 49 13 2C
BD 49 23 2C
BD 49 33 2C
BD 49 33 2C
BD 49 33 2C
BD 49 33 2C
BD 49 33 2C
BD 49 33 2C
C5 49 33 2C
C5 49 43 2C
C5 49 43 2C
C5 49 53 2C
C5 41 53 2C
C5 41 53 2C
C5 41 53 2C
C5 41 53 2C
CD 39 53 2C
CD 39 53 2C
CD 39 63 2C
CD 39 63 2C
CC 39 83 2C
CC 39 83 2C
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
379
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
79D
80D
81D
82D
83D
84D
85D
86D
87D
88D
89D
90D
91D
92D
93D
94D
95D
96D
97D
98D
99D
100D
101D
102D
103D
104D
105D
106D
107D
108D
109D
110D
111D
112D
113D
114D
115D
116D
117D
118D
119D
120D
121D
ISSUE 6
57 9C A8 AC
57 9C A8 AC
57 9C A8 AC
57 94 A8 AC
57 94 A8 AC
5F 94 A8 AC
5F 94 A8 AC
5F 94 B8 AC
5F 94 B8 AC
5F 94 B8 AC
5F 94 B8 AC
5F 94 B8 AC
5F 94 B8 AC
67 94 B8 AC
67 8C B8 AC
67 8C B8 AC
67 8C B8 AC
67 8C 99 2C
67 8C 99 2C
67 8C 99 2C
67 8C A9 2C
67 8C A9 2C
6F 8C B9 2C
6F 8C B9 2C
6F 8C C9 2C
6F 84 C9 2C
6F 84 C9 2C
6F 84 E9 2C
6F 85 09 2C
6F 85 29 2C
77 85 09 2C
77 84 F5 22
77 84 F5 22
77 84 D5 A2
77 84 D5 A2
77 7C D5 A2
77 7C E5 AC
77 7C F5 AC
77 7D 05 AC
7F 7D 15 AC
7F 7D 25 AC
7F 72 E5 AC
7F 72 E5 AC
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
207D
208D
209D
210D
211D
212D
213D
214D
215D
216D
217D
218D
219D
220D
221D
222D
223D
224D
225D
226D
227D
228D
229D
230D
231D
232D
233D
234D
235D
236D
237D
238D
239D
240D
241D
242D
243D
244D
245D
246D
247D
248D
249D
CC 39 63 AC
CC 39 63 AC
CC 39 63 AC
D4 39 63 AC
D4 39 63 AC
D4 31 63 AC
D4 31 63 AC
D4 31 73 AC
D4 31 73 AC
D4 31 73 AC
D4 31 73 AC
DC 31 73 AC
DC 31 73 AC
DC 31 73 AC
DC 31 73 AC
DC 31 73 AC
DC 29 73 AC
DC 29 73 AC
DC 29 83 AC
E4 29 83 AC
E4 29 83 AC
E4 29 83 AC
E4 29 83 AC
E4 29 83 AC
E4 29 83 AC
E4 29 83 AC
E4 29 83 AC
E4 21 83 AC
EC 21 93 AC
EC 21 93 AC
EC 21 93 AC
EC 21 93 AC
EC 21 93 AC
EC 21 93 AC
EC 21 93 AC
EC 21 93 AC
F4 21 93 AC
F4 21 93 AC
F4 19 93 AC
F4 19 A3 AC
F4 19 A3 AC
F4 19 A3 AC
F4 19 A3 AC
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
380
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
122D
123D
124D
125D
126D
127D
ISSUE 6
7F 72 E5 AC
7F 72 E5 AC
7F 72 E5 AC
7F 72 E5 AC
87 73 05 AC
87 73 05 AC
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
250D
251D
252D
253D
254D
255D
F4 19 A3 AC
FC 19 A3 AC
FC 19 A3 AC
FC 19 A3 AC
FC 19 A3 AC
FC 19 A3 AC
The Analog Loss Of Signal feature is available for short haul and ISDN signal levels only. (Other
LOS variants are available via the CDRC Interrupt Status and Alternate Loss of Signal registers.)
For short haul and ISDN signal levels, the receiver monitors if the received signal exceeds a
predefined peak amplitude and the ALOSV bit is set when this condition is not meet. The change
in ALOSV state sets the ALOSI bit and can be enabled to assert the INTB.
The RLPS is able to squelch the data in response to an assertion of ALOS. Since this action is not
mandatory, it is not enabled by default. However it can be desirable to do so in which case data
squelching can be enabled by setting the SQUELCHE register bit to logic 1.
12.9 Using the PRBS Generator and Detector
PRBS patterns may be generated in either the transmit or receive directions, and detected in the
opposite direction, as configured by the RXPATGEN bit of the PRBS Positioning/Control And
HDLC Control registers. The timeslots for PRBS generation and detection are configured by the
UNF_GEN and UNF_DET bits of the PRBS Positioning/Control registers or by the TEST bit in the
each of the TPSC’s and RPSC’s PCM Data Control byte.
12.10 Using the Per-Channel Serial Controllers and SIGX
12.10.1 Initialization
Before the TPSC (RPSC) block can be used, a proper initialization of the internal registers must
be performed to eliminate erroneous control data from being produced on the block outputs. The
output control streams should be disabled by setting the PCCE bit in the TPSC (RPSC)
Configuration register to logic 0. Then, all 96 locations of the TPSC (RPSC) must be filled with
valid data. Finally, the output streams can be enabled by setting the PCCE bit in the TPSC
(RPSC) Configuration register to logic 1.
Before the SIGX Per-Timeslot/Per-Channel Configuration register bits in the indirect registers 40H
through 5FH can be used, a proper initialization of the internal registers must be performed to
eliminate erroneous control data from being produced on the block outputs. The output control
streams should be disabled by setting the PCCE bit in the SIGX Configuration register to logic 0.
Then, all 32 locations in E1 or 24 locations in T1 of the SIGX must be filled with valid data. Finally,
the output streams can be enabled by setting the PCCE bit in the SIGX Configuration register to
logic 1.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
381
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
12.10.2 Direct Access Mode
Direct access mode to the TPSC, RPSC, or SIGX is not used in the COMET-QUAD. However,
direct access mode is selected by default whenever the COMET-QUAD is reset. The IND bit
within the TPSC, RPSC, and SIGX Configuration registers must be set to logic 1 after a reset is
applied.
12.10.3 Indirect Access Mode
Indirect access mode is selected by setting the IND bit in the TPSC, RPSC, or SIGX Configuration
register to logic 1. When using the indirect access mode, the status of the BUSY indication bit
should be polled to determine the status of the microprocessor access: when the BUSY bit is
logic 1, the TPSC, RPSC, or SIGX is processing an access request; when the BUSY bit is logic 0,
the TPSC, RPSC, or SIGX has completed the request.
The indirect write programming sequence for the TPSC (RPSC, SIGX) is as follows:
1. Check that the BUSY bit in the TPSC (RPSC) µP Access Status register is logic 0. For the
SIGX, check that the BUSY bit in the Timeslot Indirect Status register is logic 0.
2. Write the channel data to the TPSC (RPSC, SIGX) Channel Indirect Data Buffer register.
3. Write RWB=0 and the channel address to the TPSC (RPSC, SIGX) Channel Indirect
Address/Control register.
4. Poll the BUSY bit until it goes to logic 0. The BUSY bit will go to logic 1 immediately after step
3 and remain at logic 1 until the request is complete.
5. If there is more data to be written, go back to step 1.
The indirect read programming sequence for the TPSC (RPSC, SIGX) is as follows:
1. Check that the BUSY bit in the TPSC (RPSC) µP Access Status register is logic 0. For the
SIGX, check that the BUSY bit in the Timeslot Indirect Status register is logic 0.
2. Write RWB=1 and the channel address to the TPSC (RPSC, SIGX) Channel Indirect
Address/Control register.
3. Poll the BUSY bit, waiting until it goes to a logic 0. The BUSY bit will go to logic 1 immediately
after step 2 and remain at logic 1 until the request is complete.
4. Read the requested channel data from the TPSC (RPSC, SIGX) Channel Indirect Data Buffer
register.
5. If there is more data to be read, go back to step 1.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
382
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
12.11 T1/E1 Framer Loopback Modes
The COMET-QUAD provides four loopback modes to aid in network and system diagnostics. The
network loopbacks (Payload and Line) can be initiated at any time via the µP interface, but are
usually initiated once an inband loopback activate code is detected. The system Diagnostic
Digital loopback can be initiated at any time by the system via the µP interface to check the path
of system data through the framer. The Per-DS0 loopback permits the payload to be looped-back
on a per-DS0 basis to allow network testing without taking an entire link off-line.
12.11.1 Line Loopback
When LINE loopback (LINELB) is initiated by setting the LINELB bit in the Master Diagnostics
Register to logic 1, the quadrant is configured to internally connect the recovered data to the
transmit jitter attenuator, TJAT. The data sent to the TJAT is the recovered data from the output of
the CDRC block. Note that when line loopback is enabled, the contents of the TJAT Reference
Clock Divisor and Output Clock Divisor registers should be programmed to 2FH in T1 or FFH in
E1 to correctly attenuate the jitter on the receive clock. Conceptually, the data flow through a
single quadrant of the COMET-QUAD in this loopback mode is illustrated in Figure 33.
Figure 33:
BTPCM[x]
BTSIG[x]
BTCLK[x]
- Line Loopback
BTIF
TX
ELST
Transmitter
T1-XBAS /
E1-TRAN
TJAT
XLPG
TXTIP[x]
TXRING[x]
Line Loopback
BRPCM[x]
BRSIG[x]
BRCLK[x]
BRIF
RX
ELST
Framer
T1-FRMR /
E1-FRMR
RJAT
CDRC
RLPS
RXTIP[x]
RXRING[x]
12.11.2 Payload Loopback
When PAYLOAD loopback (PAYLB) is initiated by setting the PAYLB bit in the Master Diagnostics
Register to logic 1, the quadrant is configured to internally connect the output of its RX-ELST to
the PCM input of its transmitter block. The data read out of RX-ELST is timed to the transmitter
clock, and the transmit frame alignment indication is used to synchronize the output frame
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
383
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
alignment of RX-ELST. The transmit frame alignment is either arbitrary (when the TX-ELST is
used) or is specified by the BTFP[x] input (when the TX-ELST is bypassed). Conceptually, the
data flow through a single quadrant of the COMET-QUAD in this loopback mode is illustrated in
Figure 34. Note that because the transmit and receive streams are not superframe aligned, any
robbed-bit signaling in the receive stream will not fall in the correct frame once looped back and
that transmit robbed-bit signaling will overwrite the looped back data if signaling insertion is
enabled.
Figure 34:
BTPCM[x]
BTSIG[x]
BTCLK[x]
BTIF
- Payload Loopback
TX
ELST
Transmitter
T1-XBAS /
E1-TRAN
TJAT
XLPG
TXTIP[x]
TXRING[x]
RLPS
RXTIP[x]
RXRING[x]
Payload Loopback
BRPCM[x]
BRSIG[x]
BRCLK[x]
BRIF
RX
ELST
Framer
T1-FRMR /
E1-FRMR
RJAT
CDRC
12.11.3 Per-Channel Loopback
The T1 or E1 payload may be looped back on a per-channel or per-timeslot basis through the use
of the TPSC. If all channels are looped back, the result is very similar to Payload Loopback. In
order for per-channel loopback to operated correctly, the receive elastic store, RX-ELST, must be
bypassed by setting the RXELSTBYP bit to logic 1 and the backplane receive interface must be
set to clock master by setting the CMODE bit in the BRIF Receive Backplane Configuration
register to logic 0. The LOOP bit must be set to logic 1 in the TPSC Internal Registers for each
channel/timeslot desired to be looped back, and the PCCE bit in the TPSC Configuration register
must be set to logic 1. When all these parameters are configured, the incoming receive
channels/timeslots selected will overwrite their corresponding outgoing transmit
channels/timeslots; the remaining transmit channels will pass through intact. Note that because
the transmit and receive streams are not superframe aligned, any robbed-bit signaling in the
receive stream will not fall in the correct frame once looped back and that transmit robbed-bit
signaling will overwrite the looped back channel data if signaling insertion is enabled.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
384
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
12.11.4 Diagnostic Digital Loopback
When Diagnostic Digital loopback (DDLB) mode is initiated by setting the DDLB bit in the Master
Diagnostics Register to logic 1, the quadrant is configured to internally direct the output of the
TJAT to the inputs of the receiver section. The dual-rail RZ outputs of the TJAT are directed to the
dual-rail inputs of the CDRC. The single-rail NRZ outputs of the TJAT are directed to the inputs of
the RJAT. Conceptually, the data flow through a single quadrant of the COMET-QUAD in this
loopback condition is illustrated in Figure 35.
Figure 35:
BTPCM[x]
BTSIG[x]
BTCLK[x]
- Diagnostic Digital Loopback
BTIF
TX
ELST
Transmitter
T1-XBAS /
E1-TRAN
TJAT
Framer
T1-FRMR /
E1-FRMR
RJAT
XLPG
TXTIP[x]
TXRING[x]
RLPS
RXTIP[x]
RXRING[x]
Diagnostic Loopback
BRPCM[x]
BRSIG[x]
BRCLK[x]
BRIF
RX
ELST
CDRC
12.12 RSYNC Generation
The below diagram illustrates how the signal on the RSYNC output pin is generated. In this
diagram:
•
LOSV indicates the value appearing on the LOSV bit of the CDRC Interrupt Status register.
•
ALOSV indicates the value appearing on the ALOSV bit of the RLPS Configuration and Status
register.
•
RSYNC_ALOSB is the value of the RSYNC_ALOSB bit of the Global Configuration register.
•
E1/T1B is the value of the E1/T1B bit of the Global Configuration register.
•
RSYNC_MEM is the value of the RSYNC_MEM bit of the Receive Options register.
•
RSYNCSEL is the value of the RSYNCSEL bit of the Receive Options register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
385
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
•
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
RSYNC_SEL[1:0] is the value of the RSYNC_SEL[1:0] bits of the RSYNC Select register.
In T1 mode, the 1x clock illustrated will be nominally 1.544 MHz even if the CSU Configuration
register has been programmed for XCLK to accept a 2.048 MHz clock.
Figure 36
- RSYNC Generation
COMET-QUAD
Quadrant 4
Quadrant 3
Quadrant 2
Quadrant 1
Analog Clock
1x clk
Synthesis
Unit (CSU)
1x clk
E1/T1B
Divider to 8kHz
11
10
1x clk
8 kHz clk
1x clk
XCLK
1
Recovered
ALOSV
LOSV
Clock
01
1
0
RJAT
RSYNC
0
0
00
1
RSYNCSEL
1
0
RSYNC_SEL[1:0]
RSYNC_MEM
RSYNC_ALOSB
The above diagram illustrates that RSYNC generation is configurable. RSYNC_ALOSB selects
which criterion (either Analog Loss of Signal or Loss of Signal) causes RSYNC generation to
switch over from the Recovered Clock to XCLK. If RSYNC_MEM is logic 1, then RSYNC will be
held high during the loss of signal condition. RSYNCSEL selects between the line rate clock or
8kHz version of the clock. RSYNC_SEL[1:0] selects which quadrant’s internal RSYNC signal is
presented on the RSYNC pin.
Note: RSYNC is always jitter attenuated by the RJAT. Refer to the RJATBYP register bit
description and the recommendations in the RJAT Divider N2 Control register description for
additional information.
12.13 Backplane Configuration
The following tables provide programming guidelines for the Backplane Interfaces. The tables
correspond to the commonly used modes discussed in Functional Description section of this
document. In many cases, variations in the register settings are possible. Because of interaction
between register settings, it is highly recommended that the below tables be used in conjunction
with the register descriptions found in the Normal Mode Register section. Although the tables
below are intended to provide guidelines, an exhaustive list of register settings for all eventualities
may not be given.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
386
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
12.13.1 Receive Clock Master: Full T1/E1 Mode Settings
The below table provides programming guidelines for the Receive Clock Master: Full T1/E1 mode
illustrated in Figure 9, Figure 43, and Figure 44. Consult the figure discussions and the Normal
Mode Register Description section for more details on the register settings.
Register
Bit Name
Example
Setting
Receive Options
RJATBYP
0
Receive Options
RXELSTBYP
1
BRIF Configuration
NX64KBIT/S[1]
0
BRIF Configuration
NX64KBIT/S[0]
0
BRIF Configuration
CMODE
0
BRIF Configuration
RATE[1]
0
BRIF Configuration
RATE[0]
0 (T1 mode)
1 (E1 mode)
BRIF Frame Pulse
Configuration
FPMODE
0
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
387
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
12.13.2 Receive Clock Master: Nx64Kbit/s Mode Settings
The below table provides programming guidelines for the Receive Clock Master: Nx64Kbit/s mode
illustrated in Figure 10, Figure 45, and Figure 46. Consult the figure discussions and the Normal
Mode Register Description section for more details on the register settings.
Register
Bit Name
Example
Setting
Receive Options
RJATBYP
0
Receive Options
RXELSTBYP
1
BRIF Configuration
NX64KBIT/S[1]
0 or 1
BRIF Configuration
NX64KBIT/S[0]
0 or 1
BRIF Configuration
CMODE
0
BRIF Configuration
RATE[1]
0
BRIF Configuration
RATE[0]
0 (T1 mode)
1 (E1 mode)
BRIF Frame Pulse
Configuration
FPMODE
0
12.13.3 Receive Clock Master: Clear Channel Mode Settings
The below table provides programming guidelines for the Receive Clock Master: Clear Channel
mode illustrated in Figure 11 and Figure 47. Consult the figure discussions and the Normal Mode
Register Description section for more details on the register settings.
Register
Bit Name
Example
Setting
Receive Options
RJATBYP
0
Receive Options
UNF
1
Receive Options
RXELSTBYP
1
BRIF Configuration
CMODE
0
BRIF Configuration
FPMODE
0
BRIF Configuration
RATE[1]
0
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
388
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register
Bit Name
Example
Setting
BRIF Configuration
RATE[0]
0 (T1 mode)
1 (E1 mode)
12.13.4 Receive Clock Slave: Full T1/E1 Mode Settings
The below table provides programming guidelines for the Receive Clock Slave: Full T1/E1 mode
illustrated in Figure 12, Figure 48, Figure 49, and Figure 50. Consult the figure discussions and
the Normal Mode Register Description section for more details on the register settings.
Register
Bit Name
Example
Setting
Receive Options
RXELSTBYP
0
RX-ELST Configuration
IR, OR
0 (T1 mode)
1 (E1 mode)
BRIF Configuration
NX64KBIT/S[1]
0
BRIF Configuration
NX64KBIT/S[0]
0
BRIF Configuration
CMODE
1
BRIF Configuration
CMS
0 or 1
BRIF Configuration
RATE[1]
0
BRIF Configuration
RATE[0]
0 (T1 mode)
1 (E1 mode)
BRIF Frame Pulse
Configuration
FPMODE
1
12.13.5 Receive Clock Slave: H-MVIP Mode Settings
The below table provides programming guidelines for the Receive Clock Slave: H-MVIP mode
illustrated in Figure 13, Figure 55, and Figure 56. Consult the figure discussions and the Normal
Mode Register Description section for more details on the register settings.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
389
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register
Bit Name
Example
Setting
Receive Options
RXELSTBYP
0
RX-ELST Configuration
IR, OR
0 (T1 mode)
1 (E1 mode)
BRIF Configuration
CMODE
1
BRIF Configuration
DE
0
BRIF Configuration
FE
1
BRIF Configuration
CMS
1
BRIF Configuration
RATE[1]
1
BRIF Configuration
RATE[0]
1
BRIF Frame Pulse
Configuration
MAP
0
BRIF Frame Pulse
Configuration
FPINV
0
BRIF Frame Pulse
Configuration
FPMODE
1
BRIF Parity/F-bit
Configuration
TRI
1
Receive H-MVIP/CCS
Enable
RHMVIPEN
1
Quadrant 1: BRIF
Timeslot Offset
TSOFF[6:0]
0000000
Quadrant 2: BRIF
Timeslot Offset
TSOFF[6:0]
0000001
Quadrant 3: BRIF
Timeslot Offset
TSOFF[6:0]
0000010
Quadrant 4: BRIF
Timeslot Offset
TSOFF[6:0]
0000011
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
390
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
12.13.6 Receive Clock Slave: Full T1/E1 with CCS H-MVIP Mode Settings
The below table provides programming guidelines for the Receive Clock Slave: Full T1/E1 with
CCS H-MVIP mode illustrated in Figure 14 (a variation of the mode illustrated in Figure 48 and
Figure 49). Consult the figure discussions and the Normal Mode Register Description section for
more details on the register settings.
Register
Bit Name
Example
Setting
Receive Options
RXELSTBYP
0
RX-ELST Configuration
IR, OR
0 (T1 mode)
1 (E1 mode)
BRIF Configuration
NX64KBIT/S[1]
0
BRIF Configuration
NX64KBIT/S[0]
0
BRIF Configuration
CMODE
1
BRIF Configuration
CMS
0
BRIF Configuration
RATE[1]
0
BRIF Configuration
RATE[0]
0 (T1 mode)
1 (E1 mode)
BRIF Frame Pulse
Configuration
MAP
0
BRIF Frame Pulse
Configuration
FPMODE
1
RX-ELST CCS
Configuration
IR
0 (T1 mode)
1 (E1 mode)
Receive H-MVIP/CCS
Enable
RCCSEN
1
Receive H-MVIP/CCS
Enable
RHMVIPEN
0
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
391
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
12.13.7 Transmit Clock Master: Full T1/E1 Mode Settings
The below table provides programming guidelines for the Transmit Clock Master: Full T1/E1 mode
illustrated in Figure 15, Figure 63, and Figure 64. Consult the figure discussions and the Normal
Mode Register Description section for more details on the register settings.
Register
Bit Name
Example
Setting
Transmit Line Interface
Configuration
TJATBYP
0
Transmit Timing Options
TXELSTBYP
1
BTIF Configuration
NX64KBIT/S[1]
0
BTIF Configuration
NX64KBIT/S[0]
0
BTIF Configuration
CMODE
0
BTIF Configuration
RATE[1]
0
BTIF Configuration
RATE[0]
0 (T1 mode)
1 (E1 mode)
BTIF Frame Pulse
Configuration
FPMODE
0
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
392
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
12.13.8 Transmit Clock Master: Nx64Kbit/s Mode Settings
The below table provides programming guidelines for the Transmit Clock Master: Nx64Kbit/s mode
illustrated in Figure 16, Figure 65, and Figure 66. Consult the figure discussions and the Normal Mode
Register Description section for more details on the register settings.
Register
Bit Name
Example
Setting
Transmit Line Interface
Configuration
TJATBYP
0
Transmit Timing Options
TXELSTBYP
1
BTIF Configuration
NX64KBIT/S[1]
0 or 1
BTIF Configuration
NX64KBIT/S[0]
0 or 1
BTIF Configuration
CMODE
0
BTIF Configuration
RATE[1]
0
BTIF Configuration
RATE[0]
0 (T1 mode)
1 (E1 mode)
BTIF Frame Pulse
Configuration
FPMODE
0
12.13.9 Transmit Clock Master: Clear Channel Mode Settings
The below table provides programming guidelines for the Transmit Clock Master: Clear Channel mode
illustrated in Figure 17 and Figure 69. Consult the figure discussions and the Normal Mode Register
Description section for more details on the register settings.
Register
Bit Name
Example
Setting
Transmit Line Interface
Configuration
TJATBYP
0
Transmit Framing and
Bypass Options
FDIS
1
Transmit Timing Options
TXELSTBYP
1
BTIF Configuration
CMODE
0
BTIF Configuration
RATE[1]
0
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
393
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
12.13.10
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register
Bit Name
Example
Setting
BTIF Configuration
RATE[0]
0 (T1 mode)
1 (E1 mode)
Transmit Clock Slave: Full T1/E1 Mode Settings
The below table provides programming guidelines for the Transmit Clock Slave: Full T1/E1 mode
illustrated in Figure 18, Figure 70, and Figure 71. Consult the figure discussions and the Normal
Mode Register Description section for more details on the register settings.
12.13.11
Register
Bit Name
Example
Setting
Transmit Timing Options
TXELSTBYP
0 or 1
TX-ELST Configuration
IR, OR
0 (T1 mode)
1 (E1 mode)
BTIF Configuration
NX64KBIT/S[1]
0
BTIF Configuration
NX64KBIT/S[0]
0
BTIF Configuration
CMODE
1
BTIF Configuration
CMS
0
BTIF Configuration
RATE[1]
0
BTIF Configuration
RATE[0]
0 (T1 mode)
1 (E1 mode)
BTIF Frame Pulse
Configuration
FPMODE
1
Transmit Clock Slave: Clear Channel Mode Settings
The below table provides programming guidelines for the Transmit Clock Slave: Clear Channel mode
illustrated in Figure 19 and Figure 73. Consult the figure discussions and the Normal Mode Register
Description section for more details on the register settings.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
394
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
12.13.12
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register
Bit Name
Example
Setting
Transmit Line Interface
Configuration
TJATBYP
0
Transmit Framing and
Bypass Options
FDIS
1
Transmit Timing Options
TXELSTBYP
1
BTIF Configuration
CMODE
1
BTIF Configuration
RATE[1]
0
BTIF Configuration
RATE[0]
0 (T1 mode)
1 (E1 mode)
Transmit Clock Slave: H-MVIP Mode Settings
The below table provides programming guidelines for the Transmit Clock Slave: H-MVIP mode illustrated
in Figure 20, Figure 77, and Figure 78. Consult the figure discussions and the Normal Mode Register
Description section for more details on the register settings.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
395
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register
Bit Name
Example
Setting
Transmit Timing Options
TXELSTBYP
0 or 1
TX-ELST Configuration
IR, OR
0 (T1 mode)
1 (E1 mode)
BTIF Configuration
CMODE
1
BTIF Configuration
DE
1
BTIF Configuration
FE
1
BTIF Configuration
CMS
1
BTIF Configuration
RATE[1]
1
BTIF Configuration
RATE[0]
1
BTIF Frame Pulse
Configuration
FPINV
0
BTIF Frame Pulse
Configuration
FPTYP
0
BTIF Frame Pulse
Configuration
FPMODE
1
TX-ELST CCS
Configuration
OR
0 (T1 mode)
1 (E1 mode)
Transmit H-MVIP/CCS
Enable and
Configuration
THMVIPEN
1
Transmit H-MVIP/CCS
Enable and
Configuration
TCCSEN
0 (CCS insertion disabled)
1 (CCS insertion enabled)
Transmit H-MVIP/CCS
Enable and
Configuration
TCCS15, TCCS31
0 or 1
Transmit H-MVIP/CCS
Enable and
Configuration
TCCS16
0 or 1
Note: CCS is inserted upstream of
the E1-TRAN. To avoid Timeslot 16
CCS from being overwritten,
program both the SIGEN and DLEN
bits of the E1-TRAN Configuration
register to logic 0.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
396
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
12.13.13
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register
Bit Name
Example
Setting
Quadrant 1: BTIF
Timeslot Offset
TSOFF[6:0]
0000000
Quadrant 2: BTIF
Timeslot Offset
TSOFF[6:0]
0000001
Quadrant 3: BTIF
Timeslot Offset
TSOFF[6:0]
0000010
Quadrant 4: BTIF
Timeslot Offset
TSOFF[6:0]
0000011
Transmit Clock Slave: Full T1/E1 with CCS H-MVIP Mode Settings
The below table provides programming guidelines for the Transmit Clock Slave: Full T1/E1 with CCS HMVIP mode illustrated in Figure 21 (a variation of the mode illustrated in Figure 70 and Figure 71). Consult
the figure discussions and the Normal Mode Register Description section for more details on the register
settings.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
397
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Register
Bit Name
Example
Setting
Transmit Timing Options
TXELSTBYP
0 or 1
TX-ELST Configuration
IR, OR
0 (T1 mode)
1 (E1 mode)
BTIF Configuration
NX64KBIT/S[1]
0
BTIF Configuration
NX64KBIT/S[0]
0
BTIF Configuration
CMODE
1
BTIF Configuration
CMS
0
BTIF Configuration
RATE[1]
0
BTIF Configuration
RATE[0]
0 (T1 mode)
1 (E1 mode)
BTIF Frame Pulse
Configuration
FPMODE
1
Transmit H-MVIP/CCS
Enable and
Configuration
THMVIPEN
0
Transmit H-MVIP/CCS
Enable and
Configuration
TCCSEN
1
Transmit H-MVIP/CCS
Enable and
Configuration
TCCS15, TCCS16,
TCCS31
0 or 1
12.14 H-MVIP Data Format
The H-MVIP data and Channel Associated Signaling (CAS) streams on the COMET-QUAD are
able to carry all the DS0s for 4 T1s or all timeslots for 4 E1s. When carrying timeslots from E1s,
the H-MVIP frame is completely filled with 128 timeslots from four E1s. When carrying DS0s from
four T1s there are not enough DS0s to completely fill the 128 byte frame. Table 94 shows how the
DS0s and CAS bits of four T1s are formatted in the 128 timeslot H-MVIP frame. Table 95 shows
how the data timeslots and CAS bits of four E1s are formatted in the 128 timeslot H-MVIP frame.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
398
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Table 94:
Timeslot
Number
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- Data and CAS T1 H-MVIP Format
First T1 DS0
Number
Second T1 DS0
Number
Third T1 DS0
Number
Fourth T1 DS0
Number
0-3
Undefined
Undefined
Undefined
Undefined
4-7
1
1
1
1
8-11
2
2
2
2
12-15
3
3
3
3
16-19
Undefined
Undefined
Undefined
Undefined
20-23
4
4
4
4
24-27
5
5
5
5
28-31
6
6
6
6
32-35
Undefined
Undefined
Undefined
Undefined
36-39
7
7
7
7
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
108-111
21
21
21
21
112-115
Undefined
Undefined
Undefined
Undefined
116-119
22
22
22
22
120-123
23
23
23
23
124-127
24
24
24
24
Table 95:
Timeslot
Number
- Data and CAS E1 H-MVIP Format
First E1 TS
Number
Second E1 TS
Number
Third E1 TS
Number
Fourth E1 TS
Number
0-3
1
1
1
1
4-7
2
2
2
2
8-11
3
3
3
3
12-15
4
4
4
4
16-19
5
5
5
5
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
399
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
120-123
31
31
31
31
124-127
32
32
32
32
The H-MVIP Common Channel Signaling interface on COMET-QUAD carries at most 12 timeslots
when in E1 mode: four instances of timeslot 16 for ISDN signaling, and four instances each of
timeslot 15 and timeslot 31 for V5.2 interfaces. In T1 mode, the CCS H-MVIP stream carries at
most 4 timeslots: four instances of timeslot 24. Table 96 shows the H-MVIP format for carrying 4
common channeling signaling channels when in T1 mode. Note that when the transmit H-MVIP
interface is used, the MAP bit of the BTIF Frame Pulse Configuration register must be logic 0.
Similarly, when the receive H-MVIP interface is used, the MAP bit of the BRIF Frame Pulse
Configuration register must be logic 0. Table 97 shows the H-MVIP format for carrying 12
common channeling signaling channels when in E1 mode. When a signaling or V5.2 channel is
not in use, the H-MVIP timeslot is undefined.
Table 96:
- CCS T1 H-MVIP Format
H-MVIP Timeslot Number
T1 Designation
0
Undefined
1
Undefined
2
Undefined
•
•
•
•
123
Undefined
124
Quadrant 1 Timeslot 24
125
Quadrant 2 Timeslot 24
126
Quadrant 3 Timeslot 24
127
Quadrant 4 Timeslot 24
Table 97:
- CCS E1 H-MVIP Format
H-MVIP Timeslot Number
E1 Designation
0
Undefined
1
Undefined
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
400
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
•
•
•
•
•
•
59
Undefined
60
Quadrant 1 Timeslot 15
61
Quadrant 2 Timeslot 15
62
Quadrant 3 Timeslot 15
63
Quadrant 4 Timeslot 15
64
Quadrant 1 Timeslot 16
65
Quadrant 2 Timeslot 16
66
Quadrant 3 Timeslot 16
66
Quadrant 4 Timeslot 16
67
Undefined
•
•
•
•
•
•
123
Undefined
124
Quadrant 1 Timeslot 31
125
Quadrant 2 Timeslot 31
126
Quadrant 3 Timeslot 31
127
Quadrant 4 Timeslot 31
12.15 JTAG Support
The COMET-QUAD supports the IEEE Boundary Scan Specification as described in the IEEE
1149.1 standards. The Test Access Port (TAP) consists of the five standard pins, TRSTB, TCK,
TMS, TDI and TDO used to control the TAP controller and the boundary scan registers. The
TRSTB input is the active-low reset signal used to reset the TAP controller. TCK is the test clock
used to sample data on the TDI primary input and to output data on the TDO primary output. The
TMS primary input is used to direct the TAP controller through its states. The basic boundary
scan architecture is shown below.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
401
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
Figure 37:
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- Boundary Scan Architecture
Boundary Scan
Register
TDI
Device Identification
Register
Bypass
Register
Instruction
Register
and
Decode
Mux
DFF
TDO
Control
TMS
Test
Access
Port
Controller
Select
Tri-state Enable
TRSTB
TCK
The boundary scan architecture consists of a TAP controller, an instruction register with instruction
decode, a bypass register, a device identification register and a boundary scan register. The TAP
controller interprets the TMS input and generates control signals to load the instruction and data
registers. The instruction register with instruction decode block is used to select the test to be
executed and/or the register to be accessed. The bypass register offers a single-bit delay from
primary input, TDI to primary output, TDO. The device identification register contains the device
identification code.
The boundary scan register allows testing of board inter-connectivity. The boundary scan register
consists of a shift register placed in series with device inputs and outputs. Using the boundary
scan register, all digital inputs can be sampled and shifted out on primary output, TDO. In
addition, patterns can be shifted in on primary input, TDI, and forced onto all digital outputs.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
402
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
12.15.1 TAP Controller
The TAP controller is a synchronous finite state machine clocked by the rising edge of primary
input, TCK. All state transitions are controlled using primary input, TMS. The finite state machine
is described below.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
403
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Figure 38:
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- TAP Controller Finite State Machine
TRSTB=0
Test-Logic-Reset
1
0
1
1
Run-Test-Idle
1
Select-IR-Scan
Select-DR-Scan
0
0
0
1
1
Capture-IR
Capture-DR
0
0
Shift-IR
Shift-DR
1
1
0
1
1
Exit1-IR
Exit1-DR
0
0
Pause-IR
Pause-DR
0
1
Exit2-DR
0
1
0
0
Exit2-IR
1
1
Update-IR
Update-DR
1
0
1
0
0
All transitions dependent on input TMS
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
404
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Test-Logic-Reset
The test logic reset state is used to disable the TAP logic when the device is in normal mode
operation. The state is entered asynchronously by asserting input, TRSTB. The state is entered
synchronously regardless of the current TAP controller state by forcing input, TMS high for 5 TCK
clock cycles. While in this state, the instruction register is set to the IDCODE instruction.
Run-Test-Idle
The run test/idle state is used to execute tests.
Capture-DR
The capture data register state is used to load parallel data into the test data registers selected by
the current instruction. If the selected register does not allow parallel loads or no loading is
required by the current instruction, the test register maintains its value. Loading occurs on the
rising edge of TCK.
Shift-DR
The shift data register state is used to shift the selected test data registers by one stage. Shifting
is from MSB to LSB and occurs on the rising edge of TCK.
Update-DR
The update data register state is used to load a test register's parallel output latch. In general, the
output latches are used to control the device. For example, for the EXTEST instruction, the
boundary scan test register's parallel output latches are used to control the device's outputs. The
parallel output latches are updated on the falling edge of TCK.
Capture-IR
The capture instruction register state is used to load the instruction register with a fixed
instruction. The load occurs on the rising edge of TCK.
Shift-IR
The shift instruction register state is used to shift both the instruction register and the selected test
data registers by one stage. Shifting is from MSB to LSB and occurs on the rising edge of TCK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
405
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Update-IR
The update instruction register state is used to load a new instruction into the instruction register.
The new instruction must be scanned in using the Shift-IR state. The load occurs on the falling
edge of TCK.
The Pause-DR and Pause-IR states are provided to allow shifting through the test data and/or
instruction registers to be momentarily paused.
Boundary Scan Instructions
The following is a description of the standard instructions. Each instruction selects a serial test
data register path between input, TDI and output, TDO.
BYPASS
The bypass instruction shifts data from input, TDI to output, TDO with one TCK clock period delay.
The instruction is used to bypass the device.
EXTEST
The external test instruction allows testing of the interconnection to other devices. When the
current instruction is the EXTEST instruction, the boundary scan register is placed between input,
TDI and output, TDO. Primary device inputs can be sampled by loading the boundary scan
register using the Capture-DR state. The sampled values can then be viewed by shifting the
boundary scan register using the Shift-DR state. Primary device outputs can be controlled by
loading patterns shifted in through input TDI into the boundary scan register using the Update-DR
state.
SAMPLE
The sample instruction samples all the device inputs and outputs. For this instruction, the
boundary scan register is placed between TDI and TDO. Primary device inputs and outputs can
be sampled by loading the boundary scan register using the Capture-DR state. The sampled
values can then be viewed by shifting the boundary scan register using the Shift-DR state.
IDCODE
The identification instruction is used to connect the identification register between TDI and TDO.
The device's identification code can then be shifted out using the Shift-DR state.
STCTEST
The single transport chain instruction is used to test out the TAP controller and the boundary scan
register during production test. When this instruction is the current instruction, the boundary scan
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
406
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
register is connected between TDI and TDO. During the Capture-DR state, the device
identification code is loaded into the boundary scan register. The code can then be shifted out of
the output, TDO, using the Shift-DR state.
Boundary Scan Cells
In the following diagrams, CLOCK-DR is equal to TCK when the current controller state is SHIFTDR or CAPTURE-DR, and unchanging otherwise. The multiplexer in the center of the diagram
selects one of four inputs, depending on the status of select lines G1 and G2. The ID Code bit is
as listed in the Boundary Scan Register table in the JTAG Test Port section 11.2.
Figure 39:
- Input Observation Cell (IN_CELL)
IDCODE
Scan Chain Out
INPUT
to internal
logic
Input
Pad
G1
G2
SHIFT-DR
I.D. Code bit
12
1 2 MUX
12
12
D
C
CLOCK-DR
Scan Chain In
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
407
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Figure 40:
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- Output Cell (OUT_CELL) or Enable Cell (ENABLE)
Scan Chain Out
G1
EXTEST
Output or Enable
from system logic
IDOODE
SHIFT-DR
I.D. code bit
1
G1
G2
1
1
1
1
2
2 MUX
2
2
1
OUTPUT
or Enable
MUX
D
C
D
C
CLOCK-DR
UPDATE-DR
Scan Chain In
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
408
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Figure 41:
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- Bidirectional Cell (IO_CELL)
Scan Chain Out
G1
EXTEST
OUTPUT from
internal logic
IDCODE
1
1
G1
G2
SHIFT-DR
INPUT
from pin
12
1 2 MUX
12
12
I.D. code bit
MUX
D
C
INPUT
to internal
logic
OUTPUT
to pin
D
C
CLOCK-DR
UPDATE-DR
Scan Chain In
Figure 42:
- Layout of Output Enable and Bidirectional Cells
Scan Chain Out
OUTPUT ENABLE
from internal
logic (0 = drive)
INPUT to
internal logic
OUTPUT from
internal logic
OUT_CELL
IO_CELL
I/O
PAD
Scan Chain In
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
409
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
13
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
FUNCTIONAL TIMING
13.1 Backplane Receive Serial Clock and Data Interface Timing
Figure 43: - T1 Receive Clock Master : Full T1/E1 Mode
BRCLK[x]
BRFP[x]
BRPCM[x]
BRSIG[x]
1 2 3 4 5 6 7 8 F 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
A BCD
Channel 24
A BC D
Channel 1
1 2 3 4 5 6 7 8 F 1 2 3 4 5 6 7 8 1
A B C D
Channel 2
A B CD
Channel 24
Parity Bit
(if enabled)
Figure 44:
A B CD
Channel 1
Parity Bit
(if enabled)
- E1 Receive Clock Master : Full T1/E1 Mode
BRCLK[x]
BRFP[x]
BRPCM[x]
BRSIG[x]
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
A B CD
Timeslot 31
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1
A B CD
Timeslot 0
Timeslot 1
A B C D
Timeslot 31
Parity Bit
(if enabled)
Timeslot 0
Parity Bit
(if enabled)
In Figure 43 and Figure 44, the Backplane Receive Interface has been programmed for Clock
Master: Full T1/E1 mode. BRFP[x] is set high for one BRCLK[x] period every frame. If
BRXSMFP=1 in T1 mode, BRFP[x] pulses on the superframe frame boundaries (i.e. once every
12 or 24 frame periods). If ROHM=0, BRXSMFP=0, and BRXCMFP=1 in E1 mode, BRFP[x]
pulses once every CRC Multiframe. If ALTBRFP=1, BRFP[x] pulses on every second indication of
either the frame or the superframe or multiframe boundary.
The BRIF’s CMS register bit is logic 0, indicating that the BRCLK[x] clock rate is the same as the
BRPCM[x] and BRSIG[x] data rates. BRPCM[x], BRSIG[x], and BRFP[x] are configured to update
on the falling edge of BRCLK[x] by setting the DE and FE bits of the BRIF Configuration register to
logic 0. The BRIF’s TSOFF[6:0], BOFF_EN, and BOFF[2:0] register bits are all logic 0: therefore,
BRFP[x] is aligned to the first bit of the frame. The BRIF’s CMODE and FPMODE register bits are
programmed to logic 0, indicating BRCLK[x] and BRFP[x] are outputs, respectively. If the BRIF’s
RPRTYE register bit is set to logic 1, then parity is inserted into the first bit position of the frame in
the BRPCM[x] and BRSIG[x] streams.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
410
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
In Figure 43, a 1.544 Mbit/s backplane in T1 mode is configured by setting the RATE[1:0] bits of
the BRIF Configuration register to ‘b00 and the E1/T1B bit of the Global Configuration register to
logic 0. In Figure 44, a 2.048 Mbit/s backplane in E1 mode is configured by setting the RATE[1:0]
bits of the BRIF Configuration register to ‘b01 and the E1/T1B bit of the Global Configuration
register to logic 1.
Figure 45: - T1 Receive Clock Master: Nx64Kbit/s Mode
BRCLK[x]
BRFP[x]
BRPCM[x]
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
BRSIG[x]
A B CD
A B CD
Channel 24
Channel 2
Figure 46: - E1 Receive Clock Master : Nx64Kbit/s Mode
BRCLK[x]
BRFP[x]
BRPCM[x]
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
BRSIG[x]
A B C D
A B CD
Timeslot 31
Timeslot 1
In Figure 45 and Figure 46, the BRIF Configuration register is programmed to select Nx64Kbit/s
mode. The BRIF’s CMS register bit is logic 0, indicating that the BRCLK[x] clock rate is the same
as the BRPCM[x] and BRSIG[x] data rates. The DE and FE register bits are programmed to logic
0, configuring BRPCM[x], BRSIG[x], and BRFP[x] to update on the falling edge of BRCLK[x]. The
BRIF’s CMODE and FPMODE register bits are programmed to logic 0, indicating BRCLK[x] and
BRFP[x] are outputs, respectively. The RPSC backplane receive control bytes are programmed to
extract the desired channels. In Figure 45, the backplane receive control bytes for T1 channels 2
and 24 are extracted. In Figure 46, the backplane receive control bytes for E1 channels 31 and 1
are extracted. BRCLK[x] is gapped so that it is only active for those channels whose associated
DTRKC bit is programmed to logic 0. If either BRXSMFP (ROHM, BRXCMFP, and BRXSMFP in
E1 mode) or ALTBRFP is configured, then BRFP[x] will pulse only during the appropriate frames.
If the DE register bit were programmed to logic 1, BRPCM[x] and BRSIG[x] would update on the
rising edge of BRCLK[x]. If the FE register bit were programmed to logic 1, BRFP[x] would update
on the rising edge of BRCLK[x].
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
411
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Figure 47: - T1/E1 Receive Clock Master : Clear Channel Mode
BRCLK[x]
BRPCM[x]
8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2
The Backplane Receive Interface is configured for the Clock Slave: Clear Channel mode by
programming the UNF bit of the Receive Options register to logic 1, the RXELSTBYP bit to logic
1, the RJATBYP bit optionally to logic 0, and the CMODE and FPMODE bits of the BRIF
Configuration register to logic 0. The BRIF’s CMS register bit is logic 0, indicating that the
BRCLK[x] clock rate is the same as the BRPCM[x] and BRSIG[x] data rates. When the DE bit is
programmed to logic 0 as shown in Figure 47, BRPCM[x] is clocked out on the falling edge of the
BRCLK[x] output. When the DE bit is programmed to logic 1, BRPCM[x] is updated on the rising
edge of BRCLK[x], and the functional timing is described by Figure 47 with the BRCLK[x] signal
inverted.
Figure 48: - T1 Receive Clock Slave: Full T1/E1 Mode
BRCLK[x]
BRFP[x]
BRPCM[x]
BRSIG[x]
1 2 3 4 5 6 7 8 F 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
A BC D
Channel 24
A BC D
Channel 1
A B C D
Channel 2
Parity Bit
(if enabled)
1 2 3 4 5 6 7 8 F 1 2 3 4 5 6 7 8 1
A B CD
Channel 24
A B CD
Channel 1
Parity Bit
(if enabled)
Figure 49: - E1 Receive Clock Slave: Full T1/E1 Mode
BRCLK[x]
BRFP[x]
BRPCM[x]
BRSIG[x]
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
A B CD
Timeslot 31
A B CD
Timeslot 0
Timeslot 1
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1
A B CD
Timeslot 31
Parity Bit
(if enabled)
Timeslot 0
Parity Bit
(if enabled)
The Backplane Receive Interface is programmed for Clock Slave: Full T1/E1 mode by
programming the RXELSTBYP bit of the Receive Options register to logic 0 and the CMODE and
FPMODE bits of the BRIF Configuration register to logic 1. The BRIF’s CMS register bit is logic 0,
indicating that the BRCLK[x] clock rate is the same as the BRPCM[x] and BRSIG[x] data rates. In
Figure 48 and Figure 49, the BRIF’s DE and FE bits are programmed to logic 1, indicating
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
412
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
BRPCM[x], BRSIG[x], and BRFP[x] are updated on the rising edge of BRCLK[x]. BRPCM[x] and
BRSIG[x] are frame-aligned to BRFP[x] so BRFP[x] need not be provided every frame. In Figure
48, the BRIF’s RATE[1:0] bits are ‘b00, indicating a 1.544 Mbit/s data rate. In Figure 49, the
BRIF’s RATE[1:0] bits are ‘b01, indicating a 2.048 Mbit/s data rate. If the BRIF’s RPRTYE register
bit is set to logic 1, parity is inserted into the first bit position of the frame in the BRPCM[x] and
BRSIG[x] streams.
Figure 50: - E1 Receive Clock Slave: Full T1/E1 Mode (CMS=1)
BRCLK[x]
BRFP[x]
BRPCM[x]
BRSIG[x]
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
A B CD
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1
A B CD
Timeslot 31
Timeslot 0
A B C D
Timeslot 1
Timeslot 31
Timeslot 0
Parity Bit
(if enabled)
Parity Bit
(if enabled)
The configuration in Figure 50 is the same as that of Figure 49 except that in this case the BRIF’s
CMS bit is logic 1, indicating that the BRCLK[x] clock rate is twice the data rate.
Figure 51: - T1 Receive 2.048 MHz Clock Slave: Full T1/E1 Mode
BRCLK[x]
BRFP[x]
BRPCM[x]
BRSIG[x]
1 2 3 4 5 6 7 8 F
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
A BCD
Channel 24
ABCD
Filler
Channel 1
A B CD
Channel 2
A B CD
Channel 3
Filler
Parity Bit
(if enabled)
The Backplane Receive Interface is programmed for Clock Slave: Full T1/E1 mode by
programming the RXELSTBYP bit of the Receive Options register to logic 0 and the CMODE and
FPMODE bits of the BRIF Configuration register to logic 1. The 2.048 MHz internally-gapped clock
mode is selected by programming the RATE[1:0] bits of the BRIF Configuration register to “01”
(the 2.048 Mbit/s mode) and the E1/T1B bit of the Global Configuration register to logic 0 (T1
mode). The above figure applies when the MAP bit of the BRIF Configuration register is
programmed to logic 0. The BRIF’s CMS register bit is logic 0, indicating that the BRCLK[x] clock
rate is the same as the BRPCM[x] and BRSIG[x] data rates. In the above figure, the BRIF’s DE
and FE bits are logic 0, indicating BRPCM[x] and BRSIG[x] is update on the falling edge of
BRCLK[x]. Because BRFP[x] is frame-aligned to BRFP[x], BRFP[x] need not be provided every
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
413
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
frame. BRPCM[x] and BRSIG[x] may be configured to carry a parity bit during the first bit of each
frame. The values of the filler bits will depend on the exact configuration of the COMET-QUAD,
and they will be included in the parity calculation.
Figure 52: - Concentration Highway Interface Timing, Example 1
1
BRCLK[x]
2
3
4
5
6
7
8
9
10
11
12
BRFP[x]
CER = 3
BRPCM[x]
bit 5 TS 31
bit 6 TS 31
bit 7 TS 31
bit 1 TS 0
bit 0 TS 0
bit 2 TS 0
bit 3 TS 0
bit 4 TS 0
bit 5 TS 0
bit 6 TS 0
bit 7 TS 0
bit 0 TS 1
Concentration Highway Interface (CHI) timing is configured by setting the BOFF_EN bit of the
BRIF Configuration register to logic 1. In Figure 52, the BRIF’s FE bit is set to logic 0 so that
BRFP[x] is sampled on the falling edge of BRCLK[x]. DE is set to logic 1 so that BRPCM[x] is
updated on the rising edge of BRCLK[x]. CMS is set to logic 0 so that the clock rate is equal to the
data rate. BOFF[2:0] is set to ‘b000 so that the transmit clock edge (CET) is equal to three (as
determined by the table in the register description of BOFF[2:0]) and BRPCM[x] is updated 3 clock
edges after BRFP[x] is sampled. TSOFF[6:0] is set to ‘b0000000 so that there is no timeslot
offset.
Figure 53: - Concentration Highway Interface Timing, Example 2
1
2
3
4
5
6
7
8
9
10
11
12
BRCLK[x]
BRFP[x]
CER = 8
BRPCM[x]
bit 5 TS 31
Don't Care
bit 6 TS 31
Don't Care
bit 7 TS 31
Don't Care
bit 0 TS 0
Don't Care
bit 1 TS 0
Don't Care
bit 2 TS 0
CHI timing is configured by setting BOFF_EN to a logic 1. In Figure 53, FE is set to logic 1 so that
BRFP[x] is sampled on the rising edge of BRCLK[x]. DE is set to logic 1 so that BRPCM[x] is
updated on the rising edge of BRCLK[x]. CMS is set to logic 1 so that the clock rate is equal to
two times the data rate. BOFF[2:0] is set to ‘b001 so that the transmit clock edge (CET) is equal to
8 (as determined by the table in the register description of BOFF[2:0]) and BRPCM[x] is updated 8
clock edges after BRFP[x] is updated. TSOFF[6:0] is set to ‘b0000000 so that there is no timeslot
offset.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
414
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
13.2 Backplane Receive H-MVIP Timing
Figure 54: - Receive Clock Slave: H-MVIP Mode
CMV8 MCLK
( 16 MHz)
CMVFPC
( 4 MHz )
CMVFPB
MVBRD
CASBRD
CCSBRD
B8
B1
B2
B3
B4
TS 127
B5
B6
B7
B8
B1
TS 0
TS 1
The timing relationship of the common 8M H-MVIP clock (CMV8MCLK), frame pulse clock
(CMVFPC), data (MVBRD, CASBRD or CCSBRD) and frame pulse (CMVFPB) signals in 8.192
Mbit/s H-MVIP operation with a type 0 frame pulse is shown in Figure 54. The falling edges of
each CMVFPC are aligned to a falling edge of the corresponding CMV8MCLK for 8.192 Mbit/s HMVIP operation. The COMET-QUAD samples CMVFPB low on the falling edge of CMVFPC and
references this point as the start of the next frame. The COMET-QUAD updates the data
provided on MVBRD, CASBRD and CCSBRD on every second falling edge of CMV8MCLK as
indicated for bit 2 (B2) of timeslot 0 (TS 0) in Figure 54. The first bit of the next frame is updated
on MVBRD, CASBRD and CCSBRD on the falling CMV8MCLK clock edge for which CMVFPB is
also sampled low. B1 is the most significant bit (first bit output on MVBRD, CASBRD, CCSBRD)
and B8 is the least significant bit (last bit output on MVBRD, CASBRD, CCSBRD) of each octet.
Figure 55: - T1 Receive Clock Slave: H-MVIP Mode
CMV8MCLK
CMVFPC
CMVFPB
MVBRD
CASBRD
1 2 3 4 5 6 7 8 F
F
F
1 2 3 4 5 6 7 8
F
A B C D
Timeslot 127
A B C D
Timeslot 0
Parity Bit
(if enabled)
Timeslot 1
Parity Bit
(if enabled)
Timeslot 2
Parity Bit
(if enabled)
Timeslot 3
Timeslot 4
Parity Bit
(if enabled)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
415
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Figure 56: - E1 Receive Clock Slave: H-MVIP Mode
CMV8MCLK
CMVFPC
CMVFPB
MVBRD
CASBRD
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
A B C D
Timeslot 127
A B C D
Timeslot 0
Parity Bit
(if enabled)
Timeslot 1
Parity Bit
(if enabled)
Timeslot 2
Parity Bit
(if enabled)
Timeslot 3
Timeslot 4
Parity Bit
(if enabled)
The Backplane Receive Interface is programmed for Clock Slave: H-MVIP mode. The required
settings are as follows. The RHMVIPEN bit of the Receive H-MVIP/CCS Enable register is set to
logic 1. In the BRIF Configuration register for each of the four quadrants, the bits are set as
follows: CMODE=1, DE=0, FE=1, CMS=1, RATE[1]=1, RATE[0]=1. In the BRIF Frame Pulse
Configuration register for each of the four quadrants, the bits are set as follows: MAP=0,
FPINV=0, FPMODE=1. In the BRIF Parity/F-bit Configuration register for each of the four
quadrants, the TRI bit is set to logic 1. In register address 033H, TSOFF[6:0]=’b0000000. In
register address 133H, TSOFF[6:0]=’b0000001. In register address 233H,
TSOFF[6:0]=’b0000010. In register address 333H, TSOFF[6:0]=’b0000011. Because the interface
is in clock slave mode, the Receive Elastic Store for each of the four quadrants is enabled by
setting the RXELSTBYP bits of the Receive Options registers to logic 0. Parity checking is
optional and controllable on a per-quadrant basis. For quadrants with parity checking enabled,
MVBRD and CASBRD will carry a parity bit during the first bit of each frame. The values of
unused bits will depend on the exact configuration of the COMET-QUAD, and they will be included
in the parity calculation.
In Figure 55, T1 mode is selected by setting the E1/T1B bit of the Global Configuration register to
logic 0. The T1 timeslot format is summarized in Table 94. In Figure 56, E1 mode is selected by
setting the E1/T1B bit of the Global Configuration register to logic 1. The E1 timeslot format is
summarized in Table 95.
13.3 Backplane Transmit Serial Clock and Data Interface Timing
By convention in the following functional timing diagrams, the first bit transmitted in each channel
shall be designated bit 1 and the last shall be designated bit 8. Each of the Backplane Receive
and Backplane Transmit Master and Clock Modes apply to both T1 and E1 configurations with the
exception of the 2.048MHz T1 Clock Slave Modes.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
416
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Figure 57: - Transmit Backplane: CMS=0, FE=1, DE=1, BTFP is Input
BTCLK[x]
BTFP[x]
BTPCM[x]
F-bit
Figure 58: - Transmit Backplane: CMS=0, FE=1, DE=0, BTFP is Input
BTCLK[x]
BTFP[x]
BTPCM[x]
F-bit
Figure 59: - Transmit Backplane: CMS=1, FE=1, DE=1, BTFP is Input
BTCLK[x]
BTFP[x]
BTPCM[x]
F-bit
Figure 60: - Transmit Backplane: CMS=1, FE=0, DE=1, BTFP is Input
BTCLK[x]
BTFP[x]
BTPCM[x]
F-bit
Figure 57, Figure 58, Figure 59, and Figure 60 above indicate the relationship between BTCLK[x],
BTFP[x], and BTPCM[x] with various settings of the BTIF’s CMS, FE, and DE register bits in T1
mode with BTFP[x] configured as an input. When FE and DE have the same value, the frame
pulse is sampled on the same clock edge as the data. When FE and DE have opposite values,
the frame pulse is sampled one clock edge before the data. In the above figures, the TSOFF[6:0],
BOFF_EN and BOFF[2:0] register bits are logic zero.
Figure 61: - Transmit Backplane: CMS=0, FE=1, DE=1, BTFP is Output
BTCLK[x]
BTFP[x]
BTPCM[x]
F-bit
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
417
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Figure 62: - Transmit Backplane: CMS=0, FE=1, DE=0, BTFP is Output
1
2
3
BTCLK[x]
BTFP[x]
F-bit
BTPCM[x]
Figure 61 and Figure 62 above indicate the relationship between BTCLK[x], BTFP[x], and
BTPCM[x] with two settings of the BTIF’s CMS, FE, and DE register bits in T1 mode with BTFP[x]
configured as an output. When FE and DE have the same value, the frame pulse is updated on
the same clock edge as the data is sampled. When FE and DE have opposite values, the frame
pulse is updated three clock edges before the data is sampled. In the above figures, the
TSOFF[6:0], BOFF_EN and BOFF[2:0] register bits are logic zero.
Figure 63: - T1 Transmit Clock Master : Full T1/E1 Mode
BTCLK[x]
BTFP[x]
BTPCM[x]
BTSIG[x]
1 2 3 4 5 6 7 8 F 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
A BC D
Channel 24
A BC D
Channel 1
1 2 3 4 5 6 7 8 F 1 2 3 4 5 6 7 8 1
A B CD
Channel 2
A B CD
Channel 24
Parity Bit
(if enabled)
A B C D
Channel 1
Parity Bit
(if enabled)
Figure 64: - E1 Transmit Clock Master : Full T1/E1 Mode
BTCLK[x]
BTFP[x]
BTPCM[x]
BTSIG[x]
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
A B CD
Timeslot 31
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1
A B C D
Timeslot 0
Timeslot 1
A B CD
Timeslot 31
Parity Bit
(if enabled)
Timeslot 0
Parity Bit
(if enabled)
The Transmit Interface is programmed to select the Clock Master: Full T1/E1 mode by
programming CMODE bit of the BTIF Configuration register to logic 0 and the FPMODE bit of the
BTIF Frame Pulse Configuration register to logic 0. The BTIF’s FE bit is logic 0, indicating that
BTFP[x] updates on the falling edge of BTCLK[x]. The BTIF’s DE bit is logic 0, indicating that
BTPCM[x] and BTSIG[x] are sampled on the falling edge of BTCLK[x]. BTFP[x] is set high for one
BTCLK[x] period every frame. If FPTYP=1, BTFP[x] pulses on the superframe frame boundaries.
This means pulsing for one bit period every 12 or 24 frame periods when configured for T1
operation or toggling high to mark bit 1 of frame 1 of every 16 frame Signaling Multiframe and
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
418
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
toggling low following bit 1 of every 16 frame CRC Multiframe when configured for E1 operation.
The BTIF’s TSOFF[6:0], BOFF_EN, and BOFF[2:0] register bits are all logic 0, indicating no
timeslot or bit offset on BTFP[x]. If BTIF’s FE bit were logic 1, and BTIF’s DE bit were logic 0, then
the BTFP[x] frame pulse would occur half a clock cycle earlier.
BTSIG[x] should carry the signaling bits for each channel in bits 5, 6, 7 and 8. The T1 or E1
transmitter will insert these signaling bits into the data stream. If parity checking is enabled, a
parity bit should be inserted on BTPCM[x] and BTSIG[x] in the first bit of each frame. The parity
operates on all bits in the BTPCM[x] and BTSIG[x] streams, including the unused bits on
BTSIG[x].
Figure 65: - T1 Transmit Clock Master: Nx64Kbit/s Mode (DE=1, FE=0)
BTCLK[x]
BTFP[x]
BTPCM[x]
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
BTSIG[x]
A BCD
A BCD
Channel 24
Channel 1
Figure 66: - E1 Transmit Clock Master : Nx64Kbit/s Mode (DE=1, FE=0)
BTCLK[x]
BTFP[x]
BTPCM[x]
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
BTSIG[x]
A BCD
ABCD
Timeslot 1
Timeslot 31
Figure 67: - T1 Transmit Clock Master: Nx64Kbit/s Mode (DE=0, FE=0)
BTCLK[x]
BTFP[x]
BTPCM[x]
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
BTSIG[x]
ABCD
A BCD
Channel 24
Channel 1
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
419
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Figure 68: - E1 Transmit Clock Master: Nx64Kbit/s Mode (DE=0, FE=0)
BTCLK[x]
BTFP[x]
BTPCM[x]
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
BTSIG[x]
A BCD
A BCD
Timeslot 31
Timeslot 1
The BTIF Configuration register is programmed to select Nx64Kbit/s mode. The TPSC PCM Data
Control bytes are programmed to insert the desired channels. In Figure 65 and Figure 67, the
PCM Data Control bytes for T1 channels 1 and 24 are configured to insert BTPCM[x] data into
these channels. In Figure 66 and Figure 68, the PCM Data Control bytes for E1 channels 1 and
31 are configured to insert BTPCM[x] data into these channels. BTCLK[x] is gapped so that it is
only active for those channels with the associated IDLE_CHAN bit cleared (logic 0). The
remaining channels (with IDLE_CHAN set) contain the per-channel idle code as defined in the
associated Idle Code byte.
In Figure 65 and Figure 66, the BTIF’s DE bit is logic 1, indicating that BTPCM[x] and BTSIG[x]
are sampled on the rising edge of BTCLK[x]; the BTIF’s FE bit is logic 0, indicating that BTFP[x]
updates on the falling edge of BTCLK[x]. Since BTFP[x] is an output and DE and FE have
opposite values, BTFP[x] updates three clock edges before where the first bit of the frame would
be sampled (assuming the clock were not gapped). In Figure 67 and Figure 68, the BTIF’s DE bit
is logic 0, indicating that BTPCM[x] and BTSIG[x] are sampled on the falling edge of BTCLK[x];
the BTIF’s FE bit is logic 0, indicating that the BTFP[x] output updates on the falling edge of
BTCLK[x].
The level of the clock gap is determined by the BTIF’s DE bit. If DE is logic 0, the clock gap is
logic 0; if DE is logic 1, the clock gap is logic 1.
If DE and FE were both logic 1, the functional timing is as described in Figure 65 and Figure 66
but with BTFP[x] updating three clock edges later (assuming the clock were not gapped). If DE
were logic 0 and FE logic 1, then the functional timing is as described in Figure 67 and Figure 68
but with BTFP[x] updating three clock edges earlier (assuming the clock were not gapped).
Figure 69: - T1/E1 Transmit Clock Master : Clear Channel Mode
BTCLK[x]
BTPCM[x]
8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2
The Backplane Transmit Interface is configured for the Clock Master: Clear Channel mode by
programming the CMODE bit of the BTIF Configuration register to logic 0 and the FDIS bit of the
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
420
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Transmit Framing and Bypass Options register to logic 1. BTPCM[x] is clocked in on the rising
edge of the BTCLK[x] output. When the DE bit of the BTIF Configuration register is set to logic 0,
then BTPCM[x] is sampled on the falling edge of BTCLK[x], and the functional timing is described
with the BTCLK signal inverted.
Figure 70: - T1 Transmit Clock Slave: Full T1/E1 mode
BTCLK[x]
BTFP[x]
(FPTYP=0)
BTFP[x]
(FPTYP=1)
BTPCM[x]
BTSIG[x]
1 2 3 4 5 6 7 8 F 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
A BC D
Channel 24
A BC D
Channel 1
1 2 3 4 5 6 7 8 F 1 2 3 4 5 6 7 8 1
A B CD
Channel 2
A B C D
Channel 24
A B CD
Channel 1
Parity Bit
(if enabled)
Parity Bit
(if enabled)
Figure 71: - E1 Transmit Clock Slave : Full T1/E1 Mode
BTCLK[x]
BTFP[x]
(FPTYP=0)
BTFP[x]
(FPTYP=1)
BTPCM[x]
BTSIG[x]
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
A B CD
Timeslot 31
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1
A B C D
Timeslot 0
Timeslot 1
A B CD
Timeslot 31
Parity Bit
(if enabled)
Timeslot 0
Parity Bit
(if enabled)
The Backplane Transmit Interface is configured for the Clock Slave: Full T1/E1 mode by
programming the CMODE bit of the BTIF Configuration register to logic 1 and the FPMODE of the
BTIF Frame Pulse Configuration register to logic 1. The BTIF’s DE and FE bits are logic 1,
indicating that BTPCM[x], BTSIG[x], and BTFP[x] are sampled on the rising edge of BTCLK[x].
BTSIG[x] should carry the signaling bits for each channel in bits 5, 6, 7 and 8. The T1 or E1
transmitter will insert these signaling bits into the data stream. If parity checking is enabled in T1
or E1 mode, a parity bit should be inserted on BTPCM[x] and BTSIG[x] in the first bit of each
frame. The parity operates on all bits in the BTPCM[x] and BTSIG[x] streams, including the
unused bits on BTSIG[x].
In T1 mode, Figure 70, the FPTYP bit is programmed to logic 1 in the BTIF Frame Pulse
Configuration register, so that BTFP[x] must pulse once every 12 or 24 frames (for SF and ESF,
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
421
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
respectively) on the first frame bit of the superframe. When the FPTYP bit is programmed to logic
0, the BTFP[x] input should pulse high to mark the F-bit of each frame.
In E1 mode, BTFP[x] may be chosen to indicate alignment of every frame or the composite CRC
and Signaling multiframe alignment as shown in Figure 71, by programming the FPTYP bit in the
BTIF Frame Pulse Configuration register.
Figure 72: - T1 Transmit 2.048 MHz Clock Slave : Full T1/E1 Mode
BTCLK[x]
BTFP[x]
BTPCM[x]
BTSIG[x]
1 2 3 4 5 6 7 8 F
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
A BCD
Channel 24
A BCD
Filler
Channel 1
A BCD
Channel 2
A B CD
Channel 3
Filler
Parity Bit
(if enabled)
The Backplane Transmit Interface is configured for the Clock Slave: Full T1/E1 Mode by
programming the BTIF’s CMODE and FPMODE register bits to logic 1. The 2.048 MHz internally
gapped clock mode is selected by programming RATE[1]=0 and RATE[0]=1 in the BTIF
Configuration register. In Figure 72, BTFP[x] is configured for superframe alignment by writing
FPTYP to logic 1 in the BTIF Frame Pulse Configuration register, so that the BTFP[x] input must
pulse once every 12 or 24 frames (for SF and ESF, respectively) on the first F-bit of the multiframe
to specify superframe alignment, instead of once every frame to specify frame alignment. If
FPTYP is logic 0, the BTFP[x] input should pulse high to mark the F-bit of each frame.
BTSIG[x] should carry the signaling bits for each channel in bits 5, 6, 7 and 8. The T1 or E1
transmitter will insert these signaling bits into the data stream.. If parity checking is enabled, a
parity bit should be inserted on BTPCM[x] and BTSIG[x] in the first bit of each frame. The values
of the BTPCM[x] and BTSIG[x] don’t-care bits are not important, except that they will be used in
the backplane parity check if it is enabled.
Figure 73: - T1/E1 Transmit Clock Slave : Clear Channel Mode
BTCLK[x]
BTPCM[x]
8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2
The Backplane Transmit Interface is configured for the Clock Slave: Clear Channel mode by
programming FDIS=1 in the Transmit Framing and Bypass Options register. BTPCM[x] is clocked
in on the rising edge of the BTCLK[x] input. When DE=0 in the BTIF Configuration register,
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
422
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
BTPCM[x] is sampled on the falling edge of BTCLK[x], and the functional timing is described by
Figure 73 with the BTCLK[x] signal inverted.
Figure 74: - Concentration Highway Interface Timing, Example1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
BTCLK[x]
BTFP[x]
CER = 16
BTPCM[x]
bit 7 TS 31
bit 1 TS 0
bit 0 TS 0
bit 2 TS 0
bit 3 TS 0
bit 4 TS 0
bit 5 TS 0
bit 6 TS 0
bit 7 TS 0
bit 0 TS 1
bit 1 TS 1
bit 2 TS 1
Concentration Highway Interface (CHI) timing is configured by setting the BOFF_EN bit of the
BTIF Configuration register to logic 1. In Figure 74, the BTIF’s DE and FE register bits are set to
logic 0 so that BTPCM[x], BTSIG[x], and BTFP[x] are sampled on the falling edge of BTCLK[x].
CMS is set to logic 0 so that the clock rate is equal to the data rate. BOFF[2:0] is set to ‘b110 so
that the receive clock edge (CER) is equal to 16 (as determined by the table in the BTIF Bit Offset
register description of BOFF[2:0]) and BTPCM[x] (and BTSIG[x]) is sampled 16 clock edges after
BTFP[x] is sampled. TSOFF[6:0] is set to ‘b0000000 so that there is no timeslot offset. In the
above example, if TSOFF[6:0] were set to ‘b0011111, then BTPCM[x] would be sampled an
additional 31 timeslots later, exactly one E1 frame after BTFP[x] was sampled as logic 1. In the
above example, if TSOFF[6:0] were set to ‘b0010111, then BTPCM[x] would be sampled an
additional 23 timeslots later, exactly one T1 frame after BTFP[x] was sampled as logic 1.
Figure 75: - Concentration Highway Interface Timing, Example 2
1
2
3
4
5
6
7
8
9
10
11
12
BTCLK[x]
BTFP[x]
CER = 11
BTPCM[x]
bit 5 TS 31
bit 6 TS 31
bit 7 TS 31
bit 0 TS 0
bit 1 TS 0
bit 2 TS 0
Concentration Highway Interface (CHI) timing is configured by setting the BOFF_EN bit of the
BTIF Configuration register to logic 1. In Figure 75, the BTIF’s FE register bit is set to logic 1 so
that BTFP[x] is sampled on the rising edge of BTCLK[x]. The DE register bit is set to logic 0 so
that BTPCM[x] is sampled on the falling edge of BTCLK[x]. CMS is set to logic 1 so that the clock
rate is equal to two times the data rate. BOFF[2:0] is set to ‘b001 so that the receive clock edge
(CER) is equal to 11 (as determined by the table in the BTIF Bit Offset register description of
BOFF[2:0]) and BTPCM[x] is sampled 11 clock edges after BTFP[x] is sampled. TSOFF[6:0] is set
to ‘b0000000 so that there is no timeslot offset.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
423
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
13.4 Backplane Transmit H-MVIP Timing
Figure 76: - Transmit Clock Slave: H-MVIP Mode
CMV 8MCLK
(16 MHz)
CMV FPC
(4 MHz)
CMV FPB
MV BTD
CA SBTD
CCSBTD
B8
B1
B2
B3
B4
TS 127
B5
B6
B7
B8
TS 0
B1
TS 1
The timing relationship of the common 8M H-MVIP clock (CMV8MCLK), frame pulse clock
(CMVFPC), data (MVBTD, CASBTD or CCSBTD) and frame pulse (CMVFPB) signals configured
for 8.192 Mbit/s H-MVIP operation with a type 0 frame pulse is shown in Figure 76. The falling
edges of each CMVFPC are aligned to a falling edge of the corresponding CMV8MCLK for 8.192
Mbit/s H-MVIP operation. The COMET-QUAD samples CMVFPB low on the falling edge of
CMVFPC and references this point as the start of the next frame. The COMET-QUAD samples
the data provided on MVBTD, CASBTD and CCSBTD at the ¾ point of the data bit using the
rising edge of CMV8MCLK as indicated for bit 1 (B1) of timeslot 1 (TS 0) in Figure 76. B1 is the
most significant bit and B8 is the least significant bit of each octet.
Figure 77: - T1 Transmit Clock Slave: H-MVIP Mode
CMV8MCLK
CMVFPC
CMVFPB
MVBTD
1 2 3 4 5 6 7 8 F
CCSBTD
1 2 3 4 5 6 7 8
CASBTD
A B C D
Timeslot 127
F
F
1 2 3 4 5 6 7 8
F
A B C D
Timeslot 0
Parity Bit
(if enabled)
Timeslot 1
Parity Bit
(if enabled)
Timeslot 2
Parity Bit
(if enabled)
Timeslot 3
Timeslot 4
Parity Bit
(if enabled)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
424
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Figure 78: - E1 Transmit Clock Slave: H-MVIP Mode
CMV8MCLK
CMVFPC
CMVFPB
MVBTD
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
CCSBTD
1 2 3 4 5 6 7 8
CASBTD
A B CD
Timeslot 127
A B C D
Timeslot 0
Parity Bit
(if enabled)
Timeslot 1
Parity Bit
(if enabled)
Timeslot 2
Parity Bit
(if enabled)
Timeslot 3
Timeslot 4
Parity Bit
(if enabled)
The Backplane Transmit Interface is programmed for Clock Slave: H-MVIP mode. The required
settings are as follows. The THMVIPEN bit of the Transmit H-MVIP/CCS Enable and
Configuration register is set to logic 1. In the BTIF Configuration register for each of the four
quadrants, the bits are set as follows: CMODE=1, DE=1, FE=1, CMS=1, RATE[1]=1, RATE[0]=1.
In the BTIF Frame Pulse Configuration register, FPINV=0, FPTYP=0, and FPMODE=1. In register
address 043H, TSOFF[6:0]=’b0000000. In register address 143H, TSOFF[6:0]=’b0000001. In
register address 243H, TSOFF[6:0]=’b0000010. In register address 343H,
TSOFF[6:0]=’b0000011. Parity checking is optionally performed on the MVBTD and CASBTD
streams and is controllable on a per-quadrant basis. For quadrants with parity checking enabled,
MVBTD and CASBTD are to carry a parity bit during the first bit of each frame. Common Channel
Signaling (CCS) insertion is optionally enabled via the TCCSEN bit of the Transmit H-MVIP/CCS
Enable and Configuration register. If enabled, the OR bit of the TX-ELST CCS Configuration must
be programmed to logic 0 for T1 mode or logic 1 for E1 mode.
In Figure 77, T1 mode is selected by setting the E1/T1B bit of the Global Configuration register to
logic 0. The T1 MVBTD and CASBTD timeslot format is summarized in Table 94. The T1
CCSBTD timeslot format is summarized in Table 96. In Figure 78, E1 mode is selected by setting
the E1/T1B bit of the Global Configuration register to logic 1. The E1 MVBTD and CASBTD
timeslot format is summarized in Table 95. The E1 CCSBTD timeslot format is summarized in
Table 97.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
425
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
14
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
ABSOLUTE MAXIMUM RATINGS
Maximum ratings are the worst case limits that the device can withstand without sustaining
permanent damage. They are not indicative of normal mode operation conditions.
Table 98:
- Absolute Maximum Ratings
Parameter
Symbol
Ambient Temperature under
Bias
Units
-40 to +85
°C
Storage Temperature
TST
-40 to +125
°C
Supply Voltage
VDDC25
-0.3 to + 3.5
VDC
Supply Voltage
VDDall331
VDC
Voltage on Any Pin
VIN
-0.3 to + 4.6
-0.3 to VDDall33 +
0.3
VDC
Static Discharge Voltage
±1000
V
Latch-Up Current
±100
mA
±20
mA
+230
°C
+150
°C
DC Input Current
IIN
Lead Temperature
Junction Temperature
1
Value
TJ
The COMET-QUAD 3.3 Volt digital and analog power pins are collectively referred to as VDDall33.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
426
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
15
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
D.C. CHARACTERISTICS
TA = -40°C to TJ = +105°C, VDDall331 = 3.3V ±5%, VDDC25 = 2.5V ±0.2V
(Typical Conditions: TA = 25°C, VDDall33 = 3.3V, VDDC25 = 2.5V)
Table 99:
- D.C. Characteristics
Symbol
Parameter
Min
Typ
Max
Units
Conditions
VDD33,
Power Supply
3.135
3.3
3.465
Volts
VDDC25
Power Supply
2.3
2.5
2.7
Volts
VIL
Input Low Voltage
0
0.8
Volts
Guaranteed Input LOW Voltage
VIH
Input High Voltage
2.0
Volts
Guaranteed Input HIGH Voltage
Output or
0
Volts
VDD = min, IOL = -4mA for D[7:0],
VDDQ33,
TAVD1,
TAVD2,
CAVD,
RAVD1,
RAVD2,
QAVD
VOL
0.1
0.4
Bidirectional Low
BRCLK[1:4], BTCLK[1:4], and INTB
Voltage
and -2mA for others.
Note 3
VOH
Output or
VDDall33
2.4
Volts
VDD = min, IOH = 4mA for D[7:0],
Bidirectional High
BRCLK[1:4], BTCLK[1:4], and INTB
Voltage
and 2mA for others.
Note 3
VT+
Reset Input High
2.0
Volts
TTL Schmidt
Voltage
VT-
Reset Input Low
0.75
Volts
Voltage
VTH
Reset Input
0.6
Volts
Hysteresis Voltage
1
IILPU
Input Low Current
+10
+150
µA
VIL = GND. Notes 1, 3
IIHPU
Input High Current
-10
+10
µA
VIH = VDD. Notes 1, 3
IILPD
Input Low Current
-10
+10
µA
VIL = GND. Notes 5, 3
IIHPD
Input High Current
-150
-10
µA
VIH = VDD. Notes 5, 3
The COMET-QUAD 3.3 Volt digital and analog power pins are collectively referred to as VDDall33.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
427
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Symbol
Parameter
Min
IIL
Input Low Current
IIH
Input High Current
CIN
Input Capacitance
Typ
Max
Units
Conditions
-10
+10
µA
VIL = GND. Notes 2, 3
-10
+10
µA
VIH = VDD. Notes 2, 3
5
pF
Excluding Package, Package Typically
2 pF
COUT
Output
5
pF
Capacitance
CIO
Bidirectional
2 pF
5
pF
Capacitance
IDDOP33
3.3 Volt Operating
Excluding Package, Package Typically
Excluding Package, Package Typically
2 pF
441
Current
VDDall33 = 3.3 V, VDDC25 = 2.5 V,
85°C ambient temperature, T1 mode,
transmitting 50% ones density, short
haul 0-110 ft, digital outputs unloaded.
IDDOP25
2.5 Volt Operating
38
Current
VDDall33 = 3.3 V, VDDC25 = 2.5 V,
85°C ambient temperature, T1 mode,
transmitting 50% ones density, short
haul 0-110 ft, digital outputs unloaded.
Notes on D.C. Characteristics:
1. Input pin or bi-directional pin with internal pull-up resistor.
2. Input pin or bi-directional pin without internal pull-up or pull-down resistor
3. Negative currents flow into the device (sinking), positive currents flow out of the device
(sourcing).
4. Typical values are given as a design aid. This product is not tested to the typical values given
in the datasheet.
5. Input pin or bi-directional pin with internal pull-down resistor.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
428
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
16
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS
(TA = -40°C to TJ = +105°C, VDDall331 = 3.3V ±5%, VDDC25 = 2.5V ±0.2V)
Table 100:
1
- Microprocessor Interface Read Access
Symbol
Parameter
Min
Typ
tSAR
Address to Valid Read Set-up Time
tHAR
Address to Valid Read Hold Time
5
ns
tSALR
Address to Latch Set-up Time
10
ns
tHALR
Address to Latch Hold Time
10
ns
tVL
Valid Latch Pulse Width
20
ns
tSLR
Latch to Read Set-up
0
ns
tHLR
Latch to Read Hold
tPRD
Valid Read to Valid Data Propagation Delay
45
ns
tZRD
Valid Read Negated to Output Tri-state
20
ns
tZINTH
Valid Read Negated to Output Tri-state
Max
10
ns
5
50
Units
ns
ns
The COMET-QUAD 3.3 Volt digital and analog power pins are collectively referred to as VDDall33.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
429
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Figure 79:
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- Microprocessor Interface Read Timing
tSAR
A[10:0]
Valid
Address
tHAR
tS ALR
tVL
tHALR
ALE
tHLR
tSLR
(CSB+RDB)
tZ INTH
INTB
tZ RD
tPRD
D[7:0]
Valid Data
Notes on Microprocessor Interface Read Timing:
1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the
reference signal to the 1.4 Volt point of the output.
2. Maximum output propagation delays are measured with a 100 pF load on the Microprocessor
Interface data bus, (D[7:0]).
3. A valid read cycle is defined as a logical OR of the CSB and the RDB signals.
4. In non-multiplexed address/data bus architectures, ALE should be held high so parameters
tSALR, tHALR, tVL, and tSLR are not applicable.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
430
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
5. Parameter tHAR is not applicable if address latching is used.
6. When a set-up time is specified between an input and a clock, the set-up time is the time in
nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
7. When a hold time is specified between an input and a clock, the hold time is the time in
nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
Table 101:
Symbol
- Microprocessor Interface Write Access
Parameter
Min
Typ
tSAW
Address to Valid Write Set-up Time
10
ns
tSDW
Data to Valid Write Set-up Time
20
ns
tSALW
Address to Latch Set-up Time
10
ns
tHALW
Address to Latch Hold Time
10
ns
tVL
Valid Latch Pulse Width
20
ns
tSLW
Latch to Write Set-up
0
ns
tHLW
Latch to Write Hold
tHDW
Data to Valid Write Hold Time
5
ns
tHAW
Address to Valid Write Hold Time
5
ns
TVWR
Valid Write Pulse Width
40
ns
5
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
Max
Units
ns
431
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Figure 80:
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- Microprocessor Interface Write Timing
A[9:0]
Valid Address
tS ALW
tV L
tH ALW
tS LW
tHLW
ALE
tSAW
tVWR
tH AW
(CSB+WRB)
tS DW
D[7:0]
tH DW
Valid Data
Notes on Microprocessor Interface Write Timing:
1. A valid write cycle is defined as a logical OR of the CSB and the WRB signals.
2. In non-multiplexed address/data bus architectures, ALE should be held high so parameters
tSALW, tHALW, tVL, tSLW and tHLW are not applicable.
3. Parameter tHAW is not applicable if address latching is used.
4. When a set-up time is specified between an input and a clock, the set-up time is the time in
nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
5. When a hold time is specified between an input and a clock, the hold time is the time in
nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
432
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
17
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
COMET-QUAD TIMING CHARACTERISTICS
17.1 RSTB Timing
(TA = -40°C to TJ = +105°C VDDall331 = 3.3V ±5%, VDDC25 = 2.5V ±0.2V)
Table 102:
- RTSB Timing
Symbol
Description
Min
tVRSTB
RSTB Pulse Width
100
Figure 81:
Max
Units
ns
- RSTB Timing
tV RSTB
RSTB
17.2 XCLK Input Timing
Table 103:
- XCLK Input (Figure 82)
Symbol
Description
Min
Max
Units
tXCLK
XCLK Frequency, typically 1.544 MHz or
2.048 MHz ± 100ppm
1.543
2.049
MHz
tLXCLK
XCLK Low Pulse Width1
160
ns
tHXCLK
XCLK High Pulse Width1
160
ns
Figure 82:
- XCLK Input Timing
t H XCLK
XCLK
t L XCLK
1
t XCLK
The COMET-QUAD 3.3 Volt digital and analog power pins are collectively referred to as VDDall33.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
433
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
17.3 Transmit Backplane Interface (Figure 83, Figure 84)
(TA = -40°C to TJ = +105°C, VDDall331 = 3.3V ±5%, VDDC25 = 2.5V ±0.2V)
Table 104
Symbol
Description
Min
Typ
Max
Units
BTCLK Average Frequency2
(T1 mode, CMS=0, RATE[1:0]=’b00)
Typ – 200
ppm
1.544
Typ + 200
ppm
MHz
BTCLK Average Frequency2
(CMS=0, RATE[1:0]=’b01)
Typ – 200
ppm
2.048
Typ + 200
ppm
MHz
BTCLK Average Frequency2
(T1 mode, CMS=1, RATE[1:0]=’b00)
Typ – 200
ppm
3.088
Typ + 200
ppm
MHz
BTCLK Average Frequency2
(CMS=1, RATE[1:0]=’b01)
Typ – 200
ppm
4.096
Typ + 200
ppm
MHz
BTCLK Duty Cycle1
35
65
%
tSBTCLK
BTCLK to Backplane Input Set-up
Time3
20
ns
tHBTCLK
BTCLK to Backplane Input Hold
Time4
20
ns
tPBTFP
BTCLK to BTFP Output Propagation
Delay5,6
-20
Figure 83
1
- Transmit Backplane Interface
50
ns
- Backplane Transmit Input Timing Diagram
The COMET-QUAD 3.3 Volt digital and analog power pins are collectively referred to as VDDall33.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
434
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
BTPCM,
BTSIG,
BTFP (input)
Valid
tS BTCLK
tHBTCLK
BTCLK
Inputs Sampled on Rising Edge
BTPCM,
BTSIG,
BTFP (input)
Valid
tS BTCLK
tHBTCLK
BTCLK
Inputs Sampled on Falling Edge
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
435
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
Figure 84
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- Backplane Transmit Output Timing Diagram
BTCLK
BTFP (output)
Valid
tPBTF P
Fram e Pulse O utput on Rising Edge
BTCLK
BTFP (output)
Valid
tPBTF P
Fram e Pulse Output on Falling Edge
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
436
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
17.4 Receive Backplane Interface (Figure 85, Figure 86)
(TA = -40°C to TJ = +105°C, VDDall331 = 3.3V ±5%, VDDC25 = 2.5V ±0.2V)
Table 105
Symbol
1
- Receive Backplane Interface
Description
Min
Typ
Max
Units
BRCLK Average Frequency2
(T1 mode, CMS=0, RATE[1:0]=’b00)
Typ – 200
ppm
1.544
Typ + 200
ppm
MHz
BRCLK Average Frequency2
(CMS=0, RATE[1:0]=’b01)
Typ – 200
ppm
2.048
Typ + 200
ppm
MHz
BRCLK Average Frequency2
(T1 mode, CMS=1, RATE[1:0]=’b00)
Typ – 200
ppm
3.088
Typ + 200
ppm
MHz
BRCLK Average Frequency2
(CMS=1, RATE[1:0]=’b01)
Typ – 200
ppm
4.096
Typ + 200
ppm
MHz
BRCLK Duty Cycle1
35
65
%
tSBRFP
BRFP to BRCLK Input Set-up Time3
20
ns
tHBRFP
BRFP to BRCLK Input Hold Time4
20
ns
tPBRCLK
BRCLK to Backplane Output Signals
Propagation Delay5,6
-20
50
ns
The COMET-QUAD 3.3 Volt digital and analog power pins are collectively referred to as VDDall33.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
437
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
Figure 85
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- Backplane Receive Input Timing Diagram
BRFP (input)
Valid
tS BRFP
tH BRFP
BRCLK
Fram e Pulse Sam pled on Rising Edge
BRFP (input)
Valid
tS BRFP
tH BRFP
BRCLK
Fram e Pulse Sam pled on Falling Edge
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
438
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
Figure 86
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- Backplane Receive Output Timing Diagram
BRCLK
BRFP (output),
BRPCM, BRSIG
Valid
tPBRCLK
Output on Rising Edge
BRCLK
BRFP (output),
BRPCM, BRSIG
Valid
tPBRCLK
Output on Falling Edge
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
439
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Table 106:
Symbol
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- H-MVIP Transmit Timing (Figure 87)
Description
Min
Max
Units
CMV8MCLK Frequency2,8
16.368
16.400
MHz
CMV8MCLK Duty Cycle1
40
60
%
CMVFPC Frequency9
4.092
4.100
MHz
CMVFPC Duty Cycle1
40
60
%
tPMVC
CMV8MCLK to CMVFPC skew
-10
10
ns
tSHMVBTD
MVBTD, CASBTD, CCSBTD Set-Up Time3
5
ns
tHHMVBTD
MVBTD, CASBTD, CCSBTD Hold Time4
5
ns
tSMVFPB
CMVFPB Set-Up Time3
5
ns
tHMVFPB
CMVFPB Hold Time4
5
ns
Figure 87:
- H-MVIP Transmit Data and Frame Pulse Timing
CMVFPC
tS MVFPB
tHMVFPB
CMVFPB
tP MVC
CMV8MCLK
MVBTD
CASBTD
CCSBTD
tS HMVBTD
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
tHHMVBTD
440
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Table 107:
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- H-MVIP Receive Timing (Figure 88)
Symbol
Description
Min
Max
Units
tPHMVBRD
CMV8MCLK Low to MVBRD, CASBRD,
CCSBRD Valid5,6
5
30
ns
Figure 88:
- H-MVIP Receive Data Timing
CMV8 MCL K
t PHMVBRD
MVBRD
CASBRD
CCSBRD
Table 108:
Symbol
- Transmit Line Interface Timing (Figure 89)
Description
Min
Max
Units
CTCLK Frequency (when used for TJAT
Reference), typically 1.544 MHz ±130 ppm for T1
operation or 2.048 MHz ±50 ppm for E1 operation10
1.5
2.1
MHz
tHCTCLK
CTCLK High Duration1,10 (when used for TJAT
Reference)
160
ns
tLCTCLK
CTCLK Low Duration1,10 (when used for TJAT
Reference)
160
ns
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
441
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Figure 89:
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- Transmit Line Interface Timing
tHCTCLK
CTCLK
tLCTCLK
Table 109:
- JTAG Port Interface
Symbol
Description
tCTCLK
Min
TCK Frequency
Max
Units
1
MHz
60
%
TCK Duty Cycle
40
tSTMS
TMS Set-up time to TCK
50
ns
tHTMS
TMS Hold time to TCK
50
ns
tSTDI
TDI Set-up time to TCK
50
ns
tHTDI
TDI Hold time to TCK
50
ns
tPTDO
TCK Low to TDO Valid
2
tVTRSTB
TRSTB Pulse Width
100
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
50
ns
ns
442
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
Figure 90:
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
- JTAG Port Interface Timing
TCK
tS TMS
tH TMS
tS TDI
tH TDI
TMS
TDI
TCK
tP TDO
TDO
tV TRSTB
TRSTB
Notes on COMET-QUAD Timing:
1. High pulse width is measured from the 1.4 Volt points of the rise and fall ramps. Low pulse width is
measured from the 1.4 Volt points of the fall and rise ramps.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
443
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
2. Instantaneous period variation on BRCLK, BTCLK, and CMV8MCLK of +/- 8% (typical) can be
tolerated by the device, as long as the frequency specification of +/- 200ppm is complied with. These
specifications correspond to nominal XCLK input frequencies.
3. When a set-up time is specified between an input and a clock, the set-up time is the time in
nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
4. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds
from the 1.4 Volt point of the clock to the 1.4 Volt point of the input.
5. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference
signal to the 1.4 Volt point of the output.
6. Maximum and minimum output propagation delays are measured with a 50 pF load on the output.
7. XCLK accuracy is ± 100 ppm.
8. Measured between any two CMV8MCLK falling edges.
9. Measured between any two CMVFPC falling edges.
10. CTCLK[x] can be a jittered clock signal subject to the minimum high and low durations tHCTCLK,
tLCTCLK. These durations correspond to nominal XCLK input frequency.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
444
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
18
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
ORDERING AND THERMAL INFORMATION
Table 110:
- Ordering Information
Part No.
Description
PM4354-PI
208 Plastic Ball Grid Array (PBGA)
This product is designed to operate over a wide temperature range and is suited for
industrial applications such as outside plant equipment, as long as suitable thermal
management precautions are taken.
Table 111:
- Thermal Information
0
Maximum long-term operating junction temperature
to ensure adequate long-term life
Maximum junction temperature for short-term excursions with guaranteed
1
continued functional performance This condition will typically be reached when
local ambient reaches 85 Deg C.
105 C
Minimum ambient temperature
-40 C
0
125 C
0
2
Thermal Resistance vs Air Flow
Airflow
0
ΘJA ( C/W)
Device Compact Model
Natural Convection
200 LFM
400 LFM
26.3
20.1
17.0
3
0
3.3
0
13.7
ΘJT ( C/W)
ΘJB ( C/W)
Operating power is dissipated in package (watts) at
worst case power supply.
Conditions: T1 short haul 0 – 110 ft, transmitting 50%
ones, 85C ambient temperature, 3.465V / 2.625V
power supplies, digital outputs unloaded.
Power (watts)
Ambient
ΘJT
Junction
Device
Compact
Model
ΘJB
Board
1.61
Notes
1.
Short-term is understood as the definition stated in Bellcore Generic Requirements GR-63-Core.
2.
ΘJA , the total junction to ambient thermal resistance as measured according to JEDEC Standard JESD51
(2S2P)
3.
ΘJB, the junction-to-board thermal resistance and ΘJT
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
445
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
19
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
MECHANICAL INFORMATION
0.20
D
D1
(4X )
A
A1 BALL
CORNER
0.30 M C A B
0.10 M C
B
A1 BALL PAD
CORNER
16
14 12 10 8
6
4
2
15 13 11 9
7 5
3
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
e
A1 BALL
INDICATOR
E1
E
J
45ο CHAMFER
4 PLACES
I
BOTTOM VIEW
TOP VIEW
"d" DIA.
3 PLACES
30ο TYP
A
C
b
bbb C
aaa C
C
A1
SEATING PLANE
A2
SIDE VIEW
NOTES: 1) A LL DIMENSIONS IN MILLIMETER.
2) DIMENSION aaa DENOTES COPLA NA RITY .
3) DIMENSION bbb DENOTES PA RA LLEL.
1.35
1.55
0.30
0.75
14.50
0.30
0.50
14.50
1.56
1.76
0.40
0.80
17.00 15.00
0.36
0.56
17.00 15.00
1.75
1.97
0.50
0.85
15.70
0.40
0.62
15.70
0.40
1.00
1.00
0.50
0.60
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
1.00
1.00
0.15
0.35
446
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
NOTES
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
447
PM4354 COMET-QUAD
RELEASED
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
CONTACTING PMC-SIERRA, INC.
PMC-Sierra, Inc.
105-8555 Baxter Place Burnaby, BC
Canada V5A 4V7
Tel:
(604) 415-6000
Fax:
(604) 415-6200
Document Information:
Corporate Information:
Application Information:
Web Site:
[email protected]
[email protected]
[email protected]
http://www.pmc-sierra.com
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or
suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility
with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly
disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and
implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement.
In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits,
lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility
of such damage.
© 2001 PMC-Sierra, Inc.
PMC-1990315 (R6) ref PMC-1990314 (R6)
PMC-Sierra, Inc..
Issue date: May 2001
105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7
604 .415.6000