ASAHI KASEI
[AK9813A]
AK9813A
12ch 8bit D/A Converter with EEPROM
General Description
The AK9813A includes 12 channel, 8bit D/A converters with on-chip output buffer amps and it is capable to
store the input digital data of each DAC by on-chip non-volatile CMOS EEPROM. The AK9813A is optimally
designed for various circuit adjustments for consumer and industrial equipments and it is ideally suited for
replacing mechanical trimmers.
Features
EEPROM SECTION
• 12 words Õ 8bit Õ 4 organization for DAC
D/A converter section
• 12 channels
• Resolution : 8bit
• DNL
: -1a+2 LSB
• INL
: 1.5 LSB
• Analog Output Voltage Range : GND a VCC
Operating Voltage Range
• Digital section
: 2.7Va5.5V
• Analog section : 5.0V0.5V,3.3V0.3V
24pin VSOP
Block Diagram
DAD03E-00
1999/05
-1-
ASAHI KASEI
[AK9813A]
Ordering Guide
AK9813AF
-10 to +85°C
24-pinVSOP
ýPin Layout
DAD03E-00
1999/05
-2-
ASAHI KASEI
[AK9813A]
ýPin Description(1)
No.
Pin Name
I/O
20
DI
I
17
DO
O
19
CLK
I
18
CS/LD
I
Function
Serial Data Input Pin
SEL=High : 16bit data input format
SEL=Low : 14bit data input format
(SEL=High:CS I/F)
AK9813A reads out the data with LSB first in the 16bit
shift register to DO pin synchronously with falling
edge of CLK.
When the CS pin is high level, the DO pin becomes high
impedance. In STATUS mode, the DO pin outputs Ready/Busy
status.
(SEL=Low:LD I/F)
AK9813A reads out the data with MSB first in the 14bit
shift register to DO pin synchronously with falling
edge of CLK.
In WRITE mode, the DO pin outputs Ready/Busy status.
Shift Clock Input Pin(Schmitt-trigger input)
AK9813A takes in the data from DI pin synchronously with
rising edge of the CLK pin. The data are transferred to
the internal shift register.
Chip Select Input Pin(Schmitt-trigger input)
The CS/LD is internally pulled up to VCC.
(SEL=High:CS I/F)
After the CS pin changes from high level to low level
while the CLK pin is high level, the AK9813A can input
the data to the internal shift register and takes in
the data from the DI pin synchronously with the rising
edge of the CLK pin.
After the CS pin changes from high level to low level
while the CLK pin is low level, the AK9813A becomes the
status mode and reads out the Ready/Busy status to the
DO pin.
When the CS pin changes from low level to high level
regardless of Low/High level of the CLK pin, the AK9813A
removes from the status mode to the normal mode. The CS
pin usually should be kept at high level.
(SEL=Low:LD I/F)
When the LD pin receives high pulse, the data of the
internal shift register is transferred to the internal
decoder or the register for D/A. The LD pin usually
should be kept at low level.
DAD03E-00
1999/05
-3-
ASAHI KASEI
[AK9813A]
Pin Description(2)
No.
Pin Name
I/O
1
|
12
14
23
13
24
21
22
AO1
|
AO12
Vcc
GND
Vdd
Vss
EA0
EA1
16
ECL
I
15
SEL
I
Function
O
8bit D/A outputs with OP-AMP
I
Digital section Power Supply Pin
Digital section Ground Pin
OP-AMP and D/A section Power Supply
OP-AMP and D/A section Ground
(SEL=High:CS I/F)
In AUTO READ operation and ECL operation, the address
of EEPROM is selected by the EA0 and the EA1 pins.
(SEL=Low:LD I/F)
The address of EEPROM is selected by the EA0 and the
EA1 pins.
When the ECL pin receives high pulse, the data in
EEPROM is automatically loaded to each corresponding
D/A, starting from AO1 to AO12 in order. Then each D/A
output is settled to pre-determined value.
Input Data Format Select Pin
SEL=High : CS I/F
SEL=Low : LD I/F
After power-up, this pin should be kept either at "high"
or "Low."
DAD03E-00
1999/05
-4-
ASAHI KASEI
[AK9813A]
Data Configuration
AK9813A have a shift register in order to control the chip.
When the SEL pin is "H"(CS I/F), the shift register becomes 16bit configuration and the data on the DI pin
should be loaded with LSB first. When the SEL pin is "L"(LD I/F), the shift register becomes 14bit
configuration and the data on the DI pin is loaded with MSB first.
The following description shows the configuration of the shift register.
The data set consist of 2-bits for the control of the internal EEPROM, 2-bits for the address of the EEPROM
(CS I/F only), 4-bits for select of D/A converter and 8-bits for the digital input data of the 8bit D/A converter and
total data set is 16bits or 14bits.
1
{
Shift register configuration : SEL=High(CS I/F)
OUTPUT VOLTAGE FOR D/A CONVERTER
D7 D6 D5 D4 D3 D2 D1 D0 OUTPUT VOLTAGE FOR D/A
0
0
0
0
0
0
0
0 = GND=VSS
0
0
0
0
0
0
0
1 = VDD/255 Õ 1
0
0
0
0
0
0
1
0 = VDD/255 Õ 2
•
•
•
•
•
•
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
A1 A0 EEPROM ADDRESS
0
1 ADDRESS : 0
0
1 ADDRESS : 1
1
0 ADDRESS : 2
1
1 ADDRESS : 3
= VDD/255 Õ 254
= VDD
•
•
•
D/A CONVERTER CHANNEL SELECTION
D11 D10 D9 D8
D/A CHANNEL
0
0
0
0
Don't Care
0
0
0
1
AO1
0
0
1
0
AO2
0
0
1
1
AO3
0
1
0
0
AO4
0
1
0
1
AO5
0
1
1
0
AO6
0
1
1
1
AO7
•
D11
1
1
1
1
1
1
1
1
D10
0
0
0
0
1
1
1
1
D9 D8
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
D/A CHANNEL
AO8
AO9
AO10
AO11
AO12
Can't use
Can't use
Don't Care
(NOTE) Above "Don't care" state is valid only when AK9813A is in DAC mode or WRITE mode.
Refer to the following section "Instruction Set" about mode.
DAD03E-00
1999/05
-5-
ASAHI KASEI
2
{
[AK9813A]
Shift register configuration:SEL=Low(LD I/F)
OUTPUT VOLTAGE FOR D/A CONVERTER
D0 D1 D2 D3 D4 D5 D6 D7 OUTPUT VOLTAGE FOR D/A
0
0
0
0
0
0
0
0 = GND=VSS
1
0
0
0
0
0
0
0 = VDD/255 Õ 1
0
1
0
0
0
0
0
0 = VDD/255 Õ 2
•
•
•
•
•
•
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
= VDD/255 Õ 254
= VDD
•
•
•
•
EA1 EA0 EEPROM ADDRESS
0
0 ADDRESS : 0
0
1 ADDRESS : 1
1
0 ADDRESS : 2
1
1 ADDRESS : 3
NOTE)
EEPROM ADDRESS is selected
by the EA0 and EA1 pins.
D/A CONVERTER CHANNEL SELECTION
D8 D9 D10 D11
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
D/A CHANNEL
Don't Care
AO1
AO2
AO3
AO4
AO5
AO6
AO7
D8 D9 D10 D11
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
D/A CHANNEL
AO8
AO9
AO10
AO11
AO12
CAN'T USE
CAN'T USE
Don't Care
(NOTE) Above "Don't care" state is valid only when AK9813A is in DAC mode or WRITE mode.
Refer to the following section "Instruction Set" about mode.
DAD03E-00
1999/05
-6-
ASAHI KASEI
[AK9813A]
Instruction Set
The AK9813A can be controlled for the following mode. The following mode is common to the LD I/F and the
CS IF. When LD I/F is selected, "A1" and "A0" are set by the external pins (EA0 pin and EA1 pin).
1 DAC mode(External DI pin -> D/A converter)
[Õ:Don't Care]
{
A1 A0 CL WR D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Function
0
0
D/A Channel
Digital data for D/A
D/A output
Õ
Õ
2
{
CALL mode(Internal EEPROM -> D/A converter)
[Õ:Don't Care]
A1 A0 CL WR D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Function
1
0
D/A Channel
Õ
Õ
Õ
Õ
Õ
Õ
Õ
Õ READ
• The output of D/A converter is set by the data in the internal EEPROM.
ADDRESS
3
{
ALL CALL mode(Internal EEPROM -> D/A converter)
[Õ:Don't Care]
A1 A0 CL WR D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Function
0
0
0
0
0
Õ
Õ
Õ
Õ
Õ
Õ
Õ
Õ ALL CHANNEL READ
ADDRESS 1
• The outputs of all D/A converters are set by the data in the internal EEPROM.
• • • Internal ECL function
4
{
WRITE ENABLE mode(Internal EEPROM WRITE ENABLE)
[Õ:Don't Care]
A1 A0 CL WR D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Function
1
1
0
0
0
0
Õ
Õ
Õ
Õ
Õ
Õ
Õ
Õ
Õ
Õ WRITE ENABLE
• After WRITE ENABLE mode is executed, the programming to the internal EEPROM is enabled. Upon
power-up and after the execution of the ECL function, the AK9813A is in the programming disable state.
5
{
WRITE DISABLE mode(Internal EEPROM WRITE DISABLE)
[Õ:Don't Care]
A1 A0 CL WR D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Function
1
1
1
1
1
1
Õ
Õ
Õ
Õ
Õ
Õ
Õ
Õ
Õ
Õ WRITE DISABLE
• After WRITE DISABLE mode is executed, the programming to the internal EEPROM is disabled.
6
{
WRITE mode(External DI pin -> Internal EEPROM)
[Õ:Don't Care]
A1 A0 CL WR D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Function
0
1
D/A Channel
Digital data for D/A
WRITE
• The digital data for D/A (D0aD7) is written into the specified address in the internal EEPROM. The state
of the internal EEPROM must be the programming enable state.
ADDRESS
7
{
READ mode(Internal EEPROM -> External DO pin)
[Õ:Don't Care]
A1 A0 CL WR D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Function
1
D/A Channel
Õ
Õ
Õ
Õ
Õ
Õ
Õ
Õ EEPROM DATA output
ADDRESS 1
• The DO pin outputs the data in the internal EEPROM synchronously with the falling edge of of the input
pulse of the CLK pin.
DAD03E-00
1999/05
-7-
ASAHI KASEI
[AK9813A]
Functional Description
1
{
Timing Diagram for CS I/F (SEL="H")
1.DAC mode:The internal EEPROM is not used.
2.WRITE ENABLE/DISABLE mode:The programming state of the internal EEPROM is set.
3.CALL mode: The output of the D/A is set by the data in the internal EEPROM.
DAD03E-00
1999/05
-8-
ASAHI KASEI
[AK9813A]
4.ALL CALL mode : The outputs of the all D/As are set by the data in the internal EEPROM.
• The
D/A outputs are set from AO1 to AO12 in order.
5.WRITE mode:The digital input data for D/A converter is written into the internal EEPROM.
6.READ mode:The data in the internal EEPROM is read from the DO pin.
DAD03E-00
1999/05
-9-
ASAHI KASEI
[AK9813A]
7.STATUS mode: The DO pin outputs the Ready/Busy status from the DO pin.
8.ECL function : For "H" pulse to the ECL pin, the data in the selected address in the internal EEPROM is
automatically loaded. Then each D/A converter output is settled to pre-determined value.
9. Transfer mode for the cascade connection
In case that AK9813A devices are connected in cascade, the AK9813A under programming cycle can transfer
the data to the other AK9813A. The some AK9813A devices can be operated by the common CS signal at the
same time.
Please note that the input data into to the AK9813A under programming cycle should be all"0" when the CS
pin is changed from "L" to "H". If data except all"0" is input into the AK9813A under programming cycle,
accidental data disturbance may occur.
DAD03E-00
1999/05
- 10 -
ASAHI KASEI
[AK9813A]
2
{
Timing Diagram for LD I/F (SEL ="L")
1.DAC mode:The internal EEPROM is not used.
2.WRITE ENABLE/DISABLE mode:The programming state of internal EEPROM is set.
3.CALL mode: The output of the D/A is set by the data in the internal EEPROM.
DAD03E-00
1999/05
- 11 -
ASAHI KASEI
[AK9813A]
4.ALL CALL mode : The outputs of the all D/As are set by the data in the internal EEPROM.
•
The D/A outputs are set from AO1 to AO12 in order.
5.WRITE mode:The digital input data for D/A converter is written into the internal EEPROM.
(NOTE)
∗ In case that AK9813A devices are connected in cascade, when a AK9813A device is under programming
cycle, the AK9813A device under programming cycle can not transfer the data to the other AK9813A device
and some AK9813A devices can not be operated by the common CS signal at the same time.
∗ While programming cycle, the CS/LD pin should be "L".
∗ When the Ready/Busy signal from the DO pin is verified, the CS pin should be changed from "H" to "L" and
kept at "L". If the CS pin is kept at "H", the Ready/Busy signal does not output correctly.
DAD03E-00
1999/05
- 12 -
ASAHI KASEI
[AK9813A]
6.READ mode:The data in the internal EEPROM is read from the DO pin.
7.ECL function:
When the ECL pin received high pulse, the data in EEPROM is automatically loaded to each corresponding
D/A, and starting from AO1 to AO12 in order. Then each D/A output is settled to pre-determined value.
DAD03E-00
1999/05
- 13 -
ASAHI KASEI
[AK9813A]
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
VCC
VIO
Ta
TST
Power Supply
Input Voltage
Ambient Temperature
Storage Temperature
Condition
Spec.
-0.3∼+6.5
-0.3∼VCC+0.3
-10∼+85
-65∼+150
relative to GND
relative to GND
Units
V
V
°C
°C
RECOMMENDED OPERATING CONDITIONS
Parameter
Power Supply 1
(Digital section)
Power Supply 2
(DAC,AMP sections)
Analog Output
Source Current 1
Analog Output
Sink Current 1
Analog Output
Source Current 2
Analog Output
Sink Current 2
Analog Output
Load Capacitance
Symbol
Conditions
min
VCC
VDD1
VDD2
IAL
IAH
2.7
4.5
3.0
VDD≥VCC
VDD=5.0V0.5V
IAL
IAH
AOC
VDD=3.3V0.3V
Load Crcuit-A
0.8
Load Circuit-B
•Load
typ
•Load
Circuit-A
DAD03E-00
5.0
3.3
max
Units
5.5
V
5.5
3.6
1
mA
1
mA
500
uA
500
uA
0.001
uF
V
1.0
uF
1.0
uF
Circuit-B
1999/05
- 14 -
ASAHI KASEI
[AK9813A]
ELECTRICAL CHARACTERISTICS
DC Characteristics
(1)Digital Section
(VCC=2.7V∼5.5V,VDD=5.0V0.5V or 3.3V0.3V(VDD≥VCC),GND,VSS=0V,Ta=-10∼85°C)
Parameter
Symbol
Pin
Conditions
Power Supply
(Digital Section)
VCC
Operating Current
(READ) (1)(2)
Leakage Current
ICC
VCC
CLK=1MHz
ILI
CLK,DI
CS/LD
EA0,EA1
ECL,SEL
VIN=VCC
High Level
Input Voltage1
Low Level
Input Voltage1
High Level
Input Voltage2
Low Level Input
Voltage2
High Level
Output Voltage
VIH
VIL
VIH
min
max
Units
2.7
5.5
V
1.5
mA
10.0
uA
-10.0
0.5ÕVCC
DI
EA0,EA1
ECL,SEL
0.2ÕVCC
CS/LD
CLK
0.6ÕVCC
VIL
DO
DAD03E-00
V
V
0.15ÕVCC
4.5V≤VCC≤5.5V
IOH=-400uA
2.7V≤VCC<4.5V
VOH2
IOH=-200uA
4.5V≤VCC≤5.5V
Low Level
VOL1
Output Voltage
IOL=1.0mA
2.7V≤VCC<4.5V
VOL2
IOL=1.0mA
(1) All input pins are connected to either VCC or GND.
(2) DO=OPEN
VOH1
V
V
VCC-0.4
V
0.7ÕVCC
V
0.4
V
0.4
V
1999/05
- 15 -
ASAHI KASEI
[AK9813A]
(2)Analog Section
(2-1)VDD=5.0V0.5V
(VCC=2.7V∼5.5V,VDD=5.0V0.5V (VDD≥VCC),GND,VSS=0V,Ta=-10∼85°C)
Parameter
Symbol
Pin
Power Supply1
(Analog Section)
VDD1
Power Dissipation1
(Analog Section)
Resolution
IDD1
VDD
Res
AO1
|
AO12
Conditions
VDD≥VCC
min
typ
max
Units
4.5
5.0
5.5
V
10.0
mA
-1.5
1.5
LSB
-1.0
2.0
LSB
AO1∼AO12=OPEN
8
AO1∼AO12=OPEN
0.05V≤AO
≤VDD-0.1V
bits
Integral
(3)
Non-Linearity :INL
LE
Differential
Non-Linearity :DNL
DLE
Buffer-AMP Minimum
Output Voltage 1
VAOL1
IAL = 0uA
Data= 00(Hex)
GND
0.05
V
Buffer-AMP Minimum
Output Voltage 2
VAOL2
IAL = 500uA
Data= 00(Hex)
-0.1
0.1
V
Buffer-AMP Minimum
Output Voltage 3
VAOL3
IAH = 500uA
Data= 00(Hex)
GND
0.1
V
Buffer-AMP Minimum
Output Voltage 4
VAOL4
IAL = 1mA
Data= 00(Hex)
-0.2
0.2
V
Buffer-AMP Minimum
Output Voltage 5
VAOL5
IAH = 1mA
Data= 00(Hex)
GND
0.2
V
Buffer-AMP Maximum
Output Voltage 1
VAOH1
IAH = 0uA
Data= FF(Hex)
VDD-0.1
VDD
V
Buffer-AMP Maximum
Output Voltage 2
VAOH2
IAL = 500uA
Data= FF(Hex)
VDD-0.2
VDD
V
Buffer-AMP Maximum
Output Voltage 3
VAOH3
IAH = 500uA
Data= FF(Hex)
VDD-0.2
VDD+0.2
V
Buffer-AMP Maximum
Output Voltage 4
VAOH4
IAL = 1mA
Data= FF(Hex)
VDD-0.3
VDD
V
AO1
|
AO12
IAH = 1mA
VDD-0.3
VDD+0.3
V
Buffer-AMP Maximum VAOH5
Data= FF(Hex)
Output Voltage 5
(3) Integral Non-Linearity is the error between the actual line and the ideal line.
The ideal line exhibits a perfect linear D/A converter output characteristic between the input
digital data"00" and the input digital data"FF".
DAD03E-00
1999/05
- 16 -
ASAHI KASEI
[AK9813A]
(2-2) VDD=3.3V0.3V
(VCC=2.7V∼3.6V,VDD=3.3V0.3V (VDD≥VCC),GND,VSS=0V,Ta=-10∼85°C)
Parameter
Symbol
Power Supply 2
(Analog Section)
VDD2
Power Dissipation2
(Analog Section)
Resolution
Integral
(3)
Non-Linearity :INL
IDD2
Differential
Non-Linearity :DNL
Res
LE
Pin
VDD
AO1
|
AO12
DLE
Conditions
VDD ≥ VCC
min
typ
max
Units
3.0
3.3
3.6
V
7.0
mA
-1.5
1.5
bits
LSB
-1.0
2.0
LSB
0.15
V
AO1∼AO12=OPEN
8
AO1∼AO12=OPEN
0.15V≤AO
≤VDD-0.15V
AO1∼AO12=OPEN
VDD=3.3V
Output Voltage for
Input data "05"
0.1
3.15
Output Voltage for
Input data "FA"
3.25
V
Buffer-AMP Minimum
Output Voltage 6
VAOL6
IAL = 0uA
Data= 00(Hex)
GND
0.05
V
Buffer-AMP Minimum
Output Voltage 7
VAOL7
IAL = 250uA
Data= 00(Hex)
-0.1
0.1
V
Buffer-AMP Minimum
Output Voltage 8
VAOL8
IAH = 250uA
Data= 00(Hex)
GND
0.1
V
Buffer-AMP Minimum
Output Voltage 9
VAOL9
IAL = 500uA
Data= 00(Hex)
-0.2
0.2
V
Buffer-AMP Minimum
Output Voltage 10
VAOL10
IAH = 500uA
Data= 00(Hex)
GND
0.2
V
Buffer-AMP Maximum
Output Voltage 6
VAOH6
IAH = 0uA
Data= FF(Hex)
VDD-0.1
VDD
V
Buffer-AMP Maximum
Output Voltage 7
VAOH7
IAL = 250uA
Data= FF(Hex)
VDD-0.2
VDD
V
Buffer-AMP Maximum
Output Voltage 8
VAOH8
IAH = 250uA
Data= FF(Hex)
VDD-0.2
VDD+0.2
V
Buffer-AMP Maximum
Output Voltage 9
VAOH9
IAL = 500uA
Data= FF(Hex)
VDD-0.3
VDD
V
AO1
|
AO12
IAH = 500uA
VDD-0.3
VDD+0.3
V
Buffer-AMP Maximum VAOH10
Data= FF(Hex)
Output Voltage 10
(3) Integral Non-Linearity is the error between the actual line and the ideal line.
The ideal line exhibits a perfect linear D/A converter output characteristics between the input digital
data"05" and the input digital data"FA".
DAD03E-00
1999/05
- 17 -
ASAHI KASEI
[AK9813A]
AC Characteristics
(1) CS I/F, LD I/F : Common Timing
(VCC=2.7V∼5.5V,VDD=5.0V0.5V or 3.3V0.3V (VDD≥VCC),GND,VSS=0V,Ta=-10∼85°C)
Parameter
Vcc Rise Time
Auto Address Hold Time
Auto Read Time
ECL "H" Pulse Width
External Call Time
Address Set Up Time
ECL Address Hold Time
Repeat Call Prohibition Time
Symbol
tVCR
tVAH
tPOR
tECW1
tECW2
tECL
tESU1
tESU2
tEAH
tECC1
tECC2
Conditions
min
max
50
3.5
Test Load2
*1
*2
Test Load2
*1
*2
*1
*2
3.5
100
250
3.5
50
100
3.5
20
100
Units
ms
ms
ms
ns
ns
ms
ns
ns
ms
ns
ns
*1:4.5V≤Vcc≤5.5V
*2:2.7V≤Vcc<4.5V
<AUTO READ>
DAD03E-00
1999/05
- 18 -
ASAHI KASEI
[AK9813A]
(2)CS I/F Timing
(VCC=2.7V∼5.5V,VDD=5.0V0.5V or 3.3V 0.3V (VDD≥VCC),GND,VSS=0V,Ta=-10∼85°C)
Parameter
Clock "L" Pulse Width
Clock "H" Pulse Width
Clock Rising Time
Clock Falling Time
Data Set Up Time
Data Hold Time
CS Set Up Time
CS Hold Time
Symbol
tCKL1
tCKL2
tCKH1
tCKH2
tCr
tCf
tDSU1
tDSU2
tDHD1
tDHD2
tCSU1
tCSU2
tCCH
Conditions
*5
*6
*5
*6
tCSH
200
500
200
500
*5
*6
*5
*6
*5
*6
WRITE
*3,*4,*5
*3,*4,*6
*4,*5
*4,*6
CALL•READ
ALL CALL
Data Output Enable Time
Data Output Float Delay
Data Output Delay
tDOD1
tDOD2
tDOZ1
tDOZ2
tDOC1
tDOC2
D/A Output Setting Time
tCSD
Test Load1
DAC
CALL
ALL CALL
Status Set Up Time
Status Hold Time
*3:
*4:
*5:
*6:
max
*5
*6
*5
*6
*5
*6
Test Load2
Test Load2
Test Load2
Units
ns
ns
ns
ns
200
DAC etc
CS "H" Hold Time
min
30
150
60
150
100
250
200
100
250
10
15
15
3.5
200
500
200
500
170
300
200
250
3.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
us
ms
ns
ns
ns
ns
ns
ns
us
us
ms
ns
ns
ns
tSSU
100
tSHD1
*5
100
tSHD2
*6
250
Please refer to "DAC etc" regarding CS "H" Hold Time before status mode execute.
If READY/BUSY="H" is confirmed in status mode in the WRITE mode, the CS pin can be changed to
"L" shorter than the values specified on above.
Please refer to "DAC etc" regarding CS "H" Hold Time in case that AK9813 to be connected in cascade
is under programming cycle(READY/BUSY="L").
4.5V≤Vcc≤5.5V
2.7V≤Vcc<4.5V
DAD03E-00
1999/05
- 19 -
ASAHI KASEI
[AK9813A]
<Input/Output Waveform>
<STATUS Output>
DAD03E-00
1999/05
- 20 -
ASAHI KASEI
[AK9813A]
(3)LD I/F Timing
(VCC=2.7V∼5.5V,VDD=5.0V0.5V or 3.3V 0.3V (VDD≥VCC),GND,VSS=0V,Ta=-10∼85°C)
Parameter
Clock "L" Pulse Width
Clock "H" Pulse Width
Clock Rising Time
Clock Falling Time
Data Set Up Time
Data Hold Time
Load Set Up Time
Load Hold Time
Load "H" Pulse Width
Data Output Delay
Symbol
tCKL1
tCKL2
tCKH1
tCKH2
tCr
tCf
tDCH1
tDCH2
tCHD1
tCHD2
tCHL
tLDC1
tLDC2
tLDH1
tLDH2
tLDH3
tDO1
tDO2
D/A Output Setting Time
tLDDD
Address Set Up Time
Read Hold Time
tASU1
tASU2
tWAHD1
tWAHD2
tWRT
tRYD
tRYH1
tRYH2
tRHD
Read Address Hold Time
tRAHD
Write Address Hold Time
Programming Cycle
Ready Signal Delay
Repeat Write Prohibition Time
Conditions
min
*5
*6
*5
*6
max
200
500
200
500
ns
ns
ns
ns
200
*5
*6
*5
*6
*5
*6
*5
*6
modes except
READ mode
READ mode
Test Load1
*5
Test Load1
*6
DAC
Test Load2
CALL
Test Load2
ALL CALL
Test Load2
*5
*6
*5
*6
*7
Test Load1
Test Load1
*5
Test Load2
*6
CALL,READ mode
ALL CALL mode
CALL,READ mode
30
150
60
150
200
100
250
100
250
5
170
300
200
250
3.5
100
200
20
100
15
0.4
20
100
15
3.5
15
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
us
us
ms
ns
ns
ns
ns
ms
us
ns
ns
us
ms
us
ALL CALL mode
3.5
ms
*7: If READY/BUSY="L" is confirmed in status mode in the WRITE mode, the next operation can be
started.
DAD03E-00
1999/05
- 21 -
ASAHI KASEI
[AK9813A]
<Input/Output Waveform>
<Data Timing>
<Write mode>
* Please refer to the data timing regarding the input timing for the DI pin
DAD03E-00
1999/05
- 22 -
ASAHI KASEI
[AK9813A]
<Call mode>
<All Call mode>
<Read mode>
* Please refer to the data timing regarding the input timing for the DI pin
* AC measurement circuit
• Test Load1
• AC test point
Digital Input/Output Level :
Analog Output Level
:
• Test Load2
50% • 20% of Vcc
90% • 10% of Vcc
DAD03E-00
1999/05
- 23 -
IMPORTANT NOTICE
zThese products and their specifications are subject to change without notice. Before
considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM)
sales office or authorized distributor concerning their current status.
zAKM assumes no liability for infringement of any patent, intellectual property, or other
right in the application or use of any information contained herein.
zAny export of these products, or devices or systems containing them, may require an
export license or other official approval under the law and regulations of the country of
export pertaining to customs and tariffs, currency exchange, or strategic materials.
zAKM products are neither intended nor authorized for use as critical components in any
safety, life support, or other hazard related device or system, and AKM assumes no
responsibility relating to any such use, except with the express written consent of the
Representative Director of AKM. As used here:
(a) A hazard related device or system is one designed or intended for life support or
maintenance of safety or for applications in medicine, aerospace, nuclear energy, or
other fields, in which its failure to function or perform may reasonably be expected to
result in loss of life or in significant injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be
expected to result, whether directly or indirectly, in the loss of the safety or
effectiveness of the device or system containing it, and which must therefore meet
very high standards of performance and reliability.
zIt is the responsibility of the buyer or distributor of an AKM product who distributes,
disposes of, or otherwise places the product with a third party to notify that party in
advance of the above content and conditions, and the buyer or distributor agrees to
assume any and all responsibility and liability for and hold AKM harmless from any and
all claims arising from the use of said product in the absence of such notification.