54AC16620, 74AC16620 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCAS239A – JULY 1990 – REVISED APRIL 1996 D D D D D D D Members of the Texas Instruments Widebus Family 3-State Outputs Drive Bus Lines Directly Flow-Through Architecture Optimizes PCB Layout Distributed VCC and GND Pin Configurations Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-µm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Packages Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings description The ’AC16620 are inverting 16-bit transceivers designed for asynchronous communication between data buses. The control-function implementation allows for maximum flexibility in timing. These devices can be used as two 8-bit transceivers or one 16-bit transceiver. They allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the complementary output-enable (OEAB or OEBA) inputs. The output-enable inputs can be used to disable the device so that the buses are effectively isolated. 54AC16620 . . . WD PACKAGE 74AC16620 . . . DL PACKAGE (TOP VIEW) 1OEAB 1B1 1B2 GND 1B3 1B4 VCC 1B5 1B6 GND 1B7 1B8 2B1 2B2 GND 2B3 2B4 VCC 2B5 2B6 GND 2B7 2B8 2OEAB 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 1OEBA 1A1 1A2 GND 1A3 1A4 VCC 1A5 1A6 GND 1A7 1A8 2A1 2A2 GND 2A3 2A4 VCC 2A5 2A6 GND 2A7 2A8 2OEBA The dual-enable configuration gives the transceiver the capability to store data by simultaneously enabling OEAB and OEBA. Each output reinforces its input in this transceiver configuration. Thus, when both control inputs are enabled and all other data sources to the two sets of bus lines are at high impedance, the bus lines remain at their last states. The 74AC16620 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area. The 54AC16620 is characterized for operation over the full military temperature range of –55°C to 125°C. The 74AC16620 is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated. Copyright 1996, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 54AC16620, 74AC16620 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCAS239A – JULY 1990 – REVISED APRIL 1996 FUNCTION TABLE (each 8-bit section) INPUTS OPERATION OEBA OEAB L L B data to A bus L H B data to A bus, A data to B bus H L Isolation H H A data to B bus logic symbol† 1OEBA 1OEAB 2OEBA 2OEAB 1A1 48 1 25 24 47 EN1 EN2 EN3 EN4 1 1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 3 44 5 43 6 41 8 40 9 38 11 37 12 36 13 3 2A3 2A4 2A5 2A6 2A7 2A8 1 35 14 33 16 32 17 30 19 29 20 27 22 26 23 POST OFFICE BOX 655303 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 4 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2 1B1 2 46 1 2A2 2 1 • DALLAS, TEXAS 75265 2B2 2B3 2B4 2B5 2B6 2B7 2B8 54AC16620, 74AC16620 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCAS239A – JULY 1990 – REVISED APRIL 1996 logic diagram (positive logic) 1OEBA 1OEAB 1A1 48 2OEBA 1 2OEAB 47 2A1 2 25 24 36 13 1B1 2B1 To Seven Other Channels To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±400 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DL package . . . . . . . . . . . . . . . . . . . 1.2 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 54AC16620, 74AC16620 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCAS239A – JULY 1990 – REVISED APRIL 1996 recommended operating conditions (see Note 2) 54AC16620 VCC VIH Supply voltage VCC = 3 V VCC = 4.5 V High-level input voltage VCC = 5.5 V VCC = 3 V VIL Low-level input voltage VI VO 3 5 5.5 NOM MAX 3 5 5.5 2.1 3.15 3.15 0.9 1.35 1.35 1.65 1.65 0 VCC VCC 0 –4 –4 –24 –24 VCC = 5.5 V VCC = 3 V –24 –24 12 12 VCC = 4.5 V VCC = 5.5 V 24 24 24 24 TA Operating free-air temperature NOTE 3: Unused inputs must be held high or low to prevent them from floating. V V 0.9 VCC VCC 0 Input transition rise or fall rate UNIT 3.85 VCC = 3 V VCC = 4.5 V Low-level output current MIN 2.1 0 High-level output current ∆t/∆v MAX VCC = 4.5 V VCC = 5.5 V Output voltage IOL NOM 3.85 Input voltage IOH 74AC16620 MIN V V V mA mA 0 10 0 10 ns/V –55 125 –40 85 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –50 µA VOH IOH = –4 mA IOH = –24 24 mA IOH = –75 mA† MIN TA = 25°C TYP MAX IOL = 12 mA IOL = 24 mA 54AC16620 MIN 74AC16620 MIN 3V 2.9 2.9 2.9 4.4 4.4 4.4 5.5 V 5.4 5.4 5.4 3V 2.58 2.48 2.48 4.5 V 3.94 3.8 3.8 5.5 V 4.94 4.8 4.8 3.85 3.85 MAX UNIT V 3V 0.1 0.1 0.1 4.5 V 0.1 0.1 0.1 5.5 V 0.1 0.1 0.1 3V 0.36 0.44 0.44 4.5 V 0.36 0.44 0.44 5.5 V 0.36 0.44 0.44 1.65 1.65 V IOL = 75 mA† VI = VCC or GND 5.5 V 5.5 V ±0.1 ±1 ±1 µA A or B ports 5.5 V ±0.5 ±5 ±5 µA ICC Ci VO = VCC or GND VI = VCC or GND, 8 80 80 µA Control inputs Cio A or B ports VI = VCC or GND VO = VCC or GND II IOZ‡ Control inputs IO = 0 5.5 V 5V 4.5 pF 5V 16 pF † Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. ‡ For I/O ports, the parameter IOZ includes the input leakage current. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 MAX 4.5 V 5.5 V IOL = 50 µA VOL VCC POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 54AC16620, 74AC16620 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCAS239A – JULY 1990 – REVISED APRIL 1996 switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A or B B or A tPZH tPZL OEBA A tPHZ tPLZ OEBA A tPZH tPZL OEAB B tPHZ tPLZ OEAB B MIN TA = 25°C TYP MAX 54AC16620 74AC16620 MIN MAX MIN MAX 2.7 6.1 8.7 2.7 9.7 2.7 9.7 3.9 7.9 10.6 3.9 11.7 3.9 11.7 3.2 7.1 10 3.2 11.2 3.2 11.2 4.5 11.1 13.5 4.5 15 4.5 15 5.3 7.4 9.5 5.3 10.2 5.3 10.2 4.6 7 9.2 4.6 9.8 4.6 9.8 3.1 6.7 9.5 3.1 10.7 3.1 10.7 4.4 9.6 13 4.4 14.5 4.4 14.5 5 7.1 9.3 5 9.8 5 9.8 4.4 6.8 8.9 4.4 9.4 4.4 9.4 UNIT ns ns ns ns ns switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A or B B or A tPZH tPZL OEBA A tPHZ tPLZ OEBA A tPZH tPZL OEAB B tPHZ tPLZ OEAB B MIN TA = 25°C TYP MAX 54AC16620 74AC16620 MIN MAX MIN MAX 2.1 3.9 6.1 2.1 6.8 2.1 6.8 3.1 4.9 7.3 3.1 8.2 3.1 8.2 2.2 4.3 6.8 2.2 7.6 2.2 7.6 3.3 5.5 8.4 3.3 9.4 3.3 9.4 4.9 6.6 8.6 4.9 9.2 4.9 9.2 4.1 5.8 7.8 4.1 8.3 4.1 8.3 2.2 4.2 6.5 2.2 7.3 2.2 7.3 3.4 5.4 8.1 3.4 9.1 3.4 9.1 4.6 6.4 8.5 4.6 9 4.6 9 4.1 5.6 7.6 4.1 8 4.1 8 UNIT ns ns ns ns ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd d Power dissipation capacitance per transceiver TEST CONDITIONS Outputs enabled Outputs disabled CL = 50 pF, pF f = 1 MHz TYP 49 6 UNIT pF PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 54AC16620, 74AC16620 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCAS239A – JULY 1990 – REVISED APRIL 1996 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 500 Ω From Output Under Test Open GND TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND 500 Ω CL = 50 pF (see Note A) LOAD CIRCUIT VCC 50% Input 50% 0V tPHL tPLH In-Phase Output 50% VCC VOH 50% VCC VOL 50% VCC VOH 50% VCC VOL VCC Output Waveform 2 S1 at GND (see Note B) 50% 50% 0V tPZL [ VCC tPLZ Output Waveform 1 S1 at 2 × VCC (see Note B) tPLH tPHL Out-of-Phase Output Output Control (low-level enabling) 50% VCC VOL tPHZ tPZH VOLTAGE WAVEFORMS 20% VCC 50% VCC 80% VCC VOH [0V VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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