ULN2003LV
www.ti.com
SLRS059A – APRIL 2012 – REVISED APRIL 2012
7-Channel Relay and Inductive Load Sink Driver
Check for Samples: ULN2003LV
FEATURES
1
•
•
•
•
•
•
•
•
•
•
•
•
(1)
7-Channel High Current Sink Drivers
Supports up to 8V Ouput Pull-up Voltage
Supports a Wide Range of 3V-to-5V Relay and
Inductive Coils
Low Output VOL of 0.4V (Typical) with
– 100mA (Typical) Current Sink per Channel
at 3.3V Logic Input(1)
– 140mA (Typical) Current Sink per Channel
at 5.0V Logic Input(1)
Compatible to 3.3V and 5.0V Micro-controllers
and Logic Interface
Internal Free-wheeling Diodes for Inductive
Kick-back Protection
Input Pull-down Resistors Allows3-stating the
Input Driver
Input RC-Snubber to Eliminate Spurious
Operation in Noisy Environment
Low Input and Output Leakage Currents
Easy to use Parallel Interface
ESD Protection Exceeds JESD 22
– 2kV HBM, 500V CDM
Available in 16-pin SOIC and TSSOP Packages
Total current sink may be limited by the internal junction
temperature, absolute maximum current levels etc - refer to
the Electrical Specifications section for details.
APPLICATIONS
•
•
•
Relay and Inductive Load Driver in Various
Telecom, Consumer, and Industrial
Applications
Lamp and LED Displays
Logic Level Shifter
DESCRIPTION
The ULN2003LV is a low-voltage and low power
upgrade of TI’s popular ULN2003 family of 7-channel
Darlington transistor array. The ULN2003LV sink
driver features 7 low output impedance drivers to
support low voltage relay and inductive coil
applications. The low impedance drivers minimize onchip power dissipation; up to 5 times lower for typical
3V relays. The ULN2003LV driver is pin-to-pin
compatible with ULN2003 family of devices in similar
packages.
The ULN2003LV supports 3.3V to 5V CMOS logic
input interface thus making it compatible to a wide
range of micro-controllers and other logic interfaces.
The ULN2003LV features an improved input interface
that minimizes the input DC current drawn from the
external drivers. The ULN2003LV features an input
RC snubber that greatly improves its performance in
noisy operating conditions. The ULN2003LV channel
inputs feature an internal input pull-down resistor thus
allowing input logic to be tri-stated. The ULN2003LV
may also support other logic input levels, e.g. TTL
and 1.8V, refer to the Application Information section
for details.
As shown in Table 1, each output of the ULN2003LV
features an internal free-wheeling diode connected in
a common-cathode configuration at the COM pin.
The ULN2003LV provides flexibility of increasing
current sink capability through combining several
adjacent channels in parallel. Under typical conditions
the ULN2003LV can support up to 1.0A of load
current when all 7-channels are connected in parallel.
The ULN2003LV can also be used in a variety of
other applications requiring a sink drivers. The
ULN2003LV is available in 16-pin SOIC and 16-pin
TSSOP packages.
Table 1. ULN2003LV Function Table(1)
Functional Diagram
INPUT (IN1 – IN7)
OUTPUT (OUT1–OUT7)
IN1
1
16
OUT1
L
H+(2)
IN2
2
15
OUT2
H
L
IN3
3
14
OUT3
Z
H+(2)
IN4
4
13
OUT4
IN5
5
12
OUT5
(1) L = Low-level (GND); H= High-level; Z= High-impedance;
IN6
6
11
OUT6
(2) H+ = Pull-up-level
IN7
7
10
OUT7
GND
8
9
COM
ULN2003LV TSSOP/SOIC
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
ULN2003LV
SLRS059A – APRIL 2012 – REVISED APRIL 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
TA
–40°C to 85°C
(1)
PART NUMBER
PACKAGE
TOP-SIDE MARKING
ULN2003LVDR
16-Pin SOIC
Reel of 2500
UN2003LV
ULN2003LVPWR
16-Pin TSSOP
Reel of 2000
UN2003LV
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Specified at TJ = –40°C to 125°C unless otherwise noted.
VALUE
VIN
Pins IN1- IN7 to GND voltage
VOUT
Pins OUT1 – OUT7 to GND voltage
VCOM
Pin COM to GND voltage
IGND
PD
MAX
–0.3
5.5
V
8
V
8
V
Max GND-pin continuous current (TJ > +125°C)
700
mA
Max GND-pin continuous current (TJ < +100°C)
1.0
A
16 Pin - SOIC
0.58
W
16 Pin -TSSOP
0.45
W
2
kV
Total device power dissipation at TA = 85°C
ESD Rating – HBM
ESD
UNIT
MIN
500
V
TA
Operating free-air ambient temperature range
–40
85
°C
TJ
Operating virtual junction temperature
–55
150
°C
Tstg
Storage temperature range
–55
150
°C
(1)
ESD Rating – CDM
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these conditions is not implied. Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability.
DISSIPATION RATINGS (1) (2)
PACKAGE
θJC
θJA (3)
DERATING
FACTOR ABOVE
TA = 25ºC
TA < 25°C
TA = 70°C
TA = 85°C
High-K
16-Pin SOIC
69°C/W
112°C/W
8.88 mW/ºC
1.11 W
0.71 W
0.58 W
High-K
16-Pin TSSOP
74°C/W
142°C/W
7.11 mW/ºC
0.88 W
0.56 W
0.45 W
BOARD
(1)
(2)
(3)
2
Maximum dissipation values for retaining device junction temperature of 150°C
Refer to TI’s design support web page at www.ti.com/thermal for improving device thermal performance
Operating at the absolute TJ-max of 150°C can affect reliability– for higher reliability it is recommended to ensure TJ < 125°C
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ELECTRICAL CHARACTERISTICS
Specified over the recommended junction temperature range TJ = –40°C to 125°C unless otherwise noted. Typical values are
at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUTS IN1 THROUGH IN7 PARAMETERS
VI(ON)
IN1–IN7 logic high input voltage
Vpull-up = 3.3 V, Rpull-up = 1 kΩ, IOUTX = 3.2 mA
VI(OFF)
IN1–IN7 logic low input voltage
Vpull-up = 3.3 V, Rpull-up = 1 kΩ,
(IOUTX = <5 µA)
1.65
V
0.4
II(ON)
IN1–IN7 ON state input current
Vpull-up = 3.3 V, VINx = 3.3 V
12
II(OFF)
IN1–IN7 OFF state input leakage
Vpull-up = 3.3 V, VINx = 0 V
0.6
25
uA
250
nA
OUTPUTS OUT1 THROUGH OUT7 PARAMETERS
VINX = 3.3 V, IOUTX = 50 mA
0.17
0.24
VINX = 3.3 V, IOUTX = 100 mA
0.36
0.49
VINX = 5.0 V, IOUTX = 100 mA
0.26
0.42
VOL(VCE-SAT)
OUT1–OUT7 low-level output voltage
IOUT(ON)
OUT1–OUT7 ON-state continuous
current (1) (2) at VOUTX = 0.4V
VINX = 3.3 V, VOUTX = 0.4 V
80
100
VINX = 5.0 V, VOUTX = 0.4 V
95
140
IOUT(OFF)(ICEX)
OUT1–OUT7 OFF-state leakage current
VINX = 0 V, VOUTX = VCOM = 8 V
VINX = 5.0 V, IOUTX = 140 mA
V
0.40
mA
0.17
µA
SWITCHING PARAMETERS (3) (4)
tPHL
OUT1–OUT7 logic high propagation delay
tPLH
OUT1–OUT7 logic low propagation delay
RPD
IN1–IN7 input pull-down Resistance
ζ
IN1–IN7 Input filter time constant
COUT
OUT1–OUT7 output capacitance
VINX = 3.3V, Vpull-up = 3.3 V, Rpull-up = 50 Ω
25
VINX = 5.0V, Vpull-up = 5 V, Rpull-up = 1 kΩ
15
VINX = 3.3V, Vpull-up = 3.3 V, Rpull-up = 50 Ω
45
VINX = 5.0V, Vpull-up = 5 V, Rpull-up = 1kΩ
80
210k
VINX = 3.3 V, VOUTX = 0.4 V
300k
ns
ns
390k
Ω
9
ns
15
pF
FREE-WHEELING DIODE PARAMETERS (5) (4)
VF
Forward voltage drop
IF-peak
Diode peak forward current
(1)
(2)
(3)
(4)
(5)
IF-peak = 140 mA, VF = VOUTx – VCOM,
1.2
V
140
mA
The typical continuous current rating is limited by VOL= 0.4V. Whereas, absolute maximum operating continuous current may be limited
by the Thermal Performance.parameters listed in the Dissipation Rating Table and other Reliability parameters listed in the
Recommended Operating ConditionsTable.
Refer to the Absolute Maximum Ratings Table for TJ dependent absolute maximum GND-pin current.
Rise and Fall propagation delays, tPHL and tPLH, are measured between 50% values of the input and the corresponding output signal
amplitude transition.
Guaranteed by design only.
Not rated for continuous current operation – for higher reliability use an external freewheeling diode for inductive loads resulting in more
than specified maximum free-wheeling. diode peak current across various temperature conditions
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ULN2003LV
SLRS059A – APRIL 2012 – REVISED APRIL 2012
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DEVICE INFORMATION
IN1
1
16
OUT1
IN2
2
15
OUT2
IN3
3
14
OUT3
COM
RIN = 3 kW
INx
Array of
Transistors
OUTx
RPD = 300 kW
IN4
4
IN5
CPD
16-Pin
SOIC/TSSOP
13
OUT4
5
12
OUT5
IN6
6
11
OUT6
IN7
7
10
OUT7
GND
8
9
COM
CIN = 9 pF
COUT
GND
Figure 2. Channel Block Diagram
Figure 1. ULN2003LV PINOUT
ULN2003LV PIN DESCRIPTION
NAME
PIN NUMBER
IN1 – IN7
16-SOIC
16-TSSOP
DESCRIPTION
1–7
1–7
GND
8
8
Ground Reference Pin
COM
9
9
Internal Free-Wheeling Diode Common Cathode Pin
10–16
10–16
OUT7 – OUT1
4
Logic Input Pins IN1 through IN7
Channel Output Pins OUT7 through OUT1
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APPLICATION INFORMATION
TTL and other Logic Inputs
ULN2003LV input interface is specified for standard 3V and 5V CMOS logic interface. However, ULN2003LV
input interface may support other logic input levels as well. Refer to Figure 10 and Figure 11 to establish VOL
and the corresponding typical load current levels for various input voltage ranges. Application Information section
shows an implmentation to drive 1.8V relays using ULN2003LV.
Input RC Snubber
ULN2003LV features an input RC snubber that helps prevent spurious switching in noisy environment. Connect
an external 1kΩ to 5kΩ resistor in series with the input to further enhance ULN2003LV’s noise tolerance.
High-impedance Input Drivers
ULN2003LV features a 300kΩ input pull-down resistor. The presence of this resistor allows the input drivers to
be tri-stated. When a high-impedance driver is connected to a channel input the ULN2003LV detects the channel
input as a low level input and remains in the OFF position. The input RC snubber helps improve noise tolerance
when input drivers are in the high-impedance state.
On-chip Power Dissipation
Use the below equation to calculate ULN2003LV on-chip power dissipation PD:
N
PD = å VOLi ´ ILi
i=1
Where:
N is the number of channels active together.
VOLi is the OUTi pin voltage for the load current ILi.
(1)
Thermal Reliability
It is recommended to limit ULN2003LV IC’s die junction temperature to less than 125°C. The IC junction
temperature is directly proportional to the on-chip power dissipation. Use the following equation to calculate the
maximum allowable on-chip power dissipation for a target IC junction temperature:
PD(MAX) =
(T
J(MAX)
- TA )
qJA
Where:
TJ(MAX) is the target maximum junction temperature.
TA is the operating ambient temperature.
θJA is the package junction to ambient thermal resistance.
(2)
Improving Package Thermal Performance
The package θJA value under standard conditions on a High-K board is listed in the DISSIPATION RATINGS. θJA
value depends on the PC board layout. An external heat sink and/or a cooling mechanism, like a cold air fan, can
help reduce θJA and thus improve device thermal capabilities. Refer to TI’s design support web page at
www.ti.com/thermal for a general guidance on improving device thermal performance.
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ULN2003LV
SLRS059A – APRIL 2012 – REVISED APRIL 2012
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Application Examples
Inverting Logic Level Shifter
To use ULN2003LV as an open-collector or an open-drain inverting logic level shifter configure the device as
shown in Figure 3. The ULN2003LV’s each channel input and output logic levels can also be set independently.
When using different channel input and output logic voltages connect the ULN2003LV COM pin to the maximum
voltage.
VSUP Level Shift Supply(Up to 8V)
Logic Inputs
(1.8V to 5V)
ULN2003LV
IN1
OUT1
OUT1_VSUP
IN2
OUT2
OUT2_VSUP
IN3
OUT3
OUT3_VSUP
IN4
OUT4
OUT4_VSUP
IN5
OUT5
OUT5_VSUP
IN6
OUT6
OUT6_VSUP
IN7
OUT7
OUT7_VSUP
GND
COM
Figure 3. ULN2003LV as Inverting Logic Level Shifter
6
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Max Supply Selector
The Figure 4 implements a max supply selector along with a 4-channel logic level shifter using a single
ULN20003LV. This setup configures ULN2003LV’s channel clamp diodes OUT5 – OUT7 in a diode-OR
configuration and thus the maximum supply among VSUP1, VSUP2 and VSUP3 becomes available at the COM
pin. The maximum supply is then used as a pull-up voltage for level shifters. Limit the net GND pin current to
less than 100mA DC to ensure reliability of the conducting diode. The unconnected inputs IN5-IN7 are pulled to
GND potential through 300kΩ internal pull-down resistor.
VSUP _MAX
Logic Inputs
(1.8V to 5V)
ULN2003LV
IN1
OUT1
IN2
OUT2
IN3
OUT3
IN4
OUT4
IN5
OUT5
IN6
OUT6
IN7
OUT7
GND
VSUP3
VSUP2
VSUP1
VSUP_MAX
COM
VSUP_MAX = Max of {VSUP1, VSUP2, VSUP3} – VF
VF = Diode forward drop@ Total ground-pin current
Figure 4. ULN2003LV as Max Supply Selector
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ULN2003LV
SLRS059A – APRIL 2012 – REVISED APRIL 2012
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Constant Current Generation
When configured as per Figure 5 the ULN2003LV outputs OUT1-OUT6 act as independent constant current
sources. The current flowing through the resistor R1 is copied on all other channels. To increase the current
sourcing connect several output channels in parallel. To ensure best current copying set voltage drop across
connected load such that VOUTx matches to VOUT7.
VSUP
VIN (Up to 5.5V)
VSUP LED Supply(Up to 8V)
IREF7
R1 = (VIN-VOUT7)/IREF7
Use plot to estimate VOUT7 for the desired IREF7
R1
OUT7
ULN2003LV
IN1
OUT 1
IN2
OUT 2
IN3
OUT 3
IN4
OUT 4
IN5
OUT 5
IN6
OUT 6
IN7
OUT 7
GND
OUT 7
VSUP
COM
Figure 5. ULN2003LV as a Constant Current Driver
Figure 6. ULN2003LV Iref vs VOUTx
8
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SLRS059A – APRIL 2012 – REVISED APRIL 2012
Unipolar Stepper Motor Driver
The Figure 7 shows an implementation of ULN2003LV for driving a uniploar stepper motor. The unconnected
input channels can be used for other functions. When an input pin is left open the internal 300kΩ pull down
resistor pulls the respective input pin to GND potential. For higher noise immunity use an external short across
an unconnected input and GND pins.
Motor
Motor Supply(Up to 8V)
VSUP
Motor Control Pulses
(3V to 5V)
ULN2003LV
IN1
OUT1
Phase_A
IN2
OUT2
Phase_C
IN3
OUT3
Phase_B
IN4
OUT4
Phase_D
IN5
OUT5
IN6
OUT6
IN7
OUT7
GND
VSUP
COM
Figure 7. ULN2003LV as a Stepper Motor Driver
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ULN2003LV
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NOR Logic Driver
Figure 8 shows a NOR Logic driver implementation using ULN2003LV. The output channels sharing a common
pull-up resistor implement a logic NOR of the respective channel inputs. The LEDs connected to outputs OUT5OUT7 light up when any of the inputs IN5-IN7 is logic-high ( > VIH).
VSUP
Logic Inputs
(1.8V to 5V)
ULN2003LV
IN1
OUT1
IN2
OUT2
IN3
OUT3
IN4
OUT4
IN5
OUT5
IN6
OUT6
IN7
OUT7
IN1 NOR IN2
IN3 NOR IN4
VSUP
IN1 NOR IN2 NOR IN3
GND
VSUP
COM
Figure 8. ULN2003LV as a NOR driver
10
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1.8V Relay Driver
To drive lower voltage relays, like 1.8V, connect two or more adjacent channels in parallel as shown in Figure 9.
Connecting several channels in parallel lowers the channel output resistance and thus minimizes VOL for a fixed
current.
VSUP
1.8V Relays
ULN2003LV
1.8V Logic
1.8V Logic
1.8V Logic
IN1
OUT1
IN2
OUT2
IN3
OUT3
IN4
OUT4
IN5
OUT5
IN6
OUT6
IN7
OUT7
GND
VSUP
COM
Figure 9. ULN2003LV Driving 1.8V Relays
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ULN2003LV
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TYPICAL CHARACTERISTICS
TA = +25ºC
Figure 10. Load Current 1-Channel; VOL=0.4V
Figure 11. Load Current 7-Channels in parallel; VOL=0.4V
Figure 12. VOL versus IOUT VIN = 1.8V, 3.3V, 5.0V
Figure 13. VOL versus IOUT 2-Channels in parallel;
VOL=0.4V
Figure 14. Freewheeling Diode VF versus IF
12
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Apr-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
ULN2003LVDR
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
ULN2003LVPWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
ULN2003LVPWR
Package Package Pins
Type Drawing
TSSOP
PW
16
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
12.4
Pack Materials-Page 1
7.0
B0
(mm)
K0
(mm)
P1
(mm)
5.6
1.6
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ULN2003LVPWR
TSSOP
PW
16
2000
364.0
364.0
27.0
Pack Materials-Page 2
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power.ti.com
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microcontroller.ti.com
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www.ti.com/omap
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