SN74LV1T04 www.ti.com SCLS738A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 Single Power Supply Inverter Gate CMOS Logic Level Shifter Check for Samples: SN74LV1T04 FEATURES DESCRIPTION • SN74LV1T04 is Low Voltage CMOS gate logic and operates in wider voltage range for portable equipment and battery back-up equipment. All output logic level is a compatible CMOS Logic level with referring to the supply VCC which enable to output 3.3V and 5V CMOS Output. 1 • • • • • • • • • • • • • • (1) Single-Supply Voltage Translator at 5.0/3.3/2.5/1.8V Operating Range of 1.8V to 5.5V Up Translation Mode – 1.2V(1) to 1.8V at 1.8V VCC – 1.5V(1) to 2.5V at 2.5V VCC – 1.8V(1) to 3.3V at 3.3V VCC – 3.3V to 5.0V at 5.0V VCC Down Translation Mode – 3.3V to 1.8V at 1.8V VCC – 3.3V to 2.5V at 2.5V VCC – 5.0V to 3.3V at 3.3V VCC Logic Output is referring to supply VCC Optimized the output driving – 8mA Output Drive at 5V – 7mA Output Drive at 3.3V – 3mA Output Drive at 1.8V Unique Direction Translation-Up Characterized up to 50MHz at 3.3V VCC 5V Tolerance on Input Pins –40°C to 125°C Operating Temperature Range Pb-Free Packages Available: SC-70 (DCK) – 2 × 2.1 × 0.65 mm (Height 1.1mm) Latch-Up Performance Exceeds 250mA Per JESD 17 ESD Performance Tested Per JESD 22 – 2000-V Human-Body Model (A114-B, Class II) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) Enable the standard gate function and drop-in replacement Backward output compatible with AUP1G, LVC1G The input is designed with lower threshold circuit to match 1.8V Input Logic at VCC = 3.3V and can be used in 1.8V to 3.3V Level Up Translator functions. In addition, the 5V Input tolerant on input pins enable the chip to configure Down Translation as 3.3V to 2.5V Output at VCC = 2.5V. The wide VCC range of 1.8V to 5.5V allows the possibility of desired switching output level to connect the controllers or processors. The SN74LV1T04 is designed with optimized currentdrive capability of 8 mA to reduce line reflections, overshoot, and undershoot caused by high-drive outputs. DCK or DBV PACKAGE (TOP VIEW) NC 1 A 2 GND 3 5 VCC 4 Y Refer the VIH/VIL and output drive for lower VCC condition. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated SN74LV1T04 SCLS738A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. FUNCTION TABLE INPUT (Lower Level Input) OUTPUT (VCC CMOS) A Y H L L H SUPPLY VCC = 3.3V A Y VIH(min) =1.35 V VIL(max) =0.8 V VOH(min) = 2.9 V VOL(max)= 0.2 V A 2 4 Y Figure 1. Logic Diagram (NAND Gate) Figure 2. Excellent Signal Integrity (1.8V to 3.3V at 3.3V VCC) 2 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links :SN74LV1T04 SN74LV1T04 www.ti.com SCLS738A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 Figure 3. Excellent Signal Integrity (3.3V to 3.3V at 3.3V VCC) Figure 4. Excellent Signal Integrity (3.3V to 1.8V at 1.8V VCC) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links :SN74LV1T04 3 SN74LV1T04 SCLS738A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com TYPICAL DESIGN EXAMPLES VIH = 2.0V VIL = 0.8V 5.0V 3.3V System VIH = 0.99V VIL = 0.55V Vcc = 5.0V 5.0V, 3.3V 2.5V, 1.8V 1.5V, 1.2V System 5.0V System LV1Txx Logic Vcc = 1.8V 1.8V System LV1Txx Logic Vcc = 3.3V 5.0V, 3.3V 2.5V, 1.8V System LV1Txx Logic 3.3V System VOH min = 2.4V VIH min = 1.36V VOL max = 0.4V VIL min = 0.8V Figure 5. Switching Thresholds for 1.8-V to 3.3-V Translation ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 7.0 V VI Input voltage range (2) –0.5 7.0 V –0.5 4.6 V –0.5 VCC + 0.5 VO Voltage range applied to any output in the high-impedance or power-off state (2) Voltage range applied to any output in the high or low state (2) UNIT V IIK Input clamp current VI < 0 –20 mA IOK Output clamp current VO < 0 or VO > VCC ±20 mA IO Continuous output current ±25 mA Continuous current through VCC or GND ±50 mA θJA Package thermal impedance (3) Tstg Storage temperature range (1) (2) (3) 4 DBV package 206 DCK package –65 252 °C/W 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51-7. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links :SN74LV1T04 SN74LV1T04 www.ti.com SCLS738A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 RECOMMENDED OPERATING CONDITIONS (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage 1.6 5.5 V VI Input voltage 0 5.5 V VO Output voltage 0 VCC V IOH High-level output current IOL Low-level output current Δt/Δ v TA (1) Input transition rise or fall rate VCC = 1.8 V –3 VCC = 2.5 V –5 VCC = 3.3 V –7 VCC = 5.0 V –8 VCC = 1.8 V 3 VCC = 2.5 V 5 VCC = 3.3 V 7 VCC = 5.0 V 8 VCC = 1.8 V 20 VCC = 3.3 V or 2.5V 20 VCC = 5.0 V 20 Operating free-air temperature –40 125 mA mA ns/V °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS TA = 25°C VCC MIN VIH Low-level input voltage 0.94 1.0 1.02 1.03 1.135 1.18 VCC = 2.75 V 1.21 1.23 VCC = 3 V to 3.3 V 1.35 1.37 VCC = 3.6 V 1.47 1.48 VCC = 4.5 V to 5.0 V 2.02 2.03 2.1 IOH = –2.3 mA IOH = –3 mA VOH IOH = –3 mA IOH = –3.0 mA IOH = –5.5 mA IOH = –5.5 mA IOH = –4 mA IOH = –8 mA IOH = –8 mA 2.11 0.55 VCC = 2.25 V to 2.75 V 0.75 0.71 0.8 0.65 1.65 V to 5.5 V 0.8 VCC – 0.1 1.28 1.21 1.5 1.45 1.8V 2.3V 2.5V 3.0 V 3.3 V 4.5 V 5.0 V 2 2 2 1.93 2.25 2.15 2.78 2.7 2.6 2.49 2.9 2.8 4.2 4.1 4.1 3.95 4.6 4.5 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links :SN74LV1T04 V 0.8 VCC – 0.1 1.65 V UNIT V 0.58 VCC = 4.5 V to 5.5 V IOH = –2.0 mA MAX VCC = 1.65 V to 2.0 V VCC = 3 V to 3.6 V IOH = –20 µA MIN VCC = 2.0 V VCC = 5.5 V VIL TA = –40°C to 125°C MAX VCC = 1.65 V to 1.8 V VCC = 2.25 V to 2.5 V High-level input voltage TYP V V V V V V 5 SN74LV1T04 SCLS738A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX 0.1 0.1 1.65 V 0.2 0.25 0.1 0.15 2.3V IOL = 3 mA 3.0 V IOL = 4 mA 4.5 V IOL = 8 mA VI = 0 V or VCC 0.15 0.2 0.1 0.15 0.2 0.252 0.15 0.2 0.3 0.35 0.12 ±1 5.0 V 1 10 3.3 V 1 10 2.5 V 1 10 0V, 1.8V, 2.5V, 3.3V, 5.5 V VI = 0 V or VCC, IO = 0; open on loading ICC TA = –40°C to 125°C MAX 1.65 V to 5.5 V IOH = 3 mA A input TYP IOL = 1.9 mA IOL = 5.5 mA II MIN IOL = 20 µA IOH = 2.3 mA VOL TA = 25°C VCC UNIT V μA μA 1.8V 1 10 One input at 0.3V or 3.4V, Other inputs at 0 or VCC, IO = 0 5.5 V 1.35 1.5 mA One input at 0.3V or 1.1V Other inputs at 0 or VCC, IO = 0 1.8V 10 10 μA Ci VI = VCC or GND 3.3 V 2 10 pF Co VO = VCC or GND 3.3 V 2.5 ΔICC 10 2 2.5 pF SWITCHING CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7) PARAMETER FROM (INPUT) TO (OUTPUT) FREQUENCY (TYP) VCC 5.0V DC to 50 MHz 3.3V tpd Any In Y DC to 25 MHz 2.5V DC to 15 MHz 1.8V CL TA = 25°C MIN TA = –65°C to 125°C TYP MAX MIN TYP MAX 15pF 4 5 4 5 30pF 5.5 7.0 5.5 7.0 15pF 4.8 5 5 5.5 30pF 5 5.5 5.5 6.5 15pF 6 6.5 7 7.5 30pF 6.5 7.5 7.5 8.5 15pF 10.5 11 11 12 30pF 12 13 12 14 UNIT ns ns ns ns OPERATING CHARACTERISTICS TA = 25°C PARAMETER Cpd 6 Power dissipation capacitance TEST CONDITIONS f = 1 MHz and 10 MHz Submit Documentation Feedback VCC TYP 1.8 V ± 0.15 V 10 2.5 V ± 0.2 V 10 3.3 V ± 0.3 V 10 5.5 V ± 0.5 V 10 UNIT pF Copyright © 2013, Texas Instruments Incorporated Product Folder Links :SN74LV1T04 SN74LV1T04 www.ti.com SCLS738A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 PARAMETER MEASUREMENT INFORMATION From Output Under Test CL (see Note A) VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V 5, 10, 15, 30 pF VI/2 VCC/2 5, 10, 15, 30 pF VI/2 VCC/2 1 MΩ CL VMI VMO LOAD CIRCUIT VI VMI Input VMI 0V tPHL tPLH VOH VMO Output VMo VOL tPHL tPLH VOH VMo Output VMo VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS NOTES: A. B. C. D. CL includes probe and jig capacitance. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns. The outputs are measured one at a time, with one transition per measurement. tPLH and tPHL are the same as tpd. Figure 6. Load Circuit and Voltage Waveforms MORE PRODUCT SELECTION DEVICE PACKAGE DESCRIPTION SN74LV1T00 DCK, DBV 2-Input Positive-NAND Gate SN74LV1T02 DCK, DBV 2-Input Positive-NOR Gate SN74LV1T04 DCK, DBV Inverter Gate SN74LV1T08 DCK, DBV 2-Input Positive-AND Gate SN74LV1T17 DCK, DBV Single Buffer Gate with 3-state Output SN74LV1T14 DCK, DBV Single Schmitt-Trigger Inverter Gate SN74LV1T32 DCK, DBV 2-Input Positive-OR Gate SN74LV1T50 DCK, DBV Single Buffer Gate with 3-state Output SN74LV1T86 DCK, DBV Single 2-Input Exclusive-Or Gate SN74LV1T125 DCK, DBV Single Buffer Gate with 3-state Output SN74LV1T126 DCK, DBV Single Buffer Gate with 3-state Output SN74LV4T125 RGY, PW Quadruple Bus Buffer Gate With 3-State Outputs Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links :SN74LV1T04 7 SN74LV1T04 SCLS738A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com REVISION HISTORY Changes from Original (September 2013) to Revision A • 8 Page Updated VCC values for VIH parameter in the ELECTRICAL CHARACTERISTICS table. ................................................... 5 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links :SN74LV1T04 PACKAGE OPTION ADDENDUM www.ti.com 30-Sep-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) SN74LV1T04DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 (NEC3 ~ NECS) SN74LV1T04DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 (WC3 ~ WCS) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 27-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ SN74LV1T04DBVR SOT-23 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DBV 5 3000 178.0 9.2 3.3 3.2 1.55 4.0 8.0 Q3 SN74LV1T04DBVR SOT-23 DBV 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 SN74LV1T04DCKR SC70 DCK 5 3000 180.0 8.4 2.25 2.4 1.22 4.0 8.0 Q3 SN74LV1T04DCKR SC70 DCK 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 27-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LV1T04DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 SN74LV1T04DBVR SOT-23 DBV 5 3000 202.0 201.0 28.0 SN74LV1T04DCKR SC70 DCK 5 3000 202.0 201.0 28.0 SN74LV1T04DCKR SC70 DCK 5 3000 180.0 180.0 18.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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