THS7318 www.ti.com SLOS517A – JANUARY 2007 – REVISED FEBRUARY 2007 3-Channel Low-Power EDTV/SDTV Video Line Driver With Low-Pass Filters FEATURES • • • • • • • DESCRIPTION Single Supply: 2.85 V to 5 V Low Total Supply Current = 4.5 mA (max) Low Power Mode: 5 µW (max) Integrated DAC Reconstruction Filters Video Line Driver Outputs with 6 dB Gain Rail-to-Rail Output RoHS Compliant 9-Pin Wafer Scale Package APPLICATIONS • • • • Personal Media Players Digital Cameras Cellular Phone Video Output Buffering USB/Portable Low Power Video Buffering The THS7318 is a very low power single-supply 3 channel device designed to process Y’, P’B, P’R enhanced definition TV and Y’, C’, and CVBS standard definition TV signals. It integrates circuitry to perform signal processing commonly required in video output applications. All channels incorporate 3rd-order 20-MHz Butterworth DAC reconstruction filters designed for video systems with 54 MSPS DAC sampling rates like NTSC/PAL 480p/576p EDTV and 480i/576i SDTV video. Rail-to-Rail output drivers on all channels allow for both ac and dc coupled outputs. The low quiescent current makes it an excellent choice for USB powered or portable video applications. The THS7318 is available in a 9-pin NanoFree™ wafer scale package. It is specified for operation from 0°C to 70°C. THS7318 BLOCK DIAGRAM - + Y’ IN LPF 6 dB Y’ OUT LPF 6 dB PB’ OUT / CVBS OUT LPF 6 dB PR’ OUT / C’ OUT DC Offset - PB’ IN / CVBS IN + DC Offset - PR’ IN / C’ IN + DC Offset EN Bias Control GND Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoFree is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated THS7318 www.ti.com SLOS517A – JANUARY 2007 – REVISED FEBRUARY 2007 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VSS Supply voltage, VS+ to GND VI Input voltage IO Output current Continuous power dissipation Maximum junction temperature Tstg Storage temperature range ESD ratings (2) (3) UNIT 5.5 V –0.4 to VS+ V ±100 mA See Dissipation Rating Table TJ (1) VALUE Any condition (2) Continuous operation, long term reliability (3) 150 °C 125 °C –65 to 150 °C HBM 2000 V CDM 1500 V MM 200 V Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may degrade device reliability. The absolute maximum junction temperature under any condition is limited by the constraints of the silicon process. The absolute maximum junction temperature for continuous operation is limited by the package constraints. Operation above this temperature may result in reduced reliability and/or lifetime of the device. DISSIPATION RATINGS (1) (1) (2) PACKAGE θJC (°C/W) θJA (°C/W) YZF 38 105 POWER RATING (2) (TJ = 125°C) TA = 25°C TA = 70°C 950 mW 428 mW This data was taken with the JEDEC High-K test PCB. Power rating is determined with a junction temperature of 125°C. This is the point where distortion starts to substantially increase and long-term reliability starts to be reduced. Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance and reliability. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN 2 VS+ Supply voltage TA Ambient temperature Submit Documentation Feedback MAX UNIT 2.85 5 V 0 70 °C THS7318 www.ti.com SLOS517A – JANUARY 2007 – REVISED FEBRUARY 2007 PACKAGING/ORDERING INFORMATION PACKAGED DEVICES THS7318YZFT THS7318YZFR (1) PACKAGE TYPE (1) PART CODE Wafer Scale 9-pin BYR TRANSPORT MEDIA, QUANTITY Tape and Reel, 250 Tape and Reel, 3000 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. NanoFree™ Placement and Removal Procedures These procedures are generic guidelines to rework NanoFree™ packages assembled on a 0.056-inch thick FR4 board. It’s recommended to modify heating profiles for different board thicknesses and equipment used. The assembly process recommended below should be used with a new device. Do not reuse the part after it is removed. Air-VacEngineering (www.air-vac-eng.com) has established NanoFreeTM reflow profiles for their Hot Gas (convection) rework equipment DRS-24NC. The NMX090DVG nozzle is recommended for use with the YZF package. Customers can use other comparable hot gas (convection) equipment and tooling. Placement 1. Apply flux paste to component 2. Align device over pads 3. Place device on board. Care must be taken to prevent over-travel during placement which may damage the part or vacuum tip. 4. Raise nozzle 0.05" 5. Preheat board to 90°C, nozzle warming up 20% air flow, 125°C 6. Soak Stage—20% air flow, 225°C, 90 seconds 7. Ramp Stage—20% air flow, 335°C, 30 seconds 8. Reflow Stage—25% air flow, 370°C, 65 seconds 9. Cool down Stage—40% air flow, 25°C, 50 seconds Removal 1. Apply flux paste to component 2. Align Nozzle over part to be removed 3. Maintain nozzle 0.050"over device. Care must be taken to prevent over-travel of the vacuum tip which may damage the part or vacuum tip when measuring this distance. 4. Preheat board to 90°C, nozzle warming up 20% air flow, 125°C 5. Soak Stage—20% air flow, 225°C, 90 seconds 6. Ramp Stage—20% air flow, 335°C, 30 seconds 7. Reflow Stage—25% air flow, 370°C, 65 seconds 8. Enable Vacuum at the end of the reflow cycle, lower vacuum nozzle, and remove part 9. Cool down Stage—40% air flow, 25°C, 50 seconds 10. Turn off the vacuum and remove part from nozzle. 11. Care should be used if the device is to be returned to TI for failure analysis. Using any metal tweezers or rough handling can damage the part, and render it un-analyzable. Submit Documentation Feedback 3 THS7318 www.ti.com SLOS517A – JANUARY 2007 – REVISED FEBRUARY 2007 ELECTRICAL CHARACTERISTICS VS+ = 3.3V, 27°C, Y’ and P’R / C’ channels: RL = 150 Ω and CL = 6.2 pF to GND P’B / CVBS channel: 75 Ω and CL = 6.2 pF to GND (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 2.85 3.3 5 UNIT TEST LEVEL (1) V B DC CHARACTERISTICS VSS Supply voltage range IQ Quiescent supply current EN = High VSD Shutdown supply current EN = Low Output DC level shift voltage All channels Input bias current 2.8 3.5 4.5 mA A 0.150 <1 µA A 110 150 200 mV A Y’ and P’B / CVBS channels –100 –160 –240 nA A P’R / C’ channel –170 –280 –415 nA A MΩ/pF C V/V A % A dB A Input resistance / capacitance 2.4/1 Voltage gain 1.98 Channel to Channel Gain Match All Channels PSRR VOH Power supply rejection Output voltage swing high P’B output high minus output offset Output short-circuit current Max current into EN pin DC 2 2.02 ±0.14 ±1 47 Y’ and P’R / C’ channel, 150 Ω to GND 2.85 2.96 V A P’B / CVBS channel, 50 Ω to GND 2.6 2.9 V A At Vs+ = 3.135 V, P’B / CVBS channel, 50 Ω to GND 2.3 2.65 V A 70 mA C 100 mA C Y’ and P’R / C’ channel P’B / CVBS channel EN = Low <1 µA A EN = High <1 µA A 0.6 V A Disable threshold Low = off Enable threshold High = on Output impedance in shutdown EN = Low 2.1 V A 20 kΩ C 11 MHz C 17 MHz A MHz B AC PERFORMANCE tr/tf (1) 4 ±0.1 dB Bandwidth Relative to 1 MHz ±1.0 dB Bandwidth Relative to 1 MHz 14 –3 dB Bandwidth Relative to 1 MHz 17 Normalized stop band gain f = 43 MHz, Relative to 1 MHz –21 Differential gain NTSC and PAL Differential phase NTSC and PAL Group delay variation f = 11 MHz w/ref to 1 MHz Signal to noise ratio VOUT = 2-VPP sine wave Rise / fall time VOUT = 2-V step Positive/ negative slew rate THD at 1MHz 20 dB A 0.05 % C 0.03 deg C 4 ns C 62 dB C 20 ns C VOUT = 2-V step 80 V/µs C At 1MHz, 2 VPP 73 dBc C Test levels: (A) 100% tested at 25°C. Overtemperature limits set by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. Submit Documentation Feedback –12 THS7318 www.ti.com SLOS517A – JANUARY 2007 – REVISED FEBRUARY 2007 THS7318 (Top View) XXXXXX Date/Trace Code BYRS Device Code Assembly Site Code Pin A1 Index THS7318 (Bottom View) Vs+ Y’ IN C Y’ OUT EN PB’ IN / CVBS IN PR’ IN / C’ IN PB’ OUT / CVBS OUT B PR’ OUT / C’ OUT A 1 2 3 GND TERMINAL FUNCTIONS COL. ROW PIN NAME 1 C Y' IN 1 B PB’ IN / CVBS IN 1 A PR’ IN / C’ IN 2 C Vs+ Positive power supply input 2 B EN Enable input. Logic high enables part. Logic low disables part. To insure proper operation, this pin must be driven and cannot be left floating. 2 A GND 3 C Y’ OUT 3 B PB’ OUT / CVBS OUT 3 A PR’ OUT / C’ OUT DESCRIPTION Luma input Component video input / composite video input Component video input / chroma input Ground reference pin for all internal circuitry Luma output Component video output / composite video output Component video output / chroma output Submit Documentation Feedback 5 THS7318 www.ti.com SLOS517A – JANUARY 2007 – REVISED FEBRUARY 2007 THS7318 DESCRIPTION The THS7318 is an integrated analog video processor designed with integrated Butterworth filters and video line driver amplifiers to provide the analog signal conditioning required for EDTV signals in portable video applications. The device accepts 3 inputs; Y’ (Luma), P’B / CVBS (analog color difference with blue emphasis / composite video) and P’R / C’ (analog color difference with red emphasis / chroma), and provides 3 filtered and amplified outputs; Y’, P’B / CVBS and P’R / C’. The following are detailed descriptions of each channel. CHANNEL DESCRIPTIONS All channels are comprised of DC offset, 3rd order Butterworth low pass filter, and output buffer amplifier. All channels are same except the Y’ and P’R / C’ output amplifiers are designed to drive one doubly terminated 75Ω video line and the P’B / CVBS output amplifier is designed to drive two doubly terminated 75Ω video lines. Even under the fault condition where one of the video lines is shorted, the P’B / CVBS output amplifier is capable of full video performance on the properly terminated output. DC Offset The DC offset circuit is used to insure the output is not driven into saturation and video signal is not compressed. The nominal output offset caused by this circuit is 150 mV. 3rd Order Butterworth Low Pass Filter To reduce DAC images that cause aberrations in the video display, a 3rd order Butterworth low pass filter is inserted in the signal path. This DAC reconstruction filter is designed for video systems with 54 MSPS DAC sampling rates like NTSC/PAL 480p/576p EDTV and 480i/576i SDTV video, with nominal 0.1-dB flatness to 11 MHz, -3-dB bandwidth of 20 MHz, and 20 dB attenuation at 43 MHz. Output Buffer Amplifier The output buffer amplifiers are designed for a gain of 6 dB. The Y’ and P’R / C’ output amplifiers are designed to drive one doubly terminated 75Ω video line and the P’B / CVBS output amplifier is designed to drive two doubly terminated 75Ω video lines. Even under the fault condition where one of the video lines is shorted, the P’B / CVBS output amplifier is capable of full video performance on the properly terminated output. 6 Submit Documentation Feedback THS7318 www.ti.com SLOS517A – JANUARY 2007 – REVISED FEBRUARY 2007 TYPICAL APPLICATION CIRCUITS +3.3V DVDD 0.1 mF 0.1 mF Y’ IN C Y’ OUT P’B IN / CVBS IN B P’B OUT / CVBS OUT P’R IN / C’ IN A P’R OUT / C’ OUT 75 W Y’ R S Video CVBS R 75 W C’ R 1 DAC / Encoder 2 75 W 75 W 3 75 W CVBS 1 75 W CVBS 2 GND EN 75 W 75 W Figure 1. Application Drawing CVBS and S Video +3.3V DVDD 0.1 mF 0.1 mF 75 W Y’ IN C Y’ OUT P’B IN / CVBS IN B P’B OUT / CVBS OUT P’R IN / C’ IN A P’R OUT / C’ OUT 75 W Y’ R P’B R P’R R 1 DAC / Encoder 2 3 Component Video 75 W 75 W 75 W GND 75 W EN Figure 2. Application Drawing Component Video Submit Documentation Feedback 7 PACKAGE OPTION ADDENDUM www.ti.com 7-Feb-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty THS7318YZFR ACTIVE DSBGA YZF 9 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM THS7318YZFT ACTIVE DSBGA YZF 9 250 SNAGCU Level-1-260C-UNLIM Green (RoHS & no Sb/Br) Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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