AMC7820 AM C78 20 SBAS231B – MARCH 2002 ANALOG MONITORING AND CONTROL FEATURES DESCRIPTION ● 100kHz SAMPLING RATE 12-BIT ADC The AMC7820 is a complete analog monitoring and control circuit that includes an 8-channel, 12-bit Analog-to-Digital Converter (ADC), three 12-bit Digital-to-Analog Converters (DACs), nine operational amplifiers, a thermistor current source, an internal +2.5V reference, and an SPI™ serial interface. External reference may be applied. Typical power dissipation is 40mW. For the ADC, the unbuffered analog input range is 0V to +5.0V, and the buffered analog common-mode input range is 0V to +3.8V. For the DACs, the analog output range is 0V to +2.5V or 0V to +5.0V. ● 8 ANALOG INPUT CHANNELS ● THREE 12-BIT DACS ● NINE OPERATIONAL AMPLIFIERS ● THERMISTOR CURRENT SOURCE ● INTERNAL 2.5V REFERENCE ● SPI SERIAL INTERFACE ● 3V LOGIC COMPATIBLE The AMC7820 is ideal for multichannel applications where low power and small size are critical. The AMC7820 is available in a TQFP-48 package and is fully specified and tested over the –40°C to +85°C temperature range. ● SINGLE +5V SUPPLY ● LOW POWER: 40mW ● TQFP-48 PACKAGE SPI is a trademark of Motorola. APPLICATIONS ● CW LASER AND PUMP LASER CURRENT CONTROL IN DWDM ● TEC COOLER CURRENT CONTROL IN DWDM ● OPTICAL POWER MONITORING ● TUNABLE LASER Reference (2.5V) ADC Current Source up to 1mA … SPI Interface and Control 2.5V Output 8-Channel MUX External Reference AMC7820 5 Precision OPAs 12-Bit ADC/DAC DAC0 DAC1 DAC2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright © 2001, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) AVDD, DVDD, BVDD to GND .................................................. –0.3V to +6V Digital Input Voltage to GND ................................. –0.3V to BVDD + 0.3V Analog Input Voltage to GND ................................ –0.3V to AVDD + 0.3V Input Current: Continuous .............................................................. ±20mA Momentary ............................................................ ±100mA Operating Temperature Range ...................................... –40°C to +105°C Storage Temperature Range ......................................... –65°C to +150°C Junction Temperature (TJ Max) .................................................... +150°C TQFP Package Power Dissipation ....................................................... (TJ Max – TA)/θJA θJC Thermal Impedance ............................................................. 15°C/W θJA Thermal Impedance ............................................................. 60°C/W Lead Temperature (soldering) Vapor Phase (60s) .................................................................. +220°C Infrared (15s) ........................................................................... +220°C This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. PACKAGE/ORDERING INFORMATION SPECIFIED TEMPERATURE RANGE SPECIFIED PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY AMC7820Y AMC7820Y AMC7820Y/250 AMC7820Y/2K Tape and Reel, 250 Tape and Reel, 2000 PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR(1) AMC7820Y AMC7820Y TQFP-48 PFB –40°C to +85°C “ “ “ NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com. ELECTRICAL CHARACTERISTICS At –40°C to +85°C, AVDD, DVDD, BVDD = +5V, using external 2.5V reference, unless otherwise noted. AMC7820 PARAMETER ADC Input Input Input Input ANALOG INPUTS(1) Voltage Range Impedance Capacitance Leakage Current ADC Resolution No Missing Codes Integral Linearity Differential Linearity Offset Error Offset Error Drift Offset Error Match Gain Error Gain Error Match Noise Power-Supply Rejection Throughput Rate Total Conversion Time DAC(3) Output Voltage Range Output Current Resolution Integral Linearity(4) Monotonicity Differential Linearity Offset Error Offset Error Drift Gain Error Settling Time Code Change Glitch Impulse THERMISTOR CURRENT SOURCE Output Current Range Output Current Accuracy Output Impedance Compliance Voltage Power-Supply Rejection Ratio 2 CONDITION MIN TYP MAX UNITS 2 • VREF V MΩ pF µA 12 Bits Bits LSB(2) LSB LSB ppm/°C LSB % LSB µVrms LSB kHz µs Channels 2-5 0 5 15 ±1 12 ±1 ±1 ±2 ±4 0.5 ±0.3 0.3 150 1.2 100 80 Channels 2-5 Channels 2-5 +AVDD, +DVDD = +5V ±5% Scan All 8 Channels DAC_OUT_SET Connected to DAC_OUT DAC_OUT_SET = AGND Refer to the Characteristic Curves 0 0 ±1 ±4 ±2 ±5 1 ±1.5 1 VREF 2 • VREF 12 ±8 12 ±0.1 ±0.5 ±1 ±4 ±0.3 3 20 Output Range 0 – VREF Output Range 0 – 2 • VREF Output Range = 0V to 2 • VREF or 0V to VREF Step Between Codes 1024 and 2048 1LSB Change Around Major Carry RISET = 100kΩ RISET = 100kΩ 10 98 100 ±1 ±5 ±10 ±1.5 1000 102 500 0 3 60 V V mA Bits LSB Bits LSB mV mV ppm/°C % µs nV-s µA µA MΩ V dB AMC7820 www.ti.com SBAS231B ELECTRICAL CHARACTERISTICS (Cont.) At –40°C to +85°C, AVDD, DVDD, BVDD = +5V, using external 2.5V reference, unless otherwise noted. AMC7820 PARAMETER VOLTAGE REFERENCE (VREF) Internal Reference Voltage Internal Reference Drift(5) CONDITION Input Offset Current(7) Input Voltage Noise Input Voltage Noise Density Current Noise Density Common-Mode Voltage Range Common-Mode Rejection Ratio(8) Open-Loop Gain(8) Gain-Bandwidth Product Slew Rate Settling Time: 0.1% Voltage Output Swing from Rail Closed-Loop Output Impedance Output Current Short-Circuit Current DIGITAL INPUT/OUTPUT Logic Level: VIH VIL VOH VOL Logic Level: VIH VIL VOH VOL Input Capacitance POWER-SUPPLY REQUIREMENTS Power-Supply Voltage AVDD, DVDD BVDD Quiescent Current of AVDD Quiescent Current of DVDD Quiescent Current of BVDD Power Dissipation TYP MAX UNITS 2.45 2.50 ±10 ±30 0.5 ±1 ±15 2.50 10 5 2.55 V ppm/°C ppm/°C Ω mA mA V kΩ pF 0°C to +85°C –40°C to +85°C 2.5V Output Impedance (pin 26) 2.5V Output Current (pin 26) Short-Circuit Current (pin 26) External Reference Voltage Range (pin 27) External Reference Input Resistance External Reference Input Capacitance OP AMP CHARACTERISTICS(6) Input Offset Voltage vs Temperature vs Power Supply Input Bias Current(7) MIN 2.45 TA = +25°C TA = –40°C to +85°C TA = +25°C f = 0.1Hz to 10Hz f = 1kHz f = 1kHz –0.2V < VCM < AVDD – 1.2V RL = 25kΩ, 125mV < VO < AVDD – 125mV G=1 G=1 2V Step, CL = 100pF, G = 1, RL = 10kΩ RL = 25kΩ See Typical Characteristics 2.55 ±0.5 ±4 ±2 50 ±2 ±50 See Typical Characteristics ±1 ±50 6 26 0.6 –0.2 AVDD – 1.2 74 90 100 120 3 1.2 3 40 0.4 ±1 ±18 mV µV/°C µV/V pA pA µVp-p nV/√Hz fA/√Hz V dB dB MHz V/µs µs mV Ω mA mA BVDD = 5V, |IIH| ≤ 10µA BVDD = 5V, |IIL| ≤ 10µA BVDD = 5V, IOH = –3mA BVDD = 5V, IOL = 3mA 3.5 0 4.0 0 BVDD + 0.3 0.8 BVDD 0.4 V V V V BVDD = 3V, |IIH| ≤ 10µA BVDD = 3V, |IIL| ≤ 10µA BVDD = 3V, IOH = –3mA BVDD = 3V, IOL = 3mA 2.1 0 2.4 0 BVDD + 0.3 0.6 BVDD 0.4 V V V V pF 5.25 5.25 12 0.75 0.1 V V mA mA mA mW +85 +150 °C °C 5 Specified Performance Specified Performance 4.75 2.7 5 8 0.3 0.01 40 TEMPERATURE RANGE Specified Performance Storage –40 –65 NOTES: (1) For channels 2-5, fed into MUX directly. (2) LSB means Least Significant Bit. (3) DACs are tested without output load. (4) Measured from code 010 to FFF. (5) Internal reference voltage has been optimized for lowest drift from 0°C to +85°C. (6) Applies to all amplifiers; see Figure 2. (7) Offset current will double for each 10°C of temperature increase. See Operational Amplifier section. (8) Ensured by design. AMC7820 SBAS231B www.ti.com 3 PIN CONFIGURATION CH2 CH3 CH4 CH5 OPA1_IN– OPA1_OUT OPA1_IN+ SW1_OUT EXT_REF_IN REF_OUT_+2.5V OPA3_IN+ TQFP RESET Top View 36 35 34 33 32 31 30 29 28 27 26 25 SCLK 37 24 OPA3_OUT MOSI 38 23 OPA3_IN– MISO 39 22 DAC1_OUT SS 40 21 DAC1_OUT_SET BVDD 41 20 DAC2_OUT_SET DVDD 42 19 AVDD AMC7820 18 AGND DGND 43 17 DAC2_OUT THERM_I_OUTPUT 44 16 OPA4_IN+ ISET_RESISTOR 45 4 5 6 7 8 9 10 11 12 OPA2_IN+ OPA5_IN– OPA5_OUT 4 OPA2_OUT 3 OPA2_IN– 2 DAC0_OUT_SET 1 DAC0_OUT 13 OPA5_IN+ OPA6_IN+ OPA7_IN+ 48 OPA6_OUT 14 OPA4_IN– OPA6_IN– OPA7_OUT 47 T_SENSOR_VOLTAGE 15 OPA4_OUT SW2_OUT OPA7_IN– 46 AMC7820 www.ti.com SBAS231B PIN DESCRIPTIONS (Refer to Figure 1, Block Diagram) PIN DESIGNATOR 1 2 3 4 5 6 7 SW2_OUT T_SENSOR_VOLTAGE OPA6_IN– OPA6_OUT OPA6_IN+ DAC0_OUT DAC0_OUT_SET 8 9 10 11 12 13 14 15 16 17 18 19 20 OPA2_IN– OPA2_OUT OPA2_IN+ OPA5_IN– OPA5_OUT OPA5_IN+ OPA4_IN– OPA4_OUT OPA4_IN+ DAC2_OUT AGND AVDD DAC2_OUT_SET 21 DAC1_OUT_SET 22 23 24 25 26 27 28 29 30 31 32 33 34 35 DAC1_OUT OPA3_IN– OPA3_OUT OPA3_IN+ REF_OUT_+2.5V EXT_REF_IN SW1_OUT OPA1_IN+ OPA1_OUT OPA1_IN– CH5 CH4 CH3 CH2 36 37 38 39 RESET SCLK MOSI MISO 40 SS 41 42 43 44 45 46 47 48 BVDD DVDD DGND THERM_I_OUTPUT ISET_RESISTOR OPA7_IN– OPA7_OUT OPA7_IN+ DESCRIPTION Output from SW2. This pin connects to OPA7_OUT when SW2 is enabled; connects to the output of SW3 when SW2 is disabled. Output of temperature sensor (Thermistor) voltage buffer. Inverting Input of OPA6 Output of OPA6 Noninverting Input of OPA6 Output of DAC0 This pin determines the full-scale output of DAC0. When tied to DAC0_OUT, the full-scale output equals VREF. When connected to AGND, full-scale output equals 2 • VREF. Inverting Input of OPA2 Output of OPA2 Noninverting Input of OPA2 Inverting Input of OPA5 Output of OPA5 Noninverting Input of OPA5 Inverting Input of OPA4 Output of OPA4 Noninverting Input of OPA4 Output of DAC2 Analog Ground Analog Power Supply (+5V) This pin determines the full-scale output of DAC2. When tied to DAC2_OUT, the full-scale output equals VREF. When connected to AGND, full-scale output equals 2 • VREF. This pin determines the full-scale output of DAC1. When tied to DAC1_OUT, the full-scale output equals VREF. When connected to AGND, full-scale output equals 2 • VREF. Output of DAC1 Inverting Input of OPA3 Output of OPA3 Noninverting Input of OPA3 +2.5VOUT An external reference can be connected here. Also can be used as a filter for internal reference. Output from SW1. This pin connects to DAC2_OUT when SW1 is enabled; connects to AGND when SW1 is disabled. Noninverting Input of OPA1 Output of OPA1 Inverting Input of OPA1 Analog Input of Channel 5 Analog Input of Channel 4 Analog Input of Channel 3 Analog Input of Channel 2 Reset Input. Logic LOW on this pin will cause the part to perform a hardware reset. Serial Clock Input Master Out, Slave In. Digital data input for the serial interface. Master In, Slave Out. Digital data output for the serial interface. Slave Select Input (active LOW). Data will not be clocked into MOSI unless SS is LOW. When SS is HIGH, MISO is high impedance. Interface Power Supply. Connects to 3V for 3V logic; connects to 5V for 5V logic. Digital Power Supply (+5V) Digital Ground Current source output to drive the thermistor. The resistor connected to this pin sets the current output from the pin THERM_I_OUTPUT. Inverting Input of OPA7 Output of OPA7 Noninverting Input of OPA7 AMC7820 SBAS231B www.ti.com 5 TIMING CHARACTERISTICS At –40°C to +85°C, +AVDD = +DVDD = +5V, VREF = +2.5V, +BVDD = +5V, unless otherwise noted. PARAMETER SCLK Period SCLK HIGH or LOW Time Rise Time Fall Time Enable Lead Time Enable Lag Time Sequential Transfer Delay Data Setup Time Data Hold Time (inputs) Slave Access Time Data Valid Data Hold Time (outputs) Slave MISO Disable Time SYMBOL MIN tSCK tWSCK tR tF tLEAD tLAG tTD tSU tHI tA tV tHO tDIS 30 15 MAX UNITS 15 ns ns ns ns ns ns ns ns ns ns ns ns ns MAX UNITS 30 30 15 15 30 10 10 15 10 0 TIMING CHARACTERISTICS At –40°C to +85°C, +AVDD = +DVDD = +5V, VREF = +2.5V, +BVDD = +3V, unless otherwise noted. PARAMETER SCLK Period SCLK HIGH or LOW Time Rise Time Fall Time Enable Lead Time Enable Lag Time Sequential Transfer Delay Data Setup Time Data Hold Time (inputs) Slave Access Time Data Valid Data Hold Time (outputs) Slave MISO Disable Time SYMBOL MIN tSCK tWSCK tR tF tLEAD tLAG tTD tSU tHI tA tV tHO tDIS 40 20 ns ns ns ns ns ns ns ns ns ns ns ns ns 30 30 15 15 30 10 10 15 15 0 15 TIMING DIAGRAM tLAG tTD SS tSCK tLEAD tWSCK SCLK tF tR tWSCK tSU tHI Command BIT 15 (MSB) MOSI Command BIT 14 . . . 1 Command BIT 0 (LSB) DATA IN BIT 15 (MSB) DATA IN BIT 0 (LSB) DATA WRITTEN INTO AMC7820’s REGISTERS WRITE COMMAND FROM THE HOST tV MISO DATA IN BIT 14 . . . 1 Hi-Z DATA OUT BIT 15 (MSB) tHO DATA OUT BIT 14 . . . 1 tDIS DATA OUT BIT 0 (LSB) tA Previous value of register N before writing operation. NOTE: If SS is HIGH, MISO is in Hi-Z. WRITE OPERATION tLAG tTD SS tSCK tLEAD tWSCK SCLK tF tR tWSCK tSU Don’t Care MOSI tHI Command BIT 15 (MSB) Command BIT 14 . . . 1 Command BIT 0 (LSB) Don’t Care READ COMMAND FROM THE HOST tV MISO Hi-Z DATA OUT BIT 15 (MSB) tHO DATA OUT BIT 14 . . . 1 tDIS DATA OUT BIT 0 (LSB) tA READ OPERATION 6 DATA READ FROM AMC7820’s REGISTERS NOTE: If SS is HIGH, MISO is in Hi-Z. AMC7820 www.ti.com SBAS231B TYPICAL CHARACTERISTICS: ADC At TA = +25°C, +AVDD, BVDD = +5.0V, VREF = Internal +2.5V, unless otherwise noted. LINEARITY ERROR vs CODE (+25°C) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 512 1024 1536 2048 2560 3072 3584 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0 4096 512 1024 1536 2048 2560 3072 Code Code LINEARITY ERROR vs CODE (+85°C) OFFSET vs TEMPERATURE (Internal or External Reference) 3584 4096 1.0 Delta from +25°C (LSB) LE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 DLE (LSB) 0 LE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 DLE (LSB) LE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 DLE (LSB) LINEARITY ERROR vs CODE (–40°C) 0.5 0.0 –0.5 –1.0 0 512 1024 1536 2048 2560 3072 3584 –50 4096 –25 0 Code 25 50 Temperature (°C) 75 100 CHANNEL-TO-CHANNEL MATCH vs TEMPERATURE (Unbuffered Channels 2, 3, 4, 5) GAIN ERROR vs TEMPERATURE 0.40 0.20 0.18 Delta from +25°C (LSB) Delta from +25°C (%) 0.20 With 2.5V External Reference 0.00 –0.20 With 2.5V Internal Reference –0.40 –0.60 0.16 0.14 0.12 Offset Error Match 0.10 0.08 0.06 0.04 Gain Error Match 0.02 0.00 –0.80 –50 –25 0 25 50 Temperature (°C) 75 –50 100 0 25 50 75 100 Temperature (°C) AMC7820 SBAS231B –25 www.ti.com 7 TYPICAL CHARACTERISTICS: ADC (Cont.) At TA = +25°C, +AVDD, BVDD = +5.0V, VREF = Internal +2.5V, unless otherwise noted. POWER-SUPPLY REJECTION vs FREQUENCY 0.300 0.025 0.250 0.020 0.200 Internal VREF 0.015 0.150 0.010 0.100 0.005 0.050 0.000 0.000 Gain –0.005 –0.050 –0.010 –0.100 Offset –0.015 –0.150 –0.020 4.75 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 –0.200 5.20 5.25 40 Power-Supply Rejection (mV/V) 0.030 Offset Error Delta from AVDD = 5V (LSB) Gain Error, Internal VREF Delta from AVDD = 5V (%) GAIN ERROR, OFFSET ERROR, INTERNAL VREF vs AVDD SUPPLY VOLTAGE (Unbuffered Channels) 35 30 25 20 15 10 5 0 10 Supply Voltge, AVDD (V) 1k 10k 100k 1M AVDD Ripple Frequency (Hz) INTERNAL REFERENCE VOLTAGE vs TEMPERATURE INTERNAL 2.5V REFERENCE DISTRIBUTION 10 25 5 20 Percent of Units (%) Delta from +25°C (mV) 100 0 –5 –10 15 10 5 –15 0 –50 –25 0 25 50 75 2.450 2.455 2.460 2.465 2.470 2.475 2.480 2.485 2.490 2.495 2.500 2.505 2.510 2.515 2.520 2.525 2.530 2.535 2.540 2.545 2.550 –20 100 Temperature (°C) Internal Reference Voltage (V) 8 AMC7820 www.ti.com SBAS231B TYPICAL CHARACTERISTICS: DACs (DAC0, DAC1, DAC2) At TA = +25°C, +AVDD, BVDD = +5.0V, VREF = Internal +2.5V, unless otherwise noted. 0 512 1024 1536 2048 2560 3072 3584 LE (LSB) 8 6 4 2 0 –2 –4 –6 –8 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 4096 512 1024 1536 2048 3584 4096 OFFSET ERROR vs TEMPERATURE 8 6 4 2 0 –2 –4 –6 –8 2.0 1.5 Gain = +2 Delta from +25°C (mV) LE (LSB) LINEARITY ERROR vs CODE (+85°C) DLE (LSB) 3072 Code Code 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 1.0 0.5 0 Gain = +1 –0.5 –1.0 –1.5 –2.0 0 512 1024 1536 2048 2560 3072 3584 4096 –50 –25 0 Code GAIN ERROR vs TEMPERATURE (DAC Gain = +1 or +2) 25 50 Temperature (°C) 75 100 OUTPUT VOLTAGE vs OUTPUT CURRENT, GAIN = +1 0.4 2.5000 Output Voltage Sinking Current (V) 5.0 0.2 Delta from +25°C (%) 2560 0.0 –0.2 –0.4 Ext 2.5V Ref Int 2.5V Ref –0.6 Sourcing Current DAC at FFFH 4.5 4.0 2.4995 2.4990 3.5 2.4985 3.0 2.4980 2.5 2.4975 2.0 2.4970 1.5 2.4965 1.0 2.4960 Sinking Current DAC at 008H 0.5 2.4955 2.4950 0.0 –0.8 –50 –25 0 25 50 Temperature (°C) 75 100 0 1 2 3 4 5 6 7 Output Current Magnitude (mA) AMC7820 SBAS231B Output Voltage Sourcing Current (V) 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 LINEARITY ERROR vs CODE (+25°C) DLE (LSB) LE (LSB) 8 6 4 2 0 –2 –4 –6 –8 DLE (LSB) LINEARITY ERROR vs CODE (–40°C) www.ti.com 9 TYPICAL CHARACTERISTICS: DACs (DAC0, DAC1, DAC2) (Cont.) At TA = +25°C, +AVDD, BVDD = +5.0V, VREF = Internal +2.5V, unless otherwise noted. OUTPUT VOLTAGE vs OUTPUT CURRENT, GAIN = +2 SETTLING TIME, GAIN = +2 5.0 Output (500mV/div) Output Voltage (V) 4.0 CL = 10pF RL = 20kΩ Code 2048 Sourcing Current DAC at FFFH 3.5 3.0 2.5 2.0 1.5 Settling Detail (1LSB/div) 4.5 Code 1024 Settling Detail Sinking Current DAC at 008H 1.0 0.5 0.0 0 1 2 3 4 5 6 7 Time (2µs/div) Output Current Magnitude (mA) POWER-ON RESET TO 0V 5V 1V/div AVDD, DVDD, Reset Pin 0V DAC Resets to 000H 0V Time (20µs/div) TYPICAL CHARACTERISTICS: Thermistor Current Source (THERM IOUT, Pin 2) At TA = +25°C, +AVDD, BVDD = +5.0V, VREF = Internal +2.5V, unless otherwise noted. THERM_I_OUTPUT vs TEMPERATURE THERM_I_OUTPUT vs COMPLIANCE VOLTAGE 10 0.2 0 –0.2 –0.4 –0.6 Ext 2.5V Ref Int 2.5V Ref –0.8 –1.0 –25 0 25 50 Temperature (°C) 75 0 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 100µA Nominal –70 –70 –80 –80 1mA Nominal –90 100 10 –10 –90 –100 –50 10 10µA Nominal 0 Delta from 10µA and 100µA (nA) Delta from +25°C (µA) 0.4 –100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Compliance Voltage (V) 4.0 4.5 5.0 AMC7820 www.ti.com SBAS231B Delta from 1mA (µA) 0.6 TYPICAL CHARACTERISTICS: Thermistor Current Source (THERM IOUT, Pin 2) (Cont.) At TA = +25°C, +AVDD, BVDD = +5.0V, VREF = Internal +2.5V, unless otherwise noted. THERM IOUT CURRENT DISTRIBUTION WITH INTERNAL VOLTAGE REFERENCE THERM IOUT CURRENT DISTRIBUTION WITH EXTERNAL VOLTAGE REFERENCE 25 25 RISET = 100kΩ RISET = 100kΩ Percent of Units (%) 20 15 10 15 10 5 0 0 98.0 98.2 98.4 98.6 98.8 99.0 99.2 99.4 99.6 99.8 100.0 100.2 100.4 100.6 100.8 101.0 101.2 101.4 101.6 101.8 102.0 5 98.0 98.2 98.4 98.6 98.8 99.0 99.2 99.4 99.6 99.8 100.0 100.2 100.4 100.6 100.8 101.0 101.2 101.4 101.6 101.8 102.0 Percent of Units (%) 20 Therm IOUT (µA) Therm IOUT (µA) TYPICAL CHARACTERISTICS: Operational Amplifiers At TA = +25°C, +AVDD, BVDD = +5.0V, VREF = Internal +2.5V, unless otherwise noted. OFFSET VOLTAGE DRIFT DISTRIBUTION 18 18 16 Percent of Amplifiers (%) 16 14 12 10 8 6 4 14 12 10 8 6 4 2 2 0 0 –6.0 –5.5 –5.0 –4.5 –4.0 –3.5 –3.0 –2.5 –2.0 –1.5 –1.0 –0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 –2.0 –1.8 –1.6 –1.4 –1.2 –1.0 –0.8 –0.6 –0.4 –0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Percent of Amplifiers (%) OFFSET VOLTAGE DISTRIBUTION 20 Offset Voltage (mV) Offset Voltage Drift (µV/°C) INPUT BIAS CURRENT vs INPUT COMMON-MODE VOLTAGE INPUT BIAS CURRENT vs TEMPERATURE 2.0 100.0 Delta from Mid-Supply (pA) Input Bias Current (pA) 1.5 10.0 1.0 1.0 0.5 0.0 –0.5 –1.0 –1.5 0.1 –50 –25 0 25 50 Temperature (°C) 75 –2.0 –1.0 –0.5 0.0 100 AMC7820 SBAS231B 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Common-Mode Voltage (V) www.ti.com 11 TYPICAL CHARACTERISTICS: Operational Amplifiers (Cont.) At TA = +25°C, +AVDD, BVDD = +5.0V, VREF = Internal +2.5V, unless otherwise noted. INPUT VOLTAGE AND CURRENT NOISE SPECTRAL DENSITY vs FREQUENCY OP AMP OUTPUT VOLTAGE vs INPUT VOLTAGE 1k 1k 5.0 4.5 10 10 1 1 4.0 Output Voltage (V) 100 100 Current Noise (fA√Hz) Output Input 3.5 3.0 2.5 2.0 For 0.01V < VINPUT < 3.8V CMRR > 74dB 1.5 0.01 Current Noise VOUTPUT Clamps at +5mV 0.005 0.1 0.1 1 10 100 1k 10k 100k 0 1M 0 0.005 0.01 1.5 Frequency (Hz) 2 2.5 3 3.5 4 4.5 AOL, CMRR, PSRR vs TEMPERATURE 140 0 160 140 130 130 120 –45 φ –90 80 G –135 40 AOL, CMRR (dB) 100 AOL Phase (°) 120 60 20 120 110 110 100 100 90 PSRR 90 80 CMRR –180 0 80 –20 1 10 100 1k 10k 5 Input Voltage (V) OPEN-LOOP GAIN/PHASE vs FREQUENCY Open-Loop Gain (dB) CommonMode Input Range is Exceeded G= +1 100k 1M –50 10M Frequency (Hz) –25 0 25 50 Temperature (°C) 75 70 100 SMALL-SIGNAL STEP RESPONSE G = 1, CL = 100pF POWER-SUPPLY REJECTION RATIO AND COMMON-MODE REJECTION RATIO vs FREQUENCY 100 90 Op Amp Output (50mV/div) +PSRR PSRR, CMRR (dB) 80 70 60 50 CMRR 40 30 20 10 1 10 100 1k 10k 100k 1M 10M Time (1µs/div) Frequency (Hz) 12 AMC7820 www.ti.com SBAS231B PSRR (dB) Voltage Noise (nV√Hz) Voltage Noise TYPICAL CHARACTERISTICS: Operational Amplifiers (Cont.) At TA = +25°C, +AVDD, BVDD = +5.0V, VREF = Internal +2.5V, unless otherwise noted. Op Amp Output Output Settling Detail 0.1V 2.1V Op Amp Output (500mV/div) Output Settling Detail (0.2%/div) Op Amp Output (500mV/div) 2.1V Output Settling Detail (0.2%/div) LARGE-SIGNAL STEP RESPONSE AND SETTLING TIME CL = 100pF, Gain = +1 LARGE-SIGNAL STEP RESPONSE AND SETTLING TIME CL = 100pF, Gain = +1 Output Settling Detail 0.1V Op Amp Output Time (2µs/div) Time (2µs/div) SETTLING TIME vs CLOSED-LOOP GAIN SMALL-SIGNAL OVERSHOOT vs LOAD CAPACITANCE 100 60 50 Overshoot (%) Settling Time (µs) (G = ±10) 0.01% 10 0.1% 40 30 (G = ±1) 20 10 1 0 1 10 100 1k 10 100 Closed-Loop Gain (V/V) 1k 10k Load Capacitance (pF) OUTPUT VOLTAGE SWING FROM SUPPLY RAILS vs OUTPUT CURRENT 5.0 4.5 Sourcing Current Output Voltage (V) 4.0 3.5 3.0 2.5 2.0 1.5 Sinking Current 1.0 0.5 0 0 1 2 3 4 5 6 7 8 Output Current Magnitude (mA) AMC7820 SBAS231B www.ti.com 13 The AMC7820 is an analog monitoring and control circuit for control of laser diodes and TEC coolers in DWDM applications. A register-based architecture eases integration with DSP-based (or microprocessor-based) systems through a standard SPI bus. All peripheral functions are controlled through the registers and onboard state machines. The AMC7820 consists of the following blocks (refer to the block diagram of Figure 2): • • • • • 8-Channel, 12-Bit ADC Three 12-Bit DACs Nine Operational Amplifiers +2.5V Reference TEC Soft Start Controller Communication to the AMC7820 is via a standard SPI serial interface. This interface requires that SS, the Slave Select signal, be driven LOW to communicate with the AMC7820. The data is then shifted into and out of the AMC7820 under control of the host DSP or microprocessor, which also provides the serial data clock. Control of the AMC7820 and its functions is accomplished by writing to different registers in the AMC7820. A simple command protocol is used to address the 16-bit registers. Registers control the operation of the ADC, DACs, and device configuration. The results of measurements made are placed in the memory map and can be read by the host at any time. All pins have ESD protection circuitry as the first active element on the chip. All input and output pins have protection diodes connected to supply and ground that remain reverse biased under normal operation. If the input voltages exceed the absolute maximum voltage range, it is necessary to add resistance in series with the input to limit the current to 10mA or less. ADC The analog inputs are provided via a multiplexer to the Successive Approximation Register (SAR) ADC. The ADC architecture is based on capacitive redistribution architecture that inherently includes a sample-and-hold function. The multiplexer provides eight analog input channels to the ADC. Channels 0, 1, 6, and 7 are buffered by amplifiers OPA3, OPA4, OPA5, and OPA6, respectively. Channels 2, 3, 4, and 5 connect directly to external pins. The multiplexer connects each analog input to the ADC sequentially. Analog current into the device must charge the internal sampleand-hold capacitor during the sampling period. When the converter is in Hold mode, and the sampling capacitor has been fully charged, the input impedance of the analog input is greater than 1GΩ. The on resistance of each multiplexer switch is typically 150Ω. In order to charge the internal sample-and-hold capacitor completely during the acquisition time, the source impedance of the analog input should be no more than 1kΩ. The ADC runs continuously upon start-up, scanning through each channel. The results of conversions made are stored in the appropriate ADC registers. 14 Since the input range of the ADC is 2 • VREF, codes near FFF will be missing if the output range of the signal source driving an ADC input channel is limited to less than 2 • VREF. This is the case for channels 0, 1, 6, and 7 which are driven from internal op amps which have an output range limit of AVDD. If all codes including FFF are required, the value of the reference voltage must be reduced or the value of AVDD must be increased. Data Format The AMC7820 output data is in Straight Binary format, as shown in Figure 1. This figure shows the ideal output code for the given input voltage and does not include the effects of offset, gain, or noise. FS = Full-Scale Voltage = 2VREF 1LSB = 2VREF/4096 1LSB 11...111 11...110 Output Code OVERVIEW 11...101 00...010 00...001 00...000 FS – 1LSB 0V Input Voltage (V) FIGURE 1. Ideal Input Voltage and Output Codes. DACS The three 12-bit DACs of the AMC7820 use a resistor-string architecture with switchable taps that are buffered by an operational amplifier (see DAC0 in Figure 4). Each op amp buffer can be configured for a gain of +1 or +2, which sets the output range to 0V to +2.5V or 0V to +5.0V, respectively. This architecture is inherently monotonic, a critical requirement for any system requiring “smooth” setpoint control. The op amp buffer has a rail-to-rail output stage that has limitations on sinking or sourcing current when the output voltage is near AGND or AVDD, respectively (see the typical characteristics). For example, if a DAC (Gain = +1) is set to code 010H (+10mV) and is required to sink 1mA of current, the DAC output voltage will be approximately 250mV instead of the desired value of +10mV. This problem is solved by restricting the DAC output voltage to values greater than +250mV or by reducing the required sink current. This restriction does not apply for the case of sourcing current for gain set at +1. When the gain is set at +2, there is a limitation on sourcing current with the output voltage near the positive supply rail. The slope of the DAC output voltage curve for sinking or sourcing current is due to an increase in the inherent closedloop output impedance of the operational amplifier buffer, when operating near a supply rail. Refer to the typical characteristic curves. AMC7820 www.ti.com SBAS231B “1” = Disable SW1_DISABLE 21 R 22 DAC1 (12 Bits) 20 R DAC1_OUT_SET R 17 R EN 28 DIS DAC2_OUT_SET DAC2_OUT SW1_OUT SW1 29 DAC2 (12 Bits) DAC1_OUT OPA1_IN+ OPA1 30 31 10 OPA1_OUT OPA1_IN– OPA2_IN+ OPA2 9 8 MOSI MISO SS RESET 25 37 38 39 40 36 SPI and Registers SCLK 24 23 26 15 0 DVDD DGND BVDD 14 16 19 18 OPA4 1 Reference (2.5V) AGND ADC (12 Bits) MUX 42 2 35 3 34 4 33 5 32 12 43 OPA2_IN– OPA3_IN+ OPA3 27 AVDD OPA2_OUT MUX CTL Clock 11 OPA5 41 6 13 7 DAC0 (12 Bits) 4 3 OPA6 R 5 R 7 6 SW2_DISABLE OPA3_OUT OPA3_IN– EXT_REF_IN REF_OUT_+2.5V OPA4_OUT OPA4_IN– OPA4_IN+ CH2 CH3 CH4 CH5 OPA5_OUT OPA5_IN– OPA5_IN+ OPA6_OUT OPA6_IN– OPA6_IN+ DAC0_OUT_SET DAC0_OUT “1” = SW2 Disable 48 47 OPA7 Current Mirror OPA7_IN+ OPA7_OUT EN 1:4 DIS 1 SW2_OUT SW2 Unipolar_Bipolar_CTR OPA8 2.5V Bip Uni SW3 46 TEC Soft-Start Controller ON OFF SOFT_START_CTR = “1” After Reset OPA7_IN– SW4 SOFT_START_ENABLE NOTE: After power-on or reset, SW1 and SW2 are disabled, SW3 is positioned to Bip, SW4 is on, and the voltage on pin 47 equals 2.5V (VREF) if OPA7 is connected as an integrator. OPA9 2 44 45 T_SENSOR_VOLTAGE THERM_I_OUTPUT ISET_RESISTOR FIGURE 2. AMC7820 Block Diagram. AMC7820 SBAS231B www.ti.com 15 There are three other limitations when operating a DAC output near the supply rails, even if the load current is very small. 1) The output stage of the DAC buffer amplifier clamps at about +5mV above AGND. See the typical characteristics curves in the Operational Amplifier section for an illustration of this behavior. 2) If a DAC buffer amplifier has a negative input offset voltage, the output cannot increase until the input digital code is sufficient to overcome this negative offset. 3) When DAC gain is set at +2, swing near the AV DD (+5.0V) rail will be clamped if the value of VREF is greater than +2.50V and/or if the matching of the output buffer gain setting resistors gives a GAIN that is greater than +2.0. OPERATIONAL AMPLIFIER The AMC7820 has nine operational amplifiers. OPA8 is used to set the current source output. OPA9 buffers the temperature sensor voltage. All others can be configured for signal conditioning or control function. The outputs of OPA3, OPA4, OPA5, and OPA6 connect to the ADC analog input channels 0, 1, 6, and 7, respectively. The output of OPA7 connects to SW2_OUT when SW2 is enabled. Therefore, SW2 enables or disables OPA7 if SW2_OUT is used as the output of OPA7. All amplifiers use a PMOS differential input stage that allows the common-mode input to extend from 200mV below ground up to AVDD – 1.2V while maintaining very good CMRR, low offset voltage, low noise, and good PSRR. High open-loop gain provides excellent signal linearity and low closed-loop output impedance. The rail-to-rail output stage can swing to within a few millivolts of the supply rails provided the sink and source currents are small (see the typical characteristics). Refer to the DAC section for more information regarding swinging close to the supply rails. to the leakage current of ESD diodes which are connected from each op amp input to AGND and AVDD. For each 10°C rise in temperature, the leakage current will double, following classic diode leakage current versus temperature. Input offset current is the difference between the +IN and –IN bias current. In other words, the offset current is a measurement of the matching of the two input bias currents. Refer to the typical characteristics for more detail. REFERENCE The AMC7820 has an internal +2.5V bandgap voltage reference, as shown in Figure 3. Buffered by A1, the reference voltage is available on pin 26. The reference circuit can be overdriven by an external reference on pin 27. This pin also provides a point for filtering the internal reference, if desired a capacitor may be placed from pin 27 to analog ground to decrease reference noise. The time constant of this filter is (10K) • (CFILTER). The internal reference voltage can be adjusted by providing a small current into or out of pin 27. This current can be generated by a large resistor (e.g. 300kΩ) connected from pin 27 to an adjustable voltage source, such as the wiper of a potentiometer or the output of a DAC. THERMISTOR CURRENT SOURCE AND TEMPERATURE SENSOR VOLTAGE The thermistor current source output is set by the resistor connected from the ISET_RESISTOR, pin 45, to ground. The +2.5V reference voltage is forced on pin 45 by the closedloop action of OPA8. The actual thermistor current is provided by a 1:4 current mirror that provides a current drive of 4 times the current flowing through the RISET resistor (see Figure 7). Thus, the thermistor current from pin THERM_I_OUTPUT (pin 44), ITHERM, is given by: The input bias currents are very low, typically ranging from less than 1pA to a few pA. This current is almost entirely due CFILTER 2.5V REFOUT 26 27 2.5V Bandgap Reference ITHERM = 2.5V •4 RISET The thermistor is driven by the current coming out of THERM_I_OUTPUT. The voltage developed across the thermistor is then buffered by the unity-gain buffer amplifier (OPA9). The voltage on pin T_SENSOR_VOLTAGE represents the actual TEC temperature. For best performance, RISET should have a TCR of 10ppm/°C or less, and a tolerance of 0.1%. Using a current source preserves the full sensitivity of the thermistor (typically 50mV/°C). If a resistor were used to power the thermistor, the sensitivity would be reduced to approximately 25mV/°C, due to the voltage divider created by such an arrangement. 10kΩ A1 To DACs A2 Because the thermistor current source has high output impedance and wide voltage compliance, it is possible for two separate laser modules to be controlled by connecting their thermistors in series with the output of this current source. To ADC FIGURE 3. Reference Circuitry. 16 AMC7820 www.ti.com SBAS231B Since the THERM_I_OUTPUT and DAC0 reference are derived from the same reference, they track independently of any reference voltage drift, as shown in Figure 4. This can be viewed as a bridge arrangement common in instrumentation. When the temperature measured by the thermistor is equal to the temperature represented by the DAC’s output voltage, the voltages at pin 2 and pin 6 are equal regardless of the reference drift caused by the change of the ambient temperature or other conditions. Figure 5 shows the typical performance of pin 2 minus pin 6 voltage tracking over –40°C to +85°C. The error is +0.75mV at –40°C and –0.4mV at +85°C, which, out of a 50mV/°C sensitivity for the thermistor, is equivalent to 0.015°C and 0.008°C, respectively. R DAC0 7 R 1.0V 1.0V 2 6 SW1 and SW2 are controlled by the internal signals SW1_DISABLE and SW2_DISABLE, respectively. The status of these signals is determined by the four LSBs of the SHUTDOWN register (bits 0 through 3) designated SW1-1/SW1-0 and SW2-1/SW2-0. After power-on or reset, SW1 connects to ground, and SW2 connects to SW3. SW3 is controlled by bits 2 and 3 (POL1/POL0) of the CONFIGURATION/STATUS register. After power-on or reset, SW3 connects to 2.5V (the internal reference voltage on pin 26). The host can change the status of any switch by writing a proper pattern into the appropriate registers (refer to the AMC7820 Registers section). 44 DAC Set to 1.0V Thermistor 10kΩ at 25°C The AMC7820 has four internal switches (SW1, SW2, SW3, and SW4) to shut down the TEC and laser diode (see the application in Figure 7 for more detail). Closing switch SW4 activates the TEC soft-start function implemented by the TEC SOFT_START CONTROLLER. SW4 is controlled by the internal signals SW2_DISABLE and SOFT_START_CTR. The LSBs (TS1/TS0) of the CONFIGURATION/STATUS register determines the status of SOFT_START_CTR. After power-on or reset, SW4 is closed and soft-start is activated. The host can write “00” to TS1/TS0 to turn off SW4. 26 THERM_I_OUTPUT 100µA SWITCHES TEC SOFT_START_CONTROLLER FIGURE 4. The Thermistor Feedback and Setpoint Viewed as a Bridge. CHANGE IN (Vpin2 – Vpin6) vs TEMPERATURE (For Internal or External Reference) 2.0 Delta from +25°C (mV) 1.5 1.0 0.5 0.0 –0.5 –1.0 –1.5 –2.0 –50 –25 0 25 50 75 100 This controller provides a soft start for a bidirectional TEC Driver when OPA7 is configured as an integrator (see Figure 6) and the TEC driver is referenced to 2.5V (see the Application section). Pin 1 (SW2_OUT) drives the external TEC driver. A value of 2.5V from this pin sets the TEC driver output current to zero, implementing a safe (zero current) starting condition. After power-on or reset, switch SW2 is disabled interrupting control of the external TEC driver by the integrator OPA7. The actions of switches SW2 and SW3 apply 2.5V to pin 1, setting the external TEC driver output current to zero. Switch SW4 is also closed and the TEC SOFT_START_CONTROLLER is enabled. This controller drives the output of OPA7 to 2.5V which corresponds to zero TEC current. When the loop control of the external TEC driver is resumed, the TEC current is safely ramped up from zero. If the soft start controller is disabled and the control loop is also diabled with SW2, OPA7 will continue to integrate until its output reaches a supply rail. This will result in max current drive to the TEC, when the loop is enabled (a hard start). Temperature (°C) FIGURE 5. Change in (Vpin2 – Vpin6) vs Temperature. AMC7820 SBAS231B www.ti.com 17 DAC0 (12 Bits) DAC0_OUT 6 DAC0_OUT_SET 7 R R SW2_DISABLE OPA7 OPA7_IN+ 48 OPA7_OUT 47 SW2_OUT 1 Unipolar_Bipolar_CTR EN 2.5V Bip Uni SW2 SW3 C OPA7_IN– ON 46 R TEC Soft-Start Controller SW4 OFF SOFT_START_CTR To TEC DRIVER SOFT_START_ENABLE OPA9 2 T_SENSE_Voltage FIGURE 6. Soft Start Function. APPLICATION TEC CONTROL The AMC7820 can be used to control one CW type laser diode (or pump laser diode) current and one TEC cooler, two TEC coolers, or two laser diodes. See Figure 7 for a typical application to control one pump laser diode and one TEC. A similar approach can be used to control other CW type laser diodes. 18 The TEC control loop is made up of the thermistor current source, a unity-gain buffer, a thermostat DAC (DAC0), the TEC integrator (OPA7), the internal TEC SOFT_START_ CONTROLLER, an external thermistor, and an external TEC Power Current Driver. The external thermistor is driven by the current from the thermistor current source. The voltage across the thermistor represents the actual TEC temperature, and is fed into the AMC7820 www.ti.com SBAS231B FIGURE 7. Typical AMC7820 Application: TEC and Laser Diode Current Control. AMC7820 www.ti.com + + + 10µF 10µF 10µF Host Processor (DSP TI C54xx/C62xx or Microcontroller) 40 36 SS RESET BVDD DGND DVDD AGND 41 43 42 18 19 39 MISO AVDD 38 MOSI 10µF and 0.1µF can be replaced with 1µF ceramic cap. 0.1µF BVDD 0.1µF DVDD (+5V) 0.1µF AVDD (+5V) 37 SCLK SPI and Registers SOFT_START_CTR OPA8 Mux CTL 1:4 R R Current Mirror SW2_DISABLE DAC0 (12 Bits) Clock ADC (12 Bits) Reference (2.5V) DAC2 (12 Bits) DAC1 (12 Bits) R R R R 2.5V OFF ON MUX OPA4_OUT 15 OPA7 Uni Bip EN SW2 OPA9 TEC Soft-Start Controller SW3 DIS Unipolar_Bipolar_CTR OPA6 SOFT_START_ENABLE SW4 7 6 5 4 1µF THERM_I_OUTPUT ISET_RESISTOR 45 T_SENSOR_VOLTAGE OPA7_IN– SW2_OUT 44 2 46 1 OPA7_IN+ OPA7_OUT 48 DAC0_OUT DAC0_OUT_SET OPA6_IN+ OPA6_IN– OPA6_OUT OPA5_IN+ 47 6 7 5 3 4 13 OPA5_IN– OPA5_OUT 12 11 CH5 CH4 CH3 CH2 OPA4_IN+ 32 33 34 16 3 SW2_ENABLE REF_OUT_+2.5V 26 OPA4_IN– EXT_REF_IN 27 14 OPA3_IN– 23 OPA3_OUT OPA3_IN+ 24 OPA2_IN– 8 25 OPA2_OUT OPA2_IN+ 10 9 OPA1_IN– 31 35 OPA5 OPA4 OPA3 OPA2 OPA1_OUT OPA1_IN+ SW1_OUT DAC2_OUT DAC2_OUT_SET DAC1_OUT DAC1_OUT_SET 30 29 28 17 20 22 21 2 1 0 SW1 OPA1 DIS EN SW1_DISABLE RISET TEC Control C2 R1 C1 INA143 Gain = 10 Laser Diode Current Monitoring TEC Integrator TEC Temperature Initial Setting Laser Diode Control Laser Diode Integrator –V +V Offset –V +V Laser Diode Power Current Driver (OPA5xx) OUT+ OUT– TEC T Thermistor or RTD TEC Temperature Sensor –V TEC PWM Power Current Driver (can be replaced with Linear Driver, OPA5xx) DRV591 (refer to DRV591 Data Sheet for detail) IN+ IN– 0.1Ω Sense Resistor PIN Diode Optical Power Monitoring Pump Laser Diode Sense Resistor Typ. 0.1Ω Cooling AMC7820 Heating SBAS231B 19 Usually, the component values of the control loop are selected based upon the characteristics of the TEC (thermal gain and time constant), the gain of the TEC power driver, and the desired loop response. Frequently, the characteristics of the TEC are not known, which can lead to difficulty in designing the compensator analytically. An empirical design procedure using the actual loop components (TEC, power driver, and AMC7820) can be used to determine the compensator component values. inverting input of TEC integrator, OPA7. The noninverting input of OPA7 connects to the thermostat DAC(DAC0), which sets the desired temperature of the pump laser diode module. The temperature that a certain voltage represents depends upon the value of the thermistor used and the drive current provided to that thermistor. Pin 1 (SW2_OUT) controls the external TEC Power Current Driver (DRV591, a PWM power driver) which can be replaced with a linear driver (OPA5xx) if configured properly. In the application of Figure 7, 2.5V on pin 1 sets the TEC current to zero. With this method, the loop response is monitored while making step changes to the control loop. A step change can be provided by writing data values to DAC0. An oscilloscope is used to monitor the temperature of the thermistor at the T_Sensor _Voltage pin. In normal operation, SW2 is enabled and OPA7 connects to the DRV591. The voltage across the thermistor controls the TEC current. When SW2 is disabled, the DRV591 is connected to SW3, which connects to 2.5V in the bipolar mode (which is the default mode). This results in zero TEC current, and shuts down the TEC. Meanwhile, TEC SOFT_START CONTROLLER drives the output of OPA7 to become equal to the reference voltage of 2.5V. This action provides a soft start when SW2 is enabled. The suggested manual tuning procedure is based upon the components shown in Figure 8. 1) Establish the setpoint of the control loop at the lowest anticipated temperature setting of the laser module. At this operating point, the gain of the temperature control loop is at it’s highest. The loop is best compensated at this point. The TEC current is sensed across an external sense resistor (0.1Ω) by the amplifier OPA6, and is fed to analog channel 7 of the ADC. OPA6 is connected as a difference amplifier and is offset (by 2.5V) to provide the measurement of the bidirectional TEC current. The host processor monitors the current and takes proper action when necessary. 2) Initially select R1 = 2M, C1 = 1uF, C2 = 2uF. To improve the response, decrease the value of C2. This increases the gain of the compensator near the dominant pole frequency of the TEC, resulting in faster settling times of the loop. However, at some value of C2 the loop will start to oscillate. At this point, fix C2 at 3x to 4x this value. 3) Verify the settling behavior of the control loop at the highest anticipated laser module setpoint temperature. The loop response may be somewhat different at this operating point. A compromise value of C2 may be needed to balance the loop response at these operating point extremes. TEC CONTROL LOOP COMPENSATION The AMC7820 has a dedicated amplifier (OPA7) to control the temperature of a Laser Diode Module. The amplifier can be configured in several ways to implement the control loop function, but it is commonly configured as a PID (Proportional-Integral-Derivative) controller. In this mode, the control loop consists of a low-frequency pole, a zero that cancels this pole below the dominant pole frequency of the TEC and, at higher frequencies, linear gain that promotes fast settling of the TEC. Typical values of the loop compensation components are: R1 = 2M, C1 = 1uF, C2 = 0.1uF. See Figures 9 through 12 for typical loop responses. Ref Out +2.5V 2.5V Ref 100µA 61.9kΩ Monitor Pin 2 C1 143.3kΩ C2 R1 61.9kΩ OPA548 TEC+ RT 10kΩ OPA9 OPA7 143.3kΩ DAC0 TEC– FIGURE 8. Compensation Loop. 20 AMC7820 www.ti.com SBAS231B TEC LOOP RESPONSE FOR A –4°C CHANGE vs TIME (C1 = 1.0µF) TEC LOOP RESPONSE FOR A +4°C CHANGE vs TIME (C1 = 0.47µF) C2 = 0.1µF R1 = 2M DAC Step 2°C/div C2 = 0.1µF R1 = 2M DAC Step 2°C/div Pin 2 0.1°C/div Pin 2 0.1°C/div Time (2s/div) Time (2s/div) FIGURE 9. TEC Loop Response for a –4°C Change vs Time (C1 = 1.0µF). FIGURE 12. TEC Loop Response for a +4°C Change vs Time (C1 = 0.47µF). LASER DIODE CONTROL TEC LOOP RESPONSE FOR A –4°C CHANGE vs TIME (C1 = 0.47µF) The laser diode control loop, see Figure 7, maintains a constant diode current. The loop consists of an integrator (OPA1), a DAC (DAC2) to set the desired laser diode current, a transimpedance amplifier (OPA4) to monitor the optical power, an external current sense resistor, an external instrumentation amplifier (or difference amplifier) to sense the laser diode current, and an external laser diode current driver. C2 = 0.1µF R1 = 2M DAC Step 2°C/div Pin 2 0.1°C/div Time (2s/div) FIGURE 10. TEC Loop Response for a –4°C Change vs Time (C1 = 0.47µF). TEC LOOP RESPONSE FOR A +4°C CHANGE vs TIME (C1 = 1.0µF) DAC Step 2°C/div The current through the laser diode is sensed by the external sense resistor. The voltage across this resistor is fed to the instrumentation amplifier (gain of 10) which can have its inputs driven below ground. The output from this amplifier represents the laser diode current, and is fed back into the inverting input of the integrator (OPA1), closing the loop. The output of OPA1 drives the external power current driver. In normal operation, SW1 is enabled connecting the output of DAC2 (which represents the set point of the desired laser diode current) to the noninverting input of OPA1. After power-on or reset, SW1 is disabled and the noninverting input of OPA1 connects to ground. This forces laser current to zero, thereby shutting it down. For applications where the laser diode cathode is grounded, all biasing voltages will be positive relative to ground. In this case, the external INA143 instrumentation amplifier can be eliminated, and an internal op amp can be substituted and configured as a 4-resistor difference amplifier. C2 = 0.1µF R1 = 2M Pin 2 0.1°C/div Time (2s/div) FIGURE 11. TEC Loop Response for a +4°C Change vs Time (C1 = 1.0µF). The output optical power of the laser diode is monitored by the ADC (analog channel 1) through the back facet PIN diode and the transimpedance amplifier OPA4. The host processor monitors this power and takes proper action when necessary. Pin 15 is the output of OPA4 and represents the output optical power of the laser diode. The AMC7820 can put the laser diode in “constant power mode” as well. When the inverting input of the integrator OPA1 is connected to pin 15, instead of the output of INA143 that was shown in Figure 7, the laser control loop forces the output optical power of the laser diode to a constant level determined by the output of DAC2. AMC7820 SBAS231B www.ti.com 21 DIGITAL INTERFACE AMC7820 COMMUNICATION PROTOCOL The AMC7820 communicates through a standard SPI bus, which consists of four wires: SCLK (the serial clock pin), MISO (Master-Out Slave-In data pin), MOSI (Master-In SlaveOut data pin), and SS (Slave Select pin). The SPI master device activates the slave select signal (SS = LOW) to access the selected SPI slave device and generates SCLK to synchronize the movement of the data both in and out of the slave devices through the MOSI and MISO pins. The SPI slave devices depend on a master to start and synchronize transmissions. The AMC7820 is entirely controlled by registers. Reading and writing these registers is accomplished by a 16-bit command that is sent prior to the data for that register. The command is constructed, as shown in Table I. The command word begins with a R/W bit that specifies the direction of data flow. The following 4 bits specify the page of memory this command is directed to, as shown in Table II. The next five bits specify the register address on that page of memory to which the data is directed. The last six bits are reserved for future use. A transmission begins when initiated by an SPI master. The word from the master is shifted into the AMC7820 through the MOSI pin under the control of the master serial clock, SCLK. The word from the AMC7820 registers (the slave) is shifted out from the MISO pin under control of SCLK as well. PG3 PG2 PG1 PG0 PAGE ADDRESSED 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved The idle state of the serial clock for the AMC7820 is LOW, which corresponds to a clock polarity setting of 0 (typical microprocessor SPI control bit CPOL = 0). The AMC7820 interface is designed with a clock phase setting of 1 (typical microprocessor SPI control bit CPHA = 1). In both the master and slave, the data is shifted out on the rising edge of SCLK and sampled on the falling edge of SCLK, where the data is stable. The master begins driving its MOSI pin on the first rising edge of SCLK after SS is activated (SS = LOW). To write data into the AMC7820, the host activates the slave select signal (SS = LOW) and issues a WRITE command to start the data transmission. The AMC7820 always interprets the first word (from the host) immediately following the falling edge of the SS signal as a command. The data to be written into the AMC7820 follows the command. SS must remain LOW until all data is transmitted (see Figure 13), otherwise the WRITE operation is terminated. Likewise, to read the data from the AMC7820, the host activates the slave select signal and sends a READ command. Then the AMC7820 sends data out through the MISO pin under control of SCLK. SS must remain LOW until all data is shifted out (see Figure 13), otherwise the transmission is terminated. When the operation is terminated, the master must issue a new command to start a new operation. In the AMC7820, all data is 16-bit. It takes 16 clock cycles of SCLK to transfer one word of data. TABLE II. Page Addressing. To read all the first page of memory, for example, the host processor must send the command 0x8000—this specifies a read operation beginning at Page 0, Address 0. The processor can then start clocking data out of the AMC7820. The AMC7820 will automatically increment its address pointer to the end of the page; if the host processor continues clocking data out past the end of a page, the address will wrap around to the beginning of the page. This is true of either reading or writing, so it is important that the host makes sure of the address to which it is writing. Likewise, writing to Page 1 of memory would consist of the processor writing the command 0x0800 (which would specify a write operation) with PG0 set to 1, and all the ADDR bits set to 0. This would result in the address pointer pointing at the first location in memory on Page 1 of memory. See the AMC7820 Memory Map section for details of register locations. To make correct R/W operations, the host must issue SS and SCLK properly. Bit 15 MSB Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LSB R/W PG3 PG2 PG1 PG0 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 X X X X X X NOTE: R/W = 1 when reading; 0 when writing. X = Don’t care. TABLE I. AMC7820 Command Word. 22 AMC7820 www.ti.com SBAS231B Figure 13 shows an example of a complete data transaction between the host processor and the AMC7820. AMC7820 MEMORY MAP cessor. These registers are separated into two pages of memory in the AMC7820: a Data page (Page 0) and a Control page (Page 1). The memory map is shown in Tables III and IV. Locations that are marked reserved will read back 0x0000 if they are read by the host. The AMC7820 has several 16-bit registers that allow control of the device as well as providing a location for results from the AMC7820 to be stored until read by the host micropro- Read Operation Write Operation SS SCLK MOSI Command Word Data Command Word MISO Data Data FIGURE 13. Write and Read Operation of the AMC7820 Interface. PAGE 0: DATA REGISTERS PAGE 1: CONTROL REGISTERS ADDRESS REGISTER ADDRESS REGISTER 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 Reserved DAC0 DAC1 DAC2 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Shut Down Reset Configuration/Status Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved TABLE III. AMC7820 Memory Map: Page 0. TABLE IV. AMC7820 Memory Map: Page 1. AMC7820 SBAS231B www.ti.com 23 AMC7820 REGISTERS This section will describe each of the registers that were shown in the memory map of Tables III and IV. The registers are grouped according to the function they control. AMC7820 ADC REGISTERS The results of all ADC conversions are placed in the appropriate data register, as described in Table III. The data format of these read-only registers is as follows: Bit 15 MSB Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LSB A2 A1 A0 DV D11 MSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB where, A2 - A0—Channel Address Bits. These three bits will correspond to the address of the channel whose result is in the lower 12 bits. DV—Data Valid. This bit is set (“1”) when a new conversion result is placed in the register. The DV bit is cleared (“0”) after the register is read. This allows software to determine if the result it has read from the register is the result of a new conversion or a previously read result. This bit is also cleared upon power-up or reset of the AMC7820. D11 - D0—Data bits from the ADC conversion. Upon power-up, the data registers are cleared to all zeros. This also occurs with a hardware or software RESET. Since the ADC operates at 100K samples/second (10µs per conversion), the host should allow at least 80µs before reading any ADC channels to allow the multiplexer time to scan through all eight channels and write valid data to the data registers. AMC7820 DAC REGISTERS The data to be written to the DAC is written into one of the three DAC data registers that are formatted as follows: Bit 15 MSB Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LSB X X X X DB11 MSB DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 LSB where, DB11 - DB0—Data bits to be written to the DAC. The analog output of the DAC is updated when the value is written into the register. x = Don’t Care. The DAC registers are cleared to all zeros (0x0000) upon power-up or reset. The DAC registers are read and write-enabled, so that the registers can be read back to confirm the data. AMC7820 SHUTDOWN REGISTER The enable and disable functions of SW1 and SW2 are accomplished by writing a proper word into the SHUTDOWN register. When enabled, SW1 connects to the output of DAC2, and SW2 connects to the output of OPA7. When disabled, SW1 connects to analog ground, and SW2 connects to the output of SW3. The format of the SHUTDOWN register is as follows: Bit 15 MSB Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LSB X X X X X X X X X X X X SW1-1 SW1-0 SW2-1 SW2-0 where, SW1-0 - SW1-1—SW1 Disable Control Bits. For the operation of these two bits, see Table V. SW2-0 - SW2-1—SW2 Disable Control Bits. For the operation of these two bits, see Table V. x = Don’t Care. 24 AMC7820 www.ti.com SBAS231B SW1/SW2 1 SW1/SW2 0 0 0 1 1 0 1 0 1 OPERATION Invalid—a write of this value will not result in any change to the bit values stored in the register. Enable (the normal operating mode). SW1 connects to DAC2, and SW2 connects to the output of OPA7. Disable (condition after power-up or reset). SW1 connects to ground, and SW2 connects to SW3. Invalid—a write of this value will not result in any change to the bit values stored in the register. TABLE V. Shutdown Bit Patterns. The default state of this register upon power-up or reset is such that both SW1 and SW2 are disabled (0x000A). The logic level of signal SW1_DISABLE is HIGH when switch SW1 is disabled, and LOW when SW1 is enabled. The logic level of signal SW2_DISABLE is HIGH when switch SW2 is disabled, and LOW when SW2 is enabled. AMC7820 RESET REGISTER The AMC7820 has a special register, the RESET register, which acts like the RESET pin of the device. Writing the code 0xXBB3, as shown below, to this register will cause the AMC7820 to perform a software reset. Note that only the lower 12 bits have significance for this reset function. Bit 15 MSB Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LSB X X X X 1 0 1 1 1 0 1 1 0 0 1 1 where, x = Don’t Care. Writing any other values to this register will do nothing. Upon reset, this register is set to all zeros. Therefore, reading this register should always result in reading back 0x0000. AMC7820 CONFIGURATION/STATUS REGISTER AMC7820 can be configured to control bidirectional TEC and single direction TEC by properly setting SW3 and TEC_SOFT_START_CONTROLLER. This is accomplished by writing a proper word into this register. A reset status bit indicates if a reset has occurred. The register is formatted as follows: Bit 15 MSB Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LSB X X X X X X X X X X X RSTC POL1 POL0 TS1 TS0 where, RSTC—Reset Complete. This bit is set to “1” on power-up or reset. This bit can be cleared by writing a “0” to this location, but it cannot be set to “1” by the host, only a reset being performed will set it to 1. This allows the host to determine if the part has been configured after power-up, and if a reset has occurred to the AMC7820 without the host’s knowledge. POL0 – POL1—Polarity bits that control SW3. The operation is shown in Table VI. After power-up or reset, these bits are set to bipolar mode, and SW3 is positioned to 2.5V. TS1 – TS0—TEC Soft Start Enable Bits, which determine the status of the signal SOFT_START_CTR. The operation is shown in Table VII. After power-up or reset, TS1 = “0”, TS0 = “1”, SOFT_START_CTR = HIGH (“1”). POL1 POL0 0 0 1 1 0 1 0 1 OPERATION Invalid—a write of this value will not result in any change to the bit values stored in the register. Bipolar Mode. SW3 is positioned to 2.5V. (Condition after power-up or reset.) Unipolar Mode. SW3 is positioned to AGND. Invalid—a write of this value will not result in any change to the bit values stored in the register. TABLE VI. Polarity Bit Operation. TS1 TS0 0 0 0 1 1 1 0 1 OPERATION SOFT_START_CTR is LOW (“0”). TEC SOFT_START_CONTROLLER is disabled regardless of the status of SW2. SOFT_START_CTR is HIGH (“1”). TEC SOFT_START_CONTROLLER is enabled if SW2 is disabled (SW2_DISABLE = HIGH (“1”)) (Condition after power-up or reset.) SOFT_START_CTR is LOW (“0”). TEC SOFT_START_CONTROLLER is disabled regardless of the status of SW2. Invalid—a write of this value will not result in any change to the status of SOFT_START_CTR. TABLE VII. TEC Soft Start Enable Bit Operation. AMC7820 SBAS231B www.ti.com 25 LAYOUT For optimum performance, care should be taken with the physical layout of the AMC7820 circuitry. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections, and digital inputs that occur just prior to latching the output of the analog comparator of the ADC. Therefore, during any single conversion for an ‘n-bit’ SAR converter, there are n ‘windows’ in which large external transient voltages can easily affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic, and high-power devices. The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. With this in mind, power to the AMC7820 should be clean and well bypassed. A 0.1µF ceramic bypass capacitor should be placed as close to the device as possible. A 1µF to 10µF capacitor may also be needed if the impedance of the connection between AVDD and the power supply is high. 26 It is recommended to install a reference bypass capacitor (1µF) between the EXT_REF_IN pin and analog ground when internal reference is used. If an external reference voltage originates from an op amp, make sure that it can drive any bypass capacitor that is used without oscillation. The AMC7820 architecture offers no inherent rejection of noise or voltage variation coming from an external reference input. Any noise and ripple from the reference will appear directly in the analog and digital results. The AGND and DGND pins should be connected to a clean ground point. In many cases, this will be the “analog” ground. Avoid connections that are too near the grounding point of a microcontroller or digital signal processor. If needed, run a ground trace directly from the converter to the power-supply entry or battery-connection point. The ideal layout will include an analog ground plane dedicated to the AMC7820 and associated external analog circuitry. AMC7820 www.ti.com SBAS231B PACKAGE DRAWING MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0°– 7° 1,05 0,95 Seating Plane 1,20 MAX 0,75 0,45 0,08 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 AMC7820 SBAS231B www.ti.com 27 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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