TECEV103 Analog Technologies, Inc. TEC CONTROLLER EVALUATION KIT TECEV103 (updated 06/17/04) Our TEC controller modules can be evaluated conveniently by using this evaluation kit TECEV103 which comes with an evaluation board, TECEVB103 and a TEC controller module of TEC-A1 (there is no internal compensation network inside). The main purpose of using the evaluation board is to tune the compensation network on the board for matching the characteristics of users’ thermal load. The objectives of the tuning are to minimize the response time of the thermal control loop and the dynamic temperature tracking errors, while keeping the control loop stable. 1. Connection To power supply 5V Imax = 2A To A/D, D/A, and/or microprocessor For For multimeter oscilloscope probing probing To TEC To Thermistor TECN TECN +5V GND TEC+ Rth TEC- TECP GND LEDC TECP LEDA TEC Controller RTH Temp. good Vlim On Off LED S3 Power On Off TMPS TMPS CMPIN Ri CMPO Rp TMPO Cd TMPO Ci Rd CIRP CDRD VDR VDR 3V CLHT Cd TMPGD RTH 4.7uF 3.3uF 2.2uF 1.5uF 0 S1 Ci 330nF 470nF 680nF 820nF 1uF 820nF 680nF 470nF 1uF 0 S2 82nF 100nF 150nF 220nF TMPGD 330nF SDNG SDNG Wi Wd Wp W1 W2 W3 2M 500K 2M 5K 5K 20K GND GND Figure 1 TEC Controller Evaluation Board TECEV103 550 E. Weddell Dr., #4, Sunnyvale, CA 94089 U. S. A. Tel.: (408) 747-9760, Fax: (408) 747-9770. www.analogtechnologies.com Copyright 1999 – 2004, Analog Technologies, Inc. All Rights Reserved. Updated: 8/25/04 1 TECEV103 Analog Technologies, Inc. Figure 2 TECEV103 Photo positions (down side). Check the evaluation board Figure 1 shows the layout of the evaluation board and Figure connections, making sure that they are all correctly 2 shows its photo. connected. Turn on the Power side switch and see how the Controller works. These are the procedures for the adjustment. 1. Set up basic connections. Connect a 5V DC power supply and the TEC terminals in the right polarity as indicated onto the board. Connect the thermistor terminals to the board, there is no polarity requirement. Turn the two switches, for Vlim and Power, to the off 2. Tune the compensation network. The purpose for this step is to match the controller compensation network with the thermal load characteristics thus that the response time and temperature tracking error are minimized. Adjust the potentiometer W1 to change 550 E. Weddell Dr., #4, Sunnyvale, CA 94089 U. S. A. Tel.: (408) 747-9760, Fax: (408) 747-9770. www.analogtechnologies.com Copyright 1999 – 2004, Analog Technologies, Inc. All Rights Reserved. Updated: 8/25/04 2 TECEV103 Analog Technologies, Inc. the set-point temperature TMPS just a small amount, simulating a step function. At the same time, connect an oscilloscope at the VDR test pin (on the right side of the evaluation board), set it to a scrolling mode (0.2 Second/Division or slower) and monitor the waveform of VDR as TMPS is fed by a step function signal. The circuit in the compensation network is shown in Figure 3 below. Rd − VDR + TMPS Figure 3 Compensation network The transfer function of the compensation network, defined as H(ω)=VDR(ω)/TMPO(ω), is shown in figure 4. H(ω ) Gd 0.71Gd 1.41Gp Gp ω1 ω2 ω3 ω4 ω Figure 4 Transfer Function of the Compensation Network In principle, these are the impacts of the components to the tuning results: a. b. c. Cd*Ri determines the corner frequency, ω2=1/(Cd*Ri), where the differential component starts picking up (see Figure 4), as the frequency goes up. e. Cd*Rd determines the corner frequency, ω3=1/(Cd*Rd), where the differential component starts getting flat. It determines the cut-off frequency above which the TEC controller will give extra weight or gain in response. f. Cf*Rp determines the corner frequency, ω4=1/(Cf*Rp), where the differential component starts rolling down. Since this frequency is way higher than being needed for controlling the TEC, ω4 does not need to be tuned. The capacitor is built into the TEC controller module, not the evaluation board. Ci Ri TMPO d. Rp Cf Cd frequency goes down. It determines the cut-off frequency below which the TEC controller will start having a large open loop gain. The higher the open loop gain, the smaller the tracking error will be. Rp/Ri determines the gain for the proportional component of the feedback signal which is from the thermistor, Gp = Rp/Ri, in the control loop, the higher the gain, the smaller the short term error in the target temperature (which is of the cold side of the TEC) compared with the set-point temperature, but the higher the tendency of the loop’s instability. Rp/Rd determines the gain for the differential component, Gd = Rp/(Rd//Ri) ≈ Rp/Rd, where symbol “//” stands for two resistors in parallel, since Ri >> Rd, Rd//Ri = Rd. The higher the gain, the shorter the rise time of the response, the more the overshoot and/or the undershoot will be. Ci*Rp determines the corner frequency, ω1= 1/(Ci*Rp), where the integral component starts picking up, as the To start the tuning, turn off the differential circuit by setting Cd Open. Turn W1 quickly by a small angle, back and forth, approximately 5 seconds per change. Set Ci to 1uF, set Ri to 1M, and increase the ratio of Rp/Ri as much as possible, provided the loop is stable, i.e. there are no oscillations seen in VDR. Then, minimize Ci as much as possible, provided the loop is stable. The next step is to minimize Rd and maximize Cd while maintaining about 10% overshoot found in VDR. Optimum result can be obtained after diligent and patient tuning. The tuning is fun and important. When the TEC controller is used for driving a TEC to stabilize the temperature of a diode laser, there is no need to turn on the laser diode while tuning the TEC controller. To simulate the active thermal load given by the laser diode, setting the set-point temperature lower than the room temperature is enough. For a typical laser head used in EDFA’s or laser transmitters (found in DWDM applications, for instance), Ri = 1MΩ, Rp = 1MΩ, Ci = 680nF, Cd = 1.5µF, and Rd = 250kΩ. These values may vary, depending on the characteristics of a particular thermal load. To be conservative in stability, use larger Ci and larger Ri; To have quicker response, use smaller Rd and larger Cd. The closer to the TEC the thermistor is mounted, the easier to have the loop stabilized, the shorter the rise time and the settling time of the response will be. 3. After tuning, the values of the capacitors for Cd and Ci can be read off the capacitor selection switches. The values of the resistors, Ri, Rd and Rp, can be measured by an Ohm-meter by connecting to the resistor pins. As seen in the photo of Figure 2, Ri can be read off between TMPO and CMPIN test points; Rd can be read off 550 E. Weddell Dr., #4, Sunnyvale, CA 94089 U. S. A. Tel.: (408) 747-9760, Fax: (408) 747-9770. www.analogtechnologies.com Copyright 1999 – 2004, Analog Technologies, Inc. All Rights Reserved. Updated: 8/25/04 3 TECEV103 Analog Technologies, Inc. between CMPIN and CDRD test points; Rp can be read off between CMPIN and CIRP test points. 4. After the compensation network is tuned properly, we can now adjust set-point temperature to see if the TEC controller can drive the target temperature to a certain range and with high stability. Turn the temperature setpoint TMPS potentiometer W1 while monitoring its output voltage at TMPS test point (4th row on either left or right side of the board), watch the LED: when it turns to green, the target temperature is locked to the set-point temperature within 0.1°C or less. The relationship between the set-point voltage vs. the set-point temperature is given in the datasheet. After seeing the LED lock into the set-point temperature, VDR should be a constant voltage as shown in the oscilloscope and the voltage between TMPS and TMPO should be very small, less than 10mV. When a standard TEC controller is used, the 10mV represent a 0.07° temperature error. f. To control the TEC voltage directly by using a DAC, connect VDR to the output of the DAC and use this formula: TEC voltage = 2.5V – VDR (V). g. To shut down the TEC controller by using a microprocessor, turn off the Power switch, connect SDN test point (2nd row from the bottom side, on both left and right columes.) to one of its digital outputs. When pulling low, the TEC controller is shut off. When pulling high SDN, the TEC controller is turned on. h. The evaluation schematic is given in Figure 5. Using the TEC controller for more applications not described here, and/or having any questions, please free to contact us. 5. Set output voltage limit. 6. To know more parameters of the TEC controller. a. To know the actual target temperature, use a voltage meter to measure the voltage between the TMPO and the GND pins, the reading result is: target temperature = 15°C + (TMPO voltage (V))*6.67°C for approximation (see the curve in the TEC controller data sheet). b. To know how hard the TEC is working, measure the voltage VDR by a voltage meter or an ADC, TEC voltage = 2.5V – VDR. When the TEC voltage (from the calculation) is positive, it is in cooling mode; when the TEC voltage is negative, it is in heating mode. Cool/Heat Balance CLHT can be adjusted by W2. TEC maximum voltage can be reduced by reducing W3, make sure Vlim switch is now turned to the on position. c. To try other values of capacitors not provided by the evaluation board for the capacitors in the compensation network, turn the capacitor switches you want to try to the top point, the “0” position, connect the component to the corresponding soldering pads as marked on the evaluation board. d. To shut down the TEC controller, turn the Power switch to the “Off” position, see Figure 2. e. To control the set-point temperature directly by using a DAC, set the set-point temperature POT W1 to the middle point (25°C), on which the TMPS is about 1.5V, the half value of the reference voltage, connect TMPS test point to the output of the DAC and use this formula for approximation when the input voltage is between 0V and 3V: set-point temperature (°C) = 15°C + (TMPO voltage (V))*6.67°C. The maximum voltage allowed is Vps (power supply). See the curve in the TEC controller data sheet. 550 E. Weddell Dr., #4, Sunnyvale, CA 94089 U. S. A. Tel.: (408) 747-9760, Fax: (408) 747-9770. www.analogtechnologies.com Copyright 1999 – 2004, Analog Technologies, Inc. All Rights Reserved. Updated: 8/25/04 4 TECEV103 Analog Technologies, Inc. TMPO WI 2M CMPIN WP 2M 3 1 Ri RI 1 CMPO Left Side 2 1 1 CD1 330nF 2 1 2 CD2 470nF 2 1 TECN Ci 82nF CI1 2 1 3 WD 500K CD3 680nF 3 2 1 S2 ST9P 1 1 CI2 100nF 2 1 2 TECP TMPS TMPO 0 ST9P 1 2 CD6 1.5uF 1 2 CI6 2 7 CD7 2.2uF 1 2 CI7 680nF 2 1 CD8 3.3uF 1 2 0 VDR 10 CI9 1uF 1 2 Cd 7 TMPGD 2 CI 1 1 TECP S_Pad 1 1 8 1 S_Pad TMPS VDR S_Pad TMPGD TMPGD THL8 1 SDN SDN GND 1 TMPO 1 GND GND TECP 1 1 1 TT3 RTH 1 TMPGD THR8 1 1 TT4 TMPS 1 1 TT5 TMPO 1 GND 1 TT6 VDR S_Pad S_Pad S_Pad 1 S_Pad VDR SPR7 TT7 TMPGD 1 S_Pad TMPGD SPR8 TT8 SDN 1 S_Pad SDN SPR9 TT9 GND GND GND 1 S_Pad GND 2 LEDA LEDC 3V CHB LEDA LEDC VDR CMPO CMPIN TMPO 5 6 7 8 TEMPSP GNDP GND TECNEG TECCRT TECPOS VTEC RTH CMIN GND TEMP SDNG 14 13 12 11 3V PGND TMPS W1 W2 2 THM8 3V THM9 CLHT W3 20K 5V 2 2 1 3 TECP 1 R1 100 RTH 1 R2 1 S_Pad THM7 LEDC S_Pad 1 1 1 1 1 CHB 5K 5K TECN 10 9 5V SPM1 LEDA SPM2 LEDC S3 3 2 5V 3 GNDP 16 15 3 VPS 4 N1206-4 SDN LEDC 2 LEDA LED1 VDR 1 3 4 3V THM6 LEDA 2 1 2 R4 Q1 1 R3 1K 2 5V SML-LX2832SUGC 10K 1 TECEV-103 TMPGD 100K 2 3 TEMPGD THM5 CMPO 1 TMPS 2 THM4 CIRP TECA1 1 3V 1 THM3 CMPIN 1 TMPGD THM2 CDRD 2 U1 1 1 1 1 1 BottomSide THM1 TMPO MMBT6428 SDN Figure 5 Evaluation Board Schematic 550 E. Weddell Dr., #4, Sunnyvale, CA 94089 U. S. A. Tel.: (408) 747-9760, Fax: (408) 747-9770. www.analogtechnologies.com Copyright 1999 – 2004, Analog Technologies, Inc. All Rights Reserved. Updated: 8/25/04 5 PGND L_Pad 0V SPT3 TECN 1 L_Pad TECSPT4 TECP 1 L_Pad TEC+ SPT5 RTH 1 TMPO SPR6 SDN 1 S_Pad L_Pad 5V SPT2 1 TMPS SPR5 TMPGD SDN 1 RTH SPR4 VDR TMPGD SPT1 5V TEC+ SPR3 TMPO VDR S_Pad TECSPR2 TT2 TMPS SDN THR9 1 GND TMPS 1 SDN THL9 S_Pad 1 VDR THR7 1 TMPGD 1 RTH 1 VDR THL7 S_Pad RTH TMPO THR6 1 TECN TEC+ 1 THL6 VDR 1 TMPS THR5 TMPO S_Pad TECP 1 TMPS Top Side SPR1 TT1 TEC- RTH THR4 S_Pad 9 10 RTH 1 TMPS 1 TEC+ THR3 RTH THL4 SDN SPL9 1 TECP 1 RTH TECN 1 TEC+ THL3 TMPGD SPL8 GND CD S_Pad VDR SPL7 SDN Rd 1 1 TECTHR2 1 TMPO SPL6 470nF 1 6 CI8 820nF 1 2 CD9 4.7uF 9 2 1 1 5 6 8 1 TECN TECTHL2 TMPS SPL5 4 CI5 330nF 2 1 1 THR1 1 TECN RTH SPL4 3 CI4 220nF 2 1 RD S_Pad TEC+ SPL3 RTH CI3 150nF 2 1 CD4 820nF 4 2 1 CD5 1uF 5 2 1 1 THL1 TECSPL2 2 2 S1 RP RightSide SPL1 Rp 2 3 2 1 S_Pad RTH-1 SPT6 GND 1 S_Pad RTH-2(GND)