LMP92001 Analog System Monitor and Controller 1.0 General Description The LMP92001 is a complete analog monitoring and control circuit which includes a sixteen channel 12-bit Analog to Digital Converter (ADC), twelve 12-bit Digital to Analog Converters (DACs), an internal reference, an internal temp sensor, an 8-bit GPIO port, and an I2C-compatible interface. The ADC can be used to monitor rail voltages, current sense amplifier outputs or sensors and includes a programmable window comparator function on six of its 16 channels to detect out-of range conditions. The DACs can be used to control PA bias points, actuators, potentiometers, etc. When required, the outputs can be instantaneously driven to either supply rail using the output switches and the asynchronous DAC control inputs. Both ADC and DACs can use either the internal 4.5V reference or an external reference independently. The built-in temperature sensor is treated as the 17th analog sense input. In addition, the 8-bit GPIO port allows for the resources of the microcontroller to be further extended, providing even more flexibility. The LMP92001 is available in a space saving 10mmx5.5mm LLP 54-pin package and is operational over the full − 40°C to 125°C temperature range. ■ Programmable window comparator function ■ Interrupt signal generation for input out-of-bound condition 12 Programmable Analog Voltage Outputs ■ Twelve 12-bit DACs ■ Guaranteed Monotonic ■ Settling Time 8.5 µs ■ Simultaneous update of all channels to same value ■ Asynchronous output control forces rail voltage at output Voltage Reference ■ User-selectable source: External or Internal ■ Internal Reference 4.5V ±0.7% Analog Temperature Sensor ■ Readable via ADC channel 17 ■ Temperature Error ±2°C 8-bit GPIO Port ■ Each bit individually programmable I2C-Compatible Bus ■ Supports Standard and Fast Modes ■ Bus TIMEOUT function ■ Supports Block data transfers LLP-54 package (10 x 5.5 mm, 0.5 mm pitch) 2.0 Features 16 Analog Voltage Monitoring Channels ■ 12-bit ADC with programmable input MUX ■ No Missing Codes ■ Total Unadjusted Error (TUE) ±0.1% ■ Single-Shot or Continuous Conversion Modes 3.0 Applications ■ ■ ■ ■ RF PA Bias Monitoring and Control System Monitoring and Control Industrial Monitoring and Control Test Equipment and Instrumentation 4.0 Block Diagram 30132736 National Semiconductor® is a registered trademark of National Semiconductor Corporation. © 2012 Texas Instruments Incorporated 301327 SNAS507B www.ti.com LMP92001 Analog System Monitor and Controller April 19, 2012 LMP92001 5.0 Typical Application 30132706 www.ti.com 2 The LMP92001 has a flexible, feature-rich functionality which makes it ideally suited for many analog monitoring and control applications, for example base-station PA subsystems. This device provides the analog interface between a programmable supervisor, such as a microcontroller, and an analog system whose behavior is to be monitored and controlled by the supervisor. To facilitate analog monitoring functionality, the device contains a single 12-bit ADC fronted by a 17-input multiplexor. The 16 MUX inputs are available to the user via pins IN[16:1]. The last remaining MUX channel is reserved for the internal analog temperature sensor. The analog control functionality is served by twelve 12-bit voltage output DACs. Besides producing voltage corresponding to the digital input code, the DACs can be forced by the user to either rail instantaneously. Additional digital monitoring and control can be realized via the General Purpose I/O port GPIO[7:0]. Two more blocks are present for added functionality: a local temperature sensor (already mentioned above) and an internal reference voltage generator. 6.3 INTERNAL ANALOG TEMPERATURE SENSOR An on-board analog temperature sensor is available to monitor the device’s own temperature. Once enabled, the analog temperature sensor output is sampled via the MUX channel 17, and its conversion result is stored in the internal register for user read back. 6.4 INTERNAL VOLTAGE REFERENCE SOURCE Another resource available to the user is the internal, temperature-compensated reference voltage source. By default both ADC and DACs expect reference potentials to be supplied externally. The user can choose to enable the internal reference and use it with the ADC and/or the DACs. The internal reference source cannot drive an external load. 6.1 17-CHANNEL ANALOG SENSE WITH 12-BIT ADC The user can monitor up to 16 external voltages with the 12bit ADC and its 17-channel input MUX. Typically these voltages will be generated by the analog sensors, instrumentation amplifiers, current sense amplifiers, or simply resistive dividers if high potentials need to be measured. Channel 17 of the input MUX is reserved for the internal temperature sensor, and is not available as an external input to the device. User can program which MUX channels to enable, and whether to convert these channel inputs in sequence continuously, or in a single-shot mode. Upon completion all conversion results are stored in the internal data registers, and can be read back by the user via the I2C-compatible interface. Analog input channels 1-3 and 9-11 have a built-in digital window comparator function with user programmable thresholds. This function can be used to alert the supervisor microcontroller of an out-of-bound condition. The comparator function result is stored in the internal status register which is user accessible. It can also be used as the interrupt signal generator where the out of bound conditions will be reported via the INT[2:1] output pins. Sequencing of the analog sense system is governed by the internal controller. Once enabled the MUX, the ADC, the window comparator and the interrupts perform their function without further user intervention. 6.5 8-BIT GENERAL PURPOSE I/O The GPIO port can be used to expand the microcontroller capabilities. This port is memory mapped to the internal register, which in turn is accessible via the I2C-compatible interface. Since each bit is individually programmable as an Input or Output, the port is ideally suited for external switch control and status flag monitoring, without further burdening of microcontroller I/O resources. 6.6 I2C-COMPATIBLE INTERFACE The microcontroller supervisor communicates with LMP92001 via a popular I2C-compatible 2–wire interface. This interface provides the user full access to all Data, Status and Control registers of the device. There are 2 address setting pins, AS[1:0], that allow the device to occupy any one of 9 possible Interface Addresses on the bus. Block Access commands are provided to minimize the transfer overhead of larger data sets. 6.2 PROGRAMMABLE ANALOG CONTROL VOLTAGE OUTPUTS Twelve identical individually programmable 12-bit DAC blocks are available to generate analog voltages, which can 3 www.ti.com LMP92001 be used to control bias conditions of external circuits, position of servos, etc. In case simultaneous update of all outputs to the same level is needed, a single internal register is provided that effects simultaneous update of all DAC data registers. A DAC, by definition, produces an output in the range of GND to DREF. In some systems, however, it may be desirable for the OUT pins to produce either GND or VDD, i.e., beyond DREF. This is made possible via the asynchronous DAC control inputs C[4:1]. When activated, these inputs will force the OUT pins to either rail. The choice of rail is made in the internal control register. 6.0 Overview LMP92001 7.0 Connection Diagram 30132708 LLP-54 (SQA54AB) Top View www.ti.com 4 LMP92001 8.0 Pin Descriptions Name Pin VDD 14, 50 Supply rail GND 4, 13, 41, 45 Device Ground IN1 5 IN2 6 IN3 7 IN4 8 IN5 9 IN6 10 IN7 11 IN8 12 IN9 40 IN10 39 IN11 38 IN12 37 IN13 36 IN14 35 IN15 34 IN16 33 OUT1 52 OUT2 53 OUT3 54 OUT4 1 OUT5 2 OUT6 3 OUT7 48 OUT8 47 ESD Structures Function Analog Voltage Sense Inputs Analog Control Voltage Outputs OUT9 46 OUT10 44 OUT11 43 OUT12 42 SCL 23 I2C-compatible clock input SDA 24 Bidirectional I2C-compatible data line AS[0:1] 31:32 I2C-compatible Interface Address selection inputs. 5 www.ti.com LMP92001 Name Pin ESD Structures Function C[1:4] 27:30 Asynchronous DAC output control digital inputs GPIO[0:7] 15:22 Digital I/O. CMOS Input or Open-Drain Output INT[1:2] 25:26 Interrupt outputs. Open-Drain, active LOW AREF 49 ADC reference DREF 51 DAC reference 9.0 Ordering Information www.ti.com Order Number NS Package Number Transport Media LMP92001SQE SQA54AB 250 piece reel LMP92001SQX SQA54AB 2000 piece reel 6 1.0 General Description ......................................................................................................................... 1 2.0 Features ........................................................................................................................................ 1 3.0 Applications .................................................................................................................................... 1 4.0 Block Diagram ................................................................................................................................ 1 5.0 Typical Application ........................................................................................................................... 2 6.0 Overview ........................................................................................................................................ 3 6.1 17-CHANNEL ANALOG SENSE WITH 12-BIT ADC ...................................................................... 3 6.2 PROGRAMMABLE ANALOG CONTROL VOLTAGE OUTPUTS .................................................... 3 6.3 INTERNAL ANALOG TEMPERATURE SENSOR ......................................................................... 3 6.4 INTERNAL VOLTAGE REFERENCE SOURCE ........................................................................... 3 6.5 8-BIT GENERAL PURPOSE I/O ................................................................................................. 3 6.6 I2C-COMPATIBLE INTERFACE ................................................................................................. 3 7.0 Connection Diagram ........................................................................................................................ 4 8.0 Pin Descriptions .............................................................................................................................. 5 9.0 Ordering Information ........................................................................................................................ 6 10.0 Absolute Maximum Ratings ............................................................................................................. 9 11.0 Operating Conditions (Note 1, Note 2) ............................................................................................... 9 12.0 Electrical Characteristics ................................................................................................................ 9 13.0 I2C Interface Timing Diagram ........................................................................................................ 12 14.0 Typical Performance Characteristics .............................................................................................. 13 15.0 Register Set ................................................................................................................................ 16 15.1 REGISTER MAP .................................................................................................................. 16 15.2 TEST AND INFO REGISTERS ............................................................................................... 17 15.2.1 Test Register: TEST[7:0], default = 0x00 ........................................................................ 17 15.2.2 Company ID Register: ID[7:0], default = 0x01 ................................................................. 17 15.2.3 Device Version Register: VER[7:0], default = 0x10 .......................................................... 17 15.3 STATUS REGISTERS .......................................................................................................... 18 15.3.1 General Status Register: SGEN[7:0], default = 0x40 ........................................................ 18 15.3.2 GPIO Status Register: SGPI[7:0], default = 0x** .............................................................. 18 15.3.3 High-Limit Status Register: SHIL[7:0], default = 0x00 ....................................................... 18 15.3.4 Low-Limit Status Register: SLOL[7:0], default = 0x00 ...................................................... 18 15.4 CONTROL REGISTERS ....................................................................................................... 19 15.4.1 General Configuration Register: CGEN[7:0], default = 0x00 .............................................. 19 15.4.2 DAC Configuration Register: CDAC[7:0], default 0x03 ..................................................... 19 15.4.3 GPIO Output Control Register: CGPO[7:0], default = 0xFF ............................................... 19 15.4.4 INT1, INT2 High-Limit Control Register: CINH[7:0], default = 0x00 ..................................... 19 15.4.5 INT1, INT2 Low-Limit Control Register: CINL[7:0], default = 0x00 ...................................... 19 15.4.6 ADC Conversion Enable Register 1: CAD1[7:0], default = 0x00 ......................................... 19 15.4.7 ADC Conversion Enable Register 2: CAD2[7:0], default = 0x00 ......................................... 19 15.4.8 ADC Conversion Enable Register 3: CAD3[7:0], default = 0x00 ......................................... 19 15.4.9 ADC One-Shot Conversion Trigger Register : CTRIG[7:0], default = 0x00 .......................... 20 15.4.10 Reference Mode Register: CREF[7:0], default = 0x07 .................................................... 20 15.5 DATA REGISTERS .............................................................................................................. 20 15.5.1 ADC Output Data Register: ADCx[15:0], default 0x0000 .................................................. 20 15.5.2 ADC High-Limit Register: LIHx[15:0], default 0x0FFF ....................................................... 20 15.5.3 ADC Low-Limit Register: LILx[15:0], default 0x0000 ........................................................ 20 15.5.4 DAC Data Register: DACx[15:0], default 0x0000 ............................................................. 20 15.5.5 Write all DAC's Data Register: DALL[15:0], default 0x0000 ............................................... 20 15.6 BLOCK COMMANDS ............................................................................................................ 21 16.0 Application Information ................................................................................................................. 22 16.1 ANALOG SENSE SUBSYSTEM ............................................................................................. 22 16.1.1 Sampling and Conversion ............................................................................................ 22 16.1.2 Sampling Transient ..................................................................................................... 22 16.1.3 Channel Selection ...................................................................................................... 22 16.1.4 Single-Shot and Continuous Sequencing ....................................................................... 22 16.1.5 Reference .................................................................................................................. 24 16.1.6 Window Comparator Function ...................................................................................... 24 16.1.7 Interrupt Subsystem .................................................................................................... 25 16.2 PROGRAMMABLE ANALOG OUTPUT SUBSYSTEM ............................................................... 25 16.2.1 DAC Core .................................................................................................................. 25 16.2.2 Reference .................................................................................................................. 26 16.2.3 Asynchronous Output Control ....................................................................................... 26 16.3 TEMPERATURE SENSOR .................................................................................................... 27 16.4 ADC/DAC VOLTAGE REFERENCE ........................................................................................ 27 7 www.ti.com LMP92001 Table of Contents LMP92001 16.5 GENERAL PURPOSE I/O ..................................................................................................... 16.6 SERIAL INTERFACE ............................................................................................................ 16.6.1 I2C-Compatible Protocol .............................................................................................. 16.6.2 Device Address .......................................................................................................... 16.6.3 Block Access ............................................................................................................. 16.6.4 I2C-Compatible Bus Reset ........................................................................................... 17.0 Application Circuit Example ........................................................................................................... 18.0 Physical Dimensions .................................................................................................................... www.ti.com 8 28 28 29 30 31 31 32 33 For Soldering specifications: See product folder at www.national.com www.national.com/ms/MS-SOLDERING.pdf. 1, Note 2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. 11.0 Operating Conditions VDD Relative to GND Voltage between any 2 pins(Note 3) Current in or out of any pin (Note 3) Current through VDD or GND Operating Ambient Temperature VDD Voltage Range DAC Output Load C Junction Temperature Storage Temperature Range ESD Susceptibility(Note 4) Human Body Model Machine Model Charged Device Model and (Note 1, Note 2) −0.3V to 6.0V 6.0V 5mA 78 mA, TA = 125°C 120 mA, TA = 105°C +150°C −65°C to +150°C −40°C to 125°C 4.5V to 5.5V 0pF to 1500pF θJA 24°C/W θJC 2°C/W 2500V 250V 1250V 12.0 Electrical Characteristics Unless otherwise noted, these specifications apply for VDD=4.75V to 5.5V, AREF=DREF=VDD, TA=25°C. Boldface limits are over the temperature range of −40°C ≤ TA ≤ 125°C unless otherwise noted. DAC input code range 48 to 4047. DAC output CL = 200 pF unless otherwise noted. Symbol Parameter Conditions Min Typ Max Units 12 Bits DAC CHARACTERISTICS Resolution 12 Monotonicity 12 Bits DNL Differential Non-Linearity RL = 100k −0.6 0.6 INL Integral Non-Linearity RL = 100k −8 8 ZE Zero Error RL = 100k Zero Error Temperature Drift RL = 100k FSE Full-Scale Error RL = 100k 0 −0.75 GE Gain Error RL = 100k 0 −1 Gain Error Temperature Drift RL = 100k 11.0 IOUT = 200 µA 7 IOUT = 1mA 31 ZEDRIFT GEDRIFT ZCO Zero Code Output FSO Full Scale Output at code 4095 VDD = DREF = 5V, IOUT = 1mA 15 2.0 4.988 4.995 mV VDD Output Short Circuit Current (Source) (Note 5) IOS Output Short Circuit Current (Sink) (Note 5) VDD = 5V, OUT = DREF, Input Code = 000h CDAC.OFF=0 C[4:1]=HIGH IO Continuous Output Current per Channel (to prevent damage) TA = 105° C 10 TA = 125° C 6.5 CL Load Capacitance RL = 2k or ∞ RL = 100k, C[1:4] = GND, CDAC.OLVL = 1 C[1:4] = GND, CDAC.OLVL = 0 9 V mA DC Output Impedance OUT[1:12] Output Voltage when Asynchronous Output Control is activated %FS ppm/° C IOS 70 mV µV/°C VDD = 5V, OUT = 0V, Input Code = FFFh CDAC.OFF=0 C[4:1]=HIGH −60 LSB 4.992 1500 pF 8 Ω VDD V GND 0.6 mV www.ti.com LMP92001 10.0 Absolute Maximum Ratings (Note LMP92001 Symbol Parameter Conditions Min Typ Max Units ADC CHARACTERISTICS Resolution with No Missing Codes TUE Total Unadjusted Error DNL Differential Non-Linearity INL Integral Non-Linearity OE Offset Error −0.1 0.1 −0.99 1 −1.2 1 −2.3 OEMTCH Offset Error Match Gain Error Temperature Drift GEMTCH Gain Error Match 1.5 −2 2 −0.002 −1.5 Power Supply Rejection Ratio VIN FS Input Range IINA Input Current CINA Input Capacitance LSB LSB/°C −1.5 Signal-to-Noise Ratio % 2.3 0.005 Gain Error GEDRIFT PSRR Bits 12 ±0.6 Offset Error Temperature Drift SNR −40°C ≤ TA ≤ 105°C −40°C ≤ TA ≤ 105°C OEDRIFT GE 11 LSB LSB/°C 1.5 LSB 72 dB Offset Error change with VDD 77 dB Gain Error change with VDD 73 AREF In Hold or inactive ±1 µA In Track 33 pF In Hold or inactive 3 pF REFERENCE CHARACTERISTICS AREF Reference Input Range CREF.AEXT = 1 DREF Reference Input Range 2.7 VDD V 2.5 VDD V CREF.DEXT = 1 DREF Reference Input Resistance DREF Input Current DREF = 5V, CREF.DEXT = 1 AREF Peak Current AREF = 5V CREF.DEXT = 1 10 660 2.3 AREF and DREF Reference Current in Powerdown Internally Generated Reference Voltage AREF, DREF Output Impedance when Internal Reference Active kΩ 4.47 CREF.AEXT = 0 CREF.DEXT = 0 4.5 µA mA 1 µA 4.53 V Ω 5 TEMPERATURE SENSOR Sensor Gain −13.45 Temperature Error mV/°C −25°C to +85°C −2 2 −45°C to +125°C −2.5 2.5 °C DIGITAL INPUT CHARACTERISTICS (AS1:AS0) VIH Input HIGH Voltage VIM Input MID Voltage V 0.90x VDD 0.57 x VDD 0.43 x VDD VIL Input LOW Voltage IIND Digital Input Current CIND Input Capacitance ±0.005 0.1 x VDD V ±1 µA 4 pF DIGITAL INPUT CHARACTERISTICS (GPIO0:GPIO7, C1:C4) VIH Input HIGH Voltage VIL Input LOW Voltage 0.3 x VDD Hysteresis www.ti.com V 0.7 x VDD 0.47 10 V V Parameter IIND Digital Input Current CIND Input Capacitance VIH Input HIGH Voltage VIL Input LOW Voltage Conditions Min Typ Max Units ±0.005 ±1 µA 4 pF DIGITAL INPUT CHARACTERISTICS (SDA and SCL) Hysteresis IIND Digital Input Current CIND Input Capacitance V 2.2 1 V ±1 µA 0.27 ±0.005 V 4 pF DIGITAL OUTPUT CHARACTERISTICS (INT and GPIO) VOL Output LOW Voltage IOUT = 200 µA 0.005 0.4 V IOUT = 4 mA 0.16 0.4 V IOUT = 4mA 0.16 0.4 V IOUT = 6mA 0.23 0.6 V ±1 µA DIGITAL OUTPUT CHARACTERISTICS (SDA) VOL Output LOW Voltage DIGITAL OUTPUT CHARACTERISTICS (All Outputs) IOL Current from the supply rail through the pullup resistor into the drain of the open-drain output device Output Leakage when HIGH COUT Output Capacitance VDD Supply Voltage Range IDD Supply Current, converting, all blocks active PWR Power Consumption, converting, all blocks active VPOR Power-On Reset (Note 8) Force 0V or VDD 4 pF POWER SUPPLY CHARACTERISTICS 5 5.5 V OUT[1:12] pins RL = ∞ 4 6.5 mA OUT[1:12] pins RL = ∞ 25 36 mW 4.75 −40°C ≤ TA ≤ 105°C 1.9 2.4 1.85 2.45 V AC ELECTRICAL CHARACTERISTICS tTRACK ADC Track Time Interval during which internal HOLD capacitor is connected to input signal 4.7 5.3 µs tHOLD ADC Hold Time Interval during which sampled signal is converted to digital output code 3.3 3.8 µs DAC Settling Time (Note 9) 400h to C00h code change, RL= 2k CL = 200 pF 6 8.5 µs 400 kHz ts I2C TIMING CHARACTERISTICS I2C Clock Frequency tLOW Clock Low Time tHIGH Clock High Time tHD;STA Hold Time Repeated START condition tSU;STA Set-up time for a repeated START condition tHD;DAT Data hold time (Note 6, Note 7) tSU;DAT Data setup time tf SDA fall time 10 After this period, the first clock pulse is generated 1.3 µs 0.6 µs 0.6 µs 0.6 µs 0 900 IL ≤ 3mA and CL ≤ 400 pF ns ns 100 250 ns tSU;STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs Cb SDA capacitive load 400 11 pF www.ti.com LMP92001 Symbol LMP92001 Symbol Parameter tSP Pulse width of spikes that must be suppressed by the input filter tOUT SCL and SDA Timeout Conditions Min 25 Typ Max Units 50 ns 35 ms Note 1: Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified. Note 3: When the input voltage (VIN) at any pin exceeds power supplies (VIN < GND or VIN > VDD), the current at that pin must not exceed 5mA, and the voltage (VIN) at that pin relative to any other pin must not exceed 6.0V. See Pin Descriptions for additional details of input circuitry. Note 4: The Human Body Model (HBM) is a 100 pF capacitor charged to the specified voltage then discharged through a 15 kΩ resistor into each pin. The Machine Model (MM) is a 200 pF capacitor charged to specified voltage then discharged directly into each pin. The Charged Device Model (CDM) is a specified circuit characterizing an ESD event that occurs when a device acquires charge through some triboelectric (frictional) or electrostatic induction process and then abruptly touches a grounded object or surface. Note 5: Indicates the typical internal short circuit current limit. Sustained operation at this level will lead to device damage. Note 6: Data hold time is measured from the falling edge of SCL, applies to data transmission and the acknowledge. Note 7: Device internally provides a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL. Note 8: During the power up the supply rail must ramp up beyond VPOR MIN for the device to acquire default state. After the supply rail has reached the nominal level, the rail can drop as low as VPOR MAX for the current state to be maintained. Note 9: Device Specification is guaranteed by characterization and is not tested in production. 13.0 I2C Interface Timing Diagram 30132709 www.ti.com 12 LMP92001 14.0 Typical Performance Characteristics ADC: INL VDD = 5V, AREF = 4.5V, TA = 25°C CREF.AEXT = 1, Single Channel Continuous Mode 2 2 1 1 INL (lsb) DNL (lsb) ADC: DNL VDD = 5V, AREF = 4.5V, TA = 25°C CREF.AEXT = 1, Single Channel Continuous Mode 0 0 -1 -1 -2 -2 0 1024 CODE 2048 0 3072 1024 CODE 2048 3072 30132753 30132751 DAC: DNL VDD = 5V, DREF = 4.5V, TA = 25°C CREF.DEXT = 1, RL = 100kΩ DAC: INL VDD = 5V, DREF = 4.5V, TA = 25°C CREF.DEXT = 1, RL = 100kΩ 5 1.0 4 3 INL (lsb) DNL (lsb) 0.5 0.0 2 1 -0.5 0 -1 -1.0 0 CODE SPAN 48:4048 0 4048 CODE SPAN 48:4048 4048 30132754 30132752 13 www.ti.com LMP92001 ADC: DNL vs. Temperature VDD = 5V, AREF = 4.5V, CREF.AEXT = 1 2 ADC: INL vs. Temperature VDD = 5V, AREF = 4.5V, CREF.AEXT = 1 2 Minimum DNL Maximum DNL 1 INL (lsb) 1 DNL (lsb) Minimum INL Maximum INL 0 0 -1 -1 -2 -2 -50 -25 -50 0 25 50 75 100 125 TEMPERATURE (°C) -25 0 25 50 75 TEMPERATURE (°C) 100 125 30132758 30132750 DAC: DNL vs Temperature VDD = 5V, DREF = 4.5V, CREF.DEXT = 1 DAC: INL vs Temperature VDD = 5V, DREF = 4.5V, CREF.DEXT = 1 4 4 3 2 2 1 INL (lsb) DNL (lsb) 3 Minimum INL Maximum INL 0 -1 1 0 -1 -2 -2 -3 -3 -4 Minimum INL Maximum INL -4 -50 -25 0 25 50 75 TEMPERATURE (°C) 100 125 -50 -25 0 25 50 75 TEMPERATURE (°C) 100 125 30132755 30132756 OUTx Output Load Regulation VDD = 5V, DREF = 5V, TA = 25°C, CREF.DEXT = 1 Temperature Sensor Error Bounds, VDD = 5V 2.0 TEMPERATURE ERROR (°C) OUTX OUTPUT VOLTAGE (V) 5.0 4.5 4.0 Current Sink, DACx=0x000 Current Source DACx=0xFFF 3.5 3.0 2.5 2.0 1.5 1.0 0.5 Error Lower Bound Error Upper Bound 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 0.0 0 2 4 6 8 SINK/SOURCE CURRENT (mA) -50 -25 10 0 25 50 75 100 125 TEMPERATURE (°C) 30132757 30132761 www.ti.com 1.5 14 LMP92001 Internal Reference Output Temperature Drift VDD = 5V, CREF.AEXT = 0, CREF.DEXT = 0 4.505 REFERENCE OUTPUT (V) 4.504 AREF DREF 4.503 4.502 4.501 4.500 4.499 4.498 4.497 4.496 4.495 -50 -25 0 25 50 75 100 125 TEMPERATURE (°C) 30132759 15 www.ti.com LMP92001 If writing to a RESERVED bit, user must write only 0, unless otherwise stated. 15.0 Register Set RESERVED registers in the map in Section 15.1 REGISTER MAP should not be accessed for either read or write operations as this may lead to unpredictable behavior of the device. 15.1 REGISTER MAP Addr. Name 0x00 0x01 Function R/W Lock RESERVED TEST 0x02 | 0x0D Test Register RW RESERVED 0x0E ID 0x0F VER Company ID Register R Version Register R STATUS 0x10 SGEN Status: General R 0x11 SGPI Status: GPIO R 0x12 SHIL Status: over HIGH limit R 0x13 SLOL Status: under LOW limit R 0x14 CGEN General RW 0x15 CDAC DAC RW 0x16 CGPO GPIO mode RW 0x17 CINH INT HIGH enable RW Y 0x18 CINL INT LOW enable RW Y 0x19 CAD1 Analog ch enable RW Y 0x1A CAD2 Analog ch enable RW Y 0x1B CAD3 Temp. Sens. ch enable RW Y 0x1C CTRIG Single conversion trigger W Y 0x20 ADC1 Ch1 conversion Data R 0x21 ADC2 Ch2 conversion Data R 0x22 ADC3 Ch3 conversion Data R 0x23 ADC4 Ch4 conversion Data R 0x24 ADC5 Ch5 conversion Data R 0x25 ADC6 Ch6 conversion Data R 0x26 ADC7 Ch7 conversion Data R 0x27 ADC8 Ch8 conversion Data R 0x28 ADC9 Ch9 conversion Data R CONTROL ADC OUTPUT DATA 0x29 ADC10 Ch10 conversion Data R 0x2A ADC11 Ch11 conversion Data R 0x2B ADC12 Ch12 conversion Data R 0x2C ADC13 Ch13 conversion Data R 0x2D ADC14 Ch14 conversion Data R 0x2E ADC15 Ch15 conversion Data R 0x2F ADC16 Ch16 conversion Data R 0x30 ADC17 Temp. Sensor Data R ADC WINDOW COMPARATOR LIMITS www.ti.com 0x40 LIH1 ADC Ch1 HIGH limit RW Y 0x41 LIH2 ADC Ch2 HIGH limit RW Y 0x42 LIH3 ADC Ch3 HIGH limit RW Y 16 Name Function R/W Lock 0x43 LIH9 ADC Ch9 HIGH limit RW Y 0x44 LIH10 ADC Ch10 HIGH limit RW Y 0x45 LIH11 ADC Ch11 HIGH limit RW Y 0x46 LIL1 ADC Ch1 LOW limit RW Y 0x47 LIL2 ADC Ch2 LOW limit RW Y 0x48 LIL3 ADC Ch3 LOW limit RW Y 0x49 LIL9 ADC Ch9 LOW limit RW Y 0x4A LIL10 ADC Ch10 LOW limit RW Y 0x4B LIL11 ADC Ch11 LOW limit RW Y LMP92001 Addr. INTERNAL REFERENCE CONTROL 0x66 CREF Int. reference enable RW DAC INPUT DATA 0x80 DAC1 DAC Ch1 Input Data RW 0x81 DAC2 DAC Ch2 Input Data RW 0x82 DAC3 DAC Ch3 Input Data RW 0x83 DAC4 DAC Ch4 Input Data RW 0x84 DAC5 DAC Ch5 Input Data RW 0x85 DAC6 DAC Ch6 Input Data RW 0x86 DAC7 DAC Ch7 Input Data RW 0x87 DAC8 DAC Ch8 Input Data RW 0x88 DAC9 DAC Ch9 Input Data RW 0x89 DAC10 DAC Ch10 Input Data RW 0x8A DAC11 DAC Ch11 Input Data RW 0x8B DAC12 DAC Ch12 Input Data RW 0x8C | 0x8F 0x90 RESERVED DALL All DAC Data W MEMORY MAPPED BLOCK COMMANDS 0xF0 BLK0 DAC1-12 access RW 0xF1 BLK1 DAC7-12 access RW 0xF2 BLK2 ADC1-17 access R 0xF3 BLK3 ADC9-17 access R 0xF4 BLK4 LIHx, LILx access RW 0xF5 BLK5 LILx access RW 0xF6 | 0xFF RESERVED 15.2 TEST AND INFO REGISTERS The registers in section 15.2 do not affect the operation of the device. They are provided for user convenience and product identification. 15.2.2 Company ID Register: ID[7:0], default = 0x01 Product identification register, factory set. 15.2.3 Device Version Register: VER[7:0], default = 0x10 Product identification register, factory set. 15.2.1 Test Register: TEST[7:0], default = 0x00 This register can be used for verification of the I2C-compatible bus integrity. Its contents are ignored by the device. 17 www.ti.com LMP92001 15.3.3 High-Limit Status Register: SHIL[7:0], default = 0x00 15.3 STATUS REGISTERS 15.3.1 General Status Register: SGEN[7:0], default = 0x40 Bx Name Function 7 BUSY 1 - while ADC is converting 6 RDYN 0 - when power up completed 5:3 - 2 HV 1 - if any bit in SHIL is set 1 LV 1 - if any bit in SHOL is set 0 GPI 1 - if any bit in SGPI is set RESERVED 15.3.2 GPIO Status Register: SGPI[7:0], default = 0x** Bx Name 7:6 - Function 5 H11 Set if ADC11 > LIH11 4 H10 Set if ADC10 >LIH10 3 H9 1 - if ADC9 > LIH9 2 H3 1 - if ADC3 > LIH3 1 H2 1 - if ADC2 > LIH2 0 H1 1 - if ADC1 > LIH1 RESERVED 15.3.4 Low-Limit Status Register: SLOL[7:0], default = 0x00 Bx Name 7 GPI7 Indicates logic level at pin GPIO7 Bx Name 6 GPI6 Indicates logic level at pin GPIO6 7:6 - 5 GPI5 Indicates logic level at pin GPIO5 5 L11 4 GPI4 Indicates logic level at pin GPIO4 1 - if ADC11 ≤ LIH11 3 GPI3 Indicates logic level at pin GPIO3 4 L10 1 - if ADC10 ≤ LIH10 2 GPI2 Indicates logic level at pin GPIO2 3 L9 1 - if ADC9 ≤ LIH9 1 GPI1 Indicates logic level at pin GPIO1 2 L3 1 - if ADC3 ≤ LIH3 1 L2 1 - if ADC2 ≤ LIH2 0 L1 1 - if ADC1 ≤ LIH1 0 www.ti.com GPI0 Function Indicates logic level at pin GPIO0 18 Function RESERVED 15.4.1 General Configuration Register: CGEN[7:0], default = 0x00 Bx Name 7 RST 6:3 2 1 0 TOD LCK STRT Function RESERVED - 1 - Enable High limit interrupt for Ch 11 RESERVED 4 EH10 1 - Enable High limit interrupt for Ch 10 1 - disable I2C-compatible TIMEOUT. See Section 16.6.4 I2C-Compatible Bus Reset 3 EH9 1 - Enable High limit interrupt for Ch 9 2 EH3 1 - Enable High limit interrupt for Ch 3 1 EH2 1 - Enable High limit interrupt for Ch 2 1 - to lock registers. Lockable registers are shown in the Register Map in Section 15.1 REGISTER MAP. Once locked their contents will not be affected by the subsequent I2Ccompatible bus transactions 0 EH1 1 - Enable High limit interrupt for Ch 1 15.4.5 INT1, INT2 Low-Limit Control Register: CINL[7:0], default = 0x00 1 - to start continuous conversion of all enabled ADC channels. The CGEN.LCK bit must be set for the conversion sequence to begin 0 - disable continuous ADC conversion mode - RESERVED GANG Controls the association of analog output channels OUTx with asynchronous control inputs Cy. (See Section 16.2.3 Asynchronous Output Control) OFF Function EH11 7:3 0 RESERVED 5 Name OLVL - 6 Bx 1 Name 7 1 - RESETS all registers and self to POR value 15.4.2 DAC Configuration Register: CDAC[7:0], default 0x03 2 Bx 1 - Cy=0 will force associated OUTx outputs to VDD 0 - Cy=0 will force associated OUTx outputs to GND 1 - forces all OUT[1:12] outputs to HIGH impedance state Name Function GPO7 1 - Internal pulldown at pin GPIO7 is off 6 GPO6 1 - Internal pulldown at pin GPIO6 is off 5 GPO5 1 - Internal pulldown at pin GPIO5 is off 4 GPO4 1 - Internal pulldown at pin GPIO4 is off 3 GPO3 1 - Internal pulldown at pin GPIO3 is off 2 GPO2 1 - Internal pulldown at pin GPIO2 is off 1 GPO1 1 - Internal pulldown at pin GPIO1 is off 0 GPO0 1 - Internal pulldown at pin GPIO0 is off - RESERVED Function 6 - RESERVED 5 EL11 1 - Enable Low limit interrupt for Ch 11 4 EL10 1 - Enable Low limit interrupt for Ch 10 3 EL9 1 - Enable Low limit interrupt for Ch 9 2 EL3 1 - Enable Low limit interrupt for Ch 3 1 EL2 1 - Enable Low limit interrupt for Ch 2 0 EL1 1 - Enable Low limit interrupt for Ch 1 Bx Name 7 EN8 1 - Enable ADC input Ch 8 Function 6 EN7 1 - Enable ADC input Ch 7 5 EN6 1 - Enable ADC input Ch 6 4 EN5 1 - Enable ADC input Ch 5 3 EN4 1 - Enable ADC input Ch 4 2 EN3 1 - Enable ADC input Ch 3 1 EN2 1 - Enable ADC input Ch 2 0 EN1 1 - Enable ADC input Ch 1 15.4.7 ADC Conversion Enable Register 2: CAD2[7:0], default = 0x00 15.4.3 GPIO Output Control Register: CGPO[7:0], default = 0xFF 7 Name 7 15.4.6 ADC Conversion Enable Register 1: CAD1[7:0], default = 0x00 Function Bx Bx Bx Name 7 EN16 1 - Enable ADC input Ch 16 Function 6 EN15 1 - Enable ADC input Ch 15 5 EN14 1 - Enable ADC input Ch 14 4 EN13 1 - Enable ADC input Ch 13 3 EN12 1 - Enable ADC input Ch 12 2 EN11 1 - Enable ADC input Ch 11 1 EN10 1 - Enable ADC input Ch 10 0 EN9 1 - Enable ADC input Ch 9 15.4.8 ADC Conversion Enable Register 3: CAD3[7:0], default = 0x00 19 Bx Name 7:1 - 0 EN17 Function RESERVED 1 - Enable Temp Sensor ADC input channel www.ti.com LMP92001 15.4.4 INT1, INT2 High-Limit Control Register: CINH[7:0], default = 0x00 15.4 CONTROL REGISTERS LMP92001 15.5.2 ADC High-Limit Register: LIHx[15:0], default 0x0FFF The LILx registers, x=1...3 and 9...11, contain the HIGH LIMIT threshold of the window comparator function of the Analog Sense Subsystem. 15.4.9 ADC One-Shot Conversion Trigger Register : CTRIG[7:0], default = 0x00 Bx Name 7:1 - 0 SNGL Function RESERVED Writing any value, when CGEN.STRT=0, will trigger Single-Shot conversion. The CGEN.LCK bit must be set for the conversion sequence to begin. Bx 15.4.10 Reference Mode Register: CREF[7:0], default = 0x07 Bx Name 7:3 - 2 AEXT 1 - ADC external ref. enable 0 - ADC internal ref. enable 1 DEXT 1 - DAC external ref. enable 0 - DAC internal ref. enable 0 - Function - Always 0. Data written to this location will be discarded. 11:0 - Window comparator upper limit. 15.5.3 ADC Low-Limit Register: LILx[15:0], default 0x0000 The LILx registers, x=1...3 and 9...11, contain the LOW LIMIT threshold of the window comparator function of the Analog Sense Subsystem. Function RESERVED Bx Name Function 15:12 - Always 0. Data written to this location will be discarded. 11:0 - Window comparator lower limit. RESERVED, must be 1 15.5 DATA REGISTERS All registers in this section require 16-bit I2C-compatible data transaction for both read and write operations. However, only lower 12 bits are stored. All data is assumed to be in the unsigned binary format, where the lowest value is represented by 0x000 and the highest value is represented by 0xFFF. 15.5.4 DAC Data Register: DACx[15:0], default 0x0000 The DACx registers, x=1...12, are input code registers. Updating the DACx register automatically updates the VOUTx of the corresponding DAC. Note that OUTx may not update due to the state of the asynchronous control inputs C[1:4]. (See Section 16.2.3 Asynchronous Output Control.) 15.5.1 ADC Output Data Register: ADCx[15:0], default 0x0000 The ADCx registers, x = 1...16, contain results of the most recent ADC conversion cycle. Accessing these registers does not preempt the Analog Sense Subsystem sequencing. Enabling/Disabling of the ADC input channels via CADx registers does not affect the ADCx content. Bx Name 15:1 2 - Always 0 11:0 - 12-bit binary representing the ADC conversion result www.ti.com Name 15:1 2 Bx Name Function 15:12 - Always 0. Data written to this location will be discarded. 11:0 - DACx input data. 15.5.5 Write all DAC's Data Register: DALL[15:0], default 0x0000 Writing to this register updates all DACx registers simultaneously to this value. Note that OUTx may not update due to the state of the asynchronous control inputs C[1:4]. Function Bx 20 Name Function 15:12 - Always 0. Data written to this location will be discarded. 11:0 - DAC input data. LMP92001 15.6 BLOCK COMMANDS Block access functionality is discussed in Section 16.6.3 Block Access. Name Block Start Address Block End Address Block Length in Bytes Comment BLK0 0x80 0x8B 24 Single command access to registers DAC[1:12] BLK1 0x86 0x8B 12 Single command access to registers DAC[7:12] BLK2 0x20 0x30 34 Single command access to registers ADC[1:17] BLK3 0x28 0x30 18 Single command access to registers ADC[9:17] BLK4 0x40 0x4B 24 Single command access to all LIHx and LILx registers BLK5 0x46 0x4B 12 Single command access to all LILx registers 21 www.ti.com LMP92001 is measured to produce an ADC output code. The resulting output code is stored in the internal register (ADCx) corresponding to the sampled analog input channel. Typical ADC output code as a function of input voltage at device pin INx, x=1...16: 16.0 Application Information 16.1 ANALOG SENSE SUBSYSTEM The device is capable of monitoring up to 16 externally applied voltages and an internal analog temperature sensor. The system is centered around 12-bit SAR ADC fronted by a 17-input mux. Results of conversion are stored in the registers corresponding to the given input channel. The register content can be read by the supervisor via the I2C-compatible interface. The ADC timing signals are derived from the on-board temperature compensated oscillator, which assures the stable sampling interval. In the applications where an instantaneous detection of the out-of-bounds condition is required the built in digital window comparator function is provided on 6 of the input channels. This window comparator is capable of triggering the external interrupts. In the expression above VREF is the reference voltage input to the internal ADC. VREF can be either externally applied at the AREF pin of the device, or be internally generated. 16.1.2 Sampling Transient An instantaneous current will flow at the beginning of TRACK period which may lead to temporary disturbance of the input potential. This current, and resulting disturbance, will vary with the magnitude of the sampled signal and source impedance ROUT. 16.1.1 Sampling and Conversion The external voltage is sampled onto the internal CHOLD capacitor. The TRACK period is controlled by the internal oscillator, and its duration is tTRACK. The output impedance of the sensed voltage source and the analog input capacitance CINA (which is dominated by CHOLD during TRACK time) limit the bandwidth of the input signal. It is recommended to limit the output resistance ROUT of the sampled voltage source to 10 kΩ to assure 12-bit accuracy of conversion. 16.1.3 Channel Selection The analog input channels are enabled by setting corresponding enable bits ENx in the control registers CAD1, CAD2, and CAD3. Enabling of the channels does not begin the conversion process. 16.1.4 Single-Shot and Continuous Sequencing The ADC is in the idle state until either the Single-Shot or Continuous conversion is initiated. The channels whose corresponding ENx bit in the CAD(1|2|3) registers is set will be sampled and converted by the ADC. Single-Shot conversion begins when the user performs a write operation ( 0 or 1 ) to CTRIG.SNGL while CGEN.STRT=0. Once the sequence is completed the ADC returns to the idle state. Continuous conversion begins when the user sets the CGEN.STRT bit. The sequencing of events is the same as in the Single Mode. Upon completing the sequence of conversions another sequence is automatically started. This process will continue until the user clears the CGEN.STRT bit. The operation of the Analog Sense Subsystem is further illustrated in Figure 2. 30132722 FIGURE 1. ADC During TRACK Period During the HOLD period, duration of tHOLD, all mux switches are in the off state, and charge captured on the hold capacitor www.ti.com 22 LMP92001 30132710 FIGURE 2. ADC Finite State Machine Diagram 23 www.ti.com LMP92001 16.1.5 Reference By default the ADC operates from the external reference voltage applied at AREF pin of the device. Due to the architecture of the ADC the DC current flowing into the AREF input is zero during conversion. However, the transient currents during the conversion can be significant. The user can enable the internal reference generator and apply its output to the ADC VREF. This operation is described in Section 15.4 CONTROL REGISTERS. 16.1.6 Window Comparator Function The digital window comparator function is available for ADC input channels 1-3 and 9-11. This feature does not require explicit enabling, as it is always on. Comparator functional diagram is shown in Figure 3 below. The ADC conversion result stored in ADCx register can be compared against user programmable upper and lower limits: LIHx and LILx. The comparison result is reported as a single bit value in SHIL and SLOL registers. 30132730 FIGURE 3. ADC Window Comparator Function www.ti.com 24 30132735 FIGURE 4. Interrupt System 16.2 PROGRAMMABLE ANALOG OUTPUT SUBSYSTEM This subsystem consists of 12 identical DACs whose output is a function of user programmable registers DACx. This functionality is described in Section 16.2.1 DAC Core. There are instances where it is necessary to instantaneously “turn off” the devices downstream of OUTx output, without incurring the delay due to the I2C-compatible data/command transfer. This functionality is described in Section 16.2.3 Asynchronous Output Control. 16.2.1 DAC Core The DAC core is based on a Resistive String architecture which guarantees monotonicity of its transfer function. The input data is single-registered, meaning that the VOUTx of the DAC is updated as soon as the data is updated in the DACx data register at the end of the I2C-compatible transaction. The functional diagram of the DAC Core is shown in Figure 5. 25 www.ti.com LMP92001 reports out of bound conditions at ADC channels 9-11. Functional diagram of the interrupt system is shown in Figure 4. Additionally, presence of any out of bound condition is reported in the SGEN register, which can be tested via the I2Ccompatible interface. 16.1.7 Interrupt Subsystem Device outputs INT1 and INT2 report out of bounds conditions as determined by the digital window comparator. INT1 and INT2 are open collector outputs and are active LO. INT1 reports out of bound conditions at ADC channels 1-3, and INT2 LMP92001 30132717 FIGURE 5. DAC Core Typical DAC core output VOUTx as a function of the DACx input , x=1...12, can be expressed as: described in Section 16.4 ADC/DAC VOLTAGE REFERENCE. 16.2.3 Asynchronous Output Control When DACs are enabled, CDAC.OFF=0, the Cy device inputs allow the user to instantaneously disengage the VOUTx of corresponding DAC Core and force the OUTx to either rail – the rail is indicated by the CDAC.OLVL bit. Asserting either CDAC.OFF or Cy (Active LOW) will result in the corresponding DAC Core powering down. The functional diagram of the DAC Core to OUTx signal routing is shown in Figure 6. 16.2.2 Reference By default the DACs operate from the external reference voltage applied at the DREF pin of the device. Given the architecture of the DAC the DC current flowing into the DREF device input pin is dependent on the number of DACs active at the given instant. The user can enable the internal reference generator and apply its output to all DACs’ VREF inputs. This operation is www.ti.com 26 LMP92001 30132718 FIGURE 6. Asynchronous Output Control Note that CDAC.OFF affects all OUTx, whereas Cy affects only channels assigned to it. The correspondence between Cy control inputs and OUTx outputs is governed by the CDAC.GANG bit and is outlined in Table 1. TABLE 1. Cy to OUTx Assignment Device Pin Cy CDAC:GANG = 0 CDAC:GANG = 1 C1 OUT[1:4] OUT[1:3] C2 OUT[5:6] OUT[4:6] C3 OUT[7:8] OUT[7:9] C4 OUT[9:12] OUT[10:12] 16.3 TEMPERATURE SENSOR The output voltage of the analog temperature sensor can be sampled via ADC channel 17 input. The result of conversion is stored in the ADC17 register. Typical ADC output code as a function of temperature: In the expression above VREF is the reference input voltage to the internal ADC. For best temperature measurement accuracy the exposed DAP of the device should be soldered to the PCB's grounded pad, and the power dissipation of the device should be limited. The device also has a built in precision reference block which can be used to provide VREF potential to either ADC or DACs, or both at once. The internal buffers are designed to provide necessary drive to ADC and DAC blocks. The internal reference buffers are not intended to drive external loads. When internal reference is enabled the capacitance at AREF or DREF pins should be limited to 50 pF. The functional diagram of the reference selector is shown in Figure 7. NOTE: Internal reference drive must be disabled when corresponding external reference is applied; e.g., set CREF.AEXT=1 when applying external AREF. 16.4 ADC/DAC VOLTAGE REFERENCE The on-board ADC and DACs require reference voltages for their operation. By default the device is configured to accept external references applied to AREF and DREF pins respectively. In this configuration AREF and DREF can be at different potentials. The external reference voltage sources should be bypassed to ground with capacitance appropriate for those particular sources. See example application schematic in Section 17.0 Application Circuit Example. 27 www.ti.com LMP92001 30132719 FIGURE 7. Reference Select Function alizes an “open-drain” digital output. For example, writing HIGH to CGPO:GPO0 will result in HIGH output state at pin GPIO0. The functional diagram of the GPIO subcircuit is shown in Figure 8. 16.5 GENERAL PURPOSE I/O The GPIO[7:0] port is memory mapped to registers SGPI and CGPO. Both registers are accessible through the I2C-compatible interface. The SGPI register content reflects at all times the digital state at the GPIOx device pins. The CGPO register controls the individual pulldown devices at GPIOx. Together with the external pull-up resistor this re- 30132721 FIGURE 8. GPIO Functionality device. Interface functionality is compatible with I2C “Standard” and “Fast” modes. The device operates as the slave only. 16.6 SERIAL INTERFACE The serial interface provides user access to internal CONTROL and DATA registers that govern the operation of the www.ti.com 28 • • • First byte must contain 7-bit Slave Interface Address First byte is followed by a READ/WRITE bit All subsequent bytes contain 8-bit data Device, depending on the register being accessed, supports 1-byte and 2-byte transfers. Block Access commands result in multi-byte transfers In case of a 2-byte transfers, the byte order is always “MSB first” Bit order within byte is always “MSB” first” ACKNOWLEDGE condition follows every byte transfer – this can be generated by either Master or a Slave depending on the direction of data transfer 30132723 FIGURE 9. General I2C-Compatible Protocol Table 2 lists all conditions defined by the I2C-compatible specification and supported by this device. All following bus descriptions will refer to the Symbols listed in the table. TABLE 2. I2C-Compatible Symbol Set Condition Symbol Source Description START S Master Begins all bus transactions STOP P Master Terminates all transactions, and resets bus ACK (Acknowledge) A Master/Slave Handshaking bit (LOW) NAK (No Acknowledge) A Master/Slave Handshaking bit (HIGH) READ R Master Active HIGH bit that follows immediately after the slave address sequence. Indicates that the master is initiating the slave to master data transfer WRITE W Master Active LOW bit that follows immediately after the slave address sequence. Indicates that the master is initiating the master to slave data transfer REPEATED START Sr Master Generated by master, same function as the Start condition (highlights the fact that Stop condition is not strictly necessary) Data transfers of 16-bit values are shown in Figure 10 and Figure 11 below: 29 www.ti.com LMP92001 • • • • 16.6.1 I2C-Compatible Protocol Two wires, SCL and SDA, are used to carry data between master (the digital supervisor), and a slave (LMP92001). Master generates a START condition which commences all data transfers. And only the master generates the SCL signal for all transactions. However, both master and the slave can in turn be a transmitter and receiver of data. Typical bus transaction is shown in Figure 9 below. All transactions follow the format outlined as follows: • Master begins all transactions by generating START condition • All transfers comprise 8-bit bytes LMP92001 30132724 FIGURE 10. I2C-Compatible READ Access Protocol 30132714 FIGURE 11. I2C-Compatible WRITE Access Protocol LOW=GND, HIGH=VDD and MID=VDD/2. All possible Interface Addresses are listed in Table 3 below: 16.6.2 Device Address Interface Address of the device can be set via 2 pins: AS0 and AS1. Each address setting pin recognizes 3 levels: TABLE 3. Interface Address Space Device Pins AS1 AS0 Device Interface Address [A6:A0]R/W Equivalent HEX Address LOW LOW [0100 000]0 40 LOW MID [0100 001]0 42 LOW HIGH [0100 010]0 44 MID LOW [0100 011]0 46 MID MID [0100 100]0 48 MID HIGH [0100 101]0 4A HIGH LOW [0100 110]0 4C HIGH MID [0100 111]0 4E HIGH HIGH [0101 000]0 50 The Interface Address alignment within the I2C-compatible address byte is shown in Figure 12 below: 30132712 FIGURE 12. Interface Address Sequence within the I2C-Compatible Frame www.ti.com 30 30132720 FIGURE 13. Block Command READ Access 30132726 FIGURE 14. Block Command WRITE Access 16.6.4 I2C-Compatible Bus Reset In cases where Master and Slave interfaces fall out of synchronization there are 2 processes which can reset the Slave and return it to a known state: • TIMEOUT: The device will automatically reset its interface and wait for a new START condition (by the Master) if SCL is driven LOW for duration longer than tOUT (see Electrical Characteristics Table), or SDA is driven LOW by this • 31 device for duration longer than tOUT. The TIMEOUT feature can be disabled by the user, see CGEN register functionality. When SDA is in HIGH state, the Master can issue START condition at any time. The START condition resets the Slave interface, and Slave expects to see Interface Address byte next. www.ti.com LMP92001 The transfer will consist of 24 bytes – 2 bytes per DACx register. The data WRITE transfers that terminate prematurely will result in update of registers whose 16-bit words were received completely. For example, if BLK0 WRITE access is attempted, and the transfer is terminated after 3 bytes, only DAC1 register will be updated. 16.6.3 Block Access Block Access functionality minimizes overhead in bus transfers involving larger data sets (more than 2 bytes). Internal register addresses 0xF0 through 0xF5 are interpreted by the interface as block commands. Accessing any of these addresses initiates a multi-byte transfer which can be as long as 34 data bytes. The byte length of the transfer is dictated by the block command itself. Examples of access to internal register at address 0xF0 is shown in Figure 13 and Figure 14. BLK0 command is issued meaning that all DACx registers accessed are accessed sequentially. LMP92001 17.0 Application Circuit Example 30132742 www.ti.com 32 LMP92001 18.0 Physical Dimensions inches (millimeters) unless otherwise noted LLP-54 Package NS Package Number SQA54A 33 www.ti.com LMP92001 Analog System Monitor and Controller Notes www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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