SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 D D D D D D D Highest Performance Fixed-Point Digital Signal Processor (DSP) SM320C6201 – 6.67-ns Instruction Cycle Time – 150-MHz Clock Rate – Eight 32-Bit Instructions/Cycle – 1 200 MIPS Highest Performance Fixed-Point Digital Signal Processor (DSP) SMJ320C6201B – 6.67-ns Instruction Cycle Time – 150-MHz Clock Rate – Eight 32-Bit Instructions/Cycle – 1 200 MIPS VelociTI Advanced Very Long Instruction Word (VLIW) ’C6200 CPU Core – Eight Independent Functional Units: – Six ALUs (32-/40-Bit) – Two 16-Bit Multipliers (32-Bit Results) – Load-Store Architecture With 32 32-Bit General-Purpose Registers – Instruction Packing Reduces Code Size – All Instructions Conditional Instruction Set Features – Byte-Addressable (8-, 16-, 32-Bit Data) – 32-Bit Address Range – 8-Bit Overflow Protection – Saturation – Bit-Field Extract, Set, Clear – Bit-Counting – Normalization 1M-Bit On-Chip SRAM – 512K-Bit Internal Program/Cache (16K 32-Bit Instructions) – 512K-Bit Dual-Access Internal Data (64K Bytes) Organized as a Single Block (’6201) – 512K-Bit Dual-Access Internal Data (64K Bytes) Organized as Two Blocks for Improved Concurrency (’6201B) 32-Bit External Memory Interface (EMIF) – Glueless Interface to Synchronous Memories: SDRAM and SBSRAM – Glueless Interface to Asynchronous Memories: SRAM and EPROM Four-Channel Bootloading Direct-Memory-Access (DMA) Controller with an Auxiliary Channel GLE and GLP PACKAGES ( BOTTOM VIEW ) AA Y W V U T R P N M L K J H G F E D C B A 3 1 2 D D D D D D D D D D 5 4 9 7 6 8 11 10 13 12 17 15 14 16 19 18 21 20 16-Bit Host-Port Interface (HPI) – Access to Entire Memory Map Two Multichannel Buffered Serial Ports (McBSPs) – Direct Interface to T1/E1, MVIP, SCSA Framers – ST-Bus-Switching Compatible – Up to 256 Channels Each – AC97-Compatible – Serial Peripheral Interface (SPI) Compatible (Motorola) Two 32-Bit General-Purpose Timers Flexible Phase-Locked Loop (PLL) Clock Generator IEEE-1149.1 (JTAG†) Boundary-Scan Compatible 429-Pin BGA Package (GLE Suffix) (’6201) 429-Pin BGA Package (GLP Suffix) (’6201B) CMOS Technology – 0.25-µm/5-Level Metal Process (’6201) – 0.18-µm/5-Level Metal Process (’6201B) 3.3-V I/Os, 2.5-V Internal (’6201) 3.3-V I/Os, 1.8-V Internal (’6201B) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. VelociTI is a trademark of Texas Instruments Incorporated. Motorola is a trademark of Motorola, Inc. † IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. Copyright 1998, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 1 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 Signal Descriptions SIGNAL NAME NO. TYPE† DESCRIPTION CLOCK/PLL CLKIN A14 I Clock Input CLKOUT1 Y6 O Clock output at full device speed CLKOUT2 V9 O Clock output at half of device speed CLKMODE1 B17 CLKMODE0 C17 PLLFREQ3 C13 PLLFREQ2 G11 PLLFREQ1 PLLV‡ F11 D12 PLLG‡ PLLF I Clock mode select • Selects whether the output clock frequency = input clock freq x4 or x1 PLL frequency range (3, 2, and 1) I • Selects one of three frequency ranges bounding the CLKOUT1 signal. • CLKOUT1 frequency determines the 3-bit value for the PLLFREQ pins. PLL analog VCC connection for the low-pass filter G10 A§ A§ C12 A§ PLL low-pass filter connection to external components and a bypass capacitor TMS K19 I TDO R12 O/Z TDI R13 I JTAG test port data in (features an internal pull-up) TCK M20 I JTAG test port clock TRST N18 I JTAG test port reset (features an internal pull-down) EMU1 R20 I/O/Z Emulation pin 1, pull-up with a dedicated 20-kΩ resistor EMU0 T18 I/O/Z Emulation pin 0, pull-up with a dedicated 20-kΩ resistor RESET J20 I Device reset NMI K21 I Nonmaskable interrupt • Edge-driven (rising edge) EXT_INT7 R16 I External interrupts • Edge-driven (rising edge) O Interrupt acknowledge for all active interrupts serviced by the CPU O Active interrupt identification number • Valid during IACK for all active interrupts (not just external) • Encoding order follows the interrupt interru t service fetch packet acket ordering I If high, selects little-endian byte/half-word addressing order within a word If low, selects big-endian addressing PLL analog GND connection for the low-pass filter JTAG EMULATION JTAG test port mode select (features an internal pull-up) JTAG test port data out CONTROL EXT_INT6 P20 EXT_INT5 R15 EXT_INT4 R18 IACK R11 INUM3 T19 INUM2 T20 INUM1 T14 INUM0 T16 LENDIAN G20 PD D19 O Power-down mode 3 (active if high) † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground ‡ PLLV and PLLG signals are not part of external voltage supply or ground. See the CLOCK/PLL documentation for information on how to connect those pins. § A = Analog Signal (PLL Filter) 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 Signal Descriptions (Continued) SIGNAL NAME NO. TYPE† DESCRIPTION HOST PORT INTERFACE (HPI) HINT H2 O/Z HCNTL1 J6 I Host control – selects between control, address or data registers HCNTL0 H6 I Host control – selects between control, address or data registers HHWIL E4 I Host halfword select – first or second halfword (not necessarily high or low order) HBE1 G6 I Host byte select within word or half-word HBE0 F6 I Host byte select within word or half-word HR/W D4 I Host read or write select HD15 D11 HD14 B11 HD13 A11 HD12 G9 HD11 D10 HD10 A10 HD9 C10 HD8 B9 HD7 F9 HD6 C9 HD5 A9 HD4 B8 HD3 D9 HD2 D8 HD1 B7 HD0 C7 I/O/Z Host interrupt (from DSP to host) data address and control) Host port data (used for transfer of data, HAS L6 I Host address strobe HCS C5 I Host chip select HDS1 C4 I Host data strobe 1 HDS2 K6 I Host data strobe 2 HRDY H3 O Host ready (from DSP to host) BOOTMODE4 B16 BOOTMODE3 G14 BOOT MODE BOOTMODE2 F15 BOOTMODE1 C18 I Boot mode BOOTMODE0 D17 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 3 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 Signal Descriptions (Continued) SIGNAL NAME NO. TYPE† DESCRIPTION EMIF – CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY CE3 Y5 O/Z CE2 V3 O/Z Memory space enables CE1 T6 O/Z • Enabled by bits 24 and 25 of the word address CE0 U2 O/Z • Only one asserted during any external data access BE3 R8 O/Z Byte enable control BE2 T3 O/Z • Decoded from the two lowest bits of the internal address BE1 T2 O/Z • Byte write enables for most types of memory BE0 R2 O/Z • Can be directly connected to SDRAM read and write mask signal (SDQM) EA21 L4 EA20 L3 EA19 J2 EMIF – ADDRESS EA18 J1 EA17 K1 EA16 K2 EA15 L2 EA14 L1 EA13 M1 EA12 M2 EA11 M6 EA10 N4 EA9 N1 EA8 N2 EA7 N6 EA6 P4 EA5 P3 EA4 P2 EA3 P1 O/Z External address (word address) EA2 P6 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground 4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 Signal Descriptions (Continued) SIGNAL NAME NO. TYPE† DESCRIPTION EMIF – DATA ED31 U18 ED30 U20 ED29 T15 ED28 V18 ED27 V17 ED26 V16 ED25 T12 ED24 W17 ED23 T13 ED22 Y17 ED21 T11 ED20 Y16 ED19 W15 ED18 V14 ED17 Y15 ED16 R9 ED15 Y14 ED14 V13 ED13 AA13 ED12 T10 ED11 Y13 ED10 W12 ED9 Y12 ED8 Y11 ED7 V10 ED6 AA10 ED5 Y10 ED4 W10 I/O/Z External data ED3 Y9 ED2 AA9 ED1 Y8 ED0 W9 ARE R7 O/Z Asynchronous memory read enable AOE T7 O/Z Asynchronous memory output enable AWE V5 O/Z Asynchronous memory write enable EMIF – ASYNCHRONOUS MEMORY CONTROL ARDY R4 I Asynchronous memory ready input † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 5 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 Signal Descriptions (Continued) SIGNAL NAME NO. TYPE† DESCRIPTION EMIF – SYNCHRONOUS BURST SRAM CONTROL SSADS V8 O/Z SBSRAM address strobe SSOE W7 O/Z SBSRAM output enable SSWE Y7 O/Z SBSRAM write enable SSCLK AA8 O/Z SBSRAM clock SDA10 V7 O/Z SDRAM address 10 (separate for deactivate command) SDRAS V6 O/Z SDRAM row address strobe SDCAS W5 O/Z SDRAM column address strobe SDWE T8 O/Z SDRAM write enable SDCLK T9 O/Z SDRAM clock EMIF – SYNCHRONOUS DRAM CONTROL EMIF – BUS ARBITRATION HOLD R6 I Hold request from the host HOLDA B15 O Hold request acknowledge to the host TIMERS TOUT1 G2 O/Z TINP1 K3 I TOUT0 M18 O/Z TINP0 J18 I Timer 1 or general-purpose output Timer 1 or general-purpose input Timer 0 or general-purpose output Timer 0 or general-purpose input DMA ACTION COMPLETE DMAC3 E18 DMAC2 F19 DMAC1 E20 DMAC0 G16 O DMA action complete MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1) CLKS1 F4 I CLKR1 H4 I/O/Z External clock source (as opposed to internal) Receive clock CLKX1 J4 I/O/Z Transmit clock DR1 E2 I Receive data DX1 G4 O/Z Transmit data FSR1 F3 I/O/Z Receive frame sync FSX1 F2 I/O/Z Transmit frame sync † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground 6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 Signal Descriptions (Continued) SIGNAL NAME NO. TYPE† DESCRIPTION MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0) CLKS0 K18 I External clock source (as opposed to internal) CLKR0 L21 I/O/Z Receive clock CLKX0 K20 I/O/Z Transmit clock DR0 J21 I Receive data DX0 M21 O/Z Transmit data FSR0 P16 I/O/Z Receive frame sync FSX0 N16 I/O/Z Transmit frame sync RESERVED FOR TEST RSV0 N21 I Reserved for testing, pull-up with a dedicated 20-kΩ resistor RSV1 K16 I Reserved for testing, pull-up with a dedicated 20-kΩ resistor RSV2 B13 I Reserved for testing, pull-up with a dedicated 20-kΩ resistor RSV3 B14 I Reserved for testing, pull-up with a dedicated 20-kΩ resistor RSV4 F13 I Reserved for testing, pull-down with a dedicated 20-kΩ resistor RSV5 C15 O Reserved (leave unconnected, do not connect to power or ground) RSV6 F7 I RSV7 D7 I RSV8 B5 I Reserved for testing, pull-up with a dedicated 20-kW resistor Reserved for testing, pull-up with a dedicated 20-kW resistor Reserved for testing, pull-up with a dedicated 20-kW resistor SUPPLY VOLTAGE PINS C14 C8 E19 E3 H11 H13 H9 J10 J12 J14 DVDD J19 S 3.3-V supply voltage J3 J8 K11 K13 K15 K7 K9 L10 L12 L14 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 7 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 Signal Descriptions (Continued) SIGNAL NAME NO. TYPE† DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED) L8 M11 M13 M15 M7 M9 N10 N12 N14 DVDD N19 S 3.3-V supply voltage S 2.5-V supply y voltage g for ’C6201 1.8-V supply voltage for ’C6201B N3 N8 P11 P13 P9 U19 U3 W14 W8 A12 A13 B10 B12 B6 D15 D16 F10 F14 CVDD F8 G13 G7 G8 K4 M3 M4 A3 A5 A7 A16 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 Signal Descriptions (Continued) SIGNAL NAME NO. TYPE† DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED) A18 AA4 AA6 AA15 AA17 AA19 B2 B4 B19 C1 C3 C20 D2 D21 E1 E6 CVDD E8 E10 S 2.5-V supply y voltage g for ’C6201 1.8-V supply voltage for ’C6201B E12 E14 E16 F5 F17 F21 G1 H5 H17 K5 K17 M5 M17 P5 P17 R21 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 9 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 Signal Descriptions (Continued) SIGNAL NAME NO. TYPE† DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED) T1 T5 T17 U6 U8 U10 U12 U14 U16 U21 V1 V20 W2 W19 W21 Y3 Y18 Y20 CVDD AA11 S 2 5 V supply l voltage lt ffor ’C6201 2.5-V 1.8-V su ly voltage for ’C6201B C6201B 1 8-V supply AA12 F20 G18 H16 H18 L18 L19 L20 N20 P18 P19 R10 R14 U4 V11 V12 V15 W13 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 Signal Descriptions (Continued) SIGNAL NAME NO. TYPE† DESCRIPTION GROUND PINS C11 C16 C6 D5 G3 H10 H12 H14 H7 H8 J11 J13 J7 J9 K8 L7 L9 M8 N7 VSS R3 GND Ground pins A4 A6 A8 A15 A17 A19 AA3 AA5 AA7 AA14 AA16 AA18 B3 B18 B20 C2 C19 C21 D1 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 11 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 Signal Descriptions (Continued) SIGNAL NAME NO. TYPE† DESCRIPTION GROUND PINS (CONTINUED) D20 E5 E7 E9 E11 E13 E15 E17 E21 F1 G5 G17 G21 H1 J5 J17 L5 VSS L17 GND Ground pins N5 N17 P21 R1 R5 R17 T21 U1 U5 U7 U9 U11 U13 U15 U17 V2 V21 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground 12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 Signal Descriptions (Continued) SIGNAL NAME NO. TYPE† DESCRIPTION GROUND PINS (CONTINUED) W1 W3 W20 Y2 Y4 Y19 F18 G19 H15 J15 J16 K10 K12 K14 L11 L13 L15 VSS M10 GND Ground pins M12 M14 N11 N13 N15 N9 P10 P12 P14 P15 P7 P8 R19 T4 W11 W16 W6 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 13 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 Signal Descriptions (Continued) SIGNAL NAME NO. TYPE† DESCRIPTION REMAINING UNCONNECTED PINS D13 D14 D18 D3 D6 F12 F16 G12 G15 NC H19 Unconnected pins H20 H21 L16 M16 M19 V19 V4 W18 W4 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground 14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 functional block diagram Timers Interrupt Selector McBSPs HPI Control DMA Control EMIF Control Peripheral Bus Controller Host-Port Interface DMA Controller Data Memory Data Memory Controller PLL CPU EMIF Power Down Program Memory Controller BootConfig. Program Memory/Cache POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 15 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 signal groups CLKIN CLKOUT2 CLKOUT1 CLKMODE1 CLKMODE0 PLLFREQ3 PLLFREQ2 PLLFREQ1 PLLV PLLG PLLF Boot Mode BOOTMODE4 BOOTMODE3 BOOTMODE2 BOOTMODE1 BOOTMODE0 Reset and Interrupts RESET NMI EXT_INT7 EXT_INT6 EXT_INT5 EXT_INT4 IACK INUM3 INUM2 INUM1 INUM0 Little ENDIAN Big ENDIAN LENDIAN Clock/PLL TMS TDO TDI TCK TRST EMU1 EMU0 JTAG Emulation RSV9 RSV8 RSV7 RSV6 RSV5 RSV4 RSV3 RSV2 RSV1 RSV0 DMA Status DMAC3 DMAC2 DMAC1 DMAC0 Power-Down Status PD Reserved Control/Status HD[15:0] HCNTL0 HCNTL1 16 Data HPI (Host-Port Interface) Register Select Control HHWIL HBE1 HBE0 Half-Word/Byte Select Figure 1. CPU and Peripheral Signals 16 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 HAS HR/W HCS HDS1 HDS2 HRDY HINT SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 signal groups (continued) 32 ED[31:0] Data Asynchronous Memory Control CE3 CE2 CE1 CE0 EA[21:2] BE3 BE2 BE1 BE0 HOLD HOLDA ARE AOE AWE ARDY Memory Map Space Select 20 Word Address SBSRAM Control SSADS SSOE SSWE SSCLK SDRAM Control SDA10 SDRAS SDCAS SDWE SDCLK Byte Enables HOLD/ HOLDA EMIF (External Memory Interface) TOUT1 Timer 1 Timer 0 TOUT0 TINP0 TINP1 Timers McBSP1 McBSP0 CLKX1 FSX1 DX1 Transmit Transmit CLKX0 FSX0 DX0 CLKR1 FSR1 DR1 Receive Receive CLKR0 FSR0 DR0 CLKS1 Clock Clock CLKS0 McBSPs (Multichannel Buffered Serial Ports) Figure 2. Peripheral Signals POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 17 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 CPU description The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute packets are a key memory-saving feature, distinguishing the ’C6200† CPU from other VLIW architectures. The CPU features two sets of functional units. Each set contains four units and a register file. One set contains functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files each contain 16 32-bit registers for a total of 32 general-purpose registers. The two sets of functional units, along with two register files, compose sides A and B of the CPU (see Figure 3 and Figure 4). The four functional units on each side of the CPU can freely share the 16 registers belonging to that side. Additionally, each side features a single data bus connected to all the registers on the other side, by which the two sets of functional units can access data from the register files on the opposite side. While register access by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle, register access using the register file across the CPU supports one read and one write per cycle. Another key feature of the ’C6200 CPU is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data transfers between the register files and the memory. The data address driven by the .D units allows data addresses generated from one register file to be used to load or store data to or from the other register file. The ’C6200 CPU supports a variety of indirect addressing modes using either linear- or circular-addressing modes with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some registers, however, are singled out to support specific addressing or to hold the condition for conditional instructions (if the condition is not automatically “true”). The two .M functional units are dedicated for multiplies. The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle. The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the fetch packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store instructions are byte-, half-word, or word-addressable. † Where unique device characteristics are specified, SM320C6201 and SMJ320C6201B identifiers are used. For generic characteristics, no identifiers are needed, ’C62xx is used, or ’C6200 is used. 18 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 CPU description (continued) Program Memory 32-Bit Address 256-Bit Data ÁÁ ÁÁ ÁÁ Á Á Á Á Á External Memory Interface Á Á Á ÁÁ Á ’C6200 CPU Program Fetch Control Registers Instruction Dispatch Instruction Decode Data Path A Data Path B Register File A Register File B Control Logic ÁÁ Á Á ÁÁ ÁÁ ÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ ÁÁ ÁÁ ÁÁ ÁÁ ÁÁ Á Á Test .L1 .S1 .M1 .D1 .D2 .M2 .S2 Data Memory 32-Bit Address 8-, 16-, 32-Bit Data .L2 Emulation Interrupts Additional Peripherals: Timers, Serial Ports, etc. Figure 3. SM320C6200 CPU Block Diagram POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 19 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 CPU description (continued) ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁ ÁÁÁÁ ÁÁ ÁÁÁ ÁÁÁÁ ÁÁ ÁÁÁÁ Á ÁÁ ÁÁÁÁ ÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ Á ÁÁÁÁ ÁÁÁÁ ÁÁ ÁÁ ÁÁÁÁ ÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁ ÁÁ ÁÁÁÁ ÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁ ÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁ Á ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁ ÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁ Á ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁ ÁÁÁÁ src1 .L1 src2 dst long dst long src ST1 Data Path A long src long dst dst .S1 src1 8 8 32 8 Register File A (A0–A15) src2 .M1 dst src1 src2 LD1 DA1 DA2 .D1 .D2 dst src1 src2 2X 1X src2 src1 dst LD2 src2 .M2 src1 dst src2 Data Path B src1 dst long dst long src Register File B (B0–B15) .S2 ST2 long src long dst dst .L2 src2 8 32 8 src1 ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ Á 8 Figure 4. SM320C6200 CPU Data Paths 20 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Control Register File SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 clock PLL All of the ’C62xx clocks are generated from a single source through the CLKIN pin. This source clock either drives the PLL, which generates the internal CPU clock, or bypasses the PLL to become the CPU clock. To use the PLL to generate the CPU clock, the filter circuit shown in Figure 5 must be properly designed. Note that for ’C6201, the EMI filter must be powered by the core voltage (2.5 V), and for ’C6201B, it must be powered by the I/O voltage (3.3 V). To configure the ’C62xx PLL clock for proper operation, see Figure 5 and Table 1. To minimize the clock jitter, a single clean power supply should power both the ’C62x device and the external clock oscillator circuit. The minimum CLKIN rise and fall times should also be observed. See the input and output clocks section for input clock timing requirements. ’C6201 CLKOUT1 Frequency Range 40 – 200 MHz – 0 1 0 – ’C6201B CLKOUT1 Frequency Range 130 – 233 MHz ’C6201 CLKOUT1 Frequency Range 35 – 160 MHz – 0 0 1 – ’C6201B CLKOUT1 Frequency Range 65 – 200 MHz ’C6201 CLKOUT1 Frequency Range 25 – 135 MHz – 0 0 0 – ’C6201B CLKOUT1 Frequency Range 50 – 140 MHz 1 IN PLLF R1 EMIF CLKOUT1 CLKOUT 2 GND ’320C6201/C6201B 10 µF 0.1 µF (Bypass) PLLG C1 C2 CLKIN CLKMODE0 CLKMODE1 EMI Filter PLLV PLLFREQ3 PLLFREQ2 PLLFREQ1 3 OUT 3.3 V 2.5 V 1 1 – MULT × 4 CLKOUT2 SSCLK SDCLK f(CLKOUT) = f(CLKIN) × 4 0 1 – Reserved 1 0 – Reserved 0 0 – MULT × 1 f(CLKOUT) = f(CLKIN) NOTES: A. For the ’C6201 CLKMODE x4, values for C1, C2, and R1 depend on CLKIN and CLKOUT frequencies. For the ’C6201B CLKMODE x4, values for C1, C2, and R1 are fixed and apply to all valid frequency ranges of CLKIN and CLKOUT. B. For CLKMODE x1, the PLL is bypassed and all six external PLL components can be removed. For this case, the PLLV terminal has to be connected to a clean supply and the PLLG and PLLF terminals should be tied together. C. Due to overlap of frequency ranges when choosing the PLLFREQ, more than one frequency range can contain the CLKOUT1 frequency. Choose the lowest frequency range that includes the desired frequency. For example, CLKOUT1 = 133 MHz, a PLLFREQ value of 000b should be used for both the ’C6201 and the ’C6201B. For CLKOUT1 = 200 MHz, PLLFREQ should be set to 010b for the ’C6201 or 001b for the ’C6201B. PLLFREQ values other than 000b, 001b, and 010b are reserved. D. EMI filter manufacturer TDK part number ACF451832-153-T E. For the ’C6201B, the 3.3-V supply for the EMI filter (and PLLV) must be from the same 3.3-V power plane supplying the I/O voltage, DVDD. Figure 5. PLL Block Diagram POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 21 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 clock PLL (continued) Table 1. SM320C6201 PLL Component Selection Table† CYCLE TIME (ns) CLKMODE CLKIN (MHz) CLKOUT1 (MHz) R1 (Ω) C1 (µF) C2 (pF) EMI FILTER PART NO.‡ TYPICAL LOCK TIME (µs)§ 5 x4 50 200 16.9 0.15 2 700 TDK #153 59 5.5 x4 45.5 181.8 13.7 0.18 3 900 TDK #153 49 6 x4 41.6 166.7 17.4 0.15 3 300 TDK #153 68 6.5 x4 38.5 153.8 16.2 0.18 3 900 TDK #153 70 7 x4 35.7 142.9 15 0.22 3 900 TDK #153 72 7.5 x4 33.3 133.3 16.2 0.22 3 900 TDK #153 84 8 x4 31.3 125 14 0.27 4 700 TDK #153 77 8.5 x4 29.4 117.7 11.8 0.33 6 800 TDK #153 67 9 x4 27.7 111.1 11 0.39 6 800 TDK #153 68 9.5 x4 26.3 105.3 10.5 0.39 8 200 TDK #153 65 10 x4 25 100 10 0.47 8 200 TDK #153 68 † For CLKMODE x1, the PLL is bypassed and all six external PLL components can be removed. For this case, the PLLV terminal has to be connected to a clean supply and the PLLG and PLLF terminals should be tied together. ‡ Full EMI filter part number : ACF 451832-153-T § Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For example, if the typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs. Table 2. SM320C6201B PLL Component Selection Table† CLKMODE R1 (Ω) C1 (nF) C2 (pF) EMI FILTER PART NO.‡ TYPICAL LOCK TIME (µs)§ x4 60.4 27 560 TDK #153 75 † For CLKMODE x1, the PLL is bypassed and all six external PLL components can be removed. For this case, the PLLV terminal has to be connected to a clean supply and the PLLG and PLLF terminals should be tied together. ‡ Full EMI filter part number : ACF 451832-153-T § Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For example, if the typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs. power supply sequencing For the ’C6201 device, the 2.5-V supply powers the core and the 3.3-V supply powers the I/O buffers. For the ’C6201B device, the 1.8-V supply powers the core and the 3.3-V supply powers the I/O buffers. The core supply should be powered up first, or at the same time as the I/O buffers. This is to ensure that the I/O buffers have valid inputs from the core before the output buffers are powered up, thus preventing bus contention with other chips on the board. 22 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 development support Texas Instruments (TI) offers an extensive line of development tools for the ’C6200 generation of DSPs, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The following products support development of ’C6200-based applications: Software Development Tools: Assembly optimizer Assembler/Linker Simulator Optimizing ANSI C compiler Application algorithms C/Assembly debugger and code profiler Hardware Development Tools: Extended development system (XDS) emulator (supports ’C6200 multiprocessor system debug) EVM (Evaluation Module) The TMS320 DSP Development Support Reference Guide (SPRU011) contains information about development-support products for all TMS320 family member devices, including documentation. See this document for further information on TMS320 documentation or any TMS320 support products from Texas Instruments. An additional document, the TMS320 Third-Party Support Reference Guide (SPRU052), contains information about TMS320-related products from other companies in the industry. To receive TMS320 literature, contact the Literature Response Center at 800/477-8924. See Table 3 for a complete listing of development-support tools for the ’C6200. For information on pricing and availability, contact the nearest TI field sales office or authorized distributor. Table 3. TMS320C6xx Development-Support Tools DEVELOPMENT TOOL PLATFORM PART NUMBER Software C Compiler/Assembler/Linker/Assembly Optimizer Win32 TMDX3246855-07 C Compiler/Assembler/Linker/Assembly Optimizer SPARC Solaris TMDX324655-07 Win32 TMDS3246851-07 SPARC Solaris TMDS3246551-07 Win32, Windows NT TMDX324016X-07 Simulator Simulator XDS510 Debugger/Emulation Software Hardware XDS510 Emulator† PC XDS510WS Emulator‡ SCSI TMDS00510 TMDS00510WS Software/Hardware EVM Evaluation Kit PC/Win95/Windows NT TMDX3260A6201 EVM Evaluation Kit (including TMDX3246855–07) PC/Win95/Windows NT TMDX326006201 † Includes XDS510 board and JTAG emulation cable. TMDX324016X-07 C-source Debugger/Emulation software is not included. ‡ Includes XDS510WS box, SCSI cable, power supply, and JTAG emulation cable. TI, XDS, XDS510, and XDS510WS are trademarks of Texas Instruments Incorporated. Win32 and Windows NT are trademarks of Microsoft Corporation. SPARC is a trademark of SPARC International, Inc. Solaris is a trademark of Sun Microsystems, Inc. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 23 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 device and development-support tool nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320 devices and support tools. Each TMS320 member has one of three prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX / TMDX) through fully qualified production devices/tools (TMS / TMDS). This development flow follows. Device development evolutionary flow: TMX Experimental device that is not necessarily representative of the final device’s electrical specifications TMP Final silicon die that conforms to the device’s electrical specifications but has not completed quality and reliability verification TMS Fully qualified production device SMX Experimental device that is not necessarily representative of the final device’s electrical specifications, 25°C tested, military/industrial ceramic dimpled Ball Grid Array package SM Fully TI-qualified production device; offered in extended temperature ranges: –40°C to +90°C (A range), –55°C to +105°C (S range), and –55°C to +125°C (M range); in ceramic dimpled BGA package SMJ Fully SMD-qualified production device, –55°C to +125°C temperature range, in the ceramic dimpled Ball Grid Array package Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully qualified development-support product TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer: “Developmental product is intended for internal evaluation purposes.” TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI’s standard warranty applies. Predictions show that prototype devices ( TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, GGP, GJC, or GJL) and the device speed range in megahertz (for example, -200 is 200 MHz). Figure 6 provides a legend for reading the complete device name for any TMS320 family member. 24 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 device and development-support tool nomenclature (continued) SMJ 320 C 6201 PREFIX TMX = Experimental device TMP = Prototype device TMS = Qualified device SMX = Prototype device SMJ = High Rel (Mil SMD) SM = High Rel (non-SMD) SMQ= Plastic (Mil SMD) DEVICE SPEED RANGE –150 MHz –167 MHz –200 MHz –233 MHz –250 MHz PACKAGE TYPE† N = Plastic DIP J = Ceramic DIP JD = Ceramic DIP side-brazed GB = Ceramic PGA FZ = Ceramic CC FN = Plastic leaded CC FD = Ceramic leadless CC PJ = 100-pin plastic EIAJ QFP PQ = 132-pin plastic bumpered QFP PZ = 100-pin plastic TQFP PBK = 128-pin plastic TQFP PGE = 144-pin plastic TQFP GFN = 272-ball plastic BGA GGU = 144-ball plastic BGA GGP = 352-ball plastic BGA GJC = 352-ball plastic BGA GJL = 352-ball plastic BGA GJL = 452-ball plastic BGA GLE = 429-ball ceramic BGA GLP = 429-ball ceramic BGA DEVICE FAMILY 320 = TMS320 family TECHNOLOGY C = CMOS E = CMOS EPROM F = CMOS Flash EEPROM DEVICE ’1x DSP: 10 14 15 GGP –200 16 17 ’2x DSP: 25 26 ’2xx DSP: 203 204 206 209 240 ’3x DSP: 30 31 32 ’4x DSP: 40 44 ’5x DSP: 50 51 52 53 56 57 541 542 543 545 546 548 ’54x DSP: ’6x DSP: 6201 6201B 6202 6211 6701 † DIP PGA CC QFP TQFP BGA = = = = = = Dual-In-Line Package Pin Grid Array Chip Carrier Quad Flat Package Thin Quad Flat Package Ball Grid Array Figure 6. TMS320 Device Nomenclature (Including SM320C6201/SMJ320C6201B) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 25 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 documentation support Extensive documentation supports all TMS320 family generations of devices from product announcement through applications development. The types of documentation available include: data sheets, such as this document, with design specifications; complete user’s reference guides for all devices; technical briefs; development-support tools; and hardware and software applications. The following is a brief, descriptive list of support documentation specific to the ’C6x devices: The TMS320C62x/C67x CPU and Instruction Set Reference Guide (literature number SPRU189) describes the ’C62x/C67x CPU architecture, instruction set, pipeline, and associated interrupts. The TMS320C6201/C6701 Peripherals Reference Guide (literature number SPRU190) describes functionally the peripherals available on ’C6x devices, such as the external memory interface (EMIF), host-port interface (HPI), multichannel buffered serial ports (McBSPs), direct-memory-access (DMA) controller, clocking and phase-locked loop (PLL); and power-down modes. This guide also includes information on internal data and program memories. The TMS320C62x/C67x Programmer’s Guide (literature number SPRU198) describes ways to optimize C and assembly code for ’C6x devices and includes application program examples. The TMS320C6x Optimizing C Compiler User’s Guide (literature number SPRU187) describes the ’C6x C compiler and the assembly optimizer, explaining that the C compiler accepts ANSI standard C source code, and produces assembly language source code for the ’C6x generation devices, and that the assembly optimizer helps to optimize the programmer’s assembly code. The TMS320C6x C Source Debugger User’s Guide (literature number SPRU188) describes how to invoke the ’C6x simulator and emulator versions of the C source debugger interface and discusses various aspects of the debugger, including: command entry, code execution, data management, breakpoints, profiling, and analysis. The TMS320C6x Peripheral Support Library Programmer’s Reference (literature number SPRU273) describes the contents of the ’C6x peripheral support library of functions and macros. It lists functions and macros both by header file and alphabetically, provides a complete description of each, and gives code examples to show how they are used. The TMS320C6x Evaluation Module Reference Guide (literature number SPRU269) provides instructions for installing and operating the ’C6x evaluation module. It also includes support software documentation, application programming interfaces, and technical reference material. The TMS320C62x/C67x Technical Brief (literature number SPRU197) gives an introduction to the ’C62x/C67x devices, associated development tools, and third-party support. A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support DSP research and education. The TMS320 newsletter, Details on Signal Processing, is published quarterly and distributed to update TMS320 customers on product information. The TMS320 DSP bulletin board service (BBS) provides access to information pertaining to the TMS320 family, including documentation, source code, and object code for many DSP algorithms and utilities. The BBS can be reached at 281/274-2323. Information regarding TI DSP products is also available on the Worldwide Web at http://www.ti.com uniform resource locator (URL). 26 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 absolute maximum ratings over operating case temperature range (unless otherwise noted)† Supply voltage range, CVDD (see Note 1) for ’C6201 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 3 V Supply voltage range, CVDD (see Note 1) for ’C6201B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 2.3 V Supply voltage range, DVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V Operating case temperature range, TC (S temperature) . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55_C to 105_C (M temperature) . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55_C to 125_C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55_C to 150_C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS. recommended operating conditions ’C6201 ’C6201B MIN NOM MAX MIN NOM MAX UNIT CVDD Supply voltage 2.38 2.50 2.62 1.71 1.8 1.89 V DVDD Supply voltage 3.14 3.30 3.46 3.14 3.30 3.46 V VSS VIH Supply ground 0 0 0 0 0 0 V VIL IOH Low-level input voltage 0.8 0.8 V High-level output current –12 –12 mA IOL TC Low-level output current 12 12 mA 125 _C High-level input voltage 2.0 Operating case temperature –55 2.0 105 –55 V PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 27 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 electrical characteristics over recommended ranges of supply voltage and operating case temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VOH High-level output voltage DVDD = MIN, IOH = MAX VOL Low-level output voltage DVDD = MIN, IOL = MAX II IOZ Input current† ’C6201 MIN TYP ’C6201B MAX 2.4 MIN TYP MAX 2.4 UNIT V 0.6 0.6 V ±10 ±10 uA ±10 ±10 uA Off-state output current VI = VSS to DVDD VO = DVDD or 0 V IDD2V Supply current, CPU + CPU memory access‡ CVDD = NOM, CPU clock = 167 MHz 1860 780 mA IDD2V Supply current, peripherals§ CVDD = NOM, CPU clock = 167 MHz 200 140 mA IDD3V Supply current, I/O pins¶ DVDD = NOM, CPU clock = 167 MHz 100 100 mA Ci Input capacitance Co Output capacitance † TMS and TDI are not included due to internal pullups. TRST is not included due to internal pulldown. ‡ Measured with average CPU activity: 50% of time: 8 instructions per cycle, 32-bit DMEM access per cycle 50% of time: 2 instructions per cycle, 16-bit DMEM access per cycle § Measured with average peripheral activity: 50% of time: Timers at max rate McBSPs at E1 rate DMA burst transfer between DMEM and SDRAM 50% of time: Timers at max rate McBSPs at E1 rate DMA servicing McBSPs ¶ Measured with average I/O activity (30-pF load, SDCLK on): 25% of time: Reads from external SDRAM 25% of time: Writes to external SDRAM 50% of time: No activity PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 28 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 10 10 pF 10 10 pF SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION IOL Tester Pin Electronics 50 Ω Vref Output Under Test CT = 30 pF† IOH † Typical distributed load circuit capacitance Figure 7. TTL-Level Outputs signal transition levels All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels. Vref = 1.5 V Figure 8. Input and Output Voltage Reference Levels for AC Timing Measurements POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 29 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 INPUT AND OUTPUT CLOCKS timing requirements for CLKIN† (see Figure 9) (’C6201) ’C6201-150 CLKMODE = x4 NO. MIN 1 2 3 4 MAX CLKMODE = x1 MIN UNIT MAX tc(CLKIN) tw(CLKINH) Cycle time, CLKIN 24* 6.67 ns Pulse duration, CLKIN high 9.8* 2.7* ns tw(CLKINL) tt(CLKIN) Pulse duration, CLKIN low 9.8* 2.7* Transition time, CLKIN 5* ns 0.6* ns † The reference points for the rise and fall transitions are measured at 20% and 80%, respectively, of VIH. *This parameter is not production tested. timing requirements for CLKIN (see Figure 9) (’C6201B) ’C6201B-150 CLKMODE = x4 NO. MIN 1 2 3 4 MAX ’C6201B-200 CLKMODE = x1 CLKMODE = x4 CLKMODE = x1 MIN MIN MIN MAX MAX MAX tc(CLKIN) tw(CLKINH) Cycle time, CLKIN 24 6.67 20 5 ns Pulse duration, CLKIN high 9.8 2.7 8 2.25 ns tw(CLKINL) tt(CLKIN) Pulse duration, CLKIN low 9.8 2.7 Transition time, CLKIN 5 1 8 2.25 0.6 5 4 2 CLKIN 3 4 Figure 9. CLKIN Timings PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 30 UNIT POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 ns 0.6 ns SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 INPUT AND OUTPUT CLOCKS (CONTINUED) switching characteristics for CLKOUT1†‡ (see Figure 10) (’C6201) ’C6201-150 NO. 1 2 3 PARAMETER CLKMODE = x4 UNIT CLKMODE = x1 MIN MAX MIN MAX P – 0.7* P + 0.7* P – 0.7* P + 0.7* ns tc(CKO1) tw(CKO1H) Cycle time, CLKOUT1 Pulse duration, CLKOUT1 high (P/2) – 0.5* (P/2 )+ 0.5* PH – 0.5* PH + 0.5* ns tw(CKO1L) tt(CKO1) Pulse duration, CLKOUT1 low (P/2) – 0.5* (P/2 )+ 0.5* PL – 0.5* PL + 0.5* ns 0.6* ns 4 Transition time, CLKOUT1 † PH is the high period of CLKOUT1 in ns and PL is the low period of CLKOUT1 in ns. ‡ P = 1/CPU clock frequency in nanoseconds (ns). *This parameter is not production tested. 0.6* switching characteristics for CLKOUT1†‡ (see Figure 10) (’C6201B) ’C6201B-150 ’C6201B-200 NO NO. PARAMETER CLKMODE = x4 MIN 1 2 3 4 tc(CKO1) tw(CKO1H) Cycle time, CLKOUT1 tw(CKO1L) tt(CKO1) UNIT CLKMODE = x1 MAX MIN MAX P – 0.7 P + 0.7 P – 0.7 P + 0.7 ns Pulse duration, CLKOUT1 high (P/2) – 0.5 (P/2 ) + 0.5 PH – 0.5 PH + 0.5 ns Pulse duration, CLKOUT1 low (P/2) – 0.5 (P/2 ) + 0.5 PL – 0.5 PL + 0.5 ns 0.6 ns Transition time, CLKOUT1 0.6 † PH is the high period of CLKOUT1 in ns and PL is the low period of CLKOUT1 in ns. ‡ P = 1/CPU clock frequency in nanoseconds (ns). 1 4 2 CLKOUT1 3 4 Figure 10. CLKOUT1 Timings PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 31 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 INPUT AND OUTPUT CLOCKS (CONTINUED) switching characteristics for CLKOUT2† (see Figure 11) NO. 1 2 3 ’C6201B-150 ’C6201B-200 ’C6201-150 PARAMETER UNIT MIN MAX MIN MAX tc(CKO2) tw(CKO2H) Cycle time, CLKOUT2 2P – 0.7* 2P + 0.7* 2P – 0.7 2P + 0.7 ns Pulse duration, CLKOUT2 high P – 0.7* P + 0.7* P – 0.7 P + 0.7 ns tw(CKO2L) tt(CKO2) Pulse duration, CLKOUT2 low P – 0.7* P + 0.7* P – 0.7 P + 0.7 ns 0.6 ns 4 Transition time, CLKOUT2 † P = 1/CPU clock frequency in ns. *This parameter is not production tested. 0.6* 1 4 2 CLKOUT2 3 4 Figure 11. CLKOUT2 Timings SDCLK, SSCLK timing parameters SDCLK timing parameters are the same as CLKOUT2 parameters. SSCLK timing parameters are the same as CLKOUT1 or CLKOUT2 parameters, depending on SSCLK configuration. switching characteristics for the relation of SSCLK, SDCLK, and CLKOUT2 to CLKOUT1 (see Figure 12)† NO. ’C6201-150 PARAMETER MIN MAX MIN MAX UNIT 1 td(CKO1-SSCLK) Delay time, CLKOUT1 edge to SSCLK edge –1.2* 1.6* (P/2) + 0.2 (P/2) + 4.2 ns 2 td(CKO1-SSCLK1/2) Delay time, CLKOUT1 edge to SSCLK edge (1/2 clock rate) –1.0* 2.4* (P/2) – 1 (P/2) + 2.4 ns 3 td(CKO1-CKO2) Delay time, CLKOUT1 edge to CLKOUT2 edge –1.0* 2.4* (P/2) – 1 (P/2) + 2.4 ns –1.0* 2.4* (P/2) – 1 (P/2) + 2.4 ns 4 td(CKO1-SDCLK) Delay time, CLKOUT1 edge to SDCLK edge † P = 1/CPU clock frequency in ns. *This parameter is not production tested. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 32 ’C6201B-150 ’C6201B-200 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 INPUT AND OUTPUT CLOCKS (CONTINUED) CLKOUT1 1 SSCLK 2 SSCLK (1/2rate) 3 CLKOUT2 4 SDCLK Figure 12. Relation of CLKOUT2, SDCLK, and SSCLK to CLKOUT1 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 33 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 ASYNCHRONOUS MEMORY TIMING timing requirements for asynchronous memory cycles† (see Figure 13 and Figure 14) ’C6201-150 NO NO. MIN 6 tsu(EDV-CKO1H) 7 th(CKO1H-EDV) tsu(ARDY-CKO1H) 10 Setup time, read EDx valid before CLKOUT1 high MAX 5.0 ’C6201B-150 MIN MAX ’C6201B-200 MIN MAX UNIT 5.0 4.0 ns Hold time, read EDx valid after CLKOUT1 high 0 0 0.8 ns Setup time, ARDY valid before CLKOUT1 high 5.0* 5.0 4.0 ns 11 th(CKO1H-ARDY) Hold time, ARDY valid after CLKOUT1 high 0* 0 0.8 ns † To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input. *This parameter is not production tested. switching characteristics for asynchronous memory cycles‡ (see Figure 13 and Figure 14) NO NO. 1 2 3 4 5 8 9 12 13 ’C6201-150 PARAMETER td(CKO1H-CEV) td(CKO1H-BEV) Delay time, CLKOUT1 high to CEx valid td(CKO1H-BEIV) td(CKO1H-EAV) Delay time, CLKOUT1 high to BEx invalid td(CKO1H-EAIV) td(CKO1H-AOEV) Delay time, CLKOUT1 high to BEx valid ’C6201B-200 UNIT MIN MAX MIN MAX MIN MAX –1.0 5.0 –1.0 5.0 –0.2 4.0 ns –1.0 5.0 –1.0 5.0 –0.2 4.0 ns –1.0* 5.0* –1.0 5.0 –0.2 4.0 ns –1.0 5.0 –1.0 5.0 –0.2 4.0 ns Delay time, CLKOUT1 high to EAx invalid –1.0* 5.0* –1.0 5.0 –0.2 4.0 ns Delay time, CLKOUT1 high to AOE valid –1.0 5.0 –1.0 5.0 –0.2 4.0 ns td(CKO1H-AREV) td(CKO1H-EDV) Delay time, CLKOUT1 high to ARE valid –1.0 5.0 –1.0 5.0 –0.2 4.0 ns 4.0 ns td(CKO1H-EDIV) td(CKO1H-AWEV) Delay time, CLKOUT1 high to EDx invalid Delay time, CLKOUT1 high to EAx valid Delay time, CLKOUT1 high to EDx valid 14 Delay time, CLKOUT1 high to AWE valid ‡ The minimum delay is also the minimum output hold after CLKOUT1 high. *This parameter is not production tested. 5.0 –1.0* –1.0 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 34 ’C6201B-150 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 5.0 –1.0 5.0 –1.0 –0.2 5.0 –0.2 ns 4.0 ns SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 ASYNCHRONOUS MEMORY TIMING (CONTINUED) Setup = 2 Not ready = 2 Strobe = 5 HOLD = 1 CLKOUT1 1 1 2 3 4 5 CEx BE[3:0] EA[21:2] 7 6 ED[31:0] 8 8 AOE 9 9 ARE AWE 11 11 10 10 ARDY Figure 13. Asynchronous Memory Read Timing Setup = 2 Not ready = 2 Strobe = 5 HOLD = 1 CLKOUT1 1 1 2 3 4 5 CEx BE[3:0] EA[21:2] 12 13 ED[31:0] AOE ARE 14 14 AWE 11 10 11 10 ARDY Figure 14. Asynchronous Memory Write Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 35 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 SYNCHRONOUS-BURST MEMORY TIMING timing requirements for synchronous-burst SRAM cycles (full-rate SSCLK) (see Figure 15) ’C6201-150 NO. MIN 7 8 tsu(EDV-SSCLKH) th(SSCLKH-EDV) MAX ’C6201B-150 ’C6201B-200 MIN UNIT MAX Setup time, read EDx valid before SSCLK high 1.5 1.5 ns Hold time, read EDx valid after SSCLK high 1.2 1.5 ns switching characteristics for synchronous-burst SRAM cycles† (full-rate SSCLK) (see Figure 15 and Figure 16) NO. ’C6201-150 PARAMETER MIN 1 tsu(CEV-SSCLKH) toh(SSCLKH-CEV) Setup time, CEx valid before SSCLK high tsu(BEV-SSCLKH) toh(SSCLKH-BEIV) Setup time, BEx valid before SSCLK high tsu(EAV-SSCLKH) toh(SSCLKH-EAIV) Setup time, EAx valid before SSCLK high tsu(ADSV-SSCLKH) toh(SSCLKH-ADSV) Setup time, SSADS valid before SSCLK high tsu(OEV-SSCLKH) toh(SSCLKH-OEV) Setup time, SSOE valid before SSCLK high tsu(EDV-SSCLKH) toh(SSCLKH-EDIV) Setup time, EDx valid before SSCLK high 14 15 tsu(WEV-SSCLKH) Setup time, SSWE valid before SSCLK high 2 3 4 5 6 9 10 11 12 13 Output hold time, CEx valid after SSCLK high Output hold time, BEx invalid after SSCLK high Output hold time, EAx invalid after SSCLK high Output hold time, SSADS valid after SSCLK high Output hold time, SSOE valid after SSCLK high Output hold time, EDx invalid after SSCLK high MAX ’C6201B-150 ’C6201B-200 MIN UNIT MAX P – 4.7 0.5P – 1.3 ns 0 0.5P – 2.3 ns P – 4.7 0.5P – 1.3 ns 1* 0.5P – 2.3 ns P – 5.7 0.5P – 1.3 ns 1* 0.5P – 2.3 ns P – 3.7 0.5P – 1.3 ns 0 0.5P – 2.3 ns P – 4.7 0.5P – 1.3 ns 0 0.5P – 2.3 ns P – 4.7 0.5P – 1.3 ns 1* 0.5P – 2.3 ns P – 3.7 0.5P – 1.3 ns 16 toh(SSCLKH-WEV) Output hold time, SSWE valid after SSCLK high 0 0.5P – 2.3 ns † The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter or SSCLK duty cycle. P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.67 ns. *This parameter is not production tested. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 36 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED) SSCLK 1 2 CEx 3 BE[3:0] BE1 BE2 BE3 4 BE4 A1 A2 A3 6 A4 5 EA[21:2] 8 7 Q1 ED[31:0] 9 Q2 Q3 Q4 10 SSADS 11 12 SSOE SSWE Figure 15. SBSRAM Read Timing (Full-Rate SSCLK) SSCLK 1 2 CEx 3 BE[3:0] BE1 BE2 BE3 4 BE4 A1 A2 A3 6 A4 D3 14 D4 5 EA[21:2] 13 ED[31:0] D1 D2 9 10 15 16 SSADS SSOE SSWE Figure 16. SBSRAM Write Timing (Full-Rate SSCLK) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 37 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED) timing requirements for synchronous-burst SRAM cycles (half-rate SSCLK) (see Figure 17) (’C6201) ’C6201-150 NO NO. 7 8 MIN tsu(EDV-SSCLKH) th(SSCLKH-EDV) MAX UNIT Setup time, read EDx valid before SSCLK high 3.6* ns Hold time, read EDx valid after SSCLK high 1.2* ns *This parameter is not production tested. switching characteristics for synchronous-burst SRAM cycles† (half-rate SSCLK) (see Figure 17 and Figure 18) (’C6201) NO NO. 1 PARAMETER ’C6201-150 MIN MAX UNIT tsu(CEV-SSCLKH) toh(SSCLKH-CEV) Setup time, CEx valid before SSCLK high P – 4.1* ns Output hold time, CEx valid after SSCLK high P – 5.7* ns tsu(BEV-SSCLKH) toh(SSCLKH-BEIV) Setup time, BEx valid before SSCLK high P – 4* ns P – 5.7* ns tsu(EAV-SSCLKH) toh(SSCLKH-EAIV) Setup time, EAx valid before SSCLK high tsu(ADSV-SSCLKH) toh(SSCLKH-ADSV) Setup time, SSADS valid before SSCLK high tsu(OEV-SSCLKH) toh(SSCLKH-OEV) Setup time, SSOE valid before SSCLK high Setup time, EDx valid before SSCLK high 14 tsu(EDV-SSCLKH) toh(SSCLKH-EDIV) 15 tsu(WEV-SSCLKH) Setup time, SSWE valid before SSCLK high 2 3 4 5 6 9 10 11 12 13 Output hold time, BEx invalid after SSCLK high Output hold time, EAx invalid after SSCLK high Output hold time, SSADS valid after SSCLK high Output hold time, SSOE valid after SSCLK high Output hold time, EDx invalid after SSCLK high P – 4* ns P – 5.7* ns P – 4* ns P – 5.7* ns P – 4* ns P – 5.7* ns P – 4* ns P – 5.7* ns P – 4* ns 16 toh(SSCLKH-WEV) Output hold time, SSWE valid after SSCLK high P – 5.7* ns † The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter or SSCLK duty cycle. P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.67 ns. *This parameter is not production tested. 38 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED) timing requirements for synchronous-burst SRAM cycles (half-rate SSCLK) (see Figure 17) (’C6201B) ’C6201B-150 NO NO. 7 8 MIN tsu(EDV-SSCLKH) th(SSCLKH-EDV) ’C6201B-200 MAX MIN MAX UNIT Setup time, read EDx valid before SSCLK high 4.2 2.5 ns Hold time, read EDx valid after SSCLK high 1.5 1.5 ns switching characteristics for synchronous-burst SRAM cycles† (half-rate SSCLK) (see Figure 17 and Figure 18) (’C6201B) PARAMETER ’C6201B-150 ’C6201B-200 MIN MIN MAX MAX UNIT 1 tsu(CEV-SSCLKH) Setup time, CEx valid before SSCLK high 1.5P – 5.5 1.5P – 3 ns 2 toh(SSCLKH-CEV) Output hold time, CEx valid after SSCLK high 0.5P – 2.4 0.5P – 1.5 ns 3 tsu(BEV-SSCLKH) Setup time, BEx valid before SSCLK high 1.5P – 5.5 1.5P – 3 ns 4 toh(SSCLKH-BEIV) Output hold time, BEx invalid after SSCLK high 0.5P – 2.4 0.5P – 1.5 ns 5 tsu(EAV-SSCLKH) Setup time, EAx valid before SSCLK high 1.5P – 5.5 1.5P – 3 ns 6 toh(SSCLKH-EAIV) Output hold time, EAx invalid after SSCLK high 0.5P – 2.4 0.5P – 1.5 ns 9 tsu(ADSV-SSCLKH) Setup time, SSADS valid before SSCLK high 1.5P – 5.5 1.5P – 3 ns 10 toh(SSCLKH-ADSV) tsu(OEV-SSCLKH) Output hold time, SSADS valid after SSCLK high 0.5P – 2.4 0.5P – 1.5 ns Setup time, SSOE valid before SSCLK high 1.5P – 5.5 1.5P – 3 ns toh(SSCLKH-OEV) tsu(EDV-SSCLKH) Output hold time, SSOE valid after SSCLK high 0.5P – 2.4 0.5P – 1.5 ns Setup time, EDx valid before SSCLK high 1.5P – 5.5 1.5P – 3 ns toh(SSCLKH-EDIV) tsu(WEV-SSCLKH) Output hold time, EDx invalid after SSCLK high 0.5P – 2.4 0.5P – 1.5 ns Setup time, SSWE valid before SSCLK high 1.5P – 5.5 1.5P – 3 ns 11 12 13 14 15 PRODUCT PREVIEW NO NO. 16 toh(SSCLKH-WEV) Output hold time, SSWE valid after SSCLK high 0.5P – 2.4 0.5P – 1.5 ns † The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter or SSCLK duty cycle. P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.67 ns. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 39 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED) SSCLK 1 2 CEx 3 4 BE[3:0] BE1 BE2 BE3 BE4 A1 A2 A3 A4 Q1 Q2 5 6 EA[21:2] 8 7 ED[31:0] 9 Q3 Q4 10 SSADS 11 12 SSOE SDWE Figure 17. SBSRAM Read Timing (1/2 Rate SSCLK) SSCLK 1 2 CEx 3 BE[3:0] 4 BE1 BE2 BE3 A1 A2 A3 5 EA[21:2] BE4 6 13 ED[31:0] Q1 Q2 A4 14 Q3 Q4 9 10 15 16 SSADS SSOE SSWE Figure 18. SBSRAM Write Timing (1/2 Rate SSCLK) 40 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 SYNCHRONOUS DRAM TIMING timing requirements for synchronous DRAM cycles (see Figure 19) (’C6201) ’C6201-150 NO NO. 7 8 MIN tsu(EDV-SDCLKH) th(SDCLKH-EDV) MAX UNIT Setup time, read EDx valid before SDCLK high 3.5 ns Hold time, read EDx valid after SDCLK high 1.2 ns switching characteristics for synchronous DRAM cycles† (see Figure 19–Figure 24) (’C6201) NO NO. 1 2 3 4 5 6 9 10 11 12 13 14 15 16 17 ’C6201-150 PARAMETER MIN MAX UNIT tsu(CEV-SDCLKH) toh(SDCLKH-CEV) Setup time, CEx valid before SDCLK high P – 4.2 ns Output hold time, CEx valid after SDCLK high P – 5.2 ns tsu(BEV-SDCLKH) toh(SDCLKH-BEIV) Setup time, BEx valid before SDCLK high tsu(EAV-SDCLKH) toh(SDCLKH-EAIV) Setup time, EAx valid before SDCLK high tsu(SDCAS-SDCLKH) toh(SDCLKH-SDCAS) Setup time, SDCAS valid before SDCLK high tsu(EDV-SDCLKH) toh(SDCLKH-EDIV) Setup time, EDx valid before SDCLK high Output hold time, EDx invalid after SDCLK high P – 5.2* ns tsu(SDWE-SDCLKH) toh(SDCLKH-SDWE) Setup time, SDWE valid before SDCLK high P – 4.2 ns Output hold time, SDWE valid after SDCLK high P – 5.2 ns tsu(SDA10V-SDCLKH) toh(SDCLKH-SDA10IV) Setup time, SDA10 valid before SDCLK high P – 4.2 ns P – 5.2* ns tsu(SDRAS-SDCLKH) toh(SDCLKH-SDRAS) Setup time, SDRAS valid before SDCLK high P – 4.2 ns Output hold time, BEx invalid after SDCLK high Output hold time, EAx invalid after SDCLK high Output hold time, SDCAS valid after SDCLK high Output hold time, SDA10 invalid after SDCLK high P – 4.2 ns P – 5.2* ns P – 4.2 ns P – 5.2* ns P – 4.2 ns P – 5.2 ns P – 4.2* ns 18 Output hold time, SDRAS valid after SDCLK high P – 5.2 ns † The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter or SDCLK duty cycle. P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.67 ns. *This parameter is not production tested. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 41 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 SYNCHRONOUS DRAM TIMING (CONTINUED) timing requirements for synchronous DRAM cycles (see Figure 19) (’C6201B) ’C6201B-150 NO NO. 7 8 MIN tsu(EDV-SDCLKH) th(SDCLKH-EDV) Setup time, read EDx valid before SDCLK high Hold time, read EDx valid after SDCLK high MAX ’C6201B-200 MIN MAX UNIT 1.5 1 ns 3 3 ns switching characteristics for synchronous DRAM cycles† (see Figure 19–Figure 24) (’C6201B) PRODUCT PREVIEW NO NO. PARAMETER ’C6201B-150 ’C6201B-200 MIN MIN MAX MAX UNIT 1 tsu(CEV-SDCLKH) Setup time, CEx valid before SDCLK high 1.5P – 6 1.5P – 3.5 ns 2 toh(SDCLKH-CEV) Output hold time, CEx valid after SDCLK high 0.5P – 2 0.5P – 1 ns 3 tsu(BEV-SDCLKH) Setup time, BEx valid before SDCLK high 1.5P – 6 1.5P – 3.5 ns 4 toh(SDCLKH-BEIV) Output hold time, BEx invalid after SDCLK high 0.5P – 2 0.5P – 1 ns 5 tsu(EAV-SDCLKH) Setup time, EAx valid before SDCLK high 1.5P – 6 1.5P – 3.5 ns 6 toh(SDCLKH-EAIV) Output hold time, EAx invalid after SDCLK high 0.5P – 2 0.5P – 1 ns 9 tsu(SDCAS-SDCLKH) Setup time, SDCAS valid before SDCLK high 1.5P – 6 1.5P – 3.5 ns 10 toh(SDCLKH-SDCAS) Output hold time, SDCAS valid after SDCLK high 0.5P – 2 0.5P – 1 ns 11 tsu(EDV-SDCLKH) Setup time, EDx valid before SDCLK high 1.5P – 6 1.5P – 3.5 ns 12 toh(SDCLKH-EDIV) Output hold time, EDx invalid after SDCLK high 0.5P – 2 0.5P – 1 ns 13 tsu(SDWE-SDCLKH) Setup time, SDWE valid before SDCLK high 1.5P – 6 1.5P – 3.5 ns 14 toh(SDCLKH-SDWE) Output hold time, SDWE valid after SDCLK high 0.5P – 2 0.5P – 1 ns 15 tsu(SDA10V-SDCLKH) Setup time, SDA10 valid before SDCLK high 1.5P – 6 1.5P – 3.5 ns 16 toh(SDCLKH-SDA10IV) Output hold time, SDA10 invalid after SDCLK high 0.5P – 2 0.5P – 1 ns 17 tsu(SDRAS-SDCLKH) Setup time, SDRAS valid before SDCLK high 1.5P – 6 1.5P – 3.5 ns 18 toh(SDCLKH-SDRAS) Output hold time, SDRAS valid after SDCLK high 0.5P – 2 0.5P – 1 ns † The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter or SDCLK duty cycle. P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.67 ns. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 42 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 SYNCHRONOUS DRAM TIMING (CONTINUED) SDCLK 1 2 CEx 4 3 BE[3:0] BE1 BE2 CA2 CA3 BE3 6 5 CA1 EA[15:2] 8 7 D1 ED[31:0] D2 D3 15 SDA10 SDRAS 9 10 SDCAS SDWE Figure 19. Three SDRAM Read Commands SDCLK 1 2 CEx 3 4 BE[3:0] BE1 5 BE2 BE3 CA2 CA3 6 EA[15:2] CA1 11 D1 ED[31:0] 12 D2 D3 15 SDA10 SDRAS 9 10 13 14 SDCAS SDWE Figure 20. Three SDRAM WRT Commands POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 43 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 SYNCHRONOUS DRAM TIMING (CONTINUED) ACTV SDCLK 1 2 CEx BE[3:0] 5 EA[15:2] Bank activate/row address ED[31:0] 15 Row address SDA10 18 17 SDRAS SDCAS SDWE Figure 21. SDRAM ACTV Command DCAB SDCLK 1 2 CEx BE[3:0] EA[15:2] ED[31:0] 16 15 SDA10 18 17 SDRAS SDCAS 14 13 SDWE Figure 22. SDRAM DCAB Command 44 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 SYNCHRONOUS DRAM TIMING (CONTINUED) REFR SDCLK 1 2 CEx BE[3:0] EA[15:2] ED[31:0] SDA10 18 17 SDRAS 9 10 SDCAS SDWE Figure 23. SDRAM REFR Command MRS SDCLK 1 2 CEx BE[3:0] 5 EA[15:2] 6 MRS value ED[31:0] SDA10 18 17 SDRAS 9 10 SDCAS 14 13 SDWE Figure 24. SDRAM MRS Command POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 45 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 HOLD/HOLDA TIMING timing requirements for the HOLD/HOLDA cycles† (see Figure 25) MIN 1 2 ’C6201B-150 ’C6201B-200 ’C6201-150 NO. tsu(HOLDH-CKO1H) th(CKO1H-HOLDL) MAX MIN Setup time, HOLD high before CLKOUT1 high 5* 1 Hold time, HOLD low after CLKOUT1 high 2* 4 UNIT MAX ns ns † HOLD is synchronized internally. Therefore, if setup and hold times are not met, it will either be recognized in the current cycle or in the next cycle. Thus, HOLD can be an asynchronous input. *This parameter is not production tested. switching characteristics for the HOLD/HOLDA cycles (see Figure 25) NO. ’C6201B-150 ’C6201B-200 ’C6201-150 PARAMETER MIN MAX MIN MAX UNIT 3 tR(HOLDL-BHZ) Response time, HOLD low to EMIF Bus high impedance 4* ‡ 4 ‡ CLKOUT1 cycles 4 tR(BHZ-HOLDAL) Response time, EMIF Bus high impedance to HOLDA low 1* 2* 1 2 CLKOUT1 cycles 5 tR(HOLDH-HOLDAH) Response time, HOLD high to HOLDA high 4* 6 4 7 CLKOUT1 cycles 6 Delay time, CLKOUT1 high to HOLDA valid –1* 5 1 8 ns 7 td(CKO1H-HOLDAL) td(CKO1H-BHZ) Delay time, CLKOUT1 high to EMIF Bus high impedance§ –1* 5* 3 11 ns 8 td(CKO1H-BLZ) Delay time, CLKOUT1 high to EMIF Bus low impedance§ –1* 5* 3 11 ns 6 CLKOUT1 cycles 9 tR(HOLDH-BLZ) Response time, HOLD high to EMIF Bus low impedance 3* 5* 3 *This parameter is not production tested. ‡ All pending EMIF transactions are allowed to complete before HOLDA is asserted. The worst cases for this is an asynchronous read or write with external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are occurring, then the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1. § EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE. DSP Owns Bus External Requester DSP Owns Bus 5 4 9 3 CLKOUT1 2 2 1 1 HOLD 6 6 HOLDA 7 8 EMIF Bus† ’C62x Ext Req ’C62x † EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE. Figure 25. HOLD/HOLDA Timing PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 46 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 RESET TIMING timing requirements for reset (see Figure 26) MIN 1 ’C6201B-150 ’C6201B-200 ’C6201-150 NO. tw(RST) Width of the RESET pulse (PLL stable) Width of the RESET pulse (PLL needs to sync up)† MAX MIN UNIT MAX 10* 10 CLKOUT1 cycles 250* 250 µs *This parameter is not production tested. † The RESET signal is not connected internally to the clock PLL circuit. The PLL, however, may need up to 250 µs to stabilize following device powerup or after PLL configuration has been changed. During that time, RESET must be asserted to ensure proper device operation. See the clock PLL section for PLL lock times. switching characteristics during reset‡ (see Figure 26) NO. ’C6201B-150 ’C6201B-200 ’C6201-150 PARAMETER MIN MAX CLKOUT1 cycles –1 10 ns –1 10 ns 10* –1 10 ns 10 –1 10 ns –1* 10* –1 10 ns –1* 10 –1 10 ns Delay time, CLKOUT1 high to low group invalid –1* 10* –1 10 ns Delay time, CLKOUT1 high to low group valid –1* Delay time, CLKOUT1 high to high group invalid –1* Delay time, CLKOUT1 high to high group valid –1* Delay time, CLKOUT1 high to Z group high impedance –1* Delay time, CLKOUT1 high to Z group valid –1* tR(RST) Response time to change of value in RESET signal 3 td(CKO1H-CKO2IV) td(CKO1H-CKO2V) Delay time, CLKOUT1 high to CLKOUT2 invalid –1* 10* Delay time, CLKOUT1 high to CLKOUT2 valid –1* 10 td(CKO1H-SDCLKIV) td(CKO1H-SDCLKV) Delay time, CLKOUT1 high to SDCLK invalid –1* Delay time, CLKOUT1 high to SDCLK valid –1* td(CKO1H-SSCKIV) td(CKO1H-SSCKV) Delay time, CLKOUT1 high to SSCLK invalid Delay time, CLKOUT1 high to SSCLK valid td(CKO1H-LOWIV) td(CKO1H-LOWV) td(CKO1H-HIGHIV) td(CKO1H-HIGHV) td(CKO1H-ZHZ) td(CKO1H-ZV) 5 6 7 8 9 10 11 12 13 14 UNIT MAX 2 2 4 MIN 2 –1 10* –1 ns 10 –1 10* –1 –1 ns ns 10 ns ns ‡ Low group consists of: High group consists of: Z group consists of: IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1 HRDY and HINT EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, SDWE, HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, and FSR1. *This parameter is not production tested. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 47 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 RESET TIMING (CONTINUED) CLKOUT1 1 2 2 RESET 3 4 5 6 7 8 9 10 11 12 13 14 CLKOUT2 SDCLK SSCLK LOW GROUP† HIGH GROUP† Z GROUP† † Low group consists of: High group consists of: Z group consists of: IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1 HRDY and HINT EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, SDWE, HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, and FSR1. Figure 26. Reset Timing 48 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 EXTERNAL INTERRUPT/RESET TIMING timing requirements for interrupt response cycles† (see Figure 27) ’C6201B-150 ’C6201B-200 ’C6201-150 NO. MIN MAX MIN UNIT MAX 3 tw(ILOW) Width of the interrupt pulse low 2 2 CLKOUT1 cycles 4 tw(IHIGH) Width of the interrupt pulse high 2 2 CLKOUT1 cycles † Interrupt signals are synchronized internally and are potentially recognized one cycle later if setup and hold times are violated. Thus, they can be connected to asynchronous inputs. switching characteristics during interrupt response cycles (see Figure 27) NO. ’C6201B-150 ’C6201B-200 ’C6201-150 PARAMETER MIN 1 tR(EINTH-IACKH) Response time, EXT_INTx high to IACK high 2 tR(ISFP) Response time, interrupt service fetch packet execution after EXT_INTx high 5 td(CKO2L-IACKV) td(CKO2L-INUMV) MAX MIN UNIT MAX 9‡* 9‡ CLKOUT1 cycles 11‡* 11‡ CLKOUT1 cycles Delay time, CLKOUT2 low to IACK valid 0* 10 0 10 ns Delay time, CLKOUT2 low to INUMx valid 0* 10 0 10 ns 7 td(CKO2L-INUMIV) Delay time, CLKOUT2 low to INUMx invalid 0* 10* ‡ Add two CLKOUT1 cycles to this parameter if the interrupt is recognized during the high half of CLKOUT2 *This parameter is not production tested. 0 10 ns 6 1 2 3 4 5 PG PS PW PR DP DC E1 1 2 CLKOUT1 4 3 EXT_INTx, NMI Interrupt Flag 5 5 IACK 6 7 Interrupt Number INUMx CLKOUT2 Figure 27. Interrupt Timing PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 49 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 HOST-PORT INTERFACE TIMING timing requirements for host-port interface cycles† (see Figure 28, Figure 29, Figure 30, and Figure 31) NO. 1 2 tsu(SEL-HSTBL) th(HSTBL-SEL) Setup time, select signals‡ valid before HSTROBE low Hold time, select signals‡ valid after HSTROBE low ’C6201-150 ’C6201B-150 ’C6201B-200 MIN MIN MAX UNIT MAX 1 1 ns 2 2 ns 3 tw(HSTBL) Pulse duration, HSTROBE low 2 2 CLKOUT1 cycles 4 tw(HSTBH) Pulse duration, HSTROBE high between consecutive accesses 2* 2 CLKOUT1 cycles 10 tsu(SEL-HASL) th(HASL-SEL) Setup time, select signals‡ valid before HAS low Hold time, select signals‡ valid after HAS low 1 1 ns 2 2 ns tsu(HDV-HSTBH) th(HSTBH-HDV) Setup time, host data valid before HSTROBE high 1 1 ns Hold time, host data valid after HSTROBE high 1 1 ns Hold time, HSTROBE low after HRDY low. HSTROBE should not be inactivated until HRDY is active (low); otherwise, HPI writes will not complete properly. 1* 1 ns 11 12 13 14 th(HRDYL-HSTBL) † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. ‡ Select signals include: HCNTRL[1:0], HR/W, and HHWIL. *This parameter is not production tested. switching characteristics during host-port interface cycles†§ (see Figure 28, Figure 29, Figure 30, and Figure 31) NO. ’C6201-150 PARAMETER MIN 5 MAX ’C6201B-150 ’C6201B-200 MIN UNIT MAX Delay time, HCS to HRDY¶ 1* 7* 1 7 ns Delay time, HSTROBE low to HRDY high# 3* 12* 3 12 ns Output hold time, HD low impedance after HSTROBE low for an HPI read 4* 6 td(HCS-HRDY) td(HSTBL-HRDYH) 7 toh(HSTBL-HDLZ) 8 Delay time, HD valid to HRDY low 9 td(HDV-HRDYL) toh(HSTBH-HDV) 15 td(HSTBH-HDHZ) 16 td(HSTBL-HDV) 4 ns P – 3* P* P–2 P ns Output hold time, HD valid after HSTROBE high 3* 12* 3 12 ns Delay time, HSTROBE high to HD high impedance 3* 12* 3 12 ns Delay time, HSTROBE low to HD valid 3* 12* 3 12 ns Delay time, HSTROBE high to HRDY high|| 17 td(HSTBH-HRDYH) 3* 12* 3 12 ns † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. § The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.67 ns. ¶ HCS enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI is busy completing a previous HPID write or READ with autoincrement. *This parameter is not production tested. # This parameter is used during an HPID read. At the beginning of the first half-word transfer on the falling edge of HSTROBE, the HPI sends the request to the DMA auxiliary channel, and HRDY remains high until the DMA auxiliary channel loads the requested data into HPID. || This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY remains low if the access is not an HPID write or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 50 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 HOST-PORT INTERFACE TIMING (CONTINUED) HAS 1 1 2 2 HCNTL[1:0] 1 1 2 2 HR/W 1 1 2 2 HHWIL 4 3 HSTROBE† 3 HCS 15 9 7 15 9 16 HD[15:0] (output) 1st half-word 5 2nd half-word 8 17 5 HRDY (case 1) 6 8 17 5 HRDY (case 2) † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 28. HPI Read Timing (HAS Not Used, Tied High) HAS 10 11 11 10 HCNTL[1:0] 11 11 10 10 HR/W 11 11 10 10 HHWIL 4 3 HSTROBE† 3 HCS 15 7 9 15 16 9 HD[15:0] (output) 1st half-word 5 8 2nd half-word 17 5 17 5 HRDY (case 1) 6 8 HRDY (case 2) † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 29. HPI Read Timing (HAS Used) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 51 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 HOST-PORT INTERFACE TIMING (CONTINUED) HAS 1 1 2 2 HCNTL[1:0] 12 12 13 13 HBE[1:0] 1 1 2 2 HR/W 1 1 2 2 HHWIL 3 3 4 14 HSTROBE† HCS 12 12 13 13 HD[15:0] (input) 1st half-word 5 17 2nd half-word 5 HRDY † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 30. HPI Write Timing (HAS Not Used, Tied High) HAS 12 12 13 13 HBE[1:0] 11 11 10 10 HCNTL[1:0] 11 11 10 10 HR/W 11 11 10 10 HHWIL 3 3 4 14 HSTROBE† HCS 12 13 12 13 HD[15:0] (input) 5 1st half-word 2nd half-word HRDY † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 31. HPI Write Timing (HAS Used) 52 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 17 5 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING timing requirements for McBSP†‡(see Figure 32) ’C6201-150 NO. MIN MAX ’C6201B-150 ’C6201B-200 MIN 2 tc(CKRX) Cycle time, CLKR/X CLKR/X ext 2* 2 3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext P – 1* P–1 5 tsu(FRH-CKRL) (FRH CKRL) Setup time,, external FSR high g before CLKR low CLKR int 13 9 CLKR ext 4 1 6 th(CKRL FRH) h(CKRL-FRH) Hold time,, external FSR high g after CLKR low CLKR int 7* 6 CLKR ext 3.5 3 7 tsu(DRV-CKRL) (DRV CKRL) Setup time, time DR valid before CLKR low CLKR int 13.5 8 CLKR ext 1 0 8 th(CKRL DRV) h(CKRL-DRV) Hold time time, DR valid after CLKR low CLKR int 4* 3 CLKR ext 4 3 10 tsu(FXH-CKXL) (FXH CKXL) Setup time,, external FSX high g before CLKX low CLKX int 13 9 CLKX ext 4 1 11 th(CKXL h(CKXL-FXH) FXH) Hold time,, external FSX high g after CLKX low CLKX int 7 6 CLKX ext 3.5 3 UNIT MAX CLKOUT1 cycles ns ns ns ns ns ns ns † CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. ‡ The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter or SSCLK duty cycle. P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.67 ns. *This parameter is not production tested. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 53 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) switching characteristics for McBSP†‡ (see Figure 32) NO. ’C6201B-150 ’C6201B-200 ’C6201-150 PARAMETER UNIT MIN MAX MIN MAX 4* 15* 4 10 1 td(CKSH-CKRXH) Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input 2 tc(CKRX) Cycle time, CLKR/X CLKR/X int 2* 3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X int C – 1*¶ C + 1*¶ C – 1¶ C + 1¶ ns 4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR int –2* 4.5* –2 3 ns 9 td(CKXH FXV) d(CKXH-FXV) Delay y time,, CLKX high g to internal FSX valid CLKX int 0* 4* –2 3 CLKX ext 3* 16 3 9 0* 4* –1 4 tdi dis(CKXH-DXHZ) (CKXH DXHZ) Disable time, DX high impedance following last data bit from CLKX high CLKX int 12 CLKX ext 3* 16* 3 9 CLKX int 0* 4* –1 4 ns CLKOUT1 cycles 2 ns ns Delay time, CLKX high to DX valid 13 td(CKXH DXV) d(CKXH-DXV) This is also specified byy design g but not tested to be the delay time for data to be low impedance on the first data bit. ns CLKX ext 3* 16 3 9 –2* 4* –1 3 Delay time, FSX high to DX valid 14 td(FXH d(FXH-DXV) DXV) This is also specified by design but not tested to be the delay time for data to be low impedance on the first data bit. ONLY applies when in data delay 0 (XDATDLY = 00b) mode FSX int ns FSX ext 3* 16* 3 9 † CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. ‡ Minimum delay times also represent minimum output hold times. *This parameter is not production tested. ¶ C = H or L H = CLKX high pulse width = (CLKGDV/2 + 1) * T L = CLKX low pulse width = (CLKGDV/2) * T PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 54 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKS 1 2 3 3 CLKR 4 4 FSR (int) 5 6 FSR (ext) 7 DR 8 Bit(n-1) (n-2) (n-3) 2 3 3 CLKX 9 FSX (int) 11 10 FSX (ext) FSX (XDATDLY=00b) 12 DX Bit 0 14 13 Bit(n-1) 13 (n-2) (n-3) Figure 32. McBSP Timings POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 55 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for FSR when GSYNC = 1 (see Figure 33) ’C6201-150 NO. MIN 1 2 tsu(FRH-CKSH) th(CKSH-FRH) MIN UNIT MAX Setup time, FSR high before CLKS high 4* 4 ns Hold time, FSR high after CLKS high 4* 4 ns *This parameter is not production tested. CLKS 1 2 FSR external CLKR/X (no need to resync) CLKR/X(needs resync) Figure 33. FSR Timing When GSYNC = 1 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 56 MAX ’C6201B-150 ’C6201B-200 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 34) (’C6201) ’C6201-150 NO. MASTER MIN 4 5 tsu(DRV-CKXL) th(CKXL-DRV) MAX UNIT SLAVE MIN Setup time, DR valid before CLKX low 12 3P – 2* Hold time, DR valid after CLKX low 4* 5 + 6P MAX ns ns † The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.67 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. *This parameter is not production tested. switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 34) (’C6201) NO. 1 2 ’C6201-150 § MASTER SLAVE PARAMETER th(CKXL-FXL) td(FXL-CKXH) Hold time, FSX low after CLKX low¶ Delay time, FSX low to CLKX high# MIN UNIT MIN MAX MAX T – 2* T + 3* ns L – 2* L + 3* ns –2* 4* L – 2* L + 3* Delay time, CLKX high to DX valid 3 td(CKXH-DXV) 6 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from CLKX low 7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high This is also specified by design but not tested to be the delay time for data to be low impedance on the first data bit. 3P + 4* 5P + 17* ns ns P + 4* 3P + 17* ns 8 td(FXL-DXV) Delay time, FSX low to DX valid 2P + 4* 4P + 17 ns † The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.67 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § T = CLKX period = (1 + CLKGDV) * P; if CLKSM = 1, then P = 1/CPU clock frequency = CLKX period = (1 + CLKGDV) * P_clks; if CLKSM = 0, then P_clks = CLKS period. H = CLKX high pulse width = (CLKGDV/2 + 1) * T L = CLKX low pulse width = (CLKGDV/2) * T ¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP *This parameter is not production tested. # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 57 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 34) (’C6201B) ’C6201B-150 ’C6201B-200 NO NO. MASTER MIN 4 5 tsu(DRV-CKXL) th(CKXL-DRV) Setup time, DR valid before CLKX low Hold time, DR valid after CLKX low UNIT SLAVE MAX MIN 12 3P – 2 4 5 + 6P MAX ns ns † The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.67 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 34) (’C6201B) PRODUCT PREVIEW ’C6201B-150 ’C6201B-200 NO NO. 1 2 PARAMETER th(CKXL-FXL) td(FXL-CKXH) MASTER§ Hold time, FSX low after CLKX low¶ Delay time, FSX low to CLKX high# UNIT SLAVE MIN MAX T–2 T+3 MIN MAX ns L–2 L+3 ns –2 4 L–2 L+3 Delay time, CLKX high to DX valid 3 td(CKXH-DXV) 6 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from CLKX low 7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high This is also specified by design but not tested to be the delay time for data to be low impedance on the first data bit. 3P + 4 5P + 17 ns ns P+3 3P + 17 ns 8 td(FXL-DXV) Delay time, FSX low to DX valid 2P + 2 4P + 17 ns † The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.67 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § T = CLKX period = (1 + CLKGDV) * P; if CLKSM = 1, then P = 1/CPU clock frequency = CLKX period = (1 + CLKGDV) * P_clks; if CLKSM = 0, then P_clks = CLKS period. H = CLKX high pulse width = (CLKGDV/2 + 1) * T L = CLKX low pulse width = (CLKGDV/2) * T ¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 58 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKX 1 2 FSX 7 6 DX 8 3 Bit 0 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 34. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 59 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 35) (’C6201) ’C6201-150 NO. MASTER MIN 4 5 tsu(DRV-CKXH) th(CKXH-DRV) MAX UNIT SLAVE MIN Setup time, DR valid before CLKX high 11 3P – 2 Hold time, DR valid after CLKX high 4* 5 + 6P* MAX ns ns † The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.67 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. *This parameter is not production tested. switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 35) (’C6201) NO. ’C6201-150 § MASTER SLAVE PARAMETER MIN MAX L – 2* L + 3* MIN UNIT MAX 2 th(CKXL-FXL) td(FXL-CKXH) Hold time, FSX low after CLKX low¶ Delay time, FSX low to CLKX high# T – 2* T + 4.5* 3 td(CKXL-DXV) Delay time, CLKX low to DX valid –2* 4* 3P + 4* 5P + 17* ns 6 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from CLKX low –2* 4* 3P + 4* 5P + 17* ns 1 ns ns 7 td(FXL-DXV) Delay time, FSX low to DX valid H – 2* H + 4* 2P + 4* 4P + 17* ns † The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.67 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § T = CLKX period = (1 + CLKGDV) * P; if CLKSM = 1, then P = 1/CPU clock frequency = CLKX period = (1 + CLKGDV) * P_clks; if CLKSM = 0, then P_clks = CLKS period. H = CLKX high pulse width = (CLKGDV/2 + 1) * T L = CLKX low pulse width = (CLKGDV/2) * T ¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP *This parameter is not production tested. # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). 60 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 35) (’C6201B) ’C6201B-150 ’C6201B-200 NO NO. MASTER MIN 4 5 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high Hold time, DR valid after CLKX high UNIT SLAVE MAX MIN 12 3P – 2 4 5 + 6P MAX ns ns † The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.67 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 35) (’C6201B) NO NO. PARAMETER MASTER§ 2 th(CKXL-FXL) td(FXL-CKXH) Hold time, FSX low after CLKX low¶ Delay time, FSX low to CLKX high# 3 td(CKXL-DXV) Delay time, CLKX low to DX valid tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from CLKX low 1 6 UNIT SLAVE MIN MAX L–2 L+3 MIN MAX T–2 T+3 –2 4 3P + 4 5P + 17 ns –2 4 3P + 3 5P + 17 ns ns ns 7 td(FXL-DXV) Delay time, FSX low to DX valid H–2 H+4 2P + 2 4P + 17 ns † The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.67 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § T = CLKX period = (1 + CLKGDV) * P; if CLKSM = 1, then P = 1/CPU clock frequency = CLKX period = (1 + CLKGDV) * P_clks; if CLKSM = 0, then P_clks = CLKS period. H = CLKX high pulse width = (CLKGDV/2 + 1) * T L = CLKX low pulse width = (CLKGDV/2) * T ¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 61 PRODUCT PREVIEW ’C6201B-150 ’C6201B-200 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKX 1 2 6 Bit 0 7 FSX DX 3 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 35. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 62 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 36) (’C6201) ’C6201-150 NO. MASTER MIN 4 5 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high MAX MIN 12* 3P – 2 4* 5 + 6P Hold time, DR valid after CLKX high UNIT SLAVE MAX ns ns † The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.67 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. *This parameter is not production tested. switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 36) (’C6201) NO. 1 2 ’C6201-150 § MASTER SLAVE PARAMETER th(CKXH-FXL) td(FXL-CKXL) Hold time, FSX low after CLKX high¶ Delay time, FSX low to CLKX low# MIN UNIT MIN MAX MAX T – 2* T + 3* ns H – 2* H + 4.5* ns –2* 4* H – 2* H + 3* Delay time, CLKX low to DX valid This is also specified by design but not tested to be the delay time for data to be low impedance on the first data bit. 3 td(CKXL-DXV) 6 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high 7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high 3P + 4* 5P + 17* ns ns P + 4* 3P + 17* ns 8 td(FXL-DXV) Delay time, FSX low to DX valid 2P + 4* 4P + 17* ns † The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.67 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § T = CLKX period = (1 + CLKGDV) * P ; if CLKSM = 1, then P = 1/CPU clock frequency = CLKX period = (1 + CLKGDV) * P_clks; if CLKSM = 0, then P_clks = CLKS period. H = CLKX high pulse width = (CLKGDV/2 + 1) * T L = CLKX low pulse width = (CLKGDV/2) * T ¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP *This parameter is not production tested. # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 63 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 36) (’C6201B) ’C6201B-150 ’C6201B-200 NO NO. MASTER MIN 4 5 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high Hold time, DR valid after CLKX high UNIT SLAVE MAX MIN 12 3P – 2 4 5 + 6P MAX ns ns † The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.67 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 36) (’C6201B) PRODUCT PREVIEW ’C6201B-150 ’C6201B-200 NO NO. 1 2 PARAMETER th(CKXH-FXL) td(FXL-CKXL) MASTER§ Hold time, FSX low after CLKX high¶ Delay time, FSX low to CLKX low# UNIT SLAVE MIN MAX T–2 T+3 MIN MAX ns H–2 H+3 ns –2 4 H–2 H+3 Delay time, CLKX low to DX valid 3 td(CKXL-DXV) 6 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high 7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high This is also specified by design but not tested to be the delay time for data to be low impedance on the first data bit. 3P + 4 5P + 17 ns ns P+3 3P + 17 ns 8 td(FXL-DXV) Delay time, FSX low to DX valid 2P + 2 4P + 17 ns † The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.67 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § T = CLKX period = (1 + CLKGDV) * P; if CLKSM = 1, then P = 1/CPU clock frequency = CLKX period = (1 + CLKGDV) * P_clks; if CLKSM = 0, then P_clks = CLKS period. H = CLKX high pulse width = (CLKGDV/2 + 1) * T L = CLKX low pulse width = (CLKGDV/2) * T ¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 64 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKX 1 2 FSX 7 6 DX 8 3 Bit 0 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 36. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 65 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 37) (’C6201) ’C6201-150 NO. MASTER MIN 4 5 tsu(DRV-CKXL) th(CKXL-DRV) Setup time, DR valid before CLKX low Hold time, DR valid after CLKX low MAX UNIT SLAVE MIN 11 3P – 2 4.5 5 + 6P MAX ns ns † The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.67 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 37) (’C6201) NO. ’C6201-150 MASTER§ SLAVE PARAMETER MIN MAX H – 2* H + 3* ns T – 2* T + 1* ns Delay time, CLKX high to DX valid –2* 4* 3P + 4* 5P + 17 ns Disable time, DX high impedance following last data bit from CLKX high –2* 4* 3P + 4* 5P + 17* ns 2 th(CKXH-FXL) td(FXL-CKXL) Hold time, FSX low after CLKX high¶ Delay time, FSX low to CLKX low# 3 td(CKXH-DXV) tdis(CKXH-DXHZ) 1 6 MIN UNIT MAX 7 td(FXL-DXV) Delay time, FSX low to DX valid L – 2* L + 4* 2P + 4* 4P + 17* ns † The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.67 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § T = CLKX period = (1 + CLKGDV) * P; if CLKSM = 1, then P = 1/CPU clock frequency = CLKX period = (1 + CLKGDV) * P_clks; if CLKSM = 0, then P_clks = CLKS period. H = CLKX high pulse width = (CLKGDV/2 + 1) * T L = CLKX low pulse width = (CLKGDV/2) * T ¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP *This parameter is not production tested. # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). 66 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 37) (’C6201B) ’C6201B-150 ’C6201B-200 NO NO. MASTER MIN 4 5 tsu(DRV-CKXL) th(CKXL-DRV) Setup time, DR valid before CLKX low Hold time, DR valid after CLKX low UNIT SLAVE MAX MIN 12 3P – 2 4 5 + 6P MAX ns ns † The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.67 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 37) (’C6201B) NO NO. PARAMETER MASTER§ 2 th(CKXH-FXL) td(FXL-CKXL) Hold time, FSX low after CLKX high¶ Delay time, FSX low to CLKX low# 3 td(CKXH-DXV) Delay time, CLKX high to DX valid tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high 1 6 UNIT SLAVE MIN MAX H–2 H+3 MIN MAX T–2 T+1 –2 4 3P + 4 5P + 17 ns –2 4 3P + 3 5P + 17 ns ns ns 7 td(FXL-DXV) Delay time, FSX low to DX valid L–2 L+4 2P + 2 4P + 17 ns † The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.67 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § T = CLKX period = (1 + CLKGDV) * P; if CLKSM = 1, then P = 1/CPU clock frequency = CLKX period = (1 + CLKGDV) * P_clks; if CLKSM = 0, then P_clks = CLKS period. H = CLKX high pulse width = (CLKGDV/2 + 1) * T L = CLKX low pulse width = (CLKGDV/2) * T ¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 67 PRODUCT PREVIEW ’C6201B-150 ’C6201B-200 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKX 1 2 FSX 7 6 DX 3 Bit 0 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 37. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 68 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 DMAC, TIMER, POWER-DOWN TIMING switching characteristics for DMAC outputs (see Figure 38) NO. ’C6201B-150 ’C6201B-200 ’C6201-150 PARAMETER UNIT MIN MAX MIN MAX 2* 7* 2 7 1 td(CKO1H-DMACV) Delay time, CLKOUT1 high to DMAC valid *This parameter is not production tested. ns CLKOUT1 1 1 DMAC[0:3] Figure 38. DMAC Timing timing requirements for timer inputs (see Figure 39) MIN 1 ’C6201B-150 ’C6201B-200 ’C6201-150 NO. tw(TINP) Pulse duration, TINP high or low MAX MIN 2 UNIT MAX CLKOUT1 cycles 2 switching characteristics for timer outputs (see Figure 39) NO. ’C6201B-150 ’C6201B-200 ’C6201-150 PARAMETER 2 td(CKO1H-TOUTV) Delay time, CLKOUT1 high to TOUT valid *This parameter is not production tested. UNIT MIN MAX MIN MAX 3* 9 3 9 ns CLKOUT1 1 TINP 2 2 TOUT Figure 39. Timer Timing PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 69 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 DMAC, TIMER, POWER-DOWN TIMING (CONTINUED) switching characteristics for power-down outputs (see Figure 40) NO. MAX MIN MAX 2* 5 3 5 CLKOUT1 1 1 PD Figure 40. Power-Down Timing PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 UNIT MIN 1 td(CKO1H-PDV) Delay time, CLKOUT1 high to PD valid *This parameter is not production tested. 70 ’C6201B-150 ’C6201B-200 ’C6201-150 PARAMETER ns SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 MECHANICAL DATA GLE (S-CBGA-N429) CERAMIC BALL GRID ARRAY 27,20 SQ 26,80 25,40 TYP 1,27 AA Y W V U T R P N M L K J H G F E D C B A 1,27 3 1 2 2,19 1,79 5 4 9 7 6 8 10 11 13 15 17 19 21 12 14 16 18 20 3,30 MAX Seating Plane 0,90 0,60 0,10 M 0,70 0,50 0,15 4164725/B 5/98 NOTES: A. B. C. D. E. All linear dimensions are in millimeters. This drawing is subject to change without notice. Falls within JEDEC MO-156 For 320C6201 (2.5 V core device). Package weight for GLE is 7.65 grams. thermal resistance characteristics (S-CBGA package) °C/W Air Flow Junction-to-Case 1.7 N/A Junction-to-Ambient 14.4 0 NO 1 2 RΘJC RΘJA POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 71 SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 MECHANICAL DATA GLP (S-CBGA-N429) CERAMIC BALL GRID ARRAY 27,20 SQ 26,80 25,40 TYP 1,27 AA Y W V U T R P N M L K J H G F E D C B A 1,27 1 1,22 1,00 5 3 2 4 7 6 9 8 10 11 13 15 17 19 21 12 14 16 18 20 3,30 MAX Seating Plane 0,90 0,60 NOTES: A. B. C. D. E. F. ∅ 0,10 M 0,70 0,50 0,15 4164732/A 08/98 All linear dimensions are in millimeters. This drawing is subject to change without notice. Falls within JEDEC MO-156 Flip chip application only For 320C6201B (1.8 V core device). Package weight for GLP is 7.65 grams. thermal resistance characteristics (S-CBGA package) °C/W Air Flow Junction-to-Case 1.7 N/A Junction-to-Ambient 14.4 0 NO 1 2 72 RΘJC RΘJA POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1999, Texas Instruments Incorporated