PTC PT8401

Princeton Technology Corp.
MP3 Audio Decoder
Tel : 886-2-29162151
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
PT8401
Description
The PT8401 is a single chip MPEG audio decoder capable of decoding all layers compressed elementary
streams, as specified in MPEG 1 and MPEG 2 ISO standards. With external A/D converter, it can also
compress incoming signal by using ADPCM algorithm, therefore it can also playback ADPCM bitstream.
Features
??
??
??
??
??
??
??
??
??
??
??
Supports all the sampling frequency of MPEG1 (32/44.1/48KHz), MPEG2(16/22.05/24KHz) and
MPEG2.5
Serial Bit Stream Input Interface
I2S/Normal Audio Data Output Format delivered via an Serial Bus
Power Saving Mode Support
Supports DAC Master Clock (256*fs / 384*fs for 16 / 24 bit DAC)
Built-in Tone and Digital Equalizer Control
Bass Booster Function
3D Sound Effect Function
Pause Function
Fast Forward Function
Available in 44-pin Plastic LQFP Package
Applications
??
??
??
??
??
??
Portable MP3 Player (Flash Memory Type)
PDA with MP3 Player
Cellular Phone with MP3 Player
Hard Disk MP3 Player (IDE Interface)
CD MP3 Player
Digital Voice Recorder
PT8401 v 1.3
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Princeton Technology Corp.
MP3 Audio Decoder
PT8401
Block Diagram
?P
Host Interface
ROM
PLL
RAM
DSP Core
Frame
Buffer
Bitstream
Input
Output
Buffer
Serial Interface
Audio Data
Figure 1: PT8401 Block Diagram
Typical Application Diagram
Flash Memory
Host ? P
MP3 Decoder
LCD
Panel
Audio
DAC
Key Pads
Figure 2: Typical Application Diagram
PT8401 v 1.3
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Princeton Technology Corp.
MP3 Audio Decoder
PT8401
GPIO3
GPIO2
GPIO1
GPIO0
MCLKO
PWRDWN
V SS
DSPRDY
PV DD
FILT
PV SS
Pin Configuration
44 43 42 41 40 39 38 37 36 35 34
PA V D D 1
PA V SS 2
33 G PIO 4
32 B C K 1
IIC C 3
31 B _E N A 1
IIC D 4
30 B D 1
V DD 5
29 V SS
CLKI 6
V SS 7
TE
28 V D D
M P3 D ecoder
27 G PIO 5
8
26 A C K Q O
/RST 9
PD _R E Q 10
25 A L R Q O
24 A D Q O
N C 11
23 G PIO 8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
TEST1
PD_ENA
PD_ACK
GPIO6
12 13 14 15 16 17 18 19 20 21 22
Figure 3: PT8401 Pin Configuration
PT8401 v 1.3
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MP3 Audio Decoder
PT8401
Pin Description
Pin Name
PAVDD
I/O
Power
Description
Analog Supply Positive for PLL
Pin No.
PAVSS
Power
Analog Supply Ground for PLL
2
IICC
1
2
I/O
I C Clock Line
3
2
IICD
I/O
I C Data Line
VDD
CLKI
VSS
TE
/RST
Power
I
Power
I
I
Digital Supply Positive
Clock Input
Digital Supply Ground
Test Enable
Reset
PD_REQ
O
Parallel Data Request
10
NC
-
No Connection
11
GPIO6
I/O
General Purpose IO 6
12
PD_ACK
O
Parallel Data Acknowledge Signal
13
PD_ENA
I
Parallel Data Enable Transmission
14
TEST1
I
Test Pin. It is advisable to connect to Digital Ground
15
GPIO15/DATA_REQ
I/O
General Purpose IO15 or Data Request
16
GPIO14
I/O
General Purpose IO14
17
GPIO13
I/O
General Purpose IO13
18
GPIO12/ACKQI2
I/O
General Purpose IO12 or Second Serial Input Clock
GPIO11/ALRQI2
I/O
GPIO10/ADQI2
GPIO9
GPIO8
ADQO
I/O
I/O
I/O
O
General Purpose IO11 or Second Serial Input Frame
Identification
General Purpose IO10 or Second Serial Input Data
General Purpose IO9
General Purpose IO8
Serial Output Data
19
20
24
ALRQO
O
Serial Output Frame Identification
25
ACKQO
O
Serial Output Clock
26
GPIO5
I/O
GPIO5 or Start-Up Configuration
27
VDD
Power
Digital Supply Positive
VSS
BD1
B_ENA1
Power
I
I
Digital Supply Ground
First Serial Input Data
First Serial Input Frame Identification
28
29
30
31
PT8401 v 1.3
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5
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7
8
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MP3 Audio Decoder
PT8401
Pin Name
BCK1
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
MCLKO
VSS
PWRDWN_
DSPRDY
PVDD
I/O
I
I/O
I/O
I/O
I/O
I/O
O
Power
I
O
Power
Description
First Serial Input Clock
General Purpose IO4 or Start-Up Configuration
General Purpose IO3 or Start-Up Configuration
General Purpose IO2 or Start-Up Configuration
General Purpose IO1 or Start-Up Configuration
General Purpose IO0 or Start-Up Configuration
Master Oversampling Clock Output for DAC
Digital Supply Ground
Power Down Control
Decoder Operation Ready
Digital Supply Positive for PLL
Pin No.
32
33
34
35
36
37
38
39
40
41
PVSS
Power
Digital Supply Ground for PLL
43
FILT
Passive
Connect to Capacitor 820pF.
44
42
Functional Description
System and Interface Description
PT8401 is capable of decoding MPEG audio bitstream through a serial data interface. With proper external
A/D converter, it is capable of encoding audio signal by the ADPCM Method. The primary operating mode
of PT8401 is divided into three sections: MP3 Decoder, ADPCM Encoder and ADPCM Decoder.
MP3 Decoding Mode: The bitstream input may either be from the first serial bitstream interface or parallel
bitstream interface depending on the SP_SEL command. After processing, the audio data is outputted
through the serial output interface. The controller can get bitstream information through GPIO or I2C
interface even while the process is still in operation.
ADPCM Encoding Mode: By connecting additional A/D to the second serial data interface and by
issuing several basic commands like SetMode and AdpcmMode via I2C or GPIO, PT8401 can start
ADPCM encoding, bitstream output through GPIO. Please refer to the Start-up Configuration and GPIO
Setting Section for detailed timing diagram.
PT8401 v 1.3
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MP3 Audio Decoder
PT8401
ADPCM Decoding Mode : Same as MP3 Decoding Mode, except that the commands SetMode and
AdpcmMode have to be set to ADPCM Decoding Mode.
The basic operation modes of PT8401 are Stop and Play. After all the necessary commands are set properly
(like SP_SEL , PLL setting etc.), PT8401 will enter decoding/encoding process by issuing a Play command
at address 0x40 through I2C interface.
Besides, the MP3 decoding, PT8401 offers two additional modes, namely: Pause and Fast Forward . The
Pause Mode will stop MP3 decoding, wait for the PLAY command set to the other mode. If PLAY=0x01
is issued, PT8401 will resume playing from the broken point. The Fast Forward Mode is achieved with the
help of command Fward_Num(number of frame to play) and Skip_Num(number of frame to skip.
Serial Audio Interface
SERIAL OUTPUT INTERFACE
In the serial audio output interface, following signals are generated:
MCLK : Master Clock, configured as 256fs or 384fs according to Mclk Sel command.
ADQO: Serial Data Output
ACKQO: Bit Clock Output, derived from MCLK
ALRQO: Left/Right Channel Word Selection
ACKQO
ADQO
ALRQO
15 14 13 12 11
4 3 2 1 0
15 14 13 12 11
4 3 2 1 0
15
Left Channel
Right Channel
Figure 4: Serial Audio Output Timing
PT8401 v 1.3
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MP3 Audio Decoder
PT8401
The default output waveform is show in Figure 4. Each PCM sample consists of a 2's complement
16-bit MSB-first data and another 16 bits of blank data forming 32 bits data in each channel.
ADQO is valid at the rising edge of ACKQO and the last bit of a sample is aligned with the edges of
ALRQO. However, PT8401 offers 3-bit, eight combinations to fit different kinds of audio DACs via
the start-up configuration or command registers.
Bit 0 : 32/16 bits per sample selection. If 16-bit per sample is selected, each channel contains only
16-bit MSB first data.
0
Left
1
Left
Right
Right
Bit 1 : ALRQO Left Channel indicating Low/High selection.
Bit 2 : Delay Selection. When this bit is set, the transition of ALRQO is one clock cycle earlier.
This is called I2S format.
Left Channel
ALRQO
0
Right Channel
15 14 13 12 11
4 3 2 1 0
15 14 13 1211
4 3 2 1 0
ADQO
1
15 14 13 12
5 4 3 2 1 0
15 14 1312
5 4 3 2 1 0
FIRST SERIAL BITSTREAM INPUT INTERFACE
Serial Bitstream (regardless of whether it is an MPEG audio or ADPCM speech bitstream) comes from
this port. The following three signals are needed to make a complete transfer.
BD1: Serial Bitstream Data Input.
BCK1: Bit Clock Input.
B_ENA1: Serial Data Enable Signal, Active: Low
DATA_REQ : Data Request Signal.
PT8401 v 1.3
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MP3 Audio Decoder
PT8401
Microcontroller can transmit bitstream via the following two types of connections. Please refer to the
diagram below.
BCK1
OR
BD1
B_ENA1
Data_valid
Data_invalid
Data_valid
Data_valid
Data_invalid
Figure 5: Timing of First Serial Bitstream Input Interface.
The maximum bit rate of MPEG is 448kbps. Basically, the speed of input bitstream clock must be
greater than 448KHz. An input bitstream clock of 1MHz is recommended. Since the microcontroller
doesn’t know when to start the bitstream transmission, the DATA_REQ signal is needed to act as the
bitstream transmission indicator. When DATA_REQ is "High", the microcontroller starts another
new bitstream packet transmission. If the DATA_REQ is set to "Low" , bitstream transmission is
terminated. Please refer to Figure 6.
DATA_REQ
Figure 6: Timing of DATA_REQ Signal
SECOND SERIAL DATA INPUT INTERFACE
This port is usually connected with the A/D Converter and is used for speech encoding. The timing of
this port is the similar as that of the serial output interface, except that the signals of the Second Serial
Data Input Interface are inputs. This port also can connect with various ADCs through the setting in
the Start-up Configuration or command register SetSAI2. Two bits setting is described below :
Bit 0 : ALRQI2 Left Channel indicating Low/High Selection.
Bit 1 : Delay Selection. When this bit is set, the transition of ALRQI2 is one clock cycle earlier.
This is called I2S format.
PT8401 v 1.3
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MP3 Audio Decoder
PT8401
PARALLEL BITSTREAM INPUT INTERFACE
In addition to the serial interface, the microcontroller can also transmit bitstreams via parallel interface.
Parallel Mode is set via the Start-up Configuration or command register SP_SEL. Parallel data
transmission consists of the following signals:
1. PD_REQ : Parallel Data Request. A bundle of data may be requested and this is sent from
PT8401.
2. PD_ENA : Parallel Data Enable. This means that the data in the data bus is valid. This is sent
from microcontroller.
3. PD_ACK : Parallel Data Acknowledge. This means that the decoder has received one byte
successfully. This is sent from PT8401.
4. P_DATA : Parallel Data Bus is GPIO[15:8]. The GPIO15 is MSB and GPIO8 is LSB.
Due to some low speed transmission, the microcontroller may not be fast enough to know that PT8401
has closed communication. Please refer to the example described in Figure 6 wherein during the byte
7 transmission. In this example, PT8401 did not recognize an Acknowledge signal; thus, byte 7 was
not transmitted correctly.
In order to avoid instability, it is better not to set SP_SEL frequently.
PD_REQ
PD_ENA
PD_ACK
P_DATA[7:0]
B0
B1
B2
B6
B7
B8
Figure 7 : Parallel Data Transmission Timing
PT8401 v 1.3
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MP3 Audio Decoder
PT8401
PLL
PLL circuit provides two internal clocks, one for DSP and the other for the audio interface. The DSP clock
rate is twice that of the external clock while the audio interface clock rate is dependent on the external
audio clock. In order to satisfy different frequency settings, the PLL clock is divided into two sets.
PLLSet PLLfraction are used for all frequencies.
The default PLL setting assumes that the input frequency is 16.9344MHz. However, other frequency
is acceptable, too. Please refer tables below for more information. If frequency is not on the list, please
contact to PTC.
Table 1. Settings for input frequency 10 MHz.
Register Name
Value
PLLSet
0x3c20
PLLFraction
0x7f80
Table 2. Settings for input frequency 14.318MHz.
Register Name
Value
PLLSet
0x3b30
PLLFraction
0x7e88
Table 3. Settings for input frequency 14.725MHz.
PT8401 v 1.3
Register Name
Value
PLLSet
0x3930
PLLFraction
0x7ed1
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MP3 Audio Decoder
PT8401
Table 4. Settings for input frequency 12.288MHz.
Register Name
Value
PLLSet
0x3b28
PLLFraction
0x7e5e
The sampling frequency of ADPCM encoding is controlled by Serial Input Port 2; however, the
sampling frequency of ADPCM decoding is controlled via the setting of PLL. The microcontroller has
to be set properly to get the right listening results. The default setting for ADPCM decoding assumes
that sampling frequency is 8kHz; however, 11.025kHz and 12kHz are selectable, too.
Start-up Configuration and General Purpose IO
PT8401 offers another easy way to configure the basic start-up setting without using the external controller.
It is called “Start-up” Configuration. GPIO pins are configured as input pins before RESET. After RESET,
those values are latched to be the basic configuration of PT8401. After start-up, the GPIO pins are
configured as output pins.
START-UP CONFIGURATION
GPIO
Name
0
SetMode
1
PT8401 v 1.3
Description
"0" : MPEG Mode
"1" : ADPCM Mode
AdpcmMode "0" : Bitstream Decoding
"1" : Sample Encoding.
2
SP_SEL
3
Set_SAO[0]
4
Set_SAO[1]
5
Set_SAO[2]
6
Set_SAI2[0]
7
Set_SAI2[1]
"0" : First Serial Port
"1" : Parallel Input Port Selection (only in MPEG Decoding).
Set Serial Output Port. Same as Main Function Selection.
Set Second Serial Input Port. Same as Main Function Selection.
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MP3 Audio Decoder
PT8401
GPIO PINS DURING MPEG DECODING
GPIO Name
Description
0
MPEG ID
“0” : MPEG2
“1” : MPEG1
1
Layer Info
“0” : Layer III.
“1” : Layer I or Layer II.
3,2
Sampling
Frequency
“00” : 44.1/22.05 kHz
“01” : 48/24 kHz
“10” : 32/16 kHz
“11” : reserved.
4
FRAME
SYNC_INFO
An indicator for frame sync information. The period between two sync info
is less than 72 ms. The controller can treat this pin as a new frame is
decoded or if decoder is dead. Or every time this pin go high, new ancillary
is update and can be download via I2C interface.
5
CRC ERROR
“0” : no error.
“1” : CRC_error or bitstream error.
6
Half_second
Half second indicator. The period between two high signal is half second
15
Demand Signal
(No effect during parallel mode).
“0”: no request.
“1”: Ask for bitstream input.
GPIO PINS DURING ADPCM ENCODING
GPIO
Name
0
Enc_Dat[0]
1
Enc_Dat[1]
2
Enc_Dat[2]
3
Enc_Dat[3]
4
Enc_ENA
PT8401 v 1.3
Description
LSB, 4-bit data during ADPCM Encoding.
MSB
"0" : Disable Encoded Data Output
"1" : Enable Encoded Data Output
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MP3 Audio Decoder
PT8401
SPEECH ADPCM ENCODING TIMING
ALRQI2
Enc_ENA
Enc_DAT[3:0]
D1
D2
D3
DN
D N +1
D N +2
Figure 8: Speech ADPCM Encoding Timing.
In Figure 8, ALRQI2 assumes that the command register Set_SAI2 bit 0 is"0". If Bit 0 is set to "1",
the signal ALRQI2 in Figure 8 should be inverted.
I2C Microprocessor Interface
PT8401 uses I2C interface for communication. I2C communicate with multi devices using only two lines;
namely: IICD and IICC. The following control and status registers are accessible via I2C interface.
??
S is a Start Bit (a start condition). Any transmission must start with it.
??
Dev_addr is a 7-bit Device Address Identifier. Each device can only have one address. PT8401 is
fixed at "0110100b".
??
R/W issues a read or write operation
??
A/A is an Acknowledge Bit. It is performed in the receiver and is used to inform the transmitter
that the data is properly received or used to stop data transmission.
??
P is a Stop Bit. Any sequence must end with it.
The I2C write operation is a word (two-byte) writing mode, as described in Figure 8. Multi-byte write is
PT8401 v 1.3
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MP3 Audio Decoder
PT8401
allowable, but PT8401 only receives it and does nothing. PT8401 is capable of the following read
operations: Word Read, Multi-byte Read and Repeat Address Read Modes. In the Repeat Address Read
Mode, the last successful transmitted address is read again even if the decoder has not been informed of the
address. This mode is usually used for the address 0x00, FrameCount, which maybe the most frequently
requested address in all command registers. In PT8401, only the command AncillaryData is allowed to use
the Multi-byte Read Mode. Since A, no acknowledge signal is controlled by the receiver (microcontroller)
in the read mode, the microcontroller will receive repeated data after 3rd byte in other command registers in
Multi-byte Read Mode.
S
D ev_addr W
A
Sub_addr
A
Word Read
S
D ev_addr W
A
Sub_addr
A S
D ev_addr R
A
high_byte
Multi-byte Read
S
D ev_addr W
A
Sub_addr
A S
D ev_addr R
A
1st_byte
Repeat Address
Read
S
D ev_addr R
A
high_byte
A
Word Write
high_byte
low _byte
A
low _byte
A P
A
A
A P
low _byte
2nd_byte
A
A
Last_byte
A P
A P
Figure 9: Read and Write Sequence for I2C Protocol.
POWER DOWN SETTING
To enter the Power Down Mode, Pin 40 (PWRDWN_) must be set to “LOW’. The DSPRDY pin
goes to low, this indicates that PT8401 is already been powered down. There are two types of Power
Down Modes, namely: Sleep Mode and the Deep Sleep Mode. The Sleep Mode turns off the DSP
clock and only preserves PLL clock. The Deep Sleep on the other hand turns off DSP and PLL clock.
All the commands that have been previously set will preserved. PT8401’s default is the sleep mode.
With the command Pwr_Dwn_Reg set to 0x04 before power down, deep sleep is achieved.
PT8401 v 1.3
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MP3 Audio Decoder
PT8401
Command Registers
MAIN FUNCTION COMMAND
Address Register Name
0x40
Play
Description
0/1: stop/run the current operation mode. After reset, the controller set
Default R/W
0x0
R/W
0x0
R/W
0x0
R/W
1 : Mute all output signals.
0x0
R/W
necessary command, then set this bit to 1 to start decode.
2: Pause Mode.
3: Fast Forward Mode.
4: Second Fast Forward Mode
Note:2,3,4 only work on MPEG Decoding Mode.
0x41
SetMode
0 : MPEG Decoding Mode.
1 : Start ADPCM Mode.
2 : PCM bypass from First Serial Port.
3 : PCM bypass from Second Serial Port.
0x42
ADPCMMode 0 : ADPCM Decoding Mode
1 : ADPCM Encoding Mode.
0x43
Mute
0x44
Volume
Output Volume Control. The range is between 0 dB and -96dB(0x60).
0x0
R/W
0x45
SP_SEL
Serial/Parallel Input Selection.
0x0
R/W
0x0
R/W
0 : First Input Serial Port Input is selected.
1 : Input Parallel Port Input is selected.
Note : After this bit is set, it is better to run Software Reset to prevent
instability.
0x46
Set_SAO
Serial Output Port Mode Setting.
Bit 0
0 : 32 bits per sample mode.
1 : 16 bits per sample mode.
Bit 1
0 : ALRQ Signal. Left is "Low".
1 : ALRQ Signal. Left is "High".
Bit 2
0 : Relative Timing No Delay to ALRQ.
1 : Relative Timing One Delay to ALRQ.
Bit 3
0 : Data is Left Alignment.
1 : Data is Right Alignment
PT8401 v 1.3
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MP3 Audio Decoder
0x46
Set_SAO
Bit 5:4
PT8401
00 : ACQO is generated from the Internal Clock.
0x0
R/W
0x0
R/W
0x0
R/W
0x0
W
01 : ACQO is generated from the External Clock.
10 : MCLKO is generated from the External Clock.
0x47
Set_SAI2
Second Serial Input Port Mode Setting
Bit 0
0 : ALRQ Signal. Left is "Low".
1 : ALRQ Signal. Left is "High".
Bit 1
0 : Relative Timing No Delay to ALRQ.
1 : Relative Timing One Delay to ALRQ.
0x59
ADPCM_FS_SE ADPCM Decoding Mode Sampling Frequency Selection.
L
0 : 11.025kHz.
1 : 12kHz.
2 : 8kHz
0x5a
Soft_Reset
Set to 1 to software reset, but all the command registers keep the
setting values.
0x5e
Pwr_Dwn_Reg
Power Down Control Register.
0x0
W
0x63
Fward_Num
Fast Foward Mode, number of frame to be play
0x6
W
0x64
Skip_Num
Fast Foward Mode, number of frame to be skip
0x6
W
PLL SETTING COMMAND
Address Register Name
0x48
MclkSel
Description
Master Oversampling Output Clock Selection.
Default
R/W
0x0
R/W
“0” : 256fs.
“1” : 384fs.
0x4b
PllSet
PLL Control Parameter Setting.
0x3b28
R/W
0x4c
PllFraction
15-bit PLL Fraction Parameter Setting.
0x7e5e
R/W
PT8401 v 1.3
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MP3 Audio Decoder
PT8401
TONE AND 3D CONTROL COMMANDS
Tone control is allowable. It ranges up to +-15 dB cut or enhancement for bass and treble filter with
step size of 1.5 dB. Although overflow prevention is performed, under the Bass Enhancement Mode,
the gain may be reduced so that overflow may be prevented in advance by issuing the prescale
command. This would generate better listening results.
The cut off frequency for bass filter is about 250Hz for MPEG1, 125Hz for MPEG2.
The cut off frequency for treble filter is about 10kHz for MPEG1, 5kHz for MPEG2.
The 3D Mode controls the 3D effect function. Please take note that if the 3D Mode is enabled, the tone
and balance controls are disabled.
Address
Register
Name
0x50
Tone3D
0x51
0x52
0x53
0x54
PT8401 v 1.3
Description
Default
R/W
"0" : Enable Tone Control.
"1" : Enable 3D Control.
0x0
R/W
Bass
"0x1" to "0xa" with step size 1.5dB bass enhancement.
Maximum up to 15 dB.
"0xb" to "0x14" with step size 1.5dB bass attenuation..
Minimum down to –15 dB
Default is" 0x0", no enhancement.
0x0
R/W
Treble
"0x1" to "0xa" with step size 1.5dB treble enhancement.
Maximum up to 15 dB.
"0xb" to "0x14" with step size 1.5dB treble attenuation.
Minimum down to –15 dB.
Default is "0x0", no enhancement.
0x0
R/W
0x0
R/W
0x3
R/W
Prescale Prescale command to reduce overall gain. Range is between
0dB(0x0) and –96dB(0x60)
3D_Effect Control the Depth of 3D’s Effect. Range is between
between 0dB(0x0) and –96dB(0x60)
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MP3 Audio Decoder
PT8401
BALANCE CONTROL COMMAND
Balance control is implemented through 4 coefficients setting as shown in Figure 9.
Original L
Prescale
Mix_LL
+
Volume
Final L
+
Volume
Final R
Mix_LR
Mix_RL
Original R
Prescale
Mix_RR
Figure 10: Balance Control Relation.
Address Register
Name
Description
Default
R/W
0x55
Mix_LL
Mix original left channel to output left channel with 0 dB
to –96 dB(0x60).
Default is 0x0.
0x0
R/W
0x56
Mix_RL
Mix original right channel to output left channel with
0 dB to –96 dB(0x60).
Default is 0x60.
0x60
R/W
0x57
Mix_LR
Mix original left channel to output right channel with
0 dB to –96 dB(0x60).
Default is 0x60
0x60
R/W
0x58
Mix_RR
Mix original right channel to output right channel with
0 dB to –96 dB(0x60).
Default is 0x0.
0x0
R/W
PT8401 v 1.3
Page 18
Updated March 2002
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MP3 Audio Decoder
PT8401
STATUS REGISTER COMMANDS
Address Register Name
Description
Default R/
W
0x00
Frame Count
Increase one every frame, but if the following condition happen, it clear to 0.
0x0
R
0x0
R
0x0
R
1.enter stop command , 2.crc check error. 3.bitstream error.
0x01
MPEG Header
Bit
Info1
4..15
Item
Description
Reserved
3
ID
1:MPEG1 0:MPEG2
1:2
Layer
11 : Layer I
10 : Layer II
01 : Layer III
00 : reserved
0x02
0
Protection
0 : protected by CRC, 1 : don’t
MPEG Header
Bit
Item
Description
Info2
12..15 Bit Rate
Index(kbps)
mpeg1
mpeg1
mpeg1
mpeg2
mpeg2
layer I
Layer II
layer III
Layer I
Layer II
Layer III
PT8401 v 1.3
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Updated March 2002
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Princeton Technology Corp.
MP3 Audio Decoder
PT8401
0000
Free
Free
Free
Free
Free
0001
32
32
32
32
8
0010
64
48
40
48
16
0011
96
56
48
56
24
0100
128
64
56
64
32
0101
160
80
64
80
40
0110
192
96
80
96
48
0111
224
112
96
112
56
1000
256
128
112
128
64
1001
288
160
128
144
80
1010
320
192
160
160
96
1011
352
224
192
176
112
1100
384
256
224
192
128
1101
416
320
256
224
144
1110
448
384
320
256
160
1111
forbidden forbidden forbidden forbidden forbidden
10..11 Sampling
MPEG1
MPEG2
00
44.1kHz
22.05kHz
01
48kHz
24kHz
10
32kHz
16kHz
11
reserved
reserved
frequency
9
Padding_bit
8
Private bit
Bit
Item
6..7
mode
4..5
0xff
Description
00
Stereo
01
Joint_stereo
10
Dual_channel
11
Single_channel
Mode_extension
Layer I,II
Layer III
mode=joint_stereo
Intensity_ Ms_stereo
R
Stereo
PT8401 v 1.3
Page 20
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MP3 Audio Decoder
0x03
PT8401
00
Subband=4-31
Off
Off
01
Subband=8-31
On
Off
10
Subband=12-31
Off
On
11
Subband=16-31
On
On
3
copyright
0:not protected, 1: protected
2
original
0:copy, 1:original
0..1
emphasis
Indicate which type of emphesis is used
00
None
01
50/15 microseconds
10
reserved
11
CCITT J.17
NumAncillaryBits Current frame contain number of ancillary bits contain in current frame. Update in 0x0
R
every frame.
0x04.
AncillaryData
Current frame’s ancillary data. Update in every frame. Maximum is 56 bytes.
0x0
R
0x05
Error Status
Bit 0 : Set to 1 : indicates CRC check error.
0x0
R
Bit 1 : Set to 1 means bitstream error. The following several condition may cause
error :
1). Information in MPEG header point to “reserved” condition.(layer to “00”,
sampling frequency to “11”).
2). Bit rate index point to free and forbidden condition.
Electrical Characteristics
Absolute Maximum Ratings
Symbol
Parameter
VSUP
Digital supply voltage
TA
Ambient Operating Temperature
Pin Name
Min.
Max.
Unit
VDD
2.7
4
V
-10
85
?C
Recommended Operating Conditions
Symbol
TA
PT8401 v 1.3
Parameter
Pin
Name
Min. Typ. Max. Unit
Ambient Operating
25
Page 21
?C
Updated March 2002
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MP3 Audio Decoder
PT8401
temperature
VSUP
Digital supply voltage
VDD
3.3
V
INPUT LEVEL :
Symbol
VIH
VIL
Parameter
Pin Name
Min.
Typ.
Max.
Input high
/RST,PD_ENA,
1.7
voltage @ VDD = PWR_DWN, IICC, 1.7
2.7V ~ 4V
IICD, GPIO
1.9
Unit
VDD
V
2.7
3.3
4.0
Input low
voltage @ VDD =
2.7V ~ 4V
0.6
2.7
0.8
3.3
1.0
4.0
OUTPUT LEVEL :
Symbol
VOH
VOL
Parameter
Pin Name
Min.
Output
high
voltage
ADQO,ALRQO,
ACKQO,PD_REQ,
PD_ACK,DSP_RDY
Output low
voltage
ADQO,ALRQO,
VSS+0.1
ACKQO,PD_REQ,
VSS+0.1
PD_ACK,DSP_RDY VSS+0.1
Typ.
Max.
Unit
VDD
VDD-0.1
V
2.7
VDD-0.1
3.3
VDD-0.1
4.0
2.7
3.3
4.0
Current consumption
At Ta = 0 to 70 ,
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
IDD
Current
All
85
mA
VDD = 4V
IDD
consumption
supply
64
mA
VDD = 3.3V
pins
45
mA
VDD = 2.7V
IDD
I2C Bus Characteristics
Symbol
PT8401 v 1.3
Parameter
Pin
Min.
Typ.
Page 22
Max.
Unit
Test Condition
Updated March 2002
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MP3 Audio Decoder
PT8401
Name
2
FI2C
I C bus frequency
IICC
TI2C1
I2C start condition
setup time
IICC,
IICD
TI2C2
I2C stop condition
setup time
Khz
@CLKI =
8Mhz
250
ns
@CLKI =
8Mhz
IICC,
IICD
250
ns
@CLKI =
8Mhz
TI2C3
I2C Clock low pulse IICC
time
600
ns
@CLKI =
8Mhz
TI2C4
I2C Clock high
pulse time
IICC
600
ns
@CLKI =
8Mhz
TI2C5
I2C data hold time
before rising edge
of clock
IICC
80
ns
@CLKI =
8Mhz
TI2C6
I2C data hold time
after falling edge of
clock
IICC
80
ns
@CLKI =
8Mhz
TI2COL1
I2C data output
IICC,
hold time after
IICD
falling edge of clock
30
ns
@CLKI =
8Mhz,
FI2C= 400Khz
TI2COL2
I2C data output
setup time before
rising edge of clock
0
ns
@CLKI =
8Mhz
PT8401 v 1.3
IICC,
IICD
400
Page 23
Updated March 2002
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Princeton Technology Corp.
MP3 Audio Decoder
PT8401
t I2C4
H
L
IICC
t I2C1
H
L
t I2C3
t I2C5
t I2C6
IICD as input
t i2COL2
H
L
t I2C2
t I2COL1
IICD as output
I2S Characteristics - Serial input
Symbol
Parameter
2
Pin Name
Min Typ.
Max. Unit
tBCK
I S clock input
clockperiod
BCK1
tBDSTP
I2S data setup
time before
falling edge
clock
BCK1,
BD1
10
3
ns
tBDHD
I2S data hold
BCK1,
time after falling BD1
edge of clock
10
3
ns
PT8401 v 1.3
Test Conditions
ns
Page 24
@ CLKI =
16.9344MHz,
44.1Khz/Stereo,
32 bits
Updated March 2002
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Princeton Technology Corp.
MP3 Audio Decoder
PT8401
tB C K
BCK1
H
L
H
B_ENA1 L
BD1
H
L
tB D STP
tB D H D
I2S Characteristics - Serial output
Symbol
Parameter
2
Pin Name
Min Typ.
Max. Unit
tACK
I S clock output
frequency
ACKQO
tALR
I2S worst strobe
hold time after
falling edge of
clock
ACKQO,
ALRQO
1
3
ns
tADQ
I2S data hold
time after falling
edge of clock
ACKQO,
ADQO
1
3
ns
PT8401 v 1.3
354
Page 25
ns
Test Conditions
@ CLKI =
16.9344MHz,
44.1Khz/Stereo,
32 bits
Updated March 2002
Princeton Technology Corp.
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Fax: 886-2-29174598
URL: http://www.princeton.com.tw
MP3 Audio Decoder
PT8401
t ACK
H
ACKQO
L
ALRQO H
L
tA L R
ADQO
H
L
tA D O
Firmware Characteristics
Symbol
Parameter
Pin
Min
Name
Typ.
Max.
Unit
Test Conditions
24
72
ms
MPEG1 layer 3,
44.1Khz,
128Kbits/sec
Synchronization Times
tmpgsync
Synchronization on
MPEG bitstreams
Order Information
Valid Part Number
PT8401
PT8401 v 1.3
Package Type
44-pins, LQFP Package
Page 26
Updated March 2002
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Princeton Technology Corp.
MP3 Audio Decoder
PT8401
Application Circuit
Crystal
Flash Memory
/RST
MP3 Decoder
ACKQO
ALRQO
Host ? P
IICD
IICC
DATA_RQ
BD1
L
DAC
R
ADQO
MCLKO
B_ENA1
BCK1
MIC
OP
PT8401 v 1.3
ADQI2
ADC
ALRQI2
ACQI2
Page 27
Updated March 2002
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MP3 Audio Decoder
PT8401
Package Information
44 -Pin, LQFP Package (Body Size: 10x10 mm, Pitch: 0.80mm, THK Body:
1.40mm)
D
D1
A
A2
-A-
A1
-B-
L1
E
E1
-D-
e
c
b
1
-C-
SEATING PLANE
2
R1
R2
-H-
GAUGE PLANE
0.25mm
S
L
3
PT8401 v 1.3
Page 28
Updated March 2002