STMICROELECTRONICS STA015


STA015 STA015B STA015T
MPEG 2.5 LAYER III AUDIO DECODER
WITH ADPCM CAPABILITY
PRODUCT PREVIEW
SINGLE CHIP MPEG2 LAYER 3 DECODER
SUPPORTING:
- All features specified for Layer III in ISO/IEC
11172-3 (MPEG 1 Audio)
- All features specified for Layer III in ISO/IEC
13818-3.2 (MPEG 2 Audio)
- Lower sampling frequencies syntax extension,
(not specified by ISO) called MPEG 2.5
DECODES LAYER III STEREO CHANNELS,
DUAL CHANNEL,
SINGLE CHANNEL
(MONO)
SUPPORTING ALL THE MPEG 1 & 2 SAMPLING FREQUENCIES AND THE EXTENSION TO MPEG 2.5:
48, 44.1, 32, 24, 22.05, 16, 12, 11. 025, 8 KHz
ACCEPTS MPEG 2.5 LAYER III ELEMENTARY COMPRESSED BITSTREAM WITH
DATA RATE FROM 8 Kbit/s UP TO 320 Kbit/s
ADPCM CODEC CAPABILITIES:
- sample frequency from 8 kHz to 32 kHz
- sample size from 8 bits to 32 bits
- encodingalgorithm: DVI,
ITU-G726pack (G723-24,G721,G723-40)
- Tone controlandfast-forward capability
EASY PROGRAMMABLE GPSO INTERFACE
FOR ENCODED DATA UP TO 5Mbit/s
(TQFP44 & LFBGA 64)
DIGITAL VOLUME
BASS & TREBLE CONTROL
SERIAL BITSTREAM INPUT INTERFACE
EASY PROGRAMMABLE ADC INPUT INTERFACE
ANCILLARY DATA EXTRACTION VIA I2C INTERFACE.
SERIAL PCM OUTPUT INTERFACE (I2S
AND OTHER FORMATS)
PLL FOR INTERNAL CLOCK AND FOR OUTPUT PCM CLOCK GENERATION
CRC CHECK AND SYNCHRONISATION ERROR DETECTION WITH SOFTWARE INDICATORS
I2C CONTROL BUS
LOW POWER 2.4V CMOS TECHNOLOGY
WIDE RANGE OF EXTERNAL CRYSTALS
FREQUENCIES SUPPORTED
February 2000
ORDERING NUMBERS: STA015 (SO28)
STA015T (TQFP44)
STA015B (LFBGA 64)
APPLICATIONS
PC SOUND CARDS
MULTIMEDIA PLAYERS
VOICE RECORDERED
DESCRIPTION
The STA015 is a fully integrated high flexibility
MPEG Layer III Audio Decoder, capable of decoding Layer III compressed elementary streams,
as specified in MPEG 1 and MPEG 2 ISO standards. The device decodes also elementarystreams
compressed by using low sampling rates, as specified by MPEG 2.5.
STA015 receives the input data through a Serial
Input Interface. The decoded signal is a stereo,
mono, or dual channel digital output that can be
sent directly to a D/A converter, by the PCM Output Interface. This interface is software programmable to adapt the STA015 digital output to the
most common DACs architectures used on the
market.
The functional STA015 chip partitioning is described in Fig.1 and Fig.2.
1/44
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
STA015-STA015B-STA015T
Figure 1a. BLOCK DIAGRAM for TQFP44 and LFBGA64 package
SDA
SCL
31
32
TQFP44
2
I C CONTROL
GPIO
INTERFACE
34
SDI
SCKR
BIT_EN
DATA-REQ
36
38
SERIAL
INPUT
INTERFACE
DSP BASED
42
27
BUFFER
256 x 8
MPEG L III
ADPCM
CORE
PARSER
VOLUME
& TONE
CONTROL
OUTPUT
BUFFER
PCM
OUTPUT
INTERFACE
44
2
40
SCK_ADC
CRCK_ADC
SDI_ADC
26
24
3
ADC
INPUT
INTERFACE
4
GPSO
INTERFACE
SYSTEM & AUDIO CLOCKS
28
33
25
15
RESET
13
XTI
22
XTO
SDO
SCKT
LRCKT
OCLK
GPSO_REQ
GPSO_SCKL
GPSO_DATA
12
TESTEN
D99AU1116
FILT
Figure 1b. BLOCK DIAGRAM for SO28 package
SDA
SCL
3
4
SO28
2
I C CONTROL
SDI
SCKR
BIT_EN
DATA-REQ
SCK_ADC
CRCK_ADC
SDI_ADC
5
6
7
SERIAL
INPUT
INTERFACE
DSP BASED
9
28
BUFFER
256 x 8
MPEG L III
ADPCM
CORE
PARSER
VOLUME
& TONE
CONTROL
OUTPUT
BUFFER
PCM
OUTPUT
INTERFACE
8
27
25
11
12
ADC
INPUT
INTERFACE
SYSTEM & AUDIO CLOCKS
26
RESET
2/44
10
21
20
XTI
XTO
24
TESTEN
19
FILT
D99AU1117
SDO
SCKT
LRCKT
OCLK
STA015-STA015B-STA015T
Figure 2. PIN CONNECTIONS
VDD_1
1
28
VSS_1
2
27
LRCK_ADC
SDA
3
26
RESET
SCL
4
25
SDI_ADC
SDI
5
24
TESTEN
OUT_CLK/DATA_REQ
SCKR
6
23
VDD_4
BIT_EN
7
22
VSS_4
SRC_INT/SCK_ADC
8
21
XTI
SDO
9
20
XTO
SCKT
10
19
FILT
LRCKT
11
18
PVSS
OCLK
12
17
PVDD
VSS_2
13
16
VDD_3
VDD_2
14
15
VSS_3
SO28
8
7
6
5
4
SCKT
IODATA[7]
SDO
IODATA[6]
SRC_INT/SCK_ADC
IODATA[5]
BIT_EN
IODATA[4]
SCKR
GPIO/STROBE
SDI
D99AU1061
44
43
42
41
40
39
38
37
36
35
34
N.C.
1
33
GPSO_DATA
LRCKT
2
32
SCL
OCLK
3
31
SDA
GPSO_REQ
4
30
VSS_1
VSS_2
5
29
VDD_1
VDD_2
6
28
GPSO_SCKR
VSS_3
7
27
OUT_CLK/DATA_REC
VDD_3
8
26
LRCK_ADC
N.C.
9
25
RESET
PVDD
10
24
SDI_ADC
PVSS
11
23
N.C.
3
2
12
13
14
15
16
17
18
19
20
21
22
FILT
XTO
IODATA[3]
XTI
IODATA[2]
N.C.
IODATA[1]
VSS_4
IODATA[0]
VDD_4
TESTEN
TQFP44
D99AU1062
1
A1 = SDI
B2 = SCKR
D4 = BIT_EN
D1 = SRC_INT
E2 = SDO
F2 = SCKT
H1 = LRCKT
H3 = OCLK
F3 = VSS_2
E4 = VDD_2
G4 = VSS_3
G5 = VDD_3
F5 = PVDD
G6 = PVSS
A
B
C
D
E
F
G
H
G7 = FILT
G8 = XTO
F7 = XTI
E7 = VSS_4
C8 = VDD_4
D7 = TESTEN
A7 = SDI_ADC
B6 = RESET
A5 = LRCK_ADC
C5 = OUT_CLK/DATA_REQ
B5 = VDD_1
B4 = VSS_1
A4 = SDA
B3 = SCL
C2 = GPIO_STROBE
C3 = IODATA [4]
E3 = IODATA [5]
D2 = IODATA [6]
F1 = IODATA [7]
G3 = GPSO_REQ
F8 = IODATA [3]
F6 = IODATA [2]
E6 = IODATA [1]
C7 = IODATA [0]
C6 = GPSO_SCKR
A2 = GPSO_DATA
D00AU1149
LFBGA64
3/44
STA015-STA015B-STA015T
feedback line (see DATA_REQ pin) to the bitstream source (tipically an MCU).
1. OVERVIEW
1.1 - MP3 decoder engine
1.2 - ADPCM encoder/decoder engine
The MP3 decoder engine is able to decode any
Layer III compliant bitstream: MPEG1, MPEG2
and MPEG2.5 streams are supported. Besides
audio data decoding the MP3 engine also performs ANCILLARY data extraction: these data
can be retrieved via I2C bus by the application
microcontroller in order to implement specific
functions.
Decoded audio data goes through a software volume control and a two-band equalizer blocks before feeding the output I2S interface. This results
in no need for an external audio processor.
MP3 bitstream is sent to the decoder using a simple serial input interface (see pins SDI, SCKR,
BIT_EN and DATA_REQ), supporting input rate
up to 20 Mbit/s. Received data are stored in a
256 bytes long input buffer which provides a
This device also embeds a multistandard ADPCM
encoder/decoder supporting different sample
rates (from 8 KHz up to 32 KHz) and different
sample sizes (from 8 bit to 32 bits). During encoding process two different interfaces can be
used to feed data: the serial input interface (same
interface used also to feed MP3 bitstream) or the
ADC input interface, which provides a seamless
connection with an external A/D converter. The
currently used interface is selected via I2C bus.
Also to retrieve encoded data two different interfaces are available: the I2C bus or the faster
GPSO output interface. GPSO interface is able to
output data with a bitrate up to 5 Mbit/s and its
control pins (GPSO_SCKR, GPSO_DATA and
GPSO_REQ) can be configured in order to easily
fit the target application.
ABSOLUTE MAXIMUM RATINGS
Symbol
VDD
Parameter
Power Supply
Value
Unit
-0.3 to 4
V
V
Vi
Voltage on Input pins
-0.3 to VDD +0.3
VO
Voltage on output pins
-0.3 to VDD +0.3
V
Tstg
Storage Temperature
-40 to +150
°C
Toper
Operative ambient temp
-20 to +85
°C
Value
Unit
85
°C/W
THERMAL DATA
Symbol
Rth j-amb
4/44
Parameter
Thermal resistance Junction to Ambient
STA015-STA015B-STA015T
PIN DESCRIPTION
SO28 TQFP44 LFBGA64
1
29
B5
2
30
B4
3
31
A4
Pin Name
VDD_1
VSS_1
SDA
Type
I/O
Function
Supply Voltage
Ground
i2C Serial Data +
Acknowledge
2
I C Serial Clock
Receiver Serial Data
Receiver Serial Clock
Bit Enable
4
5
6
7
32
34
36
38
B3
A1
B2
D4
SCL
SDI
SCKR
BIT_EN
I
I
I
I
8
40
D1
SRC_INT/SCK_ADC
I
9
10
11
12
42
44
2
3
E2
F2
H1
H3
SDO
SCKT
LRCLKT
OCLK
O
O
O
I/O
13
14
15
16
17
18
19
5
6
7
8
10
11
12
F3
E4
G4
G5
F5
G6
G7
VSS_2
VDD_2
VSS_3
VDD_3
PVDD
PVSS
FILT
O
20
21
13
15
G8
F7
XTO
XTI
O
I
Ground
Supply Voltage
Ground
Supply Voltage
PLL Power
PLL Ground
PLL Filter Ext. Capacitor
Conn.
Crystal Output
Crystal Input (Clock Input)
22
23
24
19
21
22
E7
C8
D7
VSS_4
VDD_4
TESTEN
I
Ground
Supply Voltage
Test Enable
25
26
24
25
A7
B6
SDI_ADC
RESET
I
I
ADC Data Input
System Reset
27
28
26
27
A5
C5
I
O
20
18
16
14
37
39
41
43
35
4
28
33
C7
E6
F6
F8
C3
E3
D2
F1
C2
G3
C6
A2
LRCK_ADC
OUT_CLK/
DATA_REQ
IODATA[0]
IODATA[1]
IODATA[2]
IODATA[3]
IODATA[4]
IODATA[5]
IODATA[6]
IODATA[7]
GPIO_STROBE
GPSO_REQ
GPSO_SCKR
GPSO_DATA
ADC Left/Right Clock
Buffered Output Clock/
Data Request Signal
GPIO Data Line
GPIO Data Line
GPIO Data Line
GPIO Data Line
GPIO Data Line
GPIO Data Line
GPIO Data Line
GPIO Data Line
GPIO Strobe Signal
GPSO Request Signal
GPSO Serial Clock
GPSO Serial Data
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
O
Interrupt Line/ADC Serial
Clock
TransmitterSerial Data(PCM Data)
Transmitter Serial Clock
Transmitter Left/Right Clock
Oversampling Clock for DAC
PAD Description
CMOS Input Pad Buffer
CMOS 4mA Output Drive
CMOS Input Pad Buffer
CMOS Input Pad Buffer
CMOS Input Pad Buffer
CMOS Input Pad Buffer with
pull up
CMOS Input Pad Buffer
CMOS
CMOS
CMOS
CMOS
CMOS
4mA Output Drive
4mA Output Drive
4mA Output Drive
Input Pad Buffer
4mA Output Drive
CMOS 4mA Output Drive
Specific Level Input Pad
(see paragraph 2.1)
CMOS Input Pad Buffer with
pull up
CMOS Input Pad Buffer
CMOS Input Pad Buffer with
pull up
CMOS Output Pad Buffer
CMOS 4mA Output Drive
CMOS 4mA Schmitt Trigger
Bidir Pad Buffer
CMOS Output Pad Buffer
CMOS Input Pad Buffer
CMOS Output Pad Buffer
Note: In functional mode TESTEN must be connected to VDD.
5/44
STA015-STA015B-STA015T
1. ELECTRICAL CHARACTERISTICS: VDD = 3.3V ±0.3V; Tamb = 0 to 70°C; Rg = 50Ω unless otherwise
specified
DC OPERATING CONDITIONS
Symbol
VDD
Tj
Parameter
Value
Power Supply Voltage
2.4 to 3.6V
Operating Junction Temperature
-20 to 125°C
GENERAL INTERFACE ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Note
IIL
Low Level Input Current
Without pull-up device
Vi = 0V
-10
10
µA
1
IIH
High Level Input Current
Without pull-up device
Vi = VDD
-10
10
µA
1
Electrostatic Protection
Leakage < 1µA
V
2
Vesd
2000
Note 1: The leakage currents are generally very small, < 1nA. The value given here is a maximum that can occur after an electrostatic stress
on the pin.
Note 2: Human Body Model.
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
VIL
Low Level Input Voltage
VIH
High Level Input Voltage
Vol
Low Level Output Voltage
Voh
High Level Output Voltage
Test Condition
Min.
Typ.
Max.
Unit
0.2*VDD
V
0.8*VDD
Note
V
Iol = Xma
0.4V
0.85*VDD
V
1, 2
V
1, 2
Note 1: Takes into account 200mV voltage drop in both supply lines.
Note 2: X is the source/sink current under worst case conditions and is reflected in the name of the I/O cell according to the drive capability.
Symbol
Parameter
Ipu
Pull-up current
Rpu
Equivalent Pull-up
Resistance
Test Condition
Min.
Typ.
Max.
Vi = 0V; pin numbers 7, 24
and 26
-25
-66
-125
50
Unit
Note
µA
1
kΩ
Note 1: Min. condition: V DD = 2.7V, 125°C Min process
Max. condition: V DD = 3.6V, -20°C Max.
POWER DISSIPATION
Symbol
PD
6/44
Parameter
Power Dissipation
@ VDD = 3V
Test Condition
Min.
Typ.
Max.
Unit
Sampling_freq ≤24 kHz
76
mW
Sampling_freq ≤32 kHz
79
mW
Sampling_freq ≤48 kHz
85
mW
Note
STA015-STA015B-STA015T
Figure 3. Test Circuit (refer to SO28 package)
3
28
OUT_CLK/DATA_REQ
VDD
4
1
9
100nF
10
2
VSS
VDD
11
14
12
100nF
5
13
VSS
VDD
6
7
16
25
100nF
15
VSS
VDD
8
27
23
21
100nF
VDD
PVDD
4.7µF
20
22
VSS
SDA
SCL
SDO
SCKT
LRCKT
OCLK
SDI
SCKR
BIT_EN
SDI_ADC
SCR_INT
LRCK_ADC
XTI
XTO
10K
19
17
4.7µF
18
100nF
26
24
RESET
1K
TESTEN
470pF
VSS
PVDD
PVSS
4.7nF
PVSS
D00AU1143
Figure 4. Test Load Circuit
PVSS
Test Load
Output
VDD
SDA
IOL
OUTPUT
Other Outputs
IOL
IOH
1mA
100µA
100µA
CL
VREF
100pF
3.6V
100pF
1.5V
VREF
CL
IOH
D98AU967
2. FUNCTIONAL DESCRIPTION
2.1 - Clock Signal
The STA015 input clock is derivated from an external source or from a industry standard crystal
oscillator, generating input frequencies of 10,
14.31818 or 14.7456 MHz.
Symbol
Parameter
VIL
Low Level Input Voltage
VIH
High Level Input Voltage
Other frequencies may be supported upon request to STMicroelectronics. Each frequency is
supported by downloading a specific configuration file, provided by STM
XTI is an input Pad with specific levels.
Test Condition
Min.
Typ.
Max.
VDD-1.8
VDD-0.8
Unit
V
V
CMOS compatibility
The XTI pad low and high levels are CMOS compatible; XTI pad noise margin is better than typical
CMOS pads.
TTL compatibility
The XTI pad low level is compatible with TTL while the high level is not compatible (for example if VDD =
3V TTL min high level = 2.0V while XTI min high level = 2.2V)
7/44
STA015-STA015B-STA015T
Figure 5. PLL and Clocks Generation System
XTI
N
PFD
CP
R
C
M
C
VCO
Disable PLL
OCLK
Switching
Circuit
FRAC
X
XTI2OCLK
DCLK
Update FRAC
S
XTI2DSPCLK
16 to 24 bits/word, by setting the output precision
with PCMCONF (16, 18, 20 and 24 bits mode)
register. Data can be output either with the most
significant bit first (MS) or least significant bit first
(LS), selected by writing into a flag of the
PCMCONF register.
Figure 8 gives a description of the several
STA015 PCM Output Formats.
The sample rates set decoded by STA015 is described in Table 1.
2.4 - PCM Output Interface
The decoded audio data are output in serial PCM
format. The interface consists of the following signals:
SDO
PCM Serial Data Output
SCKT
PCM Serial Clock Output
LRCLK
Left/Right Channel Selection Clock
The output samples precision is selectable from
Figure 6. PCM Output Formats
16 SCLK Cycles
LRCKT
16 SCLK Cycles
16 SCLK Cycles
16 SCLK Cycles
16 SCLK Cycles
SDO
M
S
L
S
M
S
L
S
M
S
L
S
M
S
L
S
PCM_ORD = 0
PCM_PREC is 16 bit mode
SDO
L
S
M
S
L
S
M
S
L
S
M
S
L
S
M
S
PCM_ORD = 1
PCM_PREC is 16 bit mode
32 SCLK Cycles
LRCKT
32 SCLK Cycles
32 SCLK Cycles
32 SCLK Cycles
M
S
SDO
SDO
0
SDO
L
S
0
M
S
M
S
L
S
MSB
SDO
M
S
0
M
S
L
S
L
S
0
0 M
S
0
L
S
MSB
M
S
0
M
S
L
S
M
S
32 SCLK Cycles
L
S
0
0
0
L
S
L
S
M
S
MSB
M
S
0
L
S
M
S
L
S
M
S
0
0
0
L
S
L
S
M
S
L
S
M
S
MSB
M
S
PCM_FORMAT = 1
PCM_DIFF = 1
0
L
S
PCM_FORMAT = 0
PCM_DIFF = 0
PCM_FORMAT = 0
PCM_DIFF = 1
0
L
S
PCM_FORMAT = 1
PCM_DIFF = 1
Table 1: MPEG Sampling Rates (KHz)
8/44
MPEG 1
MPEG 2
48
24
MPEG 2.5
12
44.1
22.05
11.025
32
16
8
STA015-STA015B-STA015T
2.5 - STA015 Operation Mode
The STA015 can work in two different modes,
called Multimedia Mode and Broadcast Mode.
normally to operate in Broadcast Mode. In both
modes the MPEG Synchronisation is automatic
and transparent to the user.
In Multimedia Mode (default mode) STA015 decodes the incoming bitstream, acting as a master
of the data communication from the source to itself.
This control is done by a specific buffer management, controlled by STA015 embedded software.
The data source, by monitoring the DATA_REQ
line, send to STA015 the input data, when the
signal is high (default configuration).
The communication is stopped when the
DATA_REQ line is low.
In this mode the fractional part of the PLL is disabled and the audio clocks are generated at
nominal rates. Fig. 7 describes the default
DATA_REQ signal behaviour. Programming
STA015 it is possible to invert the polarity of the
DATA_REQ line (register REQ_POL).
2.6 - STA015 Decoding States
There are three different decoder states: Idle,
Init, and Decode. Commands to change the de2
coding states are described in the STA015 I C
registers description.
Figure 7.
SOURCE STOPS TRANSMITTING DATA
SOURCE STOPS TRANSMITTING DATA
DATA_REQ
SOURCE SEND DATA TO STA015
Idle Mode
In this mode the decoder is waiting for the RUN
command. This mode should be used to initialise
the configuration registers of the device. The
DAC connected to STA015 can be initialised during this mode (set MUTE to 1).
PLAY
MUTE
Clock State
X
0
Not Running
PCM Output
0
X
1
Running
0
Init Mode
”PLAY” and ”MUTE” changes are ignored in this
mode. The internal state of the decoder will be
updated only when the decoder changes from the
state ”init” to the state ”decode”. The ”init” phase
ends when the first decoded samples are at the
output stage of the device.
D00AU1144
Decode Mode
This mode is completely described by the following table:
In Broadcast Mode, STA015 works receiving a
bitstream with the input speed regulated by the
source. In this configuration the source has to
guarantee that the bitrate is equivalent to the
nominal bitrate of the decoded stream.
To compensate the difference between the nominal and the real sampling rates, the STA015 embedded software controls the fractional PLL operation. Portable or Mobile applications need
PCM
Output
PLAY
MUTE
Clock State
Decoding
0
0
Not Running
0
No
0
1
Running
0
No
1
0
Running
Decoded
Samples
Yes
1
1
Running
0
Yes
9/44
STA015-STA015B-STA015T
Figure 8. MPEG Decoder Interfaces.
µP
XTI
XTO
FILT
IIC
SCL
DATA_REQ
PLL
SDA
IIC
SDI
DATA
SOURCE
SDO
MPEG
DECODER
SCKR
SCKT
DAC
LRCKT
BIT_EN
SERIAL AUDIO INTERFACE
RX
TX
OCLK
D98AU912
Figure 9. Serial Input Interface Clocks
SDI
DATA
SCKR
SCLK_POL=0
SCKR
SCLK_POL=4
BIT_EN
DATA VALID
D98AU968A
2.2 - Serial Input Interface
STA015 receives the input data (MSB first)
thought the Serial Input Interface (Fig.5). It is a
serial communication interface connected to the
SDI (Serial Data Input) and SCKR (Receiver Serial Clock).
The interface can be configured to receive data
sampled on both rising and falling edge of the
SCKR clock. The BIT_EN pin, when set to low,
forces the bitstream input interface to ignore the
incoming data. For proper operation Bit_EN line
should be toggled only when SCRK is stable low
(for both SCLK_POL configuration) The possible
configurations are described in Fig. 9.
2.3 - PLL & Clock Generator System
When STA015 receives the input clock, as described in Section 2.1, and a valid layer III input
bitstream, the internal PLL locks, providing to the
DSP Core the master clock (DCLK), and to the
10/44
IGNORED
DATA IGNORED
Audio Output Interface the nominal frequencies of
the incoming compressed bit stream. The STA015
PLL block diagram is describedin Figure 5.
The audio sample rates are obtained dividing the
oversampling clock (OCLK) by software programmable factors. The operation is done by STA015 embeddedsoftware and it is transparentto the user.
The STA015 PLL can drive directly most of the commercial DACs families, providing an over sampling
clock, OCLK, obtained dividing the VCO frequency
with a software programmable dividers.
2.4 - GPSO Output Interface
In order to retrieve ADPCM encoded data a General Purpose Serial Output interface is available
(in TQFP44 and LFBGA64 packages only). The
maximum frequency for
clock is
the
GPSO_SCKR DSP system clock frequency divided by 3 (i.e. 8.192 MHz @ 24.58MHz). The interface is based on a simple and configurable 3lines protocol, as described by figure 10.
STA015-STA015B-STA015T
Figure 10.
GPSO_SCKR
STA015
GPSO_DATA
GPSO_REQ
MCU
GPSO_SCKR
GPSO_REQ
GPSO_DATA
D00AU1145
To enable the GPSO interface bit GEN of
GPSO_ENABLE register must be set. Using the
GPSO_CONF register the protocol can be configured in order to provide outcoming data on rising/falling edge of GPSO_SCKR input clock; the
GPSO_REQ request signal polarity (usually connected to an MCU interrupt line) can be configured as well.
ADC Inteface
Beside the serial input interface based on SDI
and SCKR lines a 3 wire flexible and user configurable input interface is also available, suitable to
interface with most A/D converters. To configure
2
this interface 4 specific I C registers are available
(ADC_ENABLE, ADC_CONF, ADC_WLEN and
ADC_WPOS). Refer to registers description for
more details.
General Purpose I/O Interface
A new general purpose I/O interface has been
added to this device (TQFP44 and LFBGA64
only). Actually only the strobe line is used in
INPUT (data to encode)
ADPCM to provide an interrupt; the use of the
other bits is still to be defined. The related configuration register is GPIO_CONF. See the following summary for related pin usage:
Name
I/ODATA [0]
....................
I/ODATA [7]
GPIO_STROBE
Description
GPIO data line
GPIO strobe line
2.5 ADPCM Encoding: Overview
According to the previously described interfaces
there are 4 ways to manage ADPCM data stream
while encoding. Input interface can be either the
serial receiver block (SDI + SCKR + DATA_REQ
lines) or the ADC specific interface.
Output interfaces can be either the I 2C bus (with
or without interrupt line) or the GPSO high-speed
serial interface (GPSO_REQ + GPSO_ DATA +
GPSO_SCKR lines). This result in the following 4
methods to handle encoding flow:
Output (encoded data)
ADC I/F (SDI_ADC + LRCK_ADC + SCK_ADC)
ADC I/F (SDI_ADC + LRCK_ADC + SCK_ADC)
SERIAL I/F (SCKR + SDI + DATA_REQ)
SERIAL I/F (SCKR + SDI + DATA_REQ) (*)
Dir
I/O
....
I/O
I/O
GPSO I/F (GPSO_REQ + GPSO_DATA +
GPSO_SCKR)
2
I C + Interrupt (SCL + SDA + DATA_REQ)
GPSO I/F (GPSO_REQ + GPSO_DATA +
GPSO_SCKR)
I2C (polling) (SCL + SDA)
Available on
package
TQFP44
LFBGA64
SO28/TQFP44
LFBGA64
TQFP44
LFBGA64
SO28/TQFP44
LFBGA64
(*) STA013 Compatible mode
Figure. 11
LRCK_ADC
SDI_ADC
SCK_ADC
GPSO_REQ
ADC I/F
SCKR
GPSO
GPSO_DATA
GPSO_SCKR
ENCOD
ENGINE
SDI
DATA_REQ
MUX
SERIAL
RECEIVER
I2C
SDA
SCL
DATA_REQ
D99AU1064
11/44
STA015-STA015B-STA015T
The following 4 figures (fig. 12, 13, 14, 15) show
the available connection diagrams as for as
ADPCM encoding function. As shown in the figures some configuration is not available in SO28
package.
Figure 12. Input from BITSTREAM, Output from
I2C
SDI
LRCKT
SCKR
MCU
DATA_REQ
BIT_EN
I 2C
SCKT
STA015
SDO
SO28
TQFP44
LFBGA64
OCLK
DAC
D99AU1121A
Figure 14. Input from BITSTREAM, Output from
GPSO
Figure 13. Input from ADC, Output from I2C +
IRQ
GPSO_DATA
GPSO_SCKR
GPSO_REQ
I2 C
SDI
DATA_REQ
LRCKT
LRCKT
SCKR
SCKT
MCU
DATA_REQ
SCKT
STA015
SDO
TQFP44
LFBGA64
OCLK
DAC
BIT_EN
MCU
I2C
SDO
D99AU1122A
SDI_ADC
ADC
STA015
SO28
TQFP44
LFBGA64
SLAVE
DAC
Figure 15. Input from ADC, Output from GPSO
OCLK
GPSO_DATA
MCU
MCU
I2 C
STA015
LRCK_ADC
ADC
SDI_ADC
LRCKT
GPSO_REQ
SCKT
LRCKT
DATA_REQ
SCK_ADC
GPSO_SCKR
SO28
TQFP44
LFBGA64
MASTER
LRCK_ADC
SCKT
DAC
SDO
SCK_ADC
ADC
SDI_ADC
STA015
TQFP44
LFBGA64
DAC
SDO
OCLK
OCLK
MASTER
D99AU1124A
D99AU1123A
3 - I2C BUS SPECIFICATION
3. 1 - COMMUNICATION PROTOCOL
The STA015 supports the I2C protocol. This protocol defines any device that sends data on to the
bus as a transmitter and any device that reads
the data as a receiver. The device that controls
the data transfer is known as the master and the
others as the slave. The master always starts the
transfer and provides the serial clock for synchronisation. The STA015 is always a slave device in
all its communications.
3.1.0 - Data transition or change
Data changes on the SDA line must only occur
when the SCL clock is low. SDA transition while
the clock is high are used to identify START or
STOP condition.
12/44
3.1.1 - Start condition
START is identified by a high to low transition of
the data bus SDA signal while the clock signal
SCL is stable in the high state.
A START condition must precede any command
for data transfer.
STA015-STA015B-STA015T
3.1.2 - Stop condition
STOP is identified by low to high transition of the
data bus SDA signal while the clock signal SCL is
stable in the high state. A STOP condition terminates communications between STA015 and the
bus master.
The 7 most significant bits are the device address
2
identifier, corresponding to the I C bus definition.
For the STA015 these are fixed as 1000011.
The 8th bit (LSB) is the read or write operation
RW, this bit is set to 1 in read mode and 0 for
write mode. After a START condition the STA015
identifies on the bus the device address and, if a
match is found, it acknowledges the identification
on SDA bus during the 9th bit time. The following
byte after the device identification byte is the internal space address.
3.1.3 - Acknowledge bit
An acknowledge bit is used to indicate a successful data transfer. The bus transmitter, either master or slave, releases the SDA bus after sending
8 bit of data.
During the 9th clock pulse the receiver pulls the
SDA bus low to acknowledge the receipt of 8 bits
of data.
3.3 - WRITE OPERATION (see fig. 16)
Following a START condition the master sends a
device select code with the RW bit set to 0.
The STA015 acknowledges this and waits for the
byte of internal address.
After receiving the internal bytes address the
STA015 again responds with an acknowledge.
3.1.4 - Data input
During the data input the STA015 samples the
SDA signal on the rising edge of the clock SCL.
For correct device operation the SDA signal has
to be stable during the rising edge of the clock
and the data can change only when the SCL line
is low.
3.3.1 - Byte write
In the byte write mode the master sends one data
byte, this is acknowledged by STA015. The master then terminates the transfer by generating a
STOP condition.
3.2 - DEVICE ADDRESSING
To start communication between the master and
the STA015, the master must initiate with a start
condition. Following this, the master sends onto
the SDA line 8 bits (MSB first) corresponding to
the device select address and read or write
mode.
3.3.2 - Multibyte write
The multibyte write mode can start from any internal address. The transfer is terminated by the
master generating a STOP condition.
Figure 16. Write Mode Sequence
ACK
BYTE
WRITE
ACK
DEV-ADDR
START
ACK
SUB-ADDR
DATA IN
RW
STOP
ACK
ACK
DEV-ADDR
MULTIBYTE
WRITE
START
ACK
SUB-ADDR
ACK
DATA IN
DATA IN
RW
STOP
D98AU825B
Figure 17. Read Mode Sequence
ACK
CURRENT
ADDRESS
READ
DEV-ADDR
START
NO ACK
DATA
RW
STOP
ACK
RANDOM
ADDRESS
READ
DEV-ADDR
START
SEQUENTIAL
CURRENT
READ
ACK
SUB-ADDR
RW
RW= ACK
HIGH
DEV-ADDR
ACK
DEV-ADDR
START
RW
ACK
DATA
NO ACK
DATA
STOP
ACK
DATA
NO ACK
DATA
START
STOP
ACK
SEQUENTIAL
RANDOM
READ
DEV-ADDR
START
ACK
SUB-ADDR
RW
ACK
DEV-ADDR
START
ACK
DATA
RW
ACK
DATA
NO ACK
DATA
D98AU826A
STOP
13/44
STA015-STA015B-STA015T
3.4 - READ OPERATION (see Fig. 17)
3.4.1 - Current byte address read
The STA015 has an internal byte address
counter. Each time a byte is written or read, this
counter is incremented.
For the current byte address read mode, following a START condition the master sends the device address with the RW bit set to 1.
The STA015 acknowledges this and outputs the
byte addressed by the internal byte address
counter. The master does not acknowledge the
received byte, but terminates the transfer with a
STOP condition.
3.4.2 - Sequential address read
This mode can be initiated with either a current
address read or a random address read. However in this case the master does acknowledge
the data byte output and the STA015 continues to
output the next byte in sequence.
To terminate the streams of bytes the master
does not acknowledge the last received byte, but
terminates the transfer with a STOP condition.
The output data stream is from consecutive byte
addresses, with the internal byte address counter
automatically incremented after one byte output.
2
4 - I C REGISTERS
The following table gives a description of the
MPEG Source Decoder (STA015) register list.
The first column (HEX_COD) is the hexadecimal
code for the sub-address.
The second column (DEC_COD) is the decimal
code.
The third column (DESCRIPTION) is the description of the information contained in the register.
The fourth column (RESET) inidicate the reset
value if any. When no reset value is specifyed,
the default is ”undefined”.
The fifth column (R/W) is the flag to distinguish
register ”read only” and ”read and write”, and the
useful size of the register itself.
Each register is 8 bit wide. The master shall operate reading or writing on 8 bits only.
I2C REGISTERS
HEX_COD
DEC_COD
DESCRIPTION
RESET
R/W
$00
0
VERSION
$01
1
IDENT
0xAC
R (8)
$05
5
PLLCTL [7:0]
0xA1
R/W (8)
$06
6
PLLCTL [20:16] (MF[4:0]=M)
0x0C
R/W (8)
$07
7
PLLCTL [15:12] (IDF[3:0]=N)
0x00
R/W (8)
$0C
12
REQ_POL
0x01
R/W (8)
$0D
13
SCLK_POL
0x04
R/W (8)
$0F
15
ERROR_CODE
0x00
R (8)
$10
16
SOFT_RESET
0x00
W (8)
$13
19
PLAY
0x01
R/W(8)
$14
20
MUTE
0x00
R/W(8)
$16
22
CMD_INTERRUPT
0x00
R/W(8)
24
DATA_REQ_ENABLE
0x00
R/W(8)
ADPCM_DATA_1 to ADPCM_DATA_18
0x00
R/W (8)
$18
$40 - $51
64 - 81
R (8)
$40
64
SYNCSTATUS
0x00
R (8)
$41
65
ANCCOUNT_L
0x00
R (8)
$42
66
ANCCOUNT_H
0x00
R (8)
$43
67
HEAD_H[23:16]
0x00
R(8)
$44
68
HEAD_M[15:8]
0x00
R(8)
$45
69
HEAD_L[7:0]
0x00
R(8)
$46
70
DLA
0x00
R/W (8)
$47
71
DLB
0xFF
R/W (8)
$48
72
DRA
0x00
R/W (8)
14/44
STA015-STA015B-STA015T
I2C REGISTERS (continued)
HEX_COD
DEC_COD
DESCRIPTION
RESET
R/W
0xFF
R/W (8)
$49
73
DRB
$4D
77
CHIP_MODE
0x00
R/W (2)
$4E
78
CRCR
0x00
R/W (1)
$50
80
MFSDF_441
0x00
R/W (8)
$51
81
PLLFRAC_441_L
0x00
R/W (8)
$52
82
ADPCM_DATA_READY
0x00
R/W (1)
$52
82
PLLFRAC_441_H
0x00
R/W (8)
$53
83
ADPCM_SAMPLE_FREQ
0x00
R/W (4)
$54
84
PCM DIVIDER
0x03
R/W (8)
$55
85
PCMCONF
0x21
R/W (8)
$56
86
PCMCROSS
0x00
R/W (8)
$61
97
MFSDF (X)
0x07
R/W (8)
$63
99
DAC_CLK_MODE
0x00
R/W (8)
$64
100
PLLFRAC_L
0x46
R/W (8)
$65
101
PLLFRAC_H
0x5B
R/W (8)
$67
103
FRAME_CNT_L
0x00
R (8)
$68
104
FRAME_CNT_M
0x00
R (8)
$69
105
FRAME_CNT_H
0x00
R (8)
$6A
106
AVERAGE_BITRATE
0x00
$71
113
SOFTVERSION
$72
114
RUN
0x00
R/W (8)
$77
119
TREBLE_FREQUENCY_LOW
0x00
R/W (8)
$78
120
TREBLE_FREQUENCY_HIGH
0x00
R/W (8)
$79
121
BASS_FREQUENCY_LOW
0x00
R/W (8)
$7A
122
BASS_FREQUENCY_HIGH
0x00
R/W (8)
$7B
123
TREBLE_ENHANCE
0x00
R/W (8)
$7C
124
BASS_ENHANCE
0x00
R/W (8)
$7D
125
TONE_ATTEN
0x00
R/W (8)
$7E - B5
126 - 181
R (8)
R (8)
ANC_DATA_1 to ANC_DATA_56
0x00
R (8)
$B6
182
ISR
0x00
R/W (1)
$B8
184
ADPCM_CONFIG
0x00
R/W (2)
$B9
185
GPSO_ENABLE
0x00
R/W (1)
$BA
186
GPSO_CONF
0x00
R/W (2)
$BB
187
ADC_ENABLE
0x00
R/W (1)
$BC
188
ADC_CONF
0x00
R/W (5)
$BD
189
ADPCM_FRAME_SIZE
0x00
R/W (8)
$BE
190
ADPCM_INT_CFG
0x00
R/W (8)
$BF
191
GPIO_CONF
0x00
R/W (2)
$C0
192
ADC_ WLEN
0x0F
R/W (5)
$C1
193
ADC_ WPOS
0x00
R/W (5)
$C2
194
ADPCM_SKIP_FRAME
0x00
R/W (8)
Note:
1) The HEX_COD is the hexadecimal adress that the microcontroller has to generate to access the information.
2) RESERVED: register used for production test only, or for future use.
15/44
STA015-STA015B-STA015T
4.1 - STA015 REGISTERS DESCRIPTION
The STA015 device includes 256 I2C registers. In
this document, only the user-oriented registers
are described. The undocumented registers are
reserved. These registers must never be accessed (in Read or in Write mode). The ReadOnly registers must never be written.
The following table describes
the meaning of the
abbreviations used in the I2C registers description:
Symbol
Comment
NA
Not Applicable
UND
Undefined
PLLCTL
Address: 0x05 (05)
Type: R/W
Software Reset: 0xA1
Hardware Reset: 0xA1
MSB
b7
LSB
b6
b5
b4
b3
b2
b1
b0
XTO_ XTOD OCLK SYS2O PPLD XTI2DS XTI2O UPD_F
BUF
IS
EN
CLK
IS
PCLK CLK RAC
The VERSION register is read-only and it is used
to identify the IC on the application board.
UPD_FRAC: when is set to 1, update FRAC in
the switching circuit. It is set to 1 after autoboot.
XTI2OCLK: when is set to 1, use the XTI as input
of the divider X instead of VCO output. It is set to
0 on HW reset.
XTI2DSPCLK: when is to 1, set use the XTI as input of the divider S instead of VCO output. It is
set to 0 on HW reset.
PLLDIS: when set to 1, the VCO output is disabled. It is set to 0 on HW reset.
SYS2OCLK: when is set to 1, the OCLK frequency is equal to the system frequency. It is
useful for testing. It is set to 0 on HW reset.
OCLKEN: when is set to 1, the OCLK pad is enable as output pad. It is set to 1 on HW reset.
XTODIS: when is set to 1, the XTO pad is disable. It is set to 0 on HW reset.
XTO_BUF: when this bit is set, the pin nr. 28
(OUT_CLOCK/DATA_REQ) is enabled. It is set
to 0 after autoboot.
IDENT
Address: 0x01 (01)
Type: RO
Software Reset: 0xAC
Hardware Reset: 0xAC
PLLCTL (M)
Address: 0x06 (06)
Type: R/W
Software Reset: 0x0C
Hardware Reset: 0x0C
NC
No Charge
RO
Read Only
WO
Write Only
R/W
Read and Write
R/WS
Read, Write in specific mode
VERSION
Address: 0x00 (00)
Type: RO
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
V8
V7
V6
V5
V4
V3
V2
V1
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
1
0
1
0
1
1
0
0
IDENT is a read-only register and is used to identify the IC on an application board. IDENT always
has the value ”0xAC”
16/44
PLLCTL (N)
Address: 0x07 (07)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
The M and N registers are used to configure the
STA015 PLL by DSP embedded software.
M and N registers are R/W type but they are
completely controlled, on STA015, by DSP software.
STA015-STA015B-STA015T
MSB
REQ_POL
Address: 0x0C (12)
Type: R/W
Software Reset: 0x01
Hardware Reset: 0x00
LSB
b7
b6
b5
b4
b3
b2
b1
b0
X
X
EC5
EC4
EC3
EC2
EC1
EC0
X = don’t care
ERROR_CODE register contains the last error
occourred if any. The codes can be as follows:
The REQ_POL registers is used to program the
polarity of the DATA_REQ line.
MSB
Code
Description
0x00
No error since the last SW or HW Reset
LSB
0x01
CRC Failure
DATA not available
b7
b6
b5
b4
b3
b2
b1
b0
0x02
0
0
0
0
0
0
0
1
0x04
Ancillary data not read
0x10
Audio synch word not found
Default polarity (the source sends data when the
DATA_REQ line is high)
MSB
0x2X
MPEG Header error
0x3X
MPEG Decoding errors
LSB
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
1
0
1
Inverted polarity (the source sends data when the
DATA_REQ line is low)
SCKL_POL
Address: 0x0D (13)
Type: R/W
Software Reset: 0x04
Hardware Reset: 0x04
SOFT_RESET
Address: 0x10 (16)
Type: WO
Software Reset: 0x00
Hardware Reset: 0x00
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
X
X
X
X
X
X
X
0
1
X = don’t care; 0 = normal operation; 1 = reset
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
X
X
X
X
X
0
0
0
(1)
1
0
0
(2)
When this register is written, a soft reset occours.
The STA015 core command register and the interrupt register are cleared. The decoder goes in
to idle mode.
X = don’t care
SCKL_POL is used to select the working polarity
of the Input Serial Clock (SCKR).
(1) If SCKL_POL is set to 0x00, the data (SDI)
are sent with the falling edge of SCKR
and sampled on the rising edge.
(2) If SCKL_POL is set to 0x04, the data (SDI)
are sent with the rising edge of SCKR and
sampled on the falling edge.
ERROR_CODE
Address: 0x0F (15)
Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
PLAY
Address: 0x13 (19)
Type: R/W
Software Reset: 0x01
Hardware Reset: 0x01
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
X
X
X
X
X
X
X
0
1
X = don’t care; 0 = normal operation; 1 = play
The PLAY command is handled according to the
state of the decoder, as described in section 2.5.
PLAY only becomes active when the decoder is
in DECODE mode.
17/44
STA015-STA015B-STA015T
CMD_INTERRUPT
Address: 0x16 (22)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MUTE
Address: 0x14 (20)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB
LSB
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
b7
b6
b5
b4
b3
b2
b1
b0
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
0
1
1
X = don’t care; 0 = normal operation; 1 = mute
The MUTE command is handled according to the
state of the decoder, as described in section 2.5.
MUTE sets the clock running.
X = don’t care;
0 = normal operation;
1 = write into I 2C/Ancillary Data
The INTERRUPT is used to give STA015 the
command to write into the I2C/Ancillary Data
Buffer (Registers: 0x7E ... 0xB5). Every time the
Master has to extract the new buffer content it
writes into this register, setting it to a non-zero
value.
DATA_REQ_ENABLE
Address: 0x18 (24)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
Description
X
X
X
X
X
0
X
X
buffered output clock
X
X
X
X
X
1
X
X
request signal
The DATA_REQ_ENABLE register is used to
configure Pin n. 28 working as buffered output
clock or data request signal, used for multimedia
mode.
The buffered Output Clock has the same frequency than the input clock (XTI)
SYNCSTATUS
Address: 0x40 (64)
Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
X
X
X
X
X
X
SS1
SS0
0
0
Research of sync word
0
1
Wait for Confirmation
1
0
Synchronised
18/44
Description
STA015-STA015B-STA015T
ADPCM_DATA BUFFER
Address: 0x40 - 0x51 (64 - 81)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
HEAD_L[7:0]
MSB
MSB
b7
LSB
b6
b5
b4
b3
b2
b1
b0
ENCODED DATA N to N+18
ANCCOUNT_L
Address: 0x41 (65)
Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
ANCCOUNT_H
Address: 0x42 (66)
Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
ANCCOUNT_H
MSB
b7
LSB
b6
b5
b4
b3
b2
b1
AC15 AC14 AC13 AC12 AC11 AC10 AC9
b0
AC8
ANCCOUNT registers are logically concatenated
and indicate the number of Ancillary Data bits
available at every correctly decoded MPEG
frame.
HEAD_H[23:16]
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
X
X
X
H20
H19
H18
H17
H16
x = don’t care
HEAD_M[15:8]
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
H15
H14
H13
H12
H1‘1
H10
H9
H8
LSB
b7
b6
b5
b4
b3
b2
b1
b0
H7
H6
H5
H4
H3
H2
H1
H0
Address: 0x43, 0x44, 0x45 (67, 68, 69)
Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
Head[1:0] emphasis
Head[2] original/copy
Head[3] copyrightHead
[5:4] mode extension
Head[7:6] mode
Head[8] private bit
Head[9] padding bit
Head[11:10] sampling frequency index
Head[15:12] bitrate index
Head[16] protection bit
Head[18:17] layer
Head[19] ID
Head[20] ID_ex
The HEAD registers can be viewed as logically
concatenated to store the MPEG Layer III Header
content. The set of three registers is updated
every time the synchronisation to the new MPEG
frame is achieved
The meaning of the flags are shown in the following tables:
MPEG IDs
IDex
ID
0
0
MPEG 2.5
0
1
reserved
1
0
MPEG 2
1
1
MPEG 1
Layer
in Layer III these two flags must be set always to
”01”.
Protection_bit
It equals ”1” if no redundancy has been added
and ”0” if redundancy has been added.
19/44
STA015-STA015B-STA015T
Bitrate_index
indicates the bitrate (Kbit/sec) depending on the
MPEG ID.
bitrate index
’0000’
’0001’
’0010’
’0011’
’0100’
’0101’
’0110’
’0111’
’1000’
’1001’
’1010’
’1011’
’1100’
’1101’
’1110’
’1111’
ID = 1
free
32
40
48
56
64
80
96
112
128
160
192
224
256
320
forbidden
ID = 0
free
8
16
24
32
40
48
56
64
80
96
112
128
144
160
forbidden
Mode
Indicates the mode according to the following table. The joint stereo mode is intensity_stereo
and/or ms_stereo.
mode
’00’
’01’
’10’
’11’
mode specified
stereo
joint stereo (intensity_stereo and/or ms_stereo)
dual_channel
single_channel (mono)
Mode extension
These bits are used in joint stereo mode. They indicates which type of joint stereo coding method
is applied. The frequency ranges, over which the
intensity_stereo and ms_stereo modes are applied, are implicit in the algorithm.
Sampling Frequency
indicates the sampling frequency of the encoded
audio signal (KHz) depending on the MPEG ID
Sampling
Frequency
’00’
’01’
’10’
’11’
Private bit
Bit for private use. This bit will not be used in the
future by ISO/IEC.
MPEG1
MPEG2
MPEG2.5
44.1
48
32
reserved
22.05
24
16
reserved
11.03
12
8
reserved
Padding bit
if this bit equals ’1’, the frame contains an additional slot to adjust the mean bitrate to the sampling frequency, otherwise this bit is set to ’0’.
Copyright
If this bit is equal to ’0’, there is no copyright on
the bitstream, ’1’ means copyright protected.
Original/Copy
This bit equals ’0’ if the bitstream is a copy, ’1’ if it
is original.
Emphasis
Indicates the type of de-emphasis that shall be
used.
emphasis
’00’
’01’
’10’
’11’
emphasis specified
none
50/15 microseconds
reserved
CCITT J,17
DLA
Address: 0x46 (70)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB
b7
DLA7
0
0
0
:
0
20/44
b6
DLA6
0
0
0
:
1
b5
DLA5
0
0
0
:
1
b4
DLA4
0
0
0
:
0
b3
DLA3
0
0
0
:
0
b2
DLA2
0
0
0
:
0
b1
DLA1
0
0
1
:
0
LSB
b0
DLA0
0
1
0
:
0
Description
OUTPUT ATTENUATION
NO ATTENUATION
-1dB
-2dB
:
-96dB
STA015-STA015B-STA015T
DLA register is used to attenuate the level of
audio output at the Left Channel using the butterfly shown in Fig. 18. When the register is set to
255 (0xFF), the maximum attenuation is
achieved.
A decimal unit correspond to an attenuation step
of 1 dB.
Figure 18. Volume Control and Output Setup
DSP Left Channel
DLA
X
+
Output Left Channel
DLB
X
DRB
X
DRA
DSP Right Channel
X
+
Output Right Channel
D97AU667
DLB
Address: 0x47 (71)
Type: R/W
Software Reset: 0xFF
Hardware Reset: 0xFF
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
Description
DLB7
DLB6
DLB5
DLB4
DLB3
DLB2
DLB1
DLB0
OUTPUT ATTENUATION
0
0
0
0
0
0
0
0
NO ATTENUATION
0
0
0
0
0
0
0
1
-1dB
0
0
0
0
0
0
1
0
-2dB
:
:
:
:
:
:
:
:
:
0
1
1
0
0
0
0
0
-96dB
DLB register is used to re-direct the Left Channel
on the Right, or to mix both the Channels.
Default value is 0x00, corresponding at the maximum attenuation in the re-direction channel.
DRA
Address: 0x48 (72)
Type: R/W
Software Reset: 0X00
Hardware Reset: 0X00
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
Description
DRA7
DRA6
DRA5
DRA4
DRA3
DRA2
DRA1
DRA0
OUTPUT ATTENUATION
0
0
0
0
0
0
0
0
NO ATTENUATION
0
0
0
0
0
0
0
1
-1dB
0
0
0
0
0
0
1
0
-2dB
:
:
:
:
:
:
:
:
:
0
1
1
0
0
0
0
0
-96dB
DRA register is used to attenuate the level of
audio output at the Right Channel using the butterfly shown in Fig. 11. When the register is set to
255 (0xFF), the maximum attenuation is
achieved.
A decimal unit correspond to an attenuation step
of 1 dB.
21/44
STA015-STA015B-STA015T
DRB
Address: 0x49 (73)
Type: R/W
Software Reset: 0xFF
Hardware Reset: 0xFF
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
Description
DRB7
DRB6
DRB5
DRB4
DRB3
DRB2
DRB1
DRB0
OUTPUT ATTENUATION
0
0
0
0
0
0
0
0
NO ATTENUATION
0
0
0
0
0
0
0
1
-1dB
0
0
0
0
0
0
1
0
-2dB
:
:
:
:
:
:
:
:
:
0
1
1
0
0
0
0
0
-96dB
DRB register is used to re-direct the Right Channel on the Left, or to mix both the Channels.
Default value is 0x00, corresponding at the maximum attenuation in the re-direction channel.
CHIP_MODE
Address: 0x4D (77)
Type: R/W
Hardware Reset: 0x00
Using this register it’s possible to select which operation will be performed by the DSP.
Possible values are:
0x00 - MP3 decoding
0x01 - Reserved
0x02 - ADPCM Encoder
0x03 - ADPCM Decoder
The DSP will check for the value of this register
right after the RUN command ha s been issued
(refer to RUN register). After that no more checks
will be performed: therefore a SOFT_RESET
must be generated in order to change the device
mode.
curs, the current frame is skipped and the decoder is muted. The ERROR_CODE register is
affected with the value 0x01.
If CRC_EN bit is set, the result of the CRC check
is ignored, but the ERROR_CODE register is
nevertheless affected with the value 0x01 if a discrepance has occurred.
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
X
X
X
M4
M3
M2
M1
M0
This register contains the value for the PLL X
driver for the 44.1KHz reference frequency.
The VCO output frequency, when decoding
44.1KHzbitstream, is divided by (MFSDF_441 +1)
CRCR
Address: 0x4E (78)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
X
X
X
X
X
X
X
CRCEN
The CRC register is used to enable/disable the
CRC check. If CRC_EN bit is cleared, the CRC
value encoded in the bitstream is checked
against the hardware one. If a discrepance oc22/44
MFSDF_441
Address: 0x50 (80)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
PLLFRAC_441_L
Address: 0x51 (81)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
STA015-STA015B-STA015T
ADPCM_DATA_READY
Address: 0x52 (82)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
Software Reset: 0x00
Hardware Reset: 0x00
MSB
MSB
LSB
b7
b6
b5
X
X
X
b3
b2
b1
b0
ADPCM_SF
LSB
b7
b6
b5
b4
b3
b2
b1
b0
X
X
X
X
X
X
X
ADR
ADPCM_SF: Adpcm Sample Frequency
ADR: Adpcm Data Ready
This bit signal (ADPCM encoded data ready)
MSB
LSB
b6
b5
b4
b3
b2
PF15 PF14 PF13 PF12 PF11 PF10
b1
b0
PF9
PF8
The registers are considered logically concatenated and contain the fractional values for the
PLL, for 44.1KHz reference frequency.
(see also PLLFRAC_L and PLLFRAC_H registers)
ADPCM_SAMPLE_FREQ
Address: 0x53 (83)
Type: R/W
0x02
8KHz
0x0A
16KHz
0x0E
32KHz
PCMDIVIDER
Address: 0x54 (84)
Type: RW
Software Reset: 0x03
Hardware Reset: 0x03
PLLFRAC_441_H
Address: 0x52 (82)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
b7
b4
7
6
5
4
3
2
1
0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PCMDIVIDER is used to set the frequency ratio
between the OCLK (Oversampling Clock for
DACs), and the SCKT (Serial Audio Transmitter
Clock).
The relation is the following:
SCKT_freq =
OCLK_freq
2 (1 + PCM_DIV)
23/44
STA015-STA015B-STA015T
The Oversampling Factor (O_FAC) is related to OCLK and SCKT by the following expression:
1) OCLK_freq = O_FAC * LRCKT_ Freq
(DAC relation)
2) OCLK_ Freq = 2 * (1+PCM_DIV) * 32*
LRCKT_Freq (when 16 bit PCM mode is used)
3) OCLK_ Freq = 2 * (1+PCM_DIV) * 64*
LRCKT_Freq (when 32 bit PCM mode is used)
4) PCM_DIV = (O_FAC/64) - 1 in 16 bit mode
5) PCM_DIV = (O_FAC/128) - 1 in 32 bit mode
Example for setting:
MSB
b7
PD7
0
0
0
0
0
0
LSB
b6
PD6
0
0
0
0
0
0
b5
PD5
0
0
0
0
0
0
for 16 bit PCM Mode
O_FAC = 512 ; PCM_DIV = 7
O_FAC = 256 ; PCM_DIV = 3
O_FAC = 384 ; PCM_DIV = 5
24/44
b4
PD4
0
0
0
0
0
0
b3
PD3
0
0
0
0
0
0
b2
PD2
1
1
0
0
0
0
b1
PD1
1
0
1
1
1
0
b0
PD0
1
1
1
1
0
1
Description
16
16
16
32
32
32
bit mode
bit mode
bit mode
bit mode
bit mode
bit mode
for 32 bit PCM Mode
O_FAC = 512 ; PCM_DIV = 3
O_FAC = 256 ; PCM_DIV = 1
O_FAC = 384 ; PCM_DIV = 2
512
384
256
512
384
256
x Fs
x Fs
x Fs
x Fs
x Fs
x Fs
STA015-STA015B-STA015T
PCMCONF
Address: 0x55 (85)
Type: R/W
Software Reset: 0x21
Hardware Reset: 0x21
MSB
b7
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b6
ORD
1
0
b5
DIF
b4
INV
b3
FOR
b2
SCL
LSB
b1
b0
PREC (1) PREC (1)
1
0
0
1
1
0
PCMCONF is used to set the PCM Output Interface configuration:
ORD: PCM order. If this bit is set to’1’, the LS Bit
is transmitted first, otherwise MS Bit is transmiited
first.
DIF: PCM_DIFF. It is used to select the position
of the valid data into the transmitted word. This
setting is significant only in 18/20/24 bit/word
mode.If it is set to ’0’ the word is right-padded,
otherwise it is left-padded.
INV (fig.13): It is used to select the LRCKT clock
polarity. If it is set to ’1’ the polarity is compliant to
I2S format (low -> left , high -> right), otherwise
the LRCKT is inverted. The default value is ’0’. (if
I2S have to be selected, must be set to ’1’ in the
STA015 configuration phase).
Figure 19. LRCKT Polarity Selection
left
left
LRCKT
INV_LRCLK=0
right
right
LRCKT
PCM order the LS bit is transmitted First
PCM order the MS bit is transmitted First
The word is right padded
The word is left padded
LRCKT Polarity compliant to I2S format
LRCKT Polarity inverted
I2S format
Different formats
Data are sent on the rising edge of SCKT
Data are sent on the falling edge of SCKT
16 bit mode (16 slots transmitted)
18 bit mode (18 slots transmitted)
20 bit mode (20 slots transmitted)
24 bit mode (24 slots transmitted)
0
1
0
0
1
1
left
left
INV_LRCLK=1
FOR: FORMAT is used to select the PCM Output
Interface format.
After hw and sw reset the value is set to 0 corresponding to I2S format.
SCL (fig.14): used to select the Transmitter Serial
Clock polarity. If set to ’1’ the data are sent on the
Description
0
1
0
1
rising edge of SCKT and sampled on the falling. If
set to ’0’ , the data are sent on the falling edge
and sampled on the rising. This last option is the
most commonly used by the commercial DACs.
The default configuration for this flag is ’0’.
Figure 20. SCKT Polarity Selection
SCKT
SDO
INV_SCLK=0
SCKT
SDO
INV_SCLK=1
PREC [1:0]: PCM PRECISION
It is used to select the PCM samples precision, as
follows:
’00’: 16 bit mode (16 slots transmitted)
’01’: 18 bit mode (32 slots transmitted)
’10’: 20 bit mode (32 slots transmitted)
’11’: 24 bit mode (32 slots transmitted)
The PCM samples precision in STA015 can be
16 or 18-20-24 bits.
When STA015 operates in 16 (18-20-24) bits
mode, the number of bits transmitted during a
LRCLT period is 32 (64).
25/44
STA015-STA015B-STA015T
PCMCROSS
Address: 0x56 (86)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB
b7
X
b6
X
b5
X
b4
X
b3
X
b2
X
b1
0
LSB
b0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
1
1
0
1
Description
Left channel is mapped on the left output.
Right channel is mapped on the Right output
Left channel is duplicated on both Output channels.
Right channel is duplicated on both Output channels
Right and Left channels are toggled
The default configuration for this register is ’0x00’.
Fs. When this mode is selected, the default
OCLK frequency is 12.288 MHz.
MFSDF (X)
Address: 0x61 (97)
Type: R/W
Software Reset: 0x07
Hardware Reset: 0x07
PLLFRAC_L ([7:0])
MSB
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
X
X
X
M4
M3
M2
M1
M0
LSB
b7
b6
b5
b4
b3
b2
b1
b0
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
b3
b2
b1
b0
PF9
PF8
The register contains the values for PLL X divider
(see Fig. 7).
The value is changed by the internal STA015
Core, to set the clocks frequencies, according to
the incoming bitstream. This value can be even
set by the user to select the PCM interface configuration.
The VCO output frequency is divided by (X+1).
This register is a reference for 32KHz and 48 KHz
input bitstream.
PLLFRAC_H ([15:8])
DAC_CLK_MODE (99)
Address: 0x63
Type: RW
Software Reset: 0x00
Hardware Reset: 0x00
The registers are considered logically concatenated and contain the fractional values for the
PLL, used to select the internal configuration.
After Reset, the values are NA, and the operational setting are done when the MPEG synchronisation is achieved.
The following formula describes the relationships
among all the STA015 fractional PLL parameters:
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
X
X
X
X
X
X
X
MODE
This register is used to select the operating mode
for OCLK clock signal. If it is set to ’1’, the OCLK
frequency is fixed, and it is mantained to the
value fixed by the user even if the sampling frequency of the incoming bitstream changes. It the
MODE flag is set to ’0’, the OCLK frequency
changes, and can be set to (512, 384, 256) * Fs.
The default configuration for this mode is 256 *
26/44
MSB
b7
LSB
b6
b5
b4
PF15 PF14 PF13 PF12 PF11 PF10
Address: 0x64 - 0x65 (100 - 101)
Type: R/W
Software Reset: 0x46 | 0x5B
Hardware Reset: 0xNA | 0x5B
FRAC 
 1   MCLK_freq  
OCLK_Freq = 
 ⋅
 ⋅ M + 1 + 65536 

 X + 1  N + 1  
where:
FRAC=256 x FRAC_H + FRAC_L (decimal)
These registers are a reference for 48 / 24 / 12 /
32 / 16 / 8KHz audio.
STA015-STA015B-STA015T
MSB
FRAME_CNT_L
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
FC7
FC6
FC5
FC4
FC3
FC2
FC1
FC0
FRAME_CNT_M
MSB
b7
LSB
b6
b5
b4
b3
b2
FC15 FC14 FC13 FC12 FC11 FC10
b1
b0
FC9
FC8
FRAME_CNT_H
LSB
b6
b5
b6
b5
b4
b3
b2
b1
b0
SV7
SV6
SV5
SV4
SV3
SV2
SV1
SV0
After the STA015 boot, this register contains the
version code of the embedded software.
RUN
Address: 0x72 (114)
Type: RW
Software Reset: 0x00
Hardware Reset: 0x00
MSB
MSB
b7
LSB
b7
b4
b3
b2
b1
b0
FC23 FC22 FC21 FC20 FC19 FC18 FC17 FC016
Address: 0x67, 0x68, 0x69 (103 - 104 - 105)
Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
The three registers are considered logically concatenated and compose the Global Frame
Counter as described in the table.
It is updated at every decoded MPEG Frame.
The registers are reset on both hardware and
software reset.
AVERAGE_BITRATE
Address: 0x6A (106)
Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
b6
b5
b4
b3
b2
b1
b0
X
X
X
X
X
X
X
RUN
Setting this register to 1, STA015 leaves the idle
state, starting the decoding process.
The Microcontroller is allowed to set the RUN
flag, once all the control registers have been initialized.
TREBLE_FREQUENCY_LOW
Address: 0x77 (119)
Type: RW
Software Reset: 0x00
Hardware Reset: 0x00
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
TF7
TF6
TF5
TF4
TF3
TF2
TF1
TF0
b2
b1
b0
TF9
TF8
TREBLE_FREQUENCY_HIGH
Address: 0x78 (120)
Type: RW
Software Reset: 0x00
Hardware Reset: 0x00
LSB
MSB
b7
b6
b5
b4
b3
b2
b1
b0
b7
AB7
AB6
AB5
AB4
AB3
AB2
AB1
AB0
MSB
AVERAGE_BITRATE is a read-only register and
it contains the average bitrate of the incoming bitstream. The value is rounded with an accuracy of
1 Kbit/sec.
SOFTVERSION
Address: 0x71 (113)
Type: RO
LSB
b7
LSB
b6
b5
b4
b3
TF15 TF14 TF13 TF12 TF11 TF10
The registers TREBLE_FREQUENCY-HIGH and
TREBLE_FREQUENCY-LOW, logically concatenated as a 16 bit wide register, are used to select
the frequency, in Hz, where the selected frequency is +12dB respect to the stop band.
By setting these registers, the following rule must
be kept:
Treble_Freq < Fs/2
27/44
STA015-STA015B-STA015T
Example:
Bass = 200Hz
Treble = 3kHz
BASS_FREQUENCY_LOW
Address: 0x79 (121)
Software Reset: 0x00
Hardware Reset: 0x00
MSB
TFS
LSB
b7
b6
b5
b4
b3
b2
b1
b0
BF7
BF6
BF5
BF4
BF3
BF2
BF1
BF0
BASS_FREQUENCY_HIGH
Address: 0x7A (122)
Software Reset: 0x00
Hardware Reset: 0x00
LSB
b6
b5
b4
9
8
7
6
5
4
3
2
1
0
0
0
1
1
1
0
1
1
1
0
0
0
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
1
1
0
0
1
0
0
0
0
0
0
1
BFS
MSB
b7
15 14 13 12 11 10
b3
b2
BF15 BF14 BF13 BF12 BF11 BF10
b1
b0
BF9
BF8
0
0
0
0
TREBLE_ENHANCE
Address: 0x7B (123)
Software Reset: 0x00
Hardware Reset: 0x00
The registers BASS_FREQUENCY_HIGH and
BASS_FREQUENCY_LOW, logically concatenated as a 16 bit wide register, are used to select
the frequency, in Hz, where the selected frequency is -12dB respect to the pass-band. By
setting the BASS_FREQUENCY registers, the
following rules must be kept:
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
TE7
TE6
TE5
TE4
TE3
TE2
TE1
TE0
Signed number (2 complement)
This register is used to select the enhancement
or attenuation STA015 has to perform on Treble
Frequency range at the digital signal.
A decrement (increment) of a decimal unit corresponds to a step of attenuation (enhancement) of
1.5dB.
The allowed Attenuation/Enhan cement range is
[-18dB, +18dB].
Bass_Freq <= Treble_Freq
Bass_Freq > 0
(suggested range: 20 Hz < Bass_Freq < 750 Hz)
MSB
0
LSB
ENHANCE/ATTENUATION
b7
b6
b5
b4
b3
b2
b1
b0
1.5dB step
0
0
0
0
1
1
0
0
+18
0
0
0
0
1
0
1
1
+16.5
0
0
0
0
1
0
1
0
+15
0
0
0
0
1
0
0
1
.
.
+13.5
0
0
0
0
0
0
0
1
+1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
.
.
-1
1
1
1
1
0
1
1
1
-13.5
1
1
1
1
0
1
1
0
-15
1
1
1
1
0
1
0
0
-16.5
1
1
1
1
0
1
0
0
-18
28/44
STA015-STA015B-STA015T
BASS_ENHANCE
Address: 0x7C (124)
Software Reset: 0x00
Hardware Reset: 0x00
MSB
This register is used to select the enhancement
or attenuation STA015 has to perform on Bass
Frequency range at the digital signal.
A decrement (increment) of a decimal unit corresponds to a step of attenuation (enhancement) of
1.5dB.
The allowed Attenuation/Enhan cement range is
[-18dB, +18dB].
LSB
b7
b6
b5
b4
b3
b2
b1
b0
BE7
BE6
BE5
BE4
BE3
BE2
BE1
BE0
Signed number (2 complement)
MSB
LSB
ENHANCE/ATTENUATION
b7
b6
b5
b4
b3
b2
b1
b0
1.5dB step
0
0
0
0
1
1
0
0
+18
0
0
0
0
1
0
1
1
+16.5
0
0
0
0
1
0
1
0
+15
0
0
0
0
1
0
0
1
+13.5
.
.
.
0
0
0
0
0
0
0
1
+1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
-1
.
.
.
1
1
1
1
0
1
1
1
-13.5
1
1
1
1
0
1
1
0
-15
1
1
1
1
0
1
0
0
-16.5
1
1
1
1
0
1
0
0
-18
29/44
STA015-STA015B-STA015T
son, before applying Bass & Treble Control, the
user has to set the TONE_ATTEN register to the
maximum value of enhancement is going to perform.
For example, in case of a 0 dB signal (max. level)
only attenuation would be possible. If enhancement is desired, the signal has to be attenuated
accordingly before in order to reserve a margin in dB.
An increment of a decimal unit corresponds to a Tone
Attenuationstep of 1.5dB.
TONE_ATTEN
Address: 0x7D (125)
Type: RW
Software Reset: 0x00
Hardware Reset: 0x00
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
TA7
TA6
TA5
TA4
TA3
TA2
TA1
TA0
In the digital output audio, the full signal is
achieved with 0 dB of attenuation. For this reaMSB
b7
0
0
0
0
b6
0
0
0
0
b5
0
0
0
0
b4
0
0
0
0
b3
0
0
1
0
b2
0
0
0
0
LSB
b0
0
1
0
1
b1
0
0
1
1
ATTENUATION
-1.5dB step
0dB
-1.5dB
-3dB
-4.5dB
.
.
.
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
1
0
0
1
0
-15dB
-16.5dB
-18dB
5. GENERAL INFORMATION
5.1. MPEG 2.5 Layer III Algorithm.
DEMULTIPLEXING
&
ERROR CHECK
INVERSE
QUANTISATION
&
DESCALING
HUFFMAN
DECODING
INVERSE
FILTERBANK
IMDCT
STEREOPHONIC AUDIO
SIGNAL (2*768Kbit/s)
SIDE INFORMATION
DECODING
ANCILLARY DATA
D98AU903
ENCODED AUDIO
BITSTREAM (8Kbit/s ... 128Kbit/s)
5.2 - MPEG Ancillary Data Description:
As specifyed in the ISO standard, the MPEG
Layer III frames have a variable bit lenght, and
are constant in time depending on the audio sam-
pling frequencies. The time duration of the Layer
III frames is shown in Tab 2.
Table2: MPEG Layer III Frames Time Duration
Sampling Frequency (KHz)
48
44.1
32
24
22.5
16
12
11.025
8
MPEG Frame Lenght (ms)
24
29
36
24
29
36
48
48
72
30/44
STA015-STA015B-STA015T
MSB
ANCILLARY DATA BUFFER
Address: 0x7E - 0xB5 (126 - 181)
Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
LSB
b7
b6
b5
b4
X
X
X
X
b3
b2
b1
b0
AA1 AA0 ASM_EN AFM_EN
This register controls ADPCM engine and how
data must be compressed.
STA015 can extract max 56 bytes/MPEG frame.
To know the number of A.D. bits available every
MPEG frame, the ANCCOUNT_L and ANCCOUNT_H registers (0x41 and 0x42) have to be
read.
The buffer dimension is 5 bytes, written by
STA015 core in sequential order. So the whole
set of ancillary data may be accessed in one
shot. The timing information to read the buffer
can be obtained by reading the FRAME_CNT
registers (0x67 - 0x69).
ISR
Address: 0xB6 (182)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB
AFM_EN
ADPCM Frame Mode Enable
0=
no frames (raw formed)
1=
select the framed output formate for
ADPCM encoded data
ASM_EN: ADPCM Stereo Mode Enable
0=
Disable stereo mode
1=
Enable stereo mode
AA0,AA1: ADPCM Algorithm selection
The ADPCM encoding/decoding algorithm
can be selected according to the following
table:
AA1
AA0
0
0
DVI algorithm
0
1
G723-24 algorithm (24kbp/s)
1
0
G721 algorithm (32kbp/s)
1
1
G723-40 algorithm (40kbp/s)
LSB
b7
b6
b5
b4
b3
b2
b1
b0
X
X
X
X
X
X
X
0
1
X = don’t care;
0 = no ancillary data
1 = Ancillary Data Available
The ISR is used by the microcontroller to understand when a new ancillary data block is available.
ADPCM_CONFIG
Address: 0xB8 (184)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
GPSO_ENABLE
Address: 0xB9 (185)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
X
X
X
X
X
X
X
GEN
This register enable/disable the GPSO interface.
Setting the GEN bit will enable the serial interface
for ADPCM data retrieving. Reset GEN bit to disable GPSO interface.
31/44
STA015-STA015B-STA015T
GPSO_CONF
Address: 0xBA (186)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
ADC_CONF
Address: 0xBC (188)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB
MSB
LSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
b7
b6
b5
X
X
X
X
X
X
GRP
GSP
X
X
X
GSP:
GRP:
GPSO Sclk polarity
Using this bit the GPSO_SCLK polarity can
be controlled. Clearing GSP bit data on
GPSO_DATA line will be provided on the
rising edge of GPSO_SCLK (sampling on
falling edge). Setting GSP bit data are
provided on falling edge of GPSO_SCLK
(sampling on rising edge)
GPSO Request Polarity
This bit is used to determine the polarity of
GPSO_REQ signal. If GRP bit is cleared
data are valid on GPSO_REQ signal high. If
this bit is set data are valid on GPSO_REQ
signal low
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
X
X
X
X
X
X
X
ADCEN
This register controls if the ADPCM data to be
encoded comes from AD interface or from MP3
bitstream input interface.
If ADCEN bit is set data to be encoded comes
from ADC interface, otherwise data comes from
MP3 stream interface
32/44
b3
b2
b1
b0
Using this register the ADC input interface can be
configured as follow:
AIIS:
ADC:
ASCP:
ADC_ENABLE
Address: 0xBB (187)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
b4
ALRCS ALRCP ASCP ADC AIIS
ADC I2S mode
0=
sample word must be aligned with
LRCK (no I2S mode)
1=
sample word not aligned with LRCK
(I2S compliant mode)
ADC Data Config.
0=
sample word is LSB first
1=
sample word is MSB first
ADC Serial Clock Polarity
0=
Data is sampled on rising edge
1=
Data is sampled an falling edge
ALRCP:
ADC Left/Right Clock Polarity
ALRCS:
ADC Left/Right Clock Start value this two
bits permit to determine Left/Right clock
usage according to the following table:
ALRCP ALRCS
LEFT/RIGHT COUPLE
0
0
(Data1, Data2)
(Data3, Data4)
1
0
(0, 1)
(2, 3)
0
1
(0, 1)
(2, 3)
1
1
(1, 2)
(3, 4)
LRCK
DATA
DATA 0
DATA 1
DATA 2
DATA 3
DATA 4
D99AU1065
STA015-STA015B-STA015T
ADPCM_FRAME_SIZE
Address: 0xBD (189)
Type: R/W
Software Reset: 0x13
Hardware Reset: 0x00
GPIO_CONF
Address: 0xBF (191)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB
b7
b6
b5
b4
b3
b2
b1
LSB
MSB
b0
b7
b6
b5
b4
b3
b2
b1
b0
X
X
X
X
X
X
GOSP
GISP
AFS7 AFS6 AFS5 AFS4 AFS3 AFS2 AFS1 AFS1
The ADPCM frame size may be adjusted to
match a trade-off between the bitrate overhead
and the frame length. The frame size (in bytes) is
calculated as follow:
FRAME size = (ADPCM_FRAME_SIZE * 90)
+108
The frame starts with a 5 bytes sync word
(0x5354445649) and, after that, a frame header:
- 13 bytes for DVI algorithm
- 103 bytes for G726 pack algorithms
LSB
b5
b4
INTL
6
INTL
5
INTL
4
INTL
3
b3
b2
INTL INTL
2
1
b1
b0
INTL
0
X
Using this register the ADPCM interrupt capability
can be properly configured.
INTL0 INTL6
GISP:
GPIO Strobe Polarity in INPUT mode
GOSP:
0=
data strobed an falling edge
1=
data strobed on rising edge
GPIO Strobe Polarity in OUTPUT mode
0=
non inverted
1=
inverted
MSB
MSB
b6
This register controls how data are strobed on the
GPIO interface.
ADC_WLEN
Address: 0xC0 (192)
Type: R/W
Software Reset: 0x0F
Hardware Reset: 0x0F
ADPCM_INT_CFG
Address: 0xBE (190)
Type: R/W
Software Reset: 0x0B
Hardware Reset: 0x00
b7
LSB
Interrupt Length
The interrupt length can be programmed,
using this bits, from 0 up to 128 system
clock cycles
LSB
b7
b6
b5
X
X
X
b4
b3
b2
b1
b0
AWL4 AWL3 AWL2 AWL1 AWL0
To select ADC word length AWL4 through AWL0
bits can be used. This 5 bit value must contain
the size of the significant data bits minus one.
ADC_WPOS
Address: 0xC1 (193)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB
LSB
b7
b6
b5
X
X
X
b4
b3
b2
b1
b0
AWL4 AWL3 AWL2 AWL1 AWL0
These bits specify the position of the sample
word referred to the LRCK slot boundary. Bit
AWP0 thru AWP4 must be programmed with the
number of bits to ignore after the sample word.
33/44
STA015-STA015B-STA015T
The STA015 contains 56 consecutive 8-bit registers corresponding to the maximum number of
ancillary data that may be contained in MPEG
frame. The ANCCOUNT_L and ANCOUNT_H
registers contain the number of ancillary data bits
available within the current MPEG frame.
To perform ancillary data reading a status register (0xB6 - INTERRUPT_STATUS_REGISTER)
is available: bit 0 of this register should be polled
by the microcontroller in order to understand
when new data are available.
0x7E
------------0xB5
ANC_DATA_1
--------------------------------ANC_DATA_56
0xB6
ISR
5.3. I/O CELL DESCRIPTION (pinout relative to TQFP44 package)
1) CMOS Tristate Output Pad Buffer, 4mA, with Slew Rate Control / Pin numbers 2, 4, 13, 27, 33, 42, 44
EN
Z
OUTPUT PIN
MAX LOAD
Z
100pF
A
D98AU904
2) CMOS Bidir Pad Buffer, 4mA, with Slew Rate Control / Pin numbers 3, 31
EN
IO
INPUT PIN CAPACITANCE
A
IO
ZI
D98AU905
5pF
OUTPUT
PIN
MAX
LOAD
IO
100pF
3) CMOS Inpud Pad Buffer / Pin numbers 24, 26, 32, 34, 36, 40
A
Z
INPUT PIN
CAPACITANCE
A
3.5pF
D98AU906
4) CMOS Inpud Pad Buffer with Active Pull-Up / Pin numbers 22, 25, 28, 38
A
Z
INPUT PIN
CAPACITANCE
A
3.5pF
D98AU907
5) CMOS Schmitt Trigger Bidir Pad Buffer with active Pull-up, 4mA, with slew rate control /
Pin numbers 14, 16, 18, 20, 35, 37, 39, 41, 43
EN
IO
INPUT PIN CAPACITANCE
A
IO
ZI
D00AU1150
34/44
5pF
OUTPUT
PIN
MAX
LOAD
IO
100pF
STA015-STA015B-STA015T
5.4. TIMING DIAGRAMS
5.4.1. Audio DAC Interface
a) OCLK in output. The audio PLL is used to clock the DAC
OCLK (OUTPUT)
SDO
tsdo
SCKT
tsckt
LRCLK
tlrclk
D98AU969
tsdo = 3.5 + pad_timing (Cload_SDO) - pad_timing
(Cload_ OCLK)
tsckt = 4 + pad_timing (Cload_SCKT) - pad_timing
(Cload_ OCLK)
tlrckt = 3.5 + pad_timing (Cload_LRCCKT) pad_timing (Cload_ OCLK)
Pad-timing versus load
Load (pF)
Pad_timing
25
2.90ns
50
3.82ns
75
4.68ns
100
5.52ns
Cload_XXX is the load in pF on the XXX output.
pad_timing (Cload_XXX) is the propagation delay
added to the XXX pad due to the load.
b) OCLK in input.
OCLK (INPUT)
thi
tlo
SDO
tsdo
SCKT
tsckt
LRCLK
tlrclk
toclk
D98AU970
Thi min = 3ns
Tlo min = 3ns
Toclk min = 25ns
tsdo = 5.5 + pad_timing (Cload_SDO) ns
tsckt = 6 + pad_timing (Cload_SCKT) ns
tlrckt = 5.5 + pad_timing (Cload_LRCKT) ns
35/44
STA015-STA015B-STA015T
5.4.2. Bitstream input interface (SDI, SCKR, BIT_EN) SCL_POL = 0
BIT_EN
t _biten
t_biten
tsckr_min_period
t sckr_min_low
SCKR
SCLK_POL=0
t sckr_min_high
IGNORED
SDI
VALID
t sdi_setup
IGNORED
tsdi_hold
D98AU971A
5.4.2. Bitstream input interface (SDI, SCKR, BIT_EN) SCL_POL = 1
BIT_EN
t_biten
t _biten
tsckr_min_period
t sckr_min_low
SCKR
SDI
SCLK_POL=4
t sckr_min_high
IGNORED
IGNORED
VALID
tsdi_setup
tsdi_hold
IGNORED
D99AU1038
tsdi_setup_min= 2ns
tsdi_hold_min = 3ns
tsckr_min_hi = 10ns
tsckr_min_low = 10ns
tsckr_min_lperiod = 50ns
t_biten (min) = 2ns
5.4.3. SRC_INT
This is an asynchronous input used in ”broadcast’ mode.
SRC_INT is active low
t_src_hi
SRC_INT
t_src_low
D98AU972
t_src_low min duration is 50ns (1DSP clock period)
t_src_high min duration is 50ns (1DSP clock period)
5.4.4. XTI,XTO and CLK_OUT timings
thi
XTI (INPUT)
tlo
XTO
txto
CLK_OUT
tclk_out
D98AU973
txto = 1.40 + pad_timing (Cload_XTO) ns
tclk_out = 4 + pad_timing (Cload_CLK_OUT) ns
Note: In ”multimedia” mode, the CLK_OUT pad is DATA_REQ. In that case, no timing is given between th e XTI input and this pad.
36/44
STA015-STA015B-STA015T
5.4.5. RESET
The Reset min duration (t_reset_low_min) is 100ns
RESET
treset_low_min
D98AU974
5.5. CONFIGURATION FLOW
HW RESET
set
PCM-DIVIDER
set
PCM-CONF.
set { PLL
PLL
PLL
PLL
FRAC_441_H,
FRAC_441_L,
FRAC_H,
FRAC_L }
PCM OUTPUT
INTERFACE
CONFIGURATION
PLL
CONFIGURATION
FOR:
set { MFS DF_441,
MFSDF }
• { 48, 44.1, 32
29, 22.05, 16
12, 11.025, 8 } KHz
set
• MULTIMEDIA
MODE see
{TAB 5 to TAB12}
PLL CTRL
set
SCLK_POL
INPUT SERIAL
CLOCK POLARITY
CONFIGURATION
set
DATA_REQ_ENABLE
DATA REQUEST
PIN ENABLE
REQ_POL
DATA REQUEST
POLARITY
CONFIGURATION
set
set
RUN
THE OVERALL
SETTING STEPS
ARE INCLUDED IN
THE STA015
CONFIGURATION
FILE AND CAN
BE DOWNLOADED
IN ONE STEP.
STM PROVIDES
A SPECIFIC
CONFIGURATION
FILE FOR EACH
SUPPORTED
INPUT CLOCK
FREQUENCY
D00AU1146
37/44
STA015-STA015B-STA015T
Table 5:
PLL Configuration Sequence For
10MHz Input Clock
256 Oversapling Clock
REGISTER
ADDRESS
NAME
Table 7:
PLL Configuration Sequence For
14.31818MHz Input Clock
256 Oversapling Rathio
VALUE
NAME
VALUE
6
reserved
18
6
reserved
11
reserved
3
11
reserved
3
97
MFSDF (x)
15
97
MFSDF (x)
15
80
MFSDF-441
16
80
MFSDF-441
16
101
PLLFRAC-H
169
101
PLLFRAC-H
187
82
PLLFRAC-441-H
49
82
PLLFRAC-441-H
103
100
PLLFRAC-L
42
100
PLLFRAC-L
58
81
PLLFRAC-441-L
60
81
PLLFRAC-441-L
119
5
PLLCTRL
161
5
PLLCTRL
161
Table 6:
PLL Configuration Sequence For
10MHz Input Clock
384 Oversapling Rathio
REGISTER
ADDRESS
38/44
REGISTER
ADDRESS
NAME
12
Table 8:
PLL Configuration Sequence For
14.31818MHz Input Clock
384 Oversapling Rathio
VALUE
REGISTER
ADDRESS
NAME
VALUE
6
reserved
17
6
reserved
11
11
reserved
3
11
reserved
3
97
MFSDF (x)
9
97
MFSDF (x)
6
80
MFSDF-441
10
80
MFSDF-441
7
101
PLLFRAC-H
110
101
PLLFRAC-H
82
PLLFRAC-441-H
160
82
PLLFRAC-441-H
100
PLLFRAC-L
152
100
PLLFRAC-L
211
81
PLLFRAC-441-L
186
81
PLLFRAC-441-L
157
5
PLLCTRL
161
5
PLLCTRL
161
3
157
STA015-STA015B-STA015T
Table 9:
PLL Configuration Sequence For
14.31818MHz Input Clock
512 Oversapling Rathio
REGISTER
ADDRESS
NAME
Table 11:
PLL Configuration Sequence For
14.7456MHz Input Clock
384 Oversapling Rathio
VALUE
REGISTER
ADDRESS
NAME
VALUE
6
reserved
11
6
reserved
10
11
reserved
3
11
reserved
3
97
MFSDF (x)
6
97
MFSDF (x)
8
80
MFSDF-441
7
80
MFSDF-441
9
101
PLLFRAC-H
3
101
PLLFRAC-H
64
82
PLLFRAC-441-H
157
82
PLLFRAC-441-H
124
100
PLLFRAC-L
211
100
PLLFRAC-L
81
PLLFRAC-441-L
157
81
PLLFRAC-441-L
5
PLLCTRL
161
5
PLLCTRL
Table 10:
PLL Configuration Sequence For
14.7456MHz Input Clock
256 Oversapling Rathio
REGISTER
ADDRESS
NAME
0
0
161
Table 12:
PLL Configuration Sequence For
14.7456MHz Input Clock
512 Oversapling Rathio
VALUE
REGISTER
ADDRESS
NAME
VALUE
6
reserved
12
6
reserved
11
reserved
3
11
reserved
9
2
97
MFSDF (x)
15
97
MFSDF (x)
5
80
MFSDF-441
16
80
MFSDF-441
6
101
PLLFRAC-H
85
101
PLLFRAC-H
82
PLLFRAC-441-H
4
82
PLLFRAC-441-H
100
PLLFRAC-L
85
100
PLLFRAC-L
0
81
PLLFRAC-441-L
0
81
PLLFRAC-441-L
0
5
PLLCTRL
161
5
PLLCTRL
0
184
161
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5.6. STA015 CONFIGURATION FILE FORMAT
The STA015 Configuration File is an ASCII format. An example of the file format is the following:
58 1
42 4
128 15
............
It is a sequence of rows and each one can be interpreted as an I2C command.
The first part of the row is the I 2C address (register) and the second one is the I2C data (value).
To download the STA015 configuration file into the device, a sequence of write operation to STA015 I2C
interface must be performed.
The following program describes the I2C routine to be implemented for the configuration driver:
42
4
I2C REGISTER VALUE
I2C SUB-ADDRESS
D98AU976
STA015 Configuration Code (pseudo code)
download cfg - file
{
fopen (cfg_file);
fp:=1;
do {
I2C_start_cond;
I2C_write_dev_addr;
I2C_write_subaddress(fp);
I2C_write_data (fp);
I2C_stop_cond;
fp++;
}
while (!EDF)
}
/*set file pointer to first row */
/* generate I2C start condition for STA015 device address */
/* write STA015 device address
*/
/* write subaddress
*/
/* write data
*/
/* generate I 2C stop condition
*/
/* update pointer to new file row
*/
/* repeat until End of File
/* End routine
*/
*/
Note:1
STA015 is a device based on an integrated DSP core. Some of the I2C registers default values are loaded after an internal DSP boot operation.
The bootstrap time is 60 micro second. Only after this time lenght, the data in the register can be considered stable.
Note 2:
Refer also to the application note AN1250
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STA015-STA015B-STA015T
mm
DIM.
MIN.
TYP.
A
inch
MAX.
MIN.
TYP.
2.65
MAX.
0.104
a1
0.1
0.3
0.004
0.012
b
0.35
0.49
0.014
0.019
b1
0.23
0.32
0.009
0.013
C
0.5
c1
0.020
45° (typ.)
D
17.7
18.1
0.697
0.713
E
10
10.65
0.394
0.419
e
1.27
0.050
e3
16.51
0.65
F
7.4
7.6
0.291
0.299
L
0.4
1.27
0.016
0.050
S
OUTLINE AND
MECHANICAL DATA
SO28
8 ° (max.)
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STA015-STA015B-STA015T
mm
DIM.
MIN.
TYP.
A
inch
MAX.
MIN.
TYP.
1.60
A1
0.05
A2
1.35
B
0.30
C
0.09
0.063
0.15
0.002
1.40
1.45
0.053
0.055
0.057
0.37
0.45
0.012
0.014
0.018
0.20
0.004
0.006
0.008
D
12.00
0.472
D1
10.00
0.394
D3
8.00
0.315
e
0.80
0.031
E
12.00
0.472
E1
10.00
0.394
E3
8.00
0.315
L
0.45
0.60
0.75
OUTLINE AND
MECHANICAL DATA
MAX.
0.018
0.024
L1
1.00
K
0°(min.), 3.5°(typ.), 7°(max.)
0.030
0.039
TQFP44 (10 x 10)
D
D1
A
A2
A1
33
23
34
22
0.10mm
.004
B
E
B
E1
Seating Plane
12
44
11
1
C
L
e
K
TQFP4410
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STA015-STA015B-STA015T
mm
inch
OUTLINE AND
MECHANICAL DATA
DIM.
MIN.
TYP.
MAX.
A
A1
MIN.
TYP.
1.700
0.350
0.400
0.450
MAX.
0.067
0.014
0.016
A2
1.100
0.043
b
0.500
0.20
D
8.000
0.315
D1
5.600
0.220
e
0.800
0.031
E
8.000
0.315
E1
5.600
0.220
f
1.200
0.047
0.018
Body: 8 x 8 x 1.7mm
LFBGA64
0.15
BALL 1 IDENTIFICATION
A
D1
8
7
6
5
4
f
3
2
D
A1
1
f
A
B
C
D
E1
E
E
F
G
H
φ b (64 PLACES)
e
A2
LFBGA64M
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STA015-STA015B-STA015T
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