RF9958 5 CDMA/FM TRANSMIT MODULATOR, IF AGC, AND UPCONVERTER Typical Applications • CDMA/FM Cellular Systems • Spread Spectrum Cordless Phones • CDMA PCS Systems • High Speed Data Modems • Wireless Local Loop Systems • General Purpose Digital Transmitters The RF9958 is an integrated complete Quadrature Modulator, IF AGC amplifier, and Upconverter designed for the transmit section of dual-mode CDMA/FM cellular and PCS applications. It is designed to modulate baseband I and Q signals, amplify the resulting IF signals while providing 95dB of gain control range, and perform the final upconversion to UHF. Noise Figure, IP3, and other specifications are designed to be compatible with the IS-98 Interim Standard for CDMA cellular communications. This circuit is designed as part of RFMD’s newest CDMA Chip Set, which also includes the RF9957 CDMA/FM Receive IF AGC and Demodulator. The IC is manufactured on an advanced 15GHz FT Silicon Bipolar process, and is supplied in a 28-lead plastic SSOP package. PIN 1 INDENT ü GaAs HBT GaAs MESFET Si Bi-CMOS SiGe HBT Si CMOS 0.25 0.10 7° 0.25 0.10 5 0.36 TYP 0.23 10.01 9.80 1.27 0.38 0.635 TYP 1.73 1.47 8° 0° NOTES: 1. Shaded lead is Pin1. 2. Lead frame material: Copper 194 3. Mold flash shall not exceed 0.006 (0.15 mm) per end. 4. Interlead flash shall not exceed 0.010 (0.25 mm) per side. 5. All dimensions are excluding mold flash and protrusions. Optimum Technology Matching® Applied Si BJT 6.20 5.79 3.99 3.81 MODULATORS AND UPCONVERTERS Product Description Package Style: QSOP-28 Features • Supports Dual Mode Operation MODE GC • Digitally Controlled Power Down Modes 1 27 • 2.7V to 3.3V Operation • Digital First LO Quadrature Divider Gain Control Q SIG 2 • Double-Balanced UHF Upconvert Mixer Q REF 3 LO1- 8 LO1+ 9 Quad. ÷2 Σ 25 MOD OUT+ • IF AGC Amp with 95 dB Gain Control 24 MOD OUT- I REF 5 21 MIX IN- I SIG 4 22 MIX IN+ Band Gap Reference 10 13 15 17 19 20 RF9958 G OUT PD1 PD2 RF OUT LO2+ LO2- Ordering Information RF9958 PCBA Functional Block Diagram Rev B11 010720 CDMA/FM Transmit Modulator, IF AGC, and Upconverter Fully Assembled Evaluation Board RF Micro Devices, Inc. 7628 Thorndike Road Greensboro, NC 27409, USA Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com 5-93 RF9958 Absolute Maximum Ratings Parameter Supply Voltage Power Down Voltage (VPD) I and Q Levels, per pin LO1 Level, balanced LO2 Level, balanced Operating Ambient Temperature Storage Temperature Parameter MODULATORS AND UPCONVERTERS 5 Rating Unit -0.5 to +5 -0.5 to VCC + 0.7 1 +3 +6 -40 to +85 -40 to +150 VDC V VPP dBm dBm °C °C Specification Min. Typ. Max. Caution! ESD sensitive device. RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s). Unit I/Q Modulator & AGC I/Q Input Frequency Range I/Q Input Impedance I/Q Input Reference Level LO1/FM Frequency Range LO1/FM Input Level LO1/FM Input Impedance Sideband Suppression -15 170 35 Carrier Suppression 40 Max Output, FM Mode Max Output, CDMA Mode 50 +2.5 -3 -2 Min Output, CDMA Mode Output Power Accuracy 0 -95 -3 -2 Adjacent Channel Power Rejection @ 885kHz Adjacent Channel Power Rejection @ 1.98MHz Output Noise Power Output Impedance Power Dissipation 0 to 20 80 0.6 100 to 360 -8 200 40 30 50 30 +4 0 170 110 -5 230 -89 +3 +2 MHz kΩ VDC MHz dBm Ω dBc dBc dBc dBc dBm dBm dBm dBm -55 dB dB dBc -67 dBc -116 -137 -164 200 -111 -132 -159 230 150 dBm/Hz dBm/Hz dBm/Hz Ω mW UHF Upconverter Conversion Gain Noise Figure (SSB) Output IP3 IF Input Impedance IF Input Frequency Range LO2 Input Impedance LO2 Input Level LO2 Input Frequency Range RF to LO2 Isolation 5-94 -1 170 -6 0.5 15 +14 200 50 to 180 50 -3 700 to 1100 20 230 0 dB dB dBm Ω MHz Ω dBm MHz dB Condition T=25 °C, VCC =3.0V, ZLOAD =50Ω, LO1 =-8dBm@260 MHz, LO2=-3dBm@ 960MHz, I SIG=Q SIG=300mVPP, RF Output externally matched Balanced Balanced Per Pin Balanced I/Q Amplitude adjusted to within ±20mV Unadjusted I/Q DC Offset adjusted to within ±20mV Unadjusted VGC =2.5 VDC, T=-20°C to +85°C VGC =2.5 VDC, T=-20°C to +85°C, IS-95A CDMA Modulation ISIG=QSIQ=300mVpp@ 100kHz VGC =0.5 VDC, T=-20°C to +85°C, IS-95A CDMA Modulation T=-20 to +85 °C, Ref=25 °C 1.4V≤GC≤ 2.5 IS-95A CDMA Modulation POUT = -5dBm IS-95A CDMA Modulation POUT = -5dBm POUT = -3 dBm, T=-20°C to +85°C POUT = -23 dBm, T=-20°C to +85°C POUT < -70 dBm, T=-20°C to +85°C Balanced T=-20°C to +85°C Output externally matched Balanced Single Ended Rev B11 010720 RF9958 Parameter Specification Min. Typ. Max. Unit Condition Power Supply Supply Voltage Current Consumption Current Consumption Power Down Current VPD HIGH Voltage VPD LOW Voltage 2.7 3.0 43 20 3.3 20 VCC-0.7 0.5 V mA mA µA V V Modulator and AGC only, CDMA Mode Mixer Only MODULATORS AND UPCONVERTERS 5 Rev B11 010720 5-95 RF9958 Pin 1 2 Function MODE Q SIG Description Selects between CDMA and FM mode. This is a digitally controlled input. A logic “high” (≥VCC -0.7VDC) selects CDMA mode. A logic “low” (<0.5VDC) selects FM mode. In FM mode, this switch enables the FM amplifier and turns off the I&Q modulator. The impedance on this pin is 30kΩ. A DC voltage less than or equal to the maximum allowable Vcc may be applied to this pin when no voltage is applied to the Vcc pins. Interface Schematic BIAS 60 kΩ 60 kΩ MODE Baseband input to the Q mixer. This pin is DC coupled. The DC level of 0.6V must be supplied to this pin to bias the transistor. Input impedance of this pin is 50kΩ minimum. A DC voltage less than or equal to the maximum allowable Vcc may be applied to this pin when no voltage is applied to the Vcc pins. BIAS BIAS 8 kΩ 8 kΩ Q SIG Q REF MODULATORS AND UPCONVERTERS 5 3 Q REF 4 I REF 5 I SIG Reference voltage for the Q mixer. This voltage should be the same as See pin 2. the DC voltage supplied to the Q SIG pin. For maximum carrier suppression, DC voltage on this pin relative to the Q SIG DC voltage may be adjusted. Input impedance of this pin is 50kΩ minimum. A DC voltage less than or equal to the maximum allowable Vcc may be applied to this pin when no voltage is applied to the Vcc pins. Reference voltage for the I mixer. This voltage should be the same as See pin 5. the DC voltage supplied to the I SIG pin. For maximum carrier suppression, DC voltage on this pin relative to the I SIG DC voltage may be adjusted. Input impedance of this pin is 50kΩ minimum. A DC voltage less than or equal to the maximum allowable Vcc may be applied to this pin when no voltage is applied to the Vcc pins. Baseband input to the I mixer. This pin is DC coupled. The DC level of BIAS 0.6V must be supplied to this pin to bias the transistor. Input impedance of this pin is 50kΩ minimum. A DC voltage less than or equal to 8 kΩ the maximum allowable Vcc may be applied to this pin when no voltage is applied to the Vcc pins. BIAS 8 kΩ I SIG 6 GND1 7 VCC1 8 LO1+, FM+ I REF Ground connection for all baseband circuits including bandgap, AGC, flip-flop, modulator and FM amp. Keep traces physically short and connect immediately to ground plane for best performance. Supply Voltage for the LO1 flip-flop and limiting amp only. This supply is isolated to minimize the carrier leakage. A 1nF external bypass capacitor is required, and an additional 0.1µF will be required if no other low frequency bypass capacitors are nearby. The trace length between the pin and the bypass capacitors should be minimized. The ground side of the bypass capacitors should connect immediately to ground plane. One half of the balanced modulator LO1 input. The other half of the input, LO1-, is AC grounded for single-ended input applications. The V frequency on these pins is divided by a factor of 2, hence the carrier frequency for the modulator becomes one half of the applied frequency. 100 Ω The single-ended input impedance is 100Ω (balanced is 200Ω). This pin is NOT internally DC blocked. An external blocking capacitor (1nF LO1+, FM+ recommended) must be provided if the pin is connected to a device with DC present. When FM mode is selected, the output of the flip-flop divider circuit is switched to the AGC amplifier inputs and the modulator mixers are not used. Note that the frequency deviation input here will be reduced by a factor of two, due to the frequency divider operation. One half of the balanced modulator LO1 input. In single-ended applica- See pin 8. tions (100Ω input impedance), this pin is AC grounded with a 1nF capacitor. CC1 9 5-96 LO1-, FM- VCC1 100 Ω LO1-, FM- Rev B11 010720 RF9958 Function BG OUT 11 VCC3 12 13 GND1 PD1 14 VCC4 15 PD2 Description Interface Schematic Bandgap voltage reference. This voltage, constant over temperature and supply variation, is used to bias internal circuits. A 1nF external bypass capacitor is required. Supply voltage for the AGC and the Bandgap circuitry. A 1nF external bypass capacitor is required and an additional 0.1µF will be required if no other low frequency bypass capacitors are nearby. The trace length between the pin and the bypass capacitors should be minimized. The ground side of the bypass capacitors should connect immediately to ground plane. Same as pin 6. Power down control for overall circuit. When logic “high” (≥VCC -0.7V), all circuits are operating; when logic “low” (≤0.5V), all circuits are turned off. The input impedance of this pin is >10kΩ. A DC voltage less than or equal to the maximum allowable Vcc may be applied to this pin when no voltage is applied to the Vcc pins. Supply for the mixer stage only. The supply for the mixer is separated to maximize IF to RF isolations and reduce the carrier leakage. A 100pF external bypass capacitor is required and an additional 0.1µF will be required if no other low frequency bypass capacitors are nearby. The trace length between the pin and the bypass capacitors should be minimized. The ground side of the bypass capacitors should connect immediately to ground plane. Power down control for mixer only. When connected to pin 10 (BG OUT) the mixer circuits are operating; when connected to ground (≤0.5V), the mixer is turned off but all other circuits are operating. A DC voltage less than or equal to the maximum allowable Vcc may be applied to this pin when no voltage is applied to the Vcc pins. 10 kΩ PD1 5 MODULATORS AND UPCONVERTERS Pin 10 1 kΩ PD2 450 Ω 16 GND2 17 RF OUT Ground connection for the mixer stage. Keep traces physically short and connect immediately to ground plane for best performance. RF output pin. An external shunt inductor to VCC plus a series blocking/ matching capacitor are required for 50Ω output. VCC4 300 Ω RF OUT 18 DEC 19 LO2+ Current Mirror decoupling pin. A 1000pF external capacitor is required to bypass this pin. The ground side of the bypass capacitors should connect immediately to ground plane. One half of the balanced mixer LO2 input. In single-ended applications, the other half of the input, LO2- is AC grounded. This is a 50Ω impedance port. This pin is NOT internally DC blocked. An external blocking capacitor (100pF recommended) must be provided if the pin is connected to a device with DC present. BIAS BIAS 40 Ω 40 Ω LO2+ 20 LO2- 21 MIX IN- Rev B11 010720 One half of the balance mixer LO2 input. In single ended applications, this pin is AC grounded with a 100pF capacitor. One half of the 200Ω balanced impedance input to the mixer stage. This pin is NOT internally DC blocked. An external blocking capacitor (2200pF recommended) must be provided if the pin is connected to a device with DC present. If no IF filter is needed this pin may be connected to MOD OUT+ through a DC blocking capacitor. An appropriate matching network may be needed if an IF filter is used. LO2- See pin 19. BIAS 100 Ω MIX IN- BIAS 100 Ω MIX IN+ 5-97 RF9958 Pin 22 23 24 MODULATORS AND UPCONVERTERS 5 Function MIX IN+ GND2 MOD OUT- 25 26 MOD OUT+ DEC 27 GC Description Interface Schematic Same as pin 21, except complementary input. See pin 21. Same as pin 16. One half of the balanced AGC output port. The impedance of this port is 200Ω balanced. If no filtering is required, this pin can be connected to the MIX IN- pin through a DC blocking capacitor. This pin requires an inductor to VCC to achieve full dynamic range. In order to maximize gain, this inductor should be a high-Q type and should be parallel resonated out with a capacitor (see application schematic). This pin is NOT DC blocked. A blocking capacitor of 2200pF is needed when this pin is connected to a DC path. An appropriate matching network may be needed if an IF filter is used. Same as pin 24, except complementary output. VCC3 100 Ω VCC3 100 Ω MOD OUTMOD OUT+ See pin 24. AGC decoupling pin. An external bypass capacitor of 10nF capacitor is required. The trace length between the pin and the bypass capacitors should be minimized. The ground side of the bypass capacitors should connect immediately to ground plane. Analog gain control for AGC amplifiers. Valid control voltage ranges are from 0.5VDC to 2.5VDC. The gain range for the AGC is 88dB. These voltages are valid ONLY for a 37kΩ source impedance. A DC voltage less than or equal to the maximum allowable Vcc may be applied to this pin when no voltage is applied to the Vcc pins. BIAS 21 kΩ GC 40 kΩ 28 5-98 VCC2 Supply for the modulator stage only. A 10nF external bypass capacitor is required and an additional 0.1µF will be required if no other low frequency bypass capacitors are nearby. The trace length between the pin and the bypass capacitors should be minimized. The ground side of the bypass capacitors should connect immediately to ground plane. Rev B11 010720 RF9958 RF9958 Pin-Out 28 VCC2 Q SIG 2 27 GC Q REF 3 26 DEC I REF 4 25 MOD OUT+ I SIG 5 24 MOD OUT- GND1 6 23 GND2 VCC1 7 22 MIX IN+ LO1+ 8 21 MIX IN- LO1- 9 20 LO2- BG OUT 10 19 LO2+ VCC3 11 18 DEC GND1 12 17 RF OUT PD1 13 VCC4 14 Rev B11 010720 5 MODULATORS AND UPCONVERTERS MODE 1 16 GND2 15 PD2 5-99 RF9958 Application Schematic VCC 10 nF Mode Select 1 MODE VCC2 28 Q Signal 2 Q SIG GC 27 37 kΩ Gain Control 1 nF Reference 3 Q REF DEC 26 10 nF 18 pF 10 nF I Signal 4 I REF MOD OUT+ 25 5 I SIG MOD OUT- 24 6 GND1 GND2 23 7 VCC1 MIX IN+ 22 8 LO1+ MIX IN- 21 9 LO1- LO2- 20 10 BG OUT LO2+ 19 82 nH 82 nH VCC 10 nF 18 pF 5 MODULATORS AND UPCONVERTERS VCC IF Filter, DC Blocked 10 nF LO1/FM In 1 nF 100 pF 10 nF LO2 In 100 pF 11 VCC3 1 nF 12 GND1 VCC DEC 18 1000 pF L1 RF OUT 17 1 nF Power Down 1 RF Out 13 PD1 14 VCC4 100 pF 5-100 C1 GND2 16 Power Down 2 PD2 15 1 nF Rev B11 010720 RF9958 Evaluation Board Schematic (Download Bill of Materials from www.rfmd.com.) P1 P1-1 P1-3 P3 P2 1 MODE 2 GND 3 GC P2-1 P2-3 1 VCC 2 GND 3 IREF P3-2 1 GND 2 PD1 3 P3-4 PD1 4 5 9958400B 1 MODE VCC2 28 Q SIG J3 2 Q SIG GC 27 IREF 3 Q REF DEC 26 R2 10 kΩ C2 10 nF I SIG J2 4 I REF MOD OUT+ 25 5 I SIG MOD OUT- 24 6 GND1 GND2 23 7 VCC1 MIX IN+ 22 T1 50 Ω µ strip 50 Ω µ strip 1 C15 10 nF T2 50 Ω µ strip 1 C17 2.2 nF 8 LO1+ MIX IN- 21 9 LO1- LO2- 20 10 BG OUT LO2+ 19 C3 1 nF MIX IN J5 C12 100 pF C4 100 nF C18 100 pF 50 Ω µ strip C11 1000 pF DEC 18 11 VCC3 C13 33 pF C5 1 nF MOD OUT J4 VCC C16 2.2 nF C1 1 nF 5 MODE C10 1 nF C8 10 nF C19 1 µF R1 27 kΩ MODULATORS AND UPCONVERTERS MODE LO IN J1 VCC C9 10 nF RF OUT 17 12 GND1 PD1 13 PD1 VCC 14 VCC4 GND2 16 L2 12 nH L1 15 nH LO2 IN J6 50 Ω µ strip C14 1.3 pF RF OUT J7 VCC C20 1 µF PD2 15 C6 1 nF C7 1 nF R3 0 Ω Rev B11 010720 5-101 RF9958 Evaluation Board Layout 2.689" X 2.521" MODULATORS AND UPCONVERTERS 5 5-102 Rev B11 010720 RF9958 MODULATORS AND UPCONVERTERS 5 Rev B11 010720 5-103 RF9958 MODOUT Output Power versus Gain Control Voltage MODOUT Noise Power versus Gain Control (VCC=3.0 V, 130 MHz) 10.0 (VCC=3.0 V, 85 MHz) -100.0 0.0 -110.0 MODOUT Output Power (dBm) -10.0 Noise Power (dBm/Hz) -20.0 -30.0 -40.0 -50.0 -60.0 -70.0 -120.0 -130.0 -140.0 -150.0 -80.0 -100.0 0.5 1.0 1.5 2.0 2.5 -170.0 0.5 1.0 1.5 2.0 2.5 GC(V) GC (V) MODOUT IM3 Suppression versus Output Level (VCC=3.0 V, 130 MHz) 43.0 MODOUT Output IM3 Suppression (dBc) MODULATORS AND UPCONVERTERS 5 -40 C +25C +85C -160.0 +25°C -30°C +85°C -90.0 42.0 41.0 40.0 39.0 38.0 37.0 -18.0 -16.0 -14.0 -12.0 -10.0 -8.0 -6.0 -4.0 -2.0 MODOUT Output Level (dBm) 5-104 Rev B11 010720