RF2679 Preliminary 7 W-CDMA RECEIVE AGC AND DEMODULATOR Typical Applications • W-CDMA Systems Product Description 4.00 +0.20 The RF2679 is an integrated complete IF AGC amplifier and Quadrature Demodulator designed for the receive section of W-CDMA applications. It is designed to amplify received IF signals, while providing 60dB of gain control range, a total of 90dB gain, and demodulate to baseband I and Q signals. This circuit is designed as part of RFMD’s single-mode W-CDMA Chipset, which also includes the RF2678 W-CDMA Transmit Modulator and IF AGC. The IC is manufactured on an advanced 25GHz FT Silicon Bi-CMOS process, and is packaged in a 4mmx4mm LPCC-24. 4.00 +0.20 2.80 +0.05 sq Optimum Technology Matching® Applied GC 1 FL- CALEN QDCFB Si CMOS FL+ SiGe HBT ENABLE GaAs MESFET BG OUT !Si Bi-CMOS GaAs HBT 24 23 22 21 20 19 Band Gap Reference DEC 2 CDMA IN+ 3 BB Filter CDMA IN- 4 VCC1 5 QUADRATURE DEMODULATORS Features • 2.7V to 3.3V Operation 18 IDCFB • Digital LO Quadrature Divide-by-4 17 I OUT+ • IF AGC Amp with 70dB Gain Control 16 I OUT- • 85dB Maximum Voltage Gain 14 Q OUT+ 8 9 10 11 12 VCC3 LO+ LO- GND1 VCC4 FCLK 13 Q OUT- 7 Functional Block Diagram Rev A0 000825 Package Style: LPCC-24 15 GND2 Quad. ÷4 VCC2 6 0.500 +0.025 • Digitally Controlled Power Down Mode BB Filter Gain Control 7 2.50 sq 0.40 +0.05 Si BJT 0.90 +0.10 Ordering Information RF2679 RF2679 PCBA W-CDMA Receive AGC and Demodulator Fully Assembled Evaluation Board RF Micro Devices, Inc. 7625 Thorndike Road Greensboro, NC 27409, USA Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com 7-39 RF2679 Preliminary Absolute Maximum Ratings Parameter Supply Voltage Power Down Voltage (VPD) Input RF Power Ambient Operating Temperature Storage Temperature Parameter Rating Unit -0.5 to +5 -0.5 to VCC +0.7 +3 -40 to +85 -40 to +150 VDC VDC dBm °C °C Specification Min. Typ. Max. Caution! ESD sensitive device. RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s). Unit Overall (Cascaded) Maximum Gain Minimum Gain Gain Variation vs. VCC and T Input IP3 QUADRATURE DEMODULATORS 7 +85 +15 -3 Noise Figure IF Input Frequency Range IF Input Impedance I/Q Frequency Range I/Q Amplitude Balance I/Q Phase Balance Max I/Q Output Voltage 2040 1020 2760 1380 5 1 I/Q DC Output I/Q DC Offset Filter LO Input Frequency Range LO Input Level LO Input Impedance +3 -50 -4 5 45 190 2400 1200 2.5 0.2 1 680 340 VCC -1.3 5 fC =2.5MHz+ -250kHz 760 60 to 600 800 400 dB dB dB dBm dBm dB dB MHz Ω Ω MHz dB deg VPP 20 VDC mVDC 920 460 MHz mVPP Ω Ω Condition T=25 °C, VCC =3.0V, ZLOAD ≅60kΩ, LO=760MHz @400mVPP, IF Freq=191MHz, ZS =500Ω VGC =2.4V, Balanced VGC =0.3V, Balanced VCC =2.7V to 3.3V and T=-30°C to +85°C Maximum Gain Minimum Gain Maximum Gain Minimum Gain W-CDMA, Balanced W-CDMA, Single Ended Balanced, maximum output level, ZLOAD ≅60kΩ Common Mode I OUT+ to I OUT-; QOUT+ to Q OUT3rd order Butterworth after autocal FCLK=19.2MHz@100mVrms Balanced Balanced Single Ended Power Supply Supply Voltage Current Consumption 2.7 3.0 14.5 3.3 10 7-40 VDC mA µA Sleep Mode (ENABLE≤ 0.5V) Rev A0 000825 RF2679 Preliminary Pin 1 Function GC Description Interface Schematic Analog Gain Control for AGC Amplifiers. The valid control range is from 0.3 to 2.4VDC. These voltages are valid for ONLY a 68kΩ source impedance. The gain range for the AGC is 60dB. BIAS 21 kΩ GC 40 kΩ 2 DEC 3 WCDMA IN+ AGC decoupling pin. An external bypass capacitor of 10nF capacitor is required. The trace length between the pin and the bypass capacitor should be minimized. The ground side of the bypass capacitor should connect immediately to ground plane. W-CDMA Balanced Input pin. This pin is internally DC biased and should be DC blocked if connected to a device with a DC level present. For single-ended input operation, one pin is used as an input and the other W-CDMA input is AC coupled to ground. The balanced input impedance is 2.4kΩ, while the single-ended input impedance is 1.2kΩ. BIAS 1200 Ω BIAS 1200 Ω CDMA IN- CDMA IN+ 4 5 WCDMA INVCC1 6 VCC2 7 VCC3 8 9 LO+ LO- 10 GND1 11 VCC4 Rev A0 000825 Same as pin 4, except complimentary input. See pin 3. Supply voltage for the AGC input stage, band gap and gain control bias circuitry. This pin may be connected in parallel with pins 6 and 7. It should be bypassed by a 22nF capacitor. The trace length between the pin and the bypass capacitor should be minimized. The ground side of the bypass capacitor should connect immediately to ground plane. The part is designed to work from a 2.7V to 3.3V supply. Supply voltage for the bandgap, gain control bias circuitry, and AGC stages 2 and 3. This pin may be connected in parallel with pins 5 and 7. It should be bypassed by a 22nF capacitor. The trace length between the pin and the bypass capacitor should be minimized. The ground side of the bypass capacitor should connect immediately to ground plane. The part is designed to work from a 2.7V to 3.3V supply. Supply voltage for the LO divider and limiting amp. This pin may be connected in parallel with pins 5 and 6. It should be bypassed by a 22nF capacitor. The trace length between the pin and the bypass capacitor should be minimized. The ground side of the bypass capacitor should connect immediately to ground plane. The part is designed to work from a 2.7V to 3.3V supply. Same as pin 12, except complementary input. See pin 9. LO Balanced Input pin. This pin is internally DC biased and should be DC blocked if connected to a device with DC present. For single-ended input operation, one pin is used as an input and the other LO input is AC coupled to ground. The frequency of the signal applied to these pins is internally divided by a factor of 4, hence the carrier frequency for the modulator becomes one fourth of the applied frequency. The singleended input impedance is 400Ω (balanced is 800Ω). The LO input may be driven single-ended but balanced provides optimum gain and phase balance. B IA S 400 Ω LO - QUADRATURE DEMODULATORS 7 B IA S 400 Ω LO + Ground connection. Keep traces physically short and connect immediately to ground plane for best performance. Supply voltage for the baseband stage. This pin should be bypassed by a 100nF capacitor. 7-41 RF2679 Pin 12 Function FCLK 13 Q OUT- Preliminary Description Interface Schematic Reference clock for base band filters. 300 Ω Balanced Baseband Output of Q Mixer. This pin is internally DC biased and should be DC blocked externally. The output can be used in a single-ended configuration by leaving one of the two pins unconnected, however half the output voltage will be lost. VCC VCC Q O U T+ 150 µA Q O U T150 µA 14 15 16 17 Q OUT+ GND2 I OUTI OUT+ Same as pin 13, except complementary output. See pin 13. Ground connection for the baseband stage. Same as pin 17, except complementary output. See pin 17. Balanced Baseband Output of I Mixer. This pin is internally DC biased and should be DC blocked externally. The output can be used in a single-ended configuration by leaving one of the two pins unconnected, however half the output voltage will be lost. VCC VCC I O UT+ 150 µA I O UT150 µA QUADRATURE DEMODULATORS 7 18 19 20 IDCFB QDCFB CALEN 21 FL- 22 23 FL+ ENABLE 24 BG OUT 7-42 DC feedback capacitor for in-phase channel. DC feedback capacitor for quadrature channel. Calibration enable for BB filters. Calibration is performed when CALEN goes high. The calibration takes approximately 100µs, consumes 0.5mA, and is totally independent of the ENABLE pin. Once calibration is complete, the calibration word is stored and the calibration circuit is disabled. If the CALEN pin goes low of VCC is disabled, then the calibration word is lost and the IC needs recalibration. Balanced AGC Output/Demod Input. This balanced node is pinned out to allow shunt filtering of the AGC output signal as it enters the demodulator. The basic configuration of the filter should consist of a shunt inductor and shunt capacitor, both connected to the power supply, as the internal circuitry requires this power supply connection through the inductor to operate. Same as pin 21, except complementary. FL- FL+ VCC2 1.2 kΩ VCC2 VCC1 VCC1 1.2 kΩ See pin 21. Power Down Control. When logic “high” (≥VCC-0.3V), all circuits are operating; when logic “low” (≤0.5V), all circuits are turned off. Bandgap Voltage Reference. This voltage, constant over temperature and supply variation, is used to bias internal circuits. A 10nF external bypass capacitor is required. The trace length between the pin and the bypass capacitor should be minimized. The ground side of the bypass capacitor should connect immediately to ground plane. Rev A0 000825 RF2679 Preliminary BG OUT ENABLE FL+ FL- CALEN QDCFB Pin-Out 24 23 22 21 20 19 GC 1 18 IDCFB DEC 2 17 I OUT+ CDMA IN+ 3 16 I OUT- CDMA IN- 4 15 GND2 VCC1 5 14 Q OUT+ VCC2 6 13 Q OUT- 12 7 QUADRATURE DEMODULATORS FCLK 11 VCC4 10 GND1 9 LO- 8 LO+ VCC3 7 Rev A0 000825 7-43 RF2679 Preliminary Application Schematic VCC 68 nH 8 pF 68 nH 47 nF 8 pF NOTE: Route this node close to BGOUT CALEN ENABLE 50 nF 10 nF 0Ω 10 nF 24 23 22 21 20 50 nF 19 68 kΩ VGC 1 18 2 17 3 16 100 nF 10 nF I OUT+ 10 nF CDMA IN 10 nF 7 4 15 5 14 6 13 VCC QUADRATURE DEMODULATORS I OUT100 nF 2.4 kΩ Balanced 100 nF Q OUT+ Q OUT100 nF 7 8 9 10 11 12 + 10 uF 22 nF VCC 10 pF FCLCK IN 1 nF LO IN 100 nF 51 Ω 1 nF 7-44 Rev A0 000825 RF2679 Preliminary Evaluation Board Schematic (Download Bill of Materials from www.rfmd.com.) P1-3 1 +5 VDC 2 GND 3 -5 VDC CON3 P2 1 P2-2 2 ENABLE P2-3 3 VCC P2-4 C19 47 nF VCC P2-1 P1 P1-1 VGC L4 68 nH C20 8 pF L3 68 nH C18 8 pF CALEN 4 CON4 CALEN NOTE: Route this node close to BGOUT ENABLE C21 50 nF C1 10 nF R2 0Ω 24 C2 10 nF R1 68 kΩ 23 22 21 20 C22 50 nF 19 C16 100 nF 1 18 C3 10 nF L1 150 nH T1 T4-1 C6 4.7 pF C7 4.7 pF 200 Ω Balanced 2 17 3 16 4 15 5 14 C4 10 nF C5 10 nF 3 +7 2 - R3 2.4 kΩ 820 Ω Balanced R10 10 kΩ 50 Ω µstrip 6 4 C14 100 nF +5 VDC R14 51 Ω 8 J4 I OUT 5 CLC426AJE R11 20 kΩ -5 VDC + C29 1 µF C15 100 nF VCC L2 150 nH 600 Ω Balanced 6 13 C28 + 1 µF C12 100 nF R8 20 kΩ 7 7 8 9 10 11 R7 10 kΩ LPCC24 12 C13 100 nF +5 VDC U1 3 2 + - 8 6 R9 51 Ω 50 Ω µstrip 5 J3 Q OUT 4 C10 100 nF + C24 10 uF C23 10 pF C8 22 nF R15 51 Ω J2 LO IN 50 Ω µstrip T2 T4-1 C25 1 nF R4 200 Ω R5 10 kΩ R6 20 kΩ CLC426AJE C11 100 nF + C27 1 uF 50 Ω µstrip J5 FCLCK IN VCC C9 100 nF C26 1 nF Rev A0 000825 7 -5 VDC 7-45 QUADRATURE DEMODULATORS 50 Ω µstrip R12 10 kΩ C17 100 nF U2 7 VGC J1 CDMA IN C30 + 1 uF R13 20 kΩ RF2679 Preliminary Evaluation Board Layout Board Size 3.050” x 3.050” Board Thickness 0.031”, Board Material FR-4 QUADRATURE DEMODULATORS 7 7-46 Rev A0 000825 Preliminary RF2679 QUADRATURE DEMODULATORS 7 Rev A0 000825 7-47 RF2679 Preliminary WCDMA NF, Gain, IIP3 versus VGC (LO=760MHz, IF=191MHz) 100.0 NF 80.0 Voltage Gain IIP3 60.0 40.0 dB 20.0 0.0 0.0 5.0 10.0 15.0 20.0 -20.0 -40.0 -60.0 -80.0 VGC (Volts) QUADRATURE DEMODULATORS 7 7-48 Rev A0 000825