SN74ABT3612 64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCBS129G – JULY 1992 – REVISED APRIL 1998 D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Two Independent 64 × 36 Clocked FIFOs Buffering Data in Opposite Directions Mailbox-Bypass Register for Each FIFO Programmable Almost-Full and Almost-Empty Flags Microprocessor Interface Control Logic EFA, FFA, AEA, and AFA Flags Synchronized by CLKA D D D D D D D EFB, FFB, AEB, and AFB Flags Synchronized by CLKB Passive Parity Checking on Each Port Parity Generation Can Be Selected for Each Port Low-Power Advanced BiCMOS Technology Supports Clock Frequencies up to 67 MHz Fast Access Times of 10 ns Package Options Include 120-Pin Thin Quad Flat (PCB) and 132-Pin Plastic Quad Flat (PQ) Packages description The SN74ABT3612 is a high-speed, low-power BiCMOS bidirectional clocked FIFO memory. It supports clock frequencies up to 67 MHz and has read access times as fast as 10 ns. Two independent 64 × 36 dual-port SRAM FIFOs in this device buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions and two programmable flags (almost-full and almost-empty) to indicate when a selected number of words is stored in memory. Communication between each port can bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Parity is checked passively on each port and can be ignored if not desired. Parity generation can be selected for data read from each port. Two or more devices can be used in parallel to create wider datapaths. The SN74ABT3612 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. The full flag (FFA, FFB) and almost-full (AFA, AFB) flag of a FIFO are two-stage synchronized to the port clock that writes data to its array. The empty flag (EFA, EFB) and almost-empty (AEA, AEB) flag of a FIFO are two-stage synchronized to the port clock that reads data from its array. The SN74ABT3612 is characterized for operation from 0°C to 70°C. For more information on this device family, see the following application reports: D D D FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control (literature number SCAA007) Parity-Generate and Parity-Check Features for High-Bandwidth-Computing FIFO Applications (literature number SCAA015) Metastability Performance of Clocked FIFOs (literature number SCZA004) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74ABT3612 64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCBS129G – JULY 1992 – REVISED APRIL 1998 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 NC – No internal connection 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 W/RB CLKB ENB CSB FFB 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 AFA FFA CSA ENA CLKA W/RA VCC PGA PEFA MBF2 MBA FS1 FS0 ODD/EVEN RST GND NC NC NC NC MBB MBF1 PEFB PGB VCC A23 A22 A21 GND A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 GND A9 A8 A7 VCC A6 A5 A4 A3 GND A2 A1 A0 EFA AEA 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 A24 A25 A26 VCC A27 A28 A29 GND A30 A31 A32 A33 A34 A35 GND B35 B34 B33 B32 B31 B30 GND B29 B28 B27 VCC B26 B25 B24 B23 PCB PACKAGE (TOP VIEW) B22 B21 GND B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 GND B9 B8 B7 VCC B6 B5 B4 B3 GND B2 B1 B0 EFB AEB AFB SN74ABT3612 64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCBS129G – JULY 1992 – REVISED APRIL 1998 AFA FFA CSA ENA CLKA W/RA VCC PGA PEFA GND MBF2 MBA FS1 FS0 ODD/EVEN RST GND NC NC NC NC MBB MBF1 GND PEFB PGB VCC W/RB CLKB ENB CSB FFB AFB PQ PACKAGE† (TOP VIEW) 17 16 15 14 13 12 11 10 9 GND AEA EFA A0 A1 A2 GND A3 A4 A5 A6 VCC A7 A8 A9 GND A10 A11 VCC A12 A13 A14 GND A15 A16 A17 A18 A19 A20 GND A21 A22 A23 8 7 6 5 4 3 2 18 126 124 122 120 118 1 132 130 128 129 131 125 123 121 119 127 117 116 19 115 20 114 21 113 22 112 23 111 24 110 25 109 26 108 27 107 28 106 29 105 30 104 31 103 32 102 33 101 34 100 35 99 36 98 37 97 38 96 39 95 40 94 41 93 42 92 43 91 44 90 45 89 46 88 47 87 48 86 49 85 84 50 GND AEB EFB B0 B1 B2 GND B3 B4 B5 B6 VCC B7 B8 B9 GND B10 B11 VCC B12 B13 B14 GND B15 B16 B17 B18 B19 B20 GND B21 B22 B23 VCC A24 A25 A26 GND A27 A28 A29 VCC A30 A31 A32 GND A33 A34 A35 GND B35 B34 B33 GND B32 B31 B30 VCC B29 B28 B27 GND B26 B25 B24 VCC 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 NC – No internal connection † Uses Yamaichi socket IC51-1324-828 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74ABT3612 64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCBS129G – JULY 1992 – REVISED APRIL 1998 functional block diagram CLKA CSA W/RA ENA MBA Port-A Control Logic MBF1 ODD/ EVEN 64 × 36 SRAM Write Pointer Output Register Device Control PGB Parity Generation Input Register Mail1 Register RST PEFB Parity Gen/Check 36 Read Pointer Status-Flag Logic FFA AFA EFB AEB FIFO1 36 Programmable-Flag Offset Register FS0 FS1 A0 – A35 B0 – B35 FIFO2 Status-Flag Logic Parity Generation Output Register Read Pointer PGA PEFA Parity Gen/Check 36 Write Pointer 64 × 36 SRAM Mail2 Register Port-B Control Logic MBF2 4 FFB AFB Input Register EFA AEA POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CLKB CSB W/RB ENB MBB SN74ABT3612 64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCBS129G – JULY 1992 – REVISED APRIL 1998 Terminal Functions PIN NAME I/O A0 – A35 I/O DESCRIPTION Port-A data. The 36-bit bidirectional data port for side A. AEA O (port A) Port-A almost-empty flag. Programmable flag synchronized to CLKA. AEA is low when the number of words in FIFO2 is less than or equal to the value in offset register X. AEB O (port B) Port-B almost-empty flag. Programmable flag synchronized to CLKB. AEB is low when the number of words in FIFO1 is less than or equal to the value in offset register X. AFA O (port A) Port-A almost-full flag. Programmable flag synchronized to CLKA. AFA is low when the number of empty locations in FIFO1 is less than or equal to the value in offset register X. AFB O (port B) Port-B almost-full flag. Programmable flag synchronized to CLKB. AFB is low when the number of empty locations in FIFO2 is less than or equal to the value in offset register X. B0 – B35 I/O Port-B data. The 36-bit bidirectional data port for side B. CLKA I Port-A clock. CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous or coincident to CLKB. EFA, FFA, AFA, and AEA are synchronized to the low-to-high transition of CLKA. CLKB I Port-B clock. CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous or coincident to CLKA. EFB, FFB, AFB, and AEB are synchronized to the low-to-high transition of CLKB. CSA I Port-A chip select. CSA must be low to enable a low-to-high transition of CLKA to read or write data on port A. The A0 – A35 outputs are in the high-impedance state when CSA is high. CSB I Port-B chip select. CSB must be low to enable a low-to-high transition of CLKB to read or write data on port B. The B0 – B35 outputs are in the high-impedance state when CSB is high. EFA O (port A) Port-A empty flag. EFA is synchronized to the low-to-high transition of CLKA. When EFA is low, FIFO2 is empty and reads from its memory are disabled. Data can be read from FIFO2 to the output register when EFA is high. EFA is forced low when the device is reset and is set high by the second low-to-high transition of CLKA after data is loaded into empty FIFO2 memory. EFB O (port B) Port-B empty flag. EFB is synchronized to the low-to-high transition of CLKB. When EFB is low, FIFO1 is empty and reads from its memory are disabled. Data can be read from FIFO1 to the output register when EFB is high. EFB is forced low when the device is reset and is set high by the second low-to-high transition of CLKB after data is loaded into empty FIFO1 memory. ENA I Port-A enable. ENA must be high to enable a low-to-high transition of CLKA to read or write data on port A. ENB I Port-B enable. ENB must be high to enable a low-to-high transition of CLKB to read or write data on port B. FFA O (port A) Port-A full flag. FFA is synchronized to the low-to-high transition of CLKA. When FFA is low, FIFO1 is full and writes to its memory are disabled. FFA is forced low when the device is reset and is set high by the second low-to-high transition of CLKA after reset. FFB O (port B) Port-B full flag. FFB is synchronized to the low-to-high transition of CLKB. When FFB is low, FIFO2 is full and writes to its memory are disabled. FFB is forced low when the device is reset and is set high by the second low-to-high transition of CLKB after reset. FS1, FS0 I Flag-offset selects. The low-to-high transition of RST latches the values of FS0 and FS1, which selects one of four preset values for the almost-empty flag and almost-full flag offset. MBA I Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation. When the A0 – A35 outputs are active, a high level on MBA selects data from the mail2 register for output and a low level selects FIFO2 output register data for output. MBB I Port-B mailbox select. A high level on MBB chooses a mailbox register for a port-B read or write operation. When the B0 – B35 outputs are active, a high level on MBB selects data from the mail1 register for output and a low level selects FIFO1 output register data for output. MBF1 O Mail1 register flag. MBF1 is set low by the low-to-high transition of CLKA that writes data to the mail1 register. Writes to the mail1 register are inhibited while MBF1 is low. MBF1 is set high by a low-to-high transition of CLKB when a port-B read is selected and MBB is high. MBF1 is set high when the device is reset. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74ABT3612 64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCBS129G – JULY 1992 – REVISED APRIL 1998 Terminal Functions (Continued) PIN NAME I/O DESCRIPTION MBF2 O Mail2 register flag. MBF2 is set low by the low-to-high transition of CLKB that writes data to the mail2 register. Writes to the mail2 register are inhibited while MBF2 is low. MBF2 is set high by a low-to-high transition of CLKA when a port-A read is selected and MBA is high. MBF2 is set high when the device is reset. ODD/ EVEN I Odd/even parity select. Odd parity is checked on each port when ODD/EVEN is high and even parity is checked when ODD/EVEN is low. ODD/EVEN also selects the type of parity generated for each port if parity generation is enabled for a read operation. O (port A) Port-A parity error flag. When any byte applied to A0 – A35 fails parity, PEFA is low. Bytes are organized as A0 – A8, A9 – A17, A18 – A26, and A27 – A35, with the most-significant bit of each byte serving as the parity bit. The type of parity checked is determined by the state of ODD/EVEN. The parity trees used to check the A0 – A35 inputs are shared by the mail2 register to generate parity if parity generation is selected by PGA. Therefore, if a mail2 read with parity generation is set up by having W/RA low, MBA high, and PGA high, PEFA is forced high regardless of the state of the A0 – A35 inputs. PEFB O (port B) Port-B parity error flag. When any byte applied to terminals B0 – B35 fails parity, PEFB is low. Bytes are organized as B0 – B8, B9 – B17, B18 – B26, and B27 – B35, with the most-significant bit of each byte serving as the parity bit. The type of parity checked is determined by the state of ODD/EVEN. The parity trees used to check the B0 – B35 inputs are shared by the mail1 register to generate parity if parity generation is selected by PGB. Therefore, if a mail1 read with parity generation is set up by having W/RB low, MBB high, and PGB high, PEFB is forced high regardless of the state of the B0 – B35 inputs. PGA I Port-A parity generation. Parity is generated for data reads from port A when PGA is high. The type of parity generated is selected by the state of ODD/EVEN. Bytes are organized as A0 – A8, A9 – A17, A18 – A26, and A27 – A35. The generated parity bits are output in the most-significant bit of each byte. PGB I Port-B parity generation. Parity is generated for data reads from port B when PGB is high. The type of parity generated is selected by the state of ODD/EVEN. Bytes are organized as B0 – B8, B9 – B17, B18 – B26, and B27 – B35. The generated parity bits are output in the most-significant bit of each byte. RST I Reset. To reset the device, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must occur while RST is low. This sets AFA, AFB, MBF1, and MBF2 high and EFA, EFB, AEA, AEB, FFA, and FFB low. The low-to-high transition of RST latches the status of FS1 and FS0 to select almost-full flag and almost-empty flag offset. W/RA I Port-A write/read select. W/RA high selects a write operation and a low selects a read operation on port A for a low-to-high transition of CLKA. The A0 – A35 outputs are in the high-impedance state when W/RA is high. W/RB I Port-B write/read select. W/RB high selects a write operation and a low selects a read operation on port B for a low-to-high transition of CLKB. The B0 – B35 outputs are in the high-impedance state when W/RB is high. PEFA detailed description reset The SN74ABT3612 is reset by taking the reset (RST) input low for at least four port-A clock (CLKA) and four port-B clock (CLKB) low-to-high transitions. RST can switch asynchronously to the clocks. A device reset initializes the internal read and write pointers of each FIFO and forces the full flags (FFA, FFB) low, the empty flags (EFA, EFB) low, the almost-empty flags (AEA, AEB) low, and the almost-full flags (AFA, AFB) high. A reset also forces the mailbox flags (MBF1, MBF2) high. After a reset, FFA is set high after two low-to-high transitions of CLKA and FFB is set high after two low-to-high transitions of CLKB. The device must be reset after power up before data is written to its memory. A low-to-high transition on RST loads the almost-full and almost-empty offset register (X) with the value selected by the flag-select (FS0, FS1) inputs. The values that can be loaded into the register are shown in Table 1. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ABT3612 64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCBS129G – JULY 1992 – REVISED APRIL 1998 reset (continued) Table 1. Flag Programming FS1 FS0 RST ALMOST-FULL AND ALMOST-EMPTY FLAG OFFSET REGISTER (X) H H ↑ 16 H L ↑ 12 L H ↑ 8 L L ↑ 4 FIFO write/read operation The state of the port-A data (A0 – A35) outputs is controlled by the port-A chip select (CSA) and the port-A write/read select (W/RA). The A0 – A35 outputs are in the high-impedance state when either CSA or W/RA is high. The A0 – A35 outputs are active when both CSA and W/RA are low. Data is loaded into FIFO1 from the A0– A35 inputs on a low-to-high transition of CLKA when CSA is low, W/RA is high, ENA is high, MBA is low, and FFA is high. Data is read from FIFO2 to the A0 – A35 outputs by a low-to-high transition of CLKA when CSA is low, W/RA is low, ENA is high, MBA is low, and EFA is high (see Table 2). Table 2. Port-A Enable Function Table CSA W/RA ENA MBA CLKA A0 – A35 OUTPUTS PORT FUNCTION H X X X X In high-impedance state None L H L X X In high-impedance state None L H H L ↑ In high-impedance state FIFO1 write L H H H ↑ In high-impedance state Mail1 write L L L L X Active, FIFO2 output register None L L H L ↑ Active, FIFO2 output register FIFO2 read L L L H X Active, mail2 register None L L H H ↑ Active, mail2 register Mail2 read (set MBF2 high) The port-B control signals are identical to those of port A. The state of the port-B data (B0 – B35) outputs is controlled by the port-B chip select (CSB) and the port-B write/read select (W/RB). The B0 – B35 outputs are in the high-impedance state when either CSB or W/RB is high. The B0 – B35 outputs are active when both CSB and W/RB are low. Data is loaded into FIFO2 from the B0 – B35 inputs on a low-to-high transition of CLKB when CSB is low, W/RB is high, ENB is high, MBB is low, and FFB is high. Data is read from FIFO1 to the B0 – B35 outputs by a low-to-high transition of CLKB when CSB is low, W/RB is low, ENB is high, MBB is high, and EFB is high (see Table 3). The setup- and hold-time constraints to the port clocks for the port-chip selects (CSA, CSB) and write/read selects (W/RA, W/RB) are only for enabling write and read operations and are not related to high-impedance control of the data outputs. If a port enable is low during a clock cycle, the port-chip select and write/read select can change states during the setup- and hold-time window of the cycle. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN74ABT3612 64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCBS129G – JULY 1992 – REVISED APRIL 1998 FIFO write/read operation (continued) Table 3. Port-B Enable Function Table CSB W/RB ENB MBB CLKB B0 – B35 OUTPUTS PORT FUNCTION H X X X X In high-impedance state None L H L X X In high-impedance state None L H H L ↑ In high-impedance state FIFO2 write L H H H ↑ In high-impedance state Mail2 write L L L L X Active, FIFO1 output register None L L H L ↑ Active, FIFO1 output register FIFO1 read L L L H X Active, mail1 register None L L H H ↑ Active, mail1 register Mail1 read (set MBF1 high) synchronized FIFO flags Each FIFO flag is synchronized to its port clock through two flip-flop stages. This is done to improve flag reliability by reducing the probability of metastable events on the output when CLKA and CLKB operate asynchronously to one another. EFA, AEA, FFA, and AFA are synchronized to CLKA. EFB, AEB, FFB, and AFB are synchronized to CLKB. Tables 4 and 5 show the relationship of each port flag to FIFO1 and FIFO2. Table 4. FIFO1 Flag Operation NUMBER OF WORDS IN FIFO1† SYNCHRONIZED TO CLKB EFB AEB SYNCHRONIZED TO CLKA AFA FFA 0 L L H H 1 to X H L H H (X +1) to [64 – (X +1)] H H H H (64 – X) to 63 H H L H 64 H H L L † X is the value in the almost-empty flag and almost-full flag offset register. Table 5. FIFO2 Flag Operation NUMBER OF WORDS IN FIFO2† SYNCHRONIZED TO CLKA SYNCHRONIZED TO CLKB EFA AEA AFB FFB 0 L L H H 1 to X H L H H (X +1) to [64 – (X +1)] H H H H (64 – X) to 63 H H L H 64 H H L L † X is the value in the almost-empty flag and almost-full flag offset register. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ABT3612 64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCBS129G – JULY 1992 – REVISED APRIL 1998 empty flags (EFA, EFB) The empty flag of a FIFO is synchronized to the port clock that reads data from its array. When the empty flag is high, new data can be read to the FIFO output register. When the empty flag is low, the FIFO is empty and attempted FIFO reads are ignored. The read pointer of a FIFO is incremented each time a new word is clocked to the output register. A word written to a FIFO can be read to the FIFO output register in a minimum of three cycles of the empty flag synchronizing clock; therefore, an empty flag is low if a word in memory is the next data to be sent to the FIFO output register and two cycles of the port clock that reads data from the FIFO have not elapsed since the time the word was written. The empty flag of the FIFO is set high by the second low-to-high transition of the synchronizing clock and the new data word can be read to the FIFO output register in the following cycle. A low-to-high transition on an empty flag synchronizing clock begins the first synchronization cycle of a write if the clock transition occurs at time tsk1, or greater, after the write. Otherwise, the subsequent clock cycle can be the first synchronization cycle (see Figures 6 and 7). full flags (FFA, FFB) The full flag of a FIFO is synchronized to the port clock that writes data to its array. When the full flag is high, a memory location is free in the SRAM to receive new data. No memory locations are free when the full flag is low and attempted writes to the FIFO are ignored. Each time a word is written to a FIFO, the write pointer is incremented. From the time a word is read from a FIFO, the previous memory location is ready to be written in a minimum of three cycles of the full flag synchronizing clock; therefore, a full flag is low if less than two cycles of the full-flag synchronizing clock have elapsed since the next memory write location has been read. The second low-to-high transition on the full-flag synchronizing clock after the read sets the full flag high and data can be written in the following clock cycle. A low-to-high transition on a full-flag synchronizing clock begins the first synchronization cycle of a read if the clock transition occurs at time tsk1, or greater, after the read. Otherwise, the subsequent clock cycle can be the first synchronization cycle (see Figures 8 and 9). almost-empty flags (AEA, AEB) The almost-empty flag of a FIFO is synchronized to the port clock that reads data from its array. The almost-empty state is defined by the value of the almost-full and almost-empty offset register (X). This register is loaded with one of four preset values during a device reset (see reset). An almost-empty flag is low when the FIFO contains X or less words in memory and is high when the FIFO contains (X + 1) or more words. Two low-to-high transitions of the almost-empty flag synchronizing clock are required after a FIFO write for the almost-empty flag to reflect the new level of fill; therefore, the almost-empty flag of a FIFO containing (X + 1) or more words remains low if two cycles of the synchronizing clock have not elapsed since the write that filled the memory to the (X + 1) level. An almost-empty flag is set high by the second low-to-high transition of the synchronizing clock after the FIFO write that fills memory to the (X + 1) level. A low-to-high transition of an almost-empty flag synchronizing clock begins the first synchronization cycle if it occurs at time tsk2, or greater, after the write that fills the FIFO to (X + 1) words. Otherwise, the subsequent synchronizing clock cycle can be the first synchronization cycle (see Figures 11 and 12). almost-full flags (AFA, AFB) The almost-full flag of a FIFO is synchronized to the port clock that writes data to its array. The almost-full state is defined by the value of the almost-full and almost-empty offset register (X). This register is loaded with one of four preset values during a device reset (see reset). An almost-full flag is low when the FIFO contains (64 – X) or more words in memory and is high when the FIFO contains [64 – (X + 1)] or less words. Two low-to-high transitions of the almost-full flag synchronizing clock are required after a FIFO read for the almost-full flag to reflect the new level of fill; therefore, the almost-full flag of a FIFO containing [64 – (X + 1)] or less words remains low if two cycles of the synchronizing clock have not elapsed since the read that reduced the number of words in memory to [64 – (X + 1)]. An almost-full flag is set high by the second low-to-high POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN74ABT3612 64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCBS129G – JULY 1992 – REVISED APRIL 1998 almost-full flags (AFA, AFB) (continued) transition of the synchronizing clock after the FIFO read that reduces the number of words in memory to [64 – (X + 1)]. A low-to-high transition of an almost-full flag synchronizing clock begins the first synchronization cycle if it occurs at time tsk2, or greater, after the read that reduces the number of words in memory to [64 – (X + 1)]. Otherwise, the subsequent synchronizing clock cycle can be the first synchronization cycle (see Figures 13 and 14). mailbox registers Each FIFO has a 36-bit bypass register to pass command and control information between port A and port B without putting it in queue. The mailbox-select (MBA, MBB) inputs choose between a mail register and a FIFO for a port-data-transfer operation. A low-to-high transition on CLKA writes A0 – A35 data to the mail1 register when a port-A write is selected by CSA, W/RA, and ENA and MBA is high. A low-to-high transition on CLKB writes B0 – B35 data to the mail2 register when a port-B write is selected by CSB, W/RB, and ENB and MBB is high. Writing data to a mail register sets the corresponding flag (MBF1 or MBF2) low. Attempted writes to a mail register are ignored while the mail flag is low. When a port’s data outputs are active, the data on the bus comes from the FIFO output register when the port mailbox-select input (MBA, MBB) is low and from the mail register when MBA/MBB is high. The mail1 register flag (MBF1) is set high by a low-to-high transition on CLKB when a port-B read is selected by CSB, W/RB, and ENB and MBB is high. The mail2 register flag (MBF2) is set high by a low-to-high transition on CLKA when a port-A read is selected by CSA, W/RA, and ENA and MBA is high. The data in a mail register remains intact after it is read and changes only when new data is written to the register. parity checking The port-A inputs (A0 – A35) and port-B inputs (B0 – B35) each have four parity trees to check the parity of incoming (or outgoing) data. A parity failure on one or more bytes of the input bus is reported by a low level on the port-parity-error flag (PEFA, PEFB). Odd- or even-parity checking can be selected and the parity-error flags can be ignored if this feature is not desired. Parity status is checked on each input bus according to the level of the odd/even parity (ODD/EVEN) select input. A parity error on one or more bytes of a port is reported by a low level on the corresponding PEFA, PEFB. Port-A bytes are arranged as A0 – A8, A9 – A17, A18 – A26, and A27 – A35, with the most-significant bit of each byte used as the parity bit. Port-B bytes are arranged as B0 – B8, B9 – B17, B18 – B26, and B27 – B35, with the most-significant bit of each byte used as the parity bit. When odd/even parity is selected, PEFA, PEFB is low if any byte on the port has an odd/even number of low levels applied to the bits. The four parity trees used to check the A0 – A35 inputs are shared by the mail2 register when parity generation is selected for port-A reads (PGA = high). When a port-A read from the mail2 register with parity generation is selected with W/RA low, CSA low, ENA high, MBA high, and PGA high, PEFA is held high, regardless of the levels applied to the A0 – A35 inputs. Likewise, the parity trees used to check the B0 – B35 inputs are shared by the mail1 register when parity generation is selected for port-B reads (PGB = high). When a port-B read from the mail1 register with parity generation is selected with W/RB low, CSB low, ENB high, MBB high, and PGB high, PEFB is held high, regardless of the levels applied to the B0 – B35 inputs. parity generation A high level on the port-A parity-generate select (PGA) or port-B parity-generate select (PGB) enables the SN74ABT3612 to generate parity bits for port reads from a FIFO or mailbox register. Port-A bytes are arranged as A0 – A8, A9 – A17, A18 – A26, and A27 – A35, with the most-significant bit of each byte used as the parity bit. Port-B bytes are arranged as B0 – B8, B9 – B17, B18 – B26, and B27 – B35, with the most-significant bit of each byte used as the parity bit. A write to a FIFO or mail register stores the levels applied to all 36 inputs, regardless of the state of the parity-generate select (PGA, PGB) inputs. When data is read from a port with parity generation selected, the lower eight bits of each byte are used to generate a parity bit according to the level on the ODD/EVEN select. The generated parity bits are substituted for the levels originally written to the most-significant bits of each byte as the word is read to the data outputs. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ABT3612 64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCBS129G – JULY 1992 – REVISED APRIL 1998 parity generation (continued) Parity bits for FIFO data are generated after the data is read from SRAM and before the data is written to the output register. Therefore, the port-A parity generate select (PGA) and odd/even parity select (ODD/EVEN) have setup- and hold-time constraints to the port-A clock (CLKA) and the port-B parity generate select (PGB) and ODD/EVEN have setup- and hold-time constraints to the port-B clock (CLKB). These timing constraints apply only for a rising clock edge used to read a new word to the FIFO output register. The circuit used to generate parity for the mail1 data is shared by the port-B bus (B0 – B35) to check parity and the circuit used to generate parity for the mail2 data is shared by the port-A bus (A0 – A35) to check parity. The shared parity trees of a port are used to generate parity bits for the data in a mail register when W/RA, W/RB is low; MBA, MBB is high; CSA, CSB is low; ENA, ENB is high; and PGA, PGB is high. Generating parity for mail-register data does not change the contents of the register. CLKA th(RS) CLKB tsu(RS) RST FS1, FS0 th(FS) tsu(FS) ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏ 0,1 tpd(C-FF) FFA tpd(C-FF) tpd(C-EF) EFA tpd(C-FF) FFB tpd(C-FF) tpd(C-EF) EFB tpd(C-AE) AEA tpd(C-AF) AFA MBF1, MBF2 tpd(R-F) tpd(C-AE) AEB tpd(C-AF) AFB Figure 1. Device Reset Loading the X Register With the Value of Eight POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SN74ABT3612 64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCBS129G – JULY 1992 – REVISED APRIL 1998 tc tw(CLKH) tw(CLKL) CLKA FFA High ÌÌÌ ÌÌÌ ÏÏÏÏÏÏÏÏ ÌÌÌ ÎÎÎÎÎÎ ÏÏÏÏÏÏÏÏ ÌÌÌ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÌÌÌ ÏÏÏÏÏÏ ÎÎÎÎÎÎÎÎ ÌÌÌ ÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ ÌÌÌÌÌÌ ÎÎÎÎÎÎÎ ÏÏÏÏÏÏ ÌÌÌÌÌÌÌ ÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌ ÌÌ ÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌ Ì tsu(EN1) th(EN1) tsu(EN1) th(EN1) tsu(EN3) th(EN3) tsu(EN2) th(EN2) CSA W/RA MBA th(EN) tsu(EN) tsu(EN2) ENA tsu(D) th(D) W1† A0 – A35 W2† No Operation ODD/ EVEN tpd(D-PE) PEFA tpd(D-PE) Valid Valid † Written to FIFO1 Figure 2. Port-A Write-Cycle Timing for FIFO1 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 th(EN2) SN74ABT3612 64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCBS129G – JULY 1992 – REVISED APRIL 1998 tc tw(CLKH) tw(CLKL) CLKB FFB CSB W/RB MBB ENB High ÌÌÌ ÌÌÌ ÏÏÏÏÏÏÏ ÌÌÌ ÎÎÎÎÎÎ ÏÏÏÏÏÏÏ ÌÌÌ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÌÌÌ ÏÏÏÏÏÏ ÎÎÎÎÎÎÎ ÌÌÌ ÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÌÌÌÌÌÌÌ ÎÎÎÎÎÎ ÏÏÏÏÏÏ ÌÌÌÌÌÌÌ ÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌ ÌÌ ÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌ É tsu(EN1) th(EN1) tsu(EN1) th(EN1) tsu(EN3) th(EN3) tsu(EN2) th(EN2) tsu(D) B0 – B35 ODD/ EVEN th(EN2) tsu(EN2) th(D) W1† W2† tpd(D-PE) PEFB th(EN2) tsu(EN2) No Operation tpd(D-PE) Valid Valid † Written to FIFO2 Figure 3. Port-B Write-Cycle Timing for FIFO2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 SN74ABT3612 64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCBS129G – JULY 1992 – REVISED APRIL 1998 tc tw(CLKH) tw(CLKL) CLKB High EFB CSB ÎÎÎÎ ÏÏÏÏÏ W/RB MBB tsu(EN2) ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ ÌÌ ÌÌ ÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌ ENB tpd(M-DV) ten B0 – B35 PGB, ODD/ EVEN † Read from FIFO1 tsu(PG) tsu(EN2) tsu(EN2) ÌÌÌÌÌÌ ÎÎÎÎÎÎ ÏÏÏÏÏ ÌÌÌÌÌÌ ÎÎÎÎÎÎ ÏÏÏÏÏ th(EN2) th(EN2) ta Previous Data† th(PG) No Operation ta Word 1† Word 2† tdis ÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌ tsu(PG) th(PG) Figure 4. Port-B Read-Cycle Timing for FIFO1 14 th(EN2) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ABT3612 64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCBS129G – JULY 1992 – REVISED APRIL 1998 tc tw(CLKH) tw(CLKL) CLKA EFA High CSA W/RA ÎÎÎ ÏÏÏÏÏÏ MBA tsu(EN2) ENA ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÌÌÌ ÌÌÌ ÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌ tpd(M-DV) ten A0 – A35 PGA, ODD/ EVEN † Read from FIFO2 tsu(PG) tsu(EN2) tsu(EN2) ÌÌÌÌÌÌÌ ÎÎÎÎÎÎ ÏÏÏÏÏÏ ÌÌÌÌÌÌÌ ÎÎÎÎÎÎ ÏÏÏÏÏÏ th(EN2) th(EN2) ta Previous Data† th(PG) th(EN2) No Operation ta Word 1† tdis Word 2† ÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ tsu(PG) th(PG) Figure 5. Port-A Read-Cycle Timing for FIFO2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 SN74ABT3612 64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCBS129G – JULY 1992 – REVISED APRIL 1998 tc tw(CLKH) tw(CLKL) CLKA CSA Low W/RA High tsu(EN3) ÎÎÎÎÎ ÏÏÏÏ ÏÏÏÏ ÌÌÌÌÌ tsu(EN2) th(EN2) ENA FFA High A0 – A35 ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÎÎÎÎ ÎÎÎÎ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ th(EN3) MBA tsu(D) th(D) W1 tsk1† tc tw(CLKL) tw(CLKH) 1 CLKB 2 tpd(C-EF) tpd(C-EF) FIFO1 Empty EFB CSB Low W/RB Low MBB Low ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÎÎÎÎÎÎÎÎÎÎÎÎÎ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ th(EN2) tsu(EN2) ENB ta W1 B0 – B35 † tsk1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition high in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tsk1, the transition of EFB high may occur one CLKB cycle later than shown. Figure 6. EFB-Flag Timing and First Data Read When FIFO1 Is Empty 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ABT3612 64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCBS129G – JULY 1992 – REVISED APRIL 1998 tc tw(CLKH) tw(CLKL) CLKB CSB W/RB MBB ENB FFB B0 – B35 Low High tsu(EN3) th(EN3) tsu(EN2) th(EN2) ÎÎÎÎÎ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÎÎÎÎ ÏÏÏÏÏÎÎÎÎ ÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ High tsu(D) th(D) W1 tsk1† tc tw(CLKL) tw(CLKH) 1 CLKA 2 tpd(C-EF) tpd(C-EF) FIFO2 Empty EFA CSA Low W/RA Low MBA Low ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ th(EN2) tsu(EN2) ENA ta A0 – A35 W1 † tsk1 is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition high in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tsk1, the transition of EFA high may occur one CLKA cycle later than shown. Figure 7. EFA-Flag Timing and First Data Read When FIFO2 Is Empty POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 SN74ABT3612 64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCBS129G – JULY 1992 – REVISED APRIL 1998 tc tw(CLKH) tw(CLKL) CLKB CSB Low W/RB Low MBB Low ÏÏÏ ÎÎÎÎ ÏÏÏ ÎÎÎÎ tsu(EN2) ENB EFB High th(EN2) ta B0 – B35 Previous Word in FIFO1 Output Register Next Word From FIFO1 tsk1† tc tw(CLKH) 1 CLKA FIFO1 Full FFA CSA tw(CLKL) 2 tpd(C-FF) tpd(C-FF) Low ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ W/RA High tsu(EN3) MBA tsu(EN2) ENA tsu(D) A0 – A35 ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌ th(EN3) th(EN2) th(D) To FIFO1 † tsk1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition high in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tsk1, FFA may transition high one CLKA cycle later than shown. Figure 8. FFA-Flag Timing and First Available Write When FIFO1 Is Full 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ABT3612 64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCBS129G – JULY 1992 – REVISED APRIL 1998 tc tw(CLKH) tw(CLKL) CLKA CSA Low W/RA Low MBA Low ÏÏÏÏ ÎÎÎ ÏÏÏÏ ÎÎÎ tsu(EN2) ENA EFA High th(EN2) ta A0 – A35 Previous Word in FIFO2 Output Register Next Word From FIFO2 tsk1† tc tw(CLKH) 1 CLKB FIFO2 Full FFB CSB W/RB tw(CLKL) 2 tpd(C-FF) tpd(C-FF) Low ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ High tsu(EN3) MBB tsu(EN2) ENB tsu(D) B0 – B35 ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌ th(EN3) th(EN2) th(D) To FIFO2 † tsk1 is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition high in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tsk1, FFB may transition high one CLKB cycle later than shown. Figure 9. FFB-Flag Timing and First Available Write When FIFO2 Is Full POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 SN74ABT3612 64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCBS129G – JULY 1992 – REVISED APRIL 1998 CLKA ÏÏÏÏÏÎÎÎÎÎ ÏÏÏÏÏÎÎÎÎÎ th(EN2) tsu(EN2) ENA tsk2† CLKB 1 2 tpd(C-AE) tpd(C-AE) AEB X Words in FIFO1 ÏÏÏÏÏ ÎÎÎÎ ÏÏÏÏÏ ÎÎÎÎ (X + 1) Words in FIFO1 tsu(EN2) ENB th(EN2) † tsk2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition high in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tsk2, AEB may transition high one CLKB cycle later than shown. NOTE A: FIFO1 write (CSA = L, W/RA = H, MBA = L), FIFO1 read (CSB = L, W/RB = L, MBB = L). Figure 10. Timing for AEB When FIFO1 Is Almost Empty CLKB ÏÏÏÏÏÎÎÎÎÎ ÏÏÏÏÏÎÎÎÎÎ th(EN2) tsu(EN2) ENB tsk2‡ CLKA 2 1 tpd(C-AE) tpd(C-AE) AEA X Words in FIFO2 (X + 1) Words in FIFO2 tsu(EN2) ÏÏÏÏÏ ÎÎÎÎ ÏÏÏÏÏ ÎÎÎÎ ENA th(EN2) ‡ tsk2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition high in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tsk2, AEA may transition high one CLKA cycle later than shown. NOTE A: FIFO2 write (CSB = L, W/RB = H, MBB = L), FIFO2 read (CSA = L, W/RA = L, MBA = L). Figure 11. Timing for AEA When FIFO2 Is Almost Empty 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ABT3612 64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCBS129G – JULY 1992 – REVISED APRIL 1998 tsk2† CLKA ENA ÏÏÏÏÏ ÎÎÎÎÎ ÏÏÏÏÏ ÎÎÎÎÎ 1 tpd(C-AF) AFA 2 th(EN2) tsu(EN2) tpd(C-AF) (64 – X) Words in FIFO1 [64 – (X + 1)] Words in FIFO1 ÏÏÏÏÏÎÎÎÎÎ ÏÏÏÏÏÎÎÎÎÎ CLKB tsu(EN2) ENB th(EN2) † tsk2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition high in the next CLKA cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tsk2, AFA may transition high one CLKB cycle later than shown. NOTE A: FIFO1 write (CSA = L, W/RA = H, MBA = L), FIFO1 read (CSB = L, W/RB = L, MBB = L). Figure 12. Timing for AFA When FIFO1 Is Almost Full tsk2‡ CLKB ENB ÏÏÏÏÏ ÎÎÎÎÎ ÏÏÏÏÏ ÎÎÎÎÎ 1 tpd(C-AF) AFB CLKA [64 – (X + 1)] Words in FIFO2 tpd(C-AF) (64 – X) Words in FIFO2 ÏÏÏÏÏÎÎÎÎÎ ÏÏÏÏÏÎÎÎÎÎ tsu(EN2) ENA 2 th(EN2) tsu(EN2) th(EN2) ‡ tsk2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition high in the next CLKB cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tsk2, AFB may transition high one CLKA cycle later than shown. NOTE A: FIFO2 write (CSB = L, W/RB= H, MBB = L), FIFO2 read (CSA = L, W/RA = L, MBA = L). Figure 13. Timing for AFB When FIFO2 Is Almost Full POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 SN74ABT3612 64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCBS129G – JULY 1992 – REVISED APRIL 1998 CLKA th(EN1) tsu(EN1) ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ ÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌ CSA W/RA MBA ENA tsu(D) A0 – A35 W1 ÌÌÌ ÌÌÌ ÌÌÌ ÌÌÌ ÌÌÌ ÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ th(D) CLKB tpd(C-MF) tpd(C-MF) MBF1 CSB ÎÎÎÎÎ W/RB MBB ÏÏÏÏÏÏÏ ÏÏÏÏ ÎÎÎ ÌÌÌÌ ÌÌÌÌ tsu(EN2) ENB th(EN2) tpd(M-DV) ten tpd(C-MR) B0 – B35 W1 (remains valid in mail1 register after read) FIFO1 Output Register NOTE A: Port-B parity generation off (PGB = L) Figure 14. Timing for Mail1 Register and MBF1 Flag 22 tdis POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ABT3612 64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCBS129G – JULY 1992 – REVISED APRIL 1998 CLKB th(EN1) tsu(EN1) CSB W/RB MBB ENB ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌ tsu(D) B0 – B35 ÌÌÌ ÌÌÌ ÌÌÌ ÌÌÌ ÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ th(D) W1 CLKA tpd(C-MF) tpd(C-MF) MBF2 CSA W/RA ÏÏÏÏÏ MBA ÎÎÎÎÎÎ ÏÏÏÏ ÎÎÎÎ ÌÌÌÌ ÌÌÌÌ tsu(EN2) ENA th(EN2) tpd(M-DV) ten tpd(C-MR) A0 – A35 tdis W1 (remains valid in mail2 register after read) FIFO2 Output Register NOTE A: Port-A parity generation off (PGA = L) Figure 15. Timing for Mail2 Register and MBF2 Flag POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 SN74ABT3612 64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCBS129G – JULY 1992 – REVISED APRIL 1998 ODD/ EVEN W/RA ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÎÎÎÎÎÎ ÎÎÎÎÎÎ MBA PGA tpd(O-PE) PEFA Valid tpd(O-PE) Valid tpd(E-PE) tpd(E-PE) Valid Valid NOTE A: CSA = L, ENA = H Figure 16. ODD/EVEN, W/RA, MBA, and PGA to PEFA Timing ODD/ EVEN W/RB ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ MBB PGB tpd(O-PE) PEFB Valid tpd(O-PE) tpd(E-PE) Valid Valid tpd(E-PE) NOTE A: CSB = L, ENB = H Figure 17. ODD/EVEN, W/RB, MBB, and PGB to PEFB Timing 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ Valid SN74ABT3612 64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCBS129G – JULY 1992 – REVISED APRIL 1998 ODD/ EVEN CSA Low W/RA MBA PGA A8, A17, A26, A35 ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÌÌÌÌÌÌ ÌÌÌÌÌÌ ten tpd(E-PB) tpd(M-DV) tpd(O-PB) Generated Parity tpd(E-PB) Generated Parity Mail2 Data Mail2 Data NOTE A: ENA = H Figure 18. Parity-Generation Timing When Reading From the Mail2 Register ODD/ EVEN CSB Low W/RB MBB PGB B8, B17, B26, B35 ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÌÌÌÌÌÌ ÌÌÌÌÌÌ ten tpd(E-PB) tpd(M-DV) tpd(O-PB) Generated Parity tpd(E-PB) Generated Parity Mail1 Data Mail1 Data NOTE A: ENB = H Figure 19. Parity-Generation Timing When Reading From the Mail1 Register POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25 SN74ABT3612 64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCBS129G – JULY 1992 – REVISED APRIL 1998 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 500 mA Package thermal impedance, θJA (see Note 2): PCB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28°C/W PQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions MIN 4.5 MAX VCC VIH Supply voltage VIL IOH Low-level input voltage 0.8 V High-level output current –4 mA IOL TA Low-level output current 8 mA 70 °C High-level input voltage 5.5 UNIT 2 Operating free-air temperature 0 V V electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VOH VOL VCC = 4.5 V, VCC = 4.5 V, IOH = – 4 mA IOL = 8 mA II IOZ VCC = 5.5 V, VCC = 5.5 V, VI = VCC or 0 VO = VCC or 0 ICC VCC = 5.5 V, IO = 0 mA, MIN TYP‡ 2.4 VI = VCC or GND 0.5 V ± 50 µA ± 50 µA Outputs high 60 mA Outputs low 130 mA 60 mA f = 1 MHz 4 pF Co f = 1 MHz ‡ All typical values are at VCC = 5 V, TA = 25°C. 8 pF 26 VI = 0, VO = 0, UNIT V Outputs disabled Ci MAX POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ABT3612 64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCBS129G – JULY 1992 – REVISED APRIL 1998 timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Figures 1 through 20) fclock tc Clock frequency, CLKA or CLKB tw(CLKH) tw(CLKL) tsu(D) tsu(EN1) ’ABT3612-15 ’ABT3612-20 ’ABT3612-30 MIN MIN MIN MAX 66.7 50 MAX 33.4 UNIT MHz 15 20 30 ns Pulse duration, CLKA and CLKB high 6 8 12 ns Pulse duration, CLKA and CLKB low 6 8 12 ns Setup time, A0 – A35 before CLKA↑ and B0 – B35 before CLKB↑ 4 5 6 ns Setup time, CSA, W/RA before CLKA↑; CSB, W/RB before CLKB↑ 6 6 7 ns Setup time, ENA before CLKA↑; ENB before CLKB↑ 4 5 6 ns Setup time, MBA before CLKA↑; MBB before CLKB↑ 4 5 6 ns Setup time, ODD/EVEN and PGA before CLKA↑; ODD/EVEN and PGB before CLKB↑† 4 5 6 ns tsu(RS) tsu(FS) Setup time, RST low before CLKA↑ or CLKB↑‡ 5 6 7 ns th(D) th(EN1) Hold time, A0 – A35 after CLKA↑ and B0 – B35 after CLKB↑ th(EN2) th(EN3) tsu(EN2) tsu(EN3) tsu(PG) Clock cycle time, CLKA or CLKB MAX 5 6 7 ns 2.5 2.5 2.5 ns 2 2 2 ns Hold time, ENA after CLKA↑; ENB after CLKB↑ 2.5 2.5 2.5 ns Hold time, MBA after CLKA↑; MBB after CLKB↑ 1 1 1 ns Hold time, ODD/EVEN and PGA after CLKA↑; ODD/EVEN and PGB after CLKB↑† 1 1 1 ns th(RS) th(FS) Hold time, RST low after CLKA↑ or CLKB↑‡ 5 6 7 ns Hold time, FS0 and FS1 after RST high 4 4 4 ns tsk1§ Skew time between CLKA↑ and CLKB↑ for EFA, EFB, FFA, and FFB 8 8 10 ns tsk2§ Skew time between CLKA↑ and CLKB↑ for AEA, AEB, AFA, and AFB 9 16 20 ns th(PG) Setup time, FS0 and FS1 before RST high Hold time, CSA, W/RA after CLKA↑; CSB, W/RB after CLKB↑ † Only applies for a clock edge that does a FIFO read ‡ Requirement to count the clock edge as one of at least four needed to reset a FIFO § Skew time is not a timing constraint for proper device operation and is included only to illustrate the timing relationship between CLKA cycle and CLKB cycle. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27 SN74ABT3612 64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCBS129G – JULY 1992 – REVISED APRIL 1998 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 30 pF (see Figures 1 through 20) PARAMETER fmax ta ’ABT3612-15 ’ABT3612-20 ’ABT3612-30 MIN MIN MIN MAX 66.7 MAX 50 MAX 33 UNIT MHz Access time, CLKA↑ to A0 – A35 and CLKB↑ to B0 – B35 2 10 2 12 2 15 ns tpd(C-FF) tpd(C-EF) Propagation delay time, CLKA↑ to FFA and CLKB↑ to FFB 2 10 2 12 2 15 ns Propagation delay time, CLKA↑ to EFA and CLKB↑ to EFB 2 10 2 12 2 15 ns tpd(C-AE) tpd(C-AF) Propagation delay time, CLKA↑ to AEA and CLKB↑ to AEB 2 10 2 12 2 15 ns Propagation delay time, CLKA↑ to AFA and CLKB↑ to AFB 2 10 2 12 2 15 ns tpd(C-MF) Propagation delay time, CLKA↑ to MBF1 low or MBF2 high and CLKB↑ to MBF2 low or MBF1 high 1 9 1 12 1 15 ns tpd(C-MR) Propagation delay time, CLKA↑ to B0 – B35† and CLKB↑ to A0 – A35‡ 3 11 3 13 3 15 ns tpd(M-DV) Propagation delay time, MBA to A0 – A35 valid and MBB to B0 – B35 valid 1 11 1 11.5 1 12 ns tpd(D-PE) Propagation delay time, A0-A35 valid to PEFA valid; B0-B35 valid to PEFB valid 3 10 3 11 3 13 ns tpd(O-PE) Propagation delay time, ODD/EVEN to PEFA and PEFB 3 11 3 12 3 14 ns tpd(O-PB)§ Propagation delay time, ODD/EVEN to parity bits (A8, A17, A26, A35) and (B8, B17, B26, B35) 2 11 2 12 2 14 ns tpd(E-PE) Propagation delay time, W/RA, CSA, ENA, MBA, or PGA to PEFA; W/RB, CSB, ENB, MBB, or PGB to PEFB 1 11 1 12 1 14 ns tpd(E-PB)§ Propagation delay time, W/RA, CSA, ENA, MBA, or PGA to parity bits (A8, A17, A26, A35); W/RB, CSB, ENB, MBB, or PGB to parity bits (B8, B17, B26, B35) 3 12 3 13 3 14 ns tpd(R-F) Propagation delay time, RST to (AEA, AEB) low and (AFA, AFB, MBF1, MBF2) high. 1 15 1 20 1 30 ns ten Enable time, CSA and W/RA low to A0 – A35 active and CSB low and W/RB high to B0 – B35 active 2 10 2 12 2 14 ns tdis Disable time, CSA or W/RA high to A0 – A35 at high impedance and CSB high or W/RB low to B0 – B35 at high impedance 1 8 1 9 1 11 ns † Writing data to the mail1 register when the B0 – B35 outputs are active and MBB is high ‡ Writing data to the mail2 register when the A0 – A35 outputs are active and MBA is high § Only applies when reading data from a mail register 28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ABT3612 64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCBS129G – JULY 1992 – REVISED APRIL 1998 PARAMETER MEASUREMENT INFORMATION 5V 1.1 kΩ From Output Under Test 680 Ω 30 pF (see Note A) LOAD CIRCUIT 3V Timing Input 3V High-Level Input 1.5 V 1.5 V 1.5 V GND GND th tsu tw 3V Data, Enable Input 1.5 V 1.5 V 3V Low-Level Input GND 1.5 V GND VOLTAGE WAVEFORMS PULSE DURATIONS VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Enable 1.5 V 3V 1.5 V 1.5 V GND tPLZ tPZL Low-Level Output ≈3V 1.5 V VOL 3V ≈0V tpd tpd VOH 1.5 V 1.5 V GND tPZH High-Level Output 1.5 V Input VOH In-Phase Output 1.5 V 1.5 V VOL tPHZ VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. Includes probe and jig capacitance B. tPZ: and tPZH are the same as ten. C. tPLZ and tPHZ are the same as tdis. Figure 20. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 29 SN74ABT3612 64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCBS129G – JULY 1992 – REVISED APRIL 1998 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs CLOCK FREQUENCY 400 fdata = 1/2 fclock TA = 25°C CL = 0 pF I CC(f) – Supply Current – mA 350 300 VCC = 5.5 V VCC = 5 V 250 200 VCC = 4.5 V 150 100 50 0 0 10 20 30 40 50 60 fclock – Clock Frequency – MHz Figure 21 30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 70 80 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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