TI SN74HCT623

SN54HCT623, SN74HCT623
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCLS016B – MARCH 1984 – REVISED MAY 1997
D
Inputs Are TTL-Voltage Compatible
Lock Bus-Latch Capability
True Logic
High-Current 3-State Outputs Can Drive up
to 15 LSTTL Loads
Package Options Include Plastic
Small-Outline (DW) and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J)
300-mil DIPs
SN54HCT623 . . . J OR W PACKAGE
SN74HCT623 . . . DW OR N PACKAGE
(TOP VIEW)
OEAB
A1
A2
A3
A4
A5
A6
A7
A8
GND
description
These octal bus transceivers are designed for
asynchronous two-way communication between
data buses. The control-function implementation
allows for maximum flexibility in timing.
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
OEBA
B1
B2
B3
B4
B5
B6
B7
B8
A2
A1
OEAB
VCC
SN54HCT623 . . . FK PACKAGE
(TOP VIEW)
The ’HCT623 allow data transmission from the
A bus to the B bus or from the B bus to the A bus,
depending upon the logic levels at the
output-enable (OEAB and OEBA) inputs.
A3
A4
A5
A6
A7
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
B1
B2
B3
B4
B5
A8
GND
B8
B7
B6
The output-enable inputs disable the device so
that the buses are effectively isolated. The
dual-enable configuration gives the transceivers
the capability to store data by simultaneously
enabling OEAB and OEBA. Each output
reinforces its input in this transceiver
configuration. When both OEAB and OEBA are
enabled and all other data sources to the two sets
of bus lines are in the high-impedance state, both
sets of bus lines (16 total) remain at their last
states. The 8-bit codes appearing on the two sets
of buses are identical.
OEBA
D
D
D
D
The SN54HCT623 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74HCT623 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OEBA
OEAB
OPERATION
L
L
B data to A bus
H
H
A data to B bus
H
L
Isolation
L
H
B data to A bus,
A data to B bus
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1997, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
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1
SN54HCT623, SN74HCT623
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCLS016B – MARCH 1984 – REVISED MAY 1997
logic symbol†
19
OEBA
1
OEAB
2
A1
EN1
EN2
2
3
A2
A3
A4
A5
A6
A7
A8
18
1
17
4
16
5
15
6
14
7
13
8
12
9
11
B1
B2
B3
B4
B5
B6
B7
B8
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
OEBA
OEAB
A1
19
1
2
18
B1
To Seven Other Transceivers
absolute maximum ratings over operating free-air temperature range‡
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA
Package thermal impedance, θJA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
2
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SN54HCT623, SN74HCT623
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCLS016B – MARCH 1984 – REVISED MAY 1997
recommended operating conditions
SN54HCT623
SN74HCT623
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
UNIT
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
0
0.8
0
0.8
V
Input voltage
0
0
Output voltage
0
0
VCC
VCC
V
VO
tt
VCC
VCC
0
500
0
500
ns
TA
Operating free-air temperature
–55
125
–40
85
°C
High-level input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2
Input transition (rise and fall) time
2
V
V
V
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
VOH
VI = VIH or VIL
IOH = –20 µA
IOH = –6 mA
45V
4.5
VOL
VI = VIH or VIL
IOL = 20 µA
IOL = 6 mA
45V
4.5
OEAB or
OEBA
II
IOZ
ICC
A or B
SN54HCT623
MIN
MAX
SN74HCT623
MIN
4.4
4.499
4.4
4.4
3.98
4.3
3.7
3.84
MAX
UNIT
V
0.001
0.1
0.1
0.1
0.17
0.26
0.4
0.33
V
5.5 V
±0.1
±100
±1000
±1000
nA
VO = VCC or GND
VI = VCC or 0,
5.5 V
±0.01
±0.5
±10
±5
µA
8
160
80
µA
1.4
2.4
3
2.9
mA
3
10
10
10
pF
5.5 V
5.5 V
OEAB or
OEBA
Ci
TA = 25°C
TYP
MAX
VI = VCC or 0
IO = 0
One input at 0.5 V or 2.4 V,
Other inputs at 0 or VCC
∆ICC†
MIN
4.5 V
to 5.5 V
† This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
d
A or B
B or A
ten
OEBA
A
tdis
di
OEBA
A
ten
OEAB
B
tdis
di
OEAB
B
tt
A or B
VCC
MIN
TA = 25°C
TYP
MAX
SN54HCT623
MIN
MAX
SN74HCT623
MIN
MAX
4.5 V
15
22
33
28
5.5 V
13
20
30
25
4.5 V
30
42
63
53
5.5 V
23
38
57
48
4.5 V
18
30
45
38
5.5 V
16
28
42
35
4.5 V
30
42
63
53
5.5 V
23
38
57
48
4.5 V
18
30
45
38
5.5 V
16
28
42
35
4.5 V
9
12
18
15
5.5 V
8
11
16
14
UNIT
ns
ns
ns
ns
ns
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN54HCT623, SN74HCT623
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCLS016B – MARCH 1984 – REVISED MAY 1997
switching characteristics over recommended operating free-air temperature range, CL = 150 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
d
A or B
B or A
OEBA
A
ten
OEAB
B
tt
A or B
VCC
MIN
TA = 25°C
TYP
MAX
SN54HCT623
MIN
MAX
SN74HCT623
MIN
MAX
4.5 V
18
38
58
47
5.5 V
11
34
52
42
4.5 V
36
59
89
74
5.5 V
30
53
80
67
4.5 V
36
59
89
74
5.5 V
30
53
80
67
4.5 V
17
42
63
53
5.5 V
14
38
57
48
UNIT
ns
ns
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance per transceiver
No load
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
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TYP
40
UNIT
pF
SN54HCT623, SN74HCT623
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCLS016B – MARCH 1984 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
VCC
From Output
Under Test
CL
(see Note A)
PARAMETER
S1
Test
Point
tPZH
ten
RL
S2
1 kΩ
tPZL
tPHZ
tdis
S2
50 pF
or
150 pF
Open
Closed
Closed
Open
1 kΩ
––
LOAD CIRCUIT
2.7 V
S1
50 pF
tPLZ
tpd or tt
Input 1.3 V
0.3 V
CL
RL
2.7 V
50 pF
or
150 pF
Open
Closed
Closed
Open
Open
Open
3V
1.3 V
0.3 V 0 V
tr
tf
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
3V
Input
1.3 V
1.3 V
0V
tPLH
In-Phase
Output
1.3 V
10%
tPHL
90%
90%
tr
tPHL
Out-ofPhase
Output
90%
VOH
1.3 V
10% V
OL
tf
tPLH
1.3 V
10%
1.3 V
10%
tf
Output
Control
(Low-Level
Enabling)
3V
1.3 V
1.3 V
0V
tPZL
Output
Waveform 1
(See Note B)
tPLZ
≈ VCC
1.3 V
10%
VOL
tPZH
90%
VOH
VOL
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES
Output
Waveform 2
(See Note B)
1.3 V
90%
VOH
≈0V
tPHZ
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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Copyright  1998, Texas Instruments Incorporated