LZ93BE0
LZ93BE0
Timing Pulse Generator LSI for CCD
DESCRIPTION
PIN CONNECTIONS
The LZ93BE0 is a CMOS timing generator LSI
which provides horizontal transfer pulse, reset
pulse, and sample-hold pulse used for separate
camera, in combination with single-chip driver
LSI (LZ95G55, LZ95G41 ) and timing LSI (LZ93F33,
LZ93F50, LZ93N61 or LZ95D37/M).
20-PIN MFP
TOP VIEW
/“
FH I
1
= o
FHIB 2
GND 3
FEATURES
● Switchable between 270 ~0 pixels CCD and
320000 pixels CCD
● Switchable between NTSC (EIA) and PAL
(CCIR) systems
● Single +5 V power supply
● Switchable between normal and mirror-image
● Suitable for separate camera
a Vcc
~ FCDS
18 FS
co
FH2
4
17
FH2B
5
16 c l
HDI ~
15 s o
TVMD
7
1 4 SI
FR
8
g CH
CKI
9
12 SLCT
GND 10
11
MIR
● Package : 20-pin MFP(MFP020-P)
☛ Designed for A-type and B-type CCD area sensors :
A-type CCD area sensor : LZ2314J, LZ2324J, LZ231 32, LZ23232
B-type CCD area sensor : LZ2414J, LZ2424J, LZ2313H5,
LZ2323H5, LZ2413, LZ2423
BLOCK DIAGRAM
“in tie ab%nce of con f(nnatlon by device $pectf{cation sheets, SHARP takes no respnslb(l[v for any defecs hat xcur in equipment using any of SHARPs devices, shown In cahlcgs,
256 I data bwks, etc CQntacl SHARP In order to obkln he latest version of tie device wlf!cation*wts betcn’e using any SHARPs device’
LZ93BE0
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
lnDut
voltaae
Gt
voltage
RATING
Vcc
Supply voltage
VI
I
Vo
I
UNIT
– 0.3 to 7.0
v
–0,3 to Vcc + 0.3
v
-0.3
to
VCC+O.3 ]
v
Operation temperature
Topr
– 2 0 t o +70
‘c
Storaae temperature
Tstq
–55 to +150
“c
DC CHARACTERISTICS
PRAMETER
(VCC=+5 Vf5% T a = – 2 0
SYMBOL
Input Low voltage
vlL
Input High voltage
vlH
vT +
Input Low threshold voltage
vT
Input Low current
CONDITIONS
MIN.
TYP.
t o +7UC
MAX.
UNIT
1.5
v
NOTE
1
Input High threshold voltage
Hysteresis voltage
I
3.5
Schmitt Buffer
vT+ –VTVl=o v
I
Vl=o v
I
3.8
1.0
2.4
8.0
Input High current
I
Output High voltage
vOH 1
IoH=– Z
Output Low voltage
vOL1
IOL = 4 mA
Output High voltage
vOH2
IoH=–4
OutDut LOW voltaae
v0L2
I OL = 8 mA
output High voltage
vOH3
IoH=–6 mA
Output Low voltage
vOL3
10.=12 mA
IIH I
2.2
0.4
I IIL1 I
11L2
v
VI= Vcc
mA
mA
v
v
2
v
1.0
,uA
3
60
,uA
4
1,0
PA
5
4.0
v
0.4
v
0.4
v
0.4
v
4.0
6
v
4.0
7
v
8
NOTES :
1. Applled to inputs (IC, ICU).
2. Applied to Input (ICS).
3. Applied to inputs (IC, ICS).
4. Applied to Input (ICU).
5. Applied to inputs (IC, ICU, ICS)
6. Applied to output (0)
7. Applied to output (08M)
8 Applied to output (012M)
257
LZ93BE0
:!.
SYMBOL
1/0
POIARITY
1
FH I
012M
N
PfN NAME
FLfNCTION
Horizontal transfer
pulse 1
A horizontal transfer pulse for CCD area sensor.
tinnect to 4 HI of CCD area sensor.
2
FHIB
08M
m
Horizontal transfer
pulse 1 B
A horizontal transfer pulse for CCD area sensor,
Connect to 4 HI E of CCD area sensor. If the CCD
area sensor which corresponds to Mirror mode is
driven at Normal mode (MIR = L), its drive-pulse is
the same phase as the pulse of FHI (pin 1), and it
is the same phase as the pulse of FH2 (pin 4) at
Mirror mode (MIR = H).
3
GND
–
–
Ground
A grounding pin.
4
FH2
012M
m
Horizontal transfer
pulse 2
A horizontal transfer pulse for CCD area sensor.
~nfleCt to ~ HZ of CCD area sensor,
5
FHZB
08M
m
Horizontal transfer
pulse 2B
A horizontal transfer pulse for CCD area sensor.
bnnect to 4 H2E of CCD area sensor. If the CCD
area sensor which corresponds to Mirror mode is
driven at Normal mode (MIR = L), its drive-pulse is
the same phase as the pulse of FH2 (pin 4),and it
is the same phase as the pulse of FH I (pin 1 ) at
Mirror mode (MIR = H).
6
HDI
Ics
–
Horizontal reference
pulse
Put in a horizontal reference pulse from SSG-LSI.
~nnect to HD terminal of SSG-LSI.
7
TVMD
Icu
–
TV mode select
An input-pin to select TV standards,
L level : NTSC mode
H level or o~n : PAL mode
8
FR
08M
n
Reset pulse
A reset pulse for CCD area sensor, bnnect to ~ R
of CCD area sensor through the DC offset circuit.
9
CKI
Ics
nn
Clock input
An input pin for reference clock.
The frequencies are as follows :
At EIA mode : 19.06993 MHz (1212 fH)
At CCIR mode : 19.31250 MHz (1 236 fH)
10
GND
–
–
Ground
A grounding pin.
11
MIR
Icu
—
Mirror mode select
An input pin to select Mirror mode or Normal mode.
L level : Normal Drive mode
H level or open : Mirror Drive mode
CCD type select
An input pin to select the type of CCD area sensw,
L level (A type)
LZ23t4J, LZ2314Z, LZ23t42, LZ2313A9, LZ23132
LZ2324J, LZ2324Z, LZ23242, LZ2323A9, LZ23232
H level or open (B type)
LZ2314BK, LZ2414J, LZ2313B5, LZ2313H5, LZ2413
LZ2324BK, U2424J, LZ2323B5, LZ2323H5, LZ2423
12
SLCT
Icu
—
U93BE0
WN
“~
SYMBOL
1/0
POtARiTY
PIN NAME
FUNCTION
13
CH
Icu
—
Phase control terminal
for FCDS and FS
An input pin to select the phase of FCDS (pin 19)
pulse and FS (pin 18) pulse.
L level : adjustable
H level or open : fixed
14
SI
Ic
–
Phase-adjust input
for FS
An input pin to control the phase of FS (pin 18).
SO (pin 15) pulse put in this terminal after make it
delay with resistor and capacitor.
15
so
o
nn
Phase-adjust output
for FS
An output pin to control the phase of FS (pin 18).
The output pulse put in S1 (pin 14) after make it
delay with resistor and capacitor.
18
cl
Ic
—
Phase-adjust input
for FCDS
An input pin to control the phase of FCDS (pin 19).
CD (pin 17) pulse put in this terminal after make it
delay with resistor and capacitor.
17
co
o
nrl
Phase-adjust output
for FCDS
An output pin to control the phase of FCDS (pin 19).
The output pulse put in Cl (pin 16) after make it
delay with resistor and capacitor.
n
Sample-hold pulse
output
A pulse to sample-hold the signal from CCD area
sensor. The phase of FS is fixed if CH (pin 13)
equals H level and it can be adjustable if CH (pin
13) equals L level.
CDS pulse output
A pulse to clamp the feed-through level form CCD
area sensor. The phase of FCDS is fixed if CH (pin
13) equals H level and it can be adjustable if CH
(pin 13) equals L level.
Power supply
Supply +5 V power.
18
FS
o
19
FCDS
o
n
20
Vcc
–
—
Ic
Icu
Ics
: Input pin (CMOS level input)
: Input pin (CMOS level input with pull-up resistor)
: Input pin (CMOS scnmiti input )
O, 08M, 012M : Output pin
NOTE :
At the input pin, the rising edge of HDI (pin 6) is f 20 ns shorter than that of CKI (pin 9).
259
LZ93BE0
TIMING DIAGRAM
NTSC(EIA) < A-TYPE, NORMAL MODE >
1212,0
49
120
166
1 clock = 52.4 ns
114
HDI
CBLK
CKI
FH I
FHz
FHIB
FH2B
FR
FCDS
FS
114
210
HDI
–—
CBLK
CKI
FH I
FH2
FHIB
FHZB
XX
FR
~wnnnnn
X
X1212345678
101214161 ~202224 26
nnnnnnnn~nnnnnnnn
~mdw~
FCDS
FS
1~
Ulnllnnnnnl lnnnnmnnnnlllln
~~~m
NTSC(EIA) < A-TYPE, MIRROR MODE >
1212,0
1
8
clock = 52.4 ns
114
HDI
CBLK
CKI
FH I
FH2
FHIB
FH2B
OBIXXX
FR
FCDS
FS
CBLK
CKI
FH I
FHz
FHIe
FH2B
FR
FCDS
FS
1111 JIJlnnn
Mnn nnnnnn~flflflnnnflfl~flfl
m~nnnnL!lnnnnllnnn
nnnnlln
flfl
n rd~
nluLJlnnflnnn ~d~w
lnnnnnnn~ nnnrlnnnnnnnn ~~JL
114 116 120
HDI
XXX
Pw~nnnn
T
210
LZ93BE0
1
NTSC(EIA) < B-TYPE, NORMAL MODE >
HDI
CBLK
I
174
—
47
1212,0
1
clock= 52.4 ns
CKI
FH 1
FH2
FHIB
FH2B
FR
FCDS
FS
210
163
120
14
I
HDI
!
CBLK
CKI
FH I
FH2
FHiB
FHZB
FR
FCDS
FS
NTSC(EIA) < B-TYPE, MIRROR MODE >
1 clock =52.4 ns
111 114
1212,0 3
HDI
J
CBLK
CKI
FH T
FH2
FHIB
FHZB
x
OBIXX X X
FR
nnnnruulnnnnnnn~n
nnn~flflnflnflflfl
flu
FCDS
nnnnnluln
FS
114
nnnluuuulnllnnnn
nnluuuuLnnnfl~flflflflfl
flnflfl~
210
120
HDI
CBLK
CKI
,
1
FH I
FH2
FHIB
FH2B
XX X X XOB28
FR
FCDS
0B20
OB1O
nnnll~nn
OBI 512 510 W 5C6 W W2 500 498 496 494 492 4W W
nnlLrLn nnnrLnflnnn~
Jflflflflflflnflflfl~
flflfl~
‘nnnm
FS
261
U93BE0
PAL(CCIR) < A-TYPE, NORMAL MODE >
48
1236,0
HDI
1 clock = 51.8 ns
114
—
CBLK
CKI
FH I
FH.
FHi B
FH2B
0B4
FR
OB1O
nnnflnnn
FCDS
FS
OB20
0B28
nnnnnn~nnnmnnnnnm
nnllnnn
mflnnnn nnflnflnnnn~
114
HDI
nnnnnnn
nnwflflnnnnJLluLll
nnnnnnflnnnnnnnnn~
nnnnnn
Mnnnnnnn
nnnnn Mnnnnnn
nnflnnnnnnnn
nnnnfln~
192
120
234
I
1
CBLK
CKI
mm
UlnMMM~llln
J u“ m T’-1u J-LnnrL UuuLrLrI_-
FH I
FH2
Ju n UL--11-nruLrL UuuLnr 1.-
FHIB
FH2B
X X X X 1 2 1 2 3 4 5 8 7 8
FR
nnnnnnn
FCDS
FS
nnflm
MnnnnnJ nnnnLILIL
nnnnnJnnnnnMnnnn
nmnnnnn
nllnnllmnnnn~nnnnn
lnnnnll
nMnnflnnnnunnn
nmnnnnnnnnnnnn
1 4
nn~llnllnnnnnnn
nllflfl nnnnllll
n~nllnnnnll
n~
nmnnnnllnnm r
1
PAL(CCIR) < A-TYPE, MIRROR MODE >
12%,0
10 12
m~
clock =51.8 ns
114
3
HDI
CBLK
CKI
m Ju
FH I
FH2
FHIB
m lr
JL
FH2B
FR
OBIXXXXXX
nnllnnluLll_n
FCDS
FS
nnnnn~n
mnnnlLll
114
HDI
i 20
nnLILrLJuLILIL
Mnnnnflfln~
nnnnnlLn_lLn nllflllnllnnnnmfl
nnnnnnllnn~
234
L
m Uul~~
u ULruL-uuLv ~ mnnnn~
nn~
XX X XOB28
OB20
OB1O
OB1 512 510 5W 506 504 502 ~
FH2B
262
nnnnnnnnnnnnnnnn
nflnnn
140
F HIB
FS
nnnnnnn
nnnnnnn
I
FH I
FHz
FR
nnnfl Mnnllnn
nnnnnMnnnnnllnnn
CBLK
CKI
FCDS
nnnnnn~
Mnnnnnn ruLnnnhnnnnn~ nnnnnnn nnnnnnnnnn~n nnnnnnnnnnnn
nnnnnnn
nnnnnnnnnnnnnnnn
JMnnnnn
nnnn Mnnnnnnnnn
nnflnnn nnnnnnnnnnnnnnnnn
nnnnn~ ~L
nnnJnnn nn~nnnnnnnnnufl
flflflflfl~
LZ93BE0
PAL(CCIR) < B-TYPE, NORMAL MODE >
7236,0
1 clock =51,8 ns
47
114
HDI
CBLK
CKI
FH I
FH.
FHIe
FH2B
OB4
FR
OB1O
FCDS
FS
OB~
OB28
m~Lrlnn llnnnnnnllllfln
Ln nnnnnnn nMnnflnnnnnnnnn~
0
lnnflnn nnmnnnnnnllnn~ nnnn~
114 120
187
234
HDI
L
CBLK
CKI
u Juuu m Jm MmJ- nv.
FH t
FH2
uWm1mmm J nu-
FHIB
FH2B
nn~
XXXXXX121234567
8 10 12 14
FR
nnnnnMn nnnnnn Lnnnnflnn nnnnn~
FCDS
nnnllnn~ nnllnllnrL
m~nn nnnnnnnnn~nnnlln~ nnnnr
FS
PAL(CCIR) < B-TYPE, MIRROR MODE >
i236,0 3
1
clock=51.8
ns
i14
HDI
CBLK
CKI
M UIM~~
FH I
FHz
FHIB
mm 7n
rLul 7n
FH2B
OBIX X X X
FR
FCDS
nnnllnlln~
FS
114
120
135
234
HDI
L
CBLK
CKI
FH I
FHz
Hum~
XXXXXXOB28
FR
FCDS
FS
OBm
OB1O
OBI 512 510 W ~ 504 W2 500 :
mnnnnnnn~ nnnnnnn nnnnflnnnnnnnnnnnn nnnn;
nnnnnnn
nnnnnnnnnnnnnnnnn nnnnnnn nnnnnnnnnMnnnnnn ruuuuulnllllllllll
lnnnnnn nnnnJnnnnnnnnnn nlLILnnnllnnnllnn~
263
LZ93F33
LZ93F33
Timing Pulse Generator LSI for CCD
DESCRIPTION
PIN CONNECTIONS
The LZ93F33 is a CMOS timing generator LSI
which provides timing pulses used to drive a
CCD area sensor, in combination with the SSG
LSI (LZ93N19 or LZ93B53).
48-PIN QFP
cx$:i~::$ic~
>S>>oa>z+>z 2
FEATURES
●
●
●
●
●
37
24 MCDI
V4X $
23 MFS2
v3k
● Switchable between 270000 pixels CCD and
●
TOP VIEW
OFDX 39
320000 pixels CCD
Switchable between NTSC (EIA) and PAL
(CCIR) systems
Built-in EE (Electronic Exposure) control
Flicker-less function
Switchable between normal and mirror image
Single +5 V power supply
Package : 48-pin QFP(QFP048-P-101 O)
22 MFSI
FR 40
21 FS
FHZB 41
20 FCDS
FH2 42
19 INSL
GND 43
18 TO
FH I z
17 SE
FH IB 45
16 SINV
15 SESL
CKI 46
14 SP2
CKO 47
0
TEST 48
13 SP1
llf121131141] 511611711811911101111 ]l12
aaogoood>om o
r>nzzzz~~~z
~tiu<uwwm+
UJwu.lk
TO
GND
GND
GND
Vcc
TEST
TSTO
Vlx
V2X
VDI
V3X
V4X
TVMD
MIR
ACL
TOSL
DO
CKI
CKO
4
HDI
EEST
i
r
EEUD
EENR
SHU~ER
UP/DOWN
CONTROL
EEMD
FLMD
SHUTTER
SPEED
CONTROL
1 C“NTR”’ B
VHIX
VH3X
OBCP
SINV
SESL
FHI
FHIE
FH2
FHZB
FR
FS
FCDS
SE
SP2
SPI
MFSI
MFS2
MCDI
MCD2
MFR I
MFR2
INS’
OFDX
“In be abwnce of confinnahon by dev[ce sw[flcahon aheek, SHARP takes no rewnmblllv fci any defacta tiat cccur in equipment using any of WARPs devices, ah~ In ca~lws,
264 I data
Wks, etc. Contact SHARP uder to obm(n tie Iateat wmlon of the dev!ce Wlfcahon shwts kf~ using any SHARPs device”
Im