Silan Semiconductors SC9256 PLL FOR DTS DESCRIPTION The SC9256 is phase-locked loop (PLL) LSIs for digital tuning systems (DTS) with built in 2 modulus prescalers. All functions ate controlled through 3 serial bus lines. These LSIs DIP-16-300-2.54 are used to configure high-performance digital tuning system. FEATURES * Optimal for configuring digital tuning systems in high-fi tuners and car stereos. * built-in prescalers. Operate at input frequency ranging from SOP-16-300-1.27 30~150 MHz during FMIN input (with 2 modulus prescaler) and at 0.5~40MHz during AMIN input (with 2 modulus prescaler or direct dividing). * 16 bit programmable counter, dual parallel output phase * Standby mode function (turns off FM, AM comparator, crystal oscillator and reference counter. and * 3.6MHz, 4.5MHz, 7.2MHz or 10.8MHz crystal oscillators can be IF amps) to save current consumption. used. * All functions controlled through 3 serial * 15 possible reference frequencies. ( When using 4.5MHz crystal) bus lines. * Built-in 20 bit general-purpose counter for such uses as * CMOS structure with operating power supply range of VDD=5.0±0.5V. measuring intermediate frequencies (IFIN1 and IFIN2) * High-precision (±0.55~±7.15µs) PLL phase error detection. * Numerous general-purpose I/O pins for such uses as peripheral ORDERING INFORMATION Device Package * 3 N-channel open-drain output ports (OFF withstanding SC9256 DIP-16-300-2.54 voltage:12V) for such uses as control signal output. SC9256S SOP-16-300-1.27 circuit control. PIN CONFIGURATION XT 1 16 DO2/OT-4 XT 2 15 DO1 PERIOD 3 14 I/O-5/IFIN1 CLOCK 4 DATA 5 12 GND OT-1 6 11 FMIN OT-2 7 10 AMIN OT-3 8 9 SC9256 13 I/O-6/IFIN2 VDD HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 1 2002.01.30. Silan Semiconductors SC9256 BLOCK DIAGRAM VDD 1/2 2 MODULUS PERSCALER 4bit SWALLOW COUNTER POWER ON RESET FMH HF AMIN FM XT OSC CIRCUIT XT 12bit PROGRAMMABLE COUNTER LF MODE 4 12 REFERENCE COUNTER MAX 15 4 1ms OSC RESET PHASE COMPARATOR FML AMP FMIN GND PSC TRI-STATE BUFFER DO1 TRI-STATE BUFFER DO2/OT-4 OT4 UNLOCK 24bit REGISTER I/O PORT 5 DATA 24bit SHIFT REGISTER CLOCK 8 TEST 5 ADDRESS DECODER 24 22 PERIOD 10 24bit REGISTER 4 OUTPUT PORT 4 I/O-6/IFIN2 AMP 20bit BINARY COUNTER UNIVERSAL COUNTER CONTROL AMP GATE I/O-5/IFIN1 1ms XT OT-1 OT-2 OT-3 ABSOLUTE MAXIMUM RATINGS (Ta=25°C) Characteristic Symbol Value Unit V Supply Voltage VCC -0.3~6.0 Input Voltage VIN -0.3~VDD+0.3 V VOFF 13 V N-ch Open-Drain Off withstanding Voltage Power Dissipation PD 300(200) mW Operating Temperature TOPR -40~85 °C Storage Temperature TSTG -65~150 °C ( ): Flat package HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 2 2002.01.30. Silan Semiconductors SC9256 ELECTRICAL CHARACTERISTICS (unless otherwise specified, Ta= -40~85°C, VDD=4.5~5.58V.) Characteristic Symbol Operating Power Supply Voltage VDD1 Operating Power Supply Current IDD1 Test Condition/Pin PLL operation (normal operating) VDD=5.0V, XT=10.8MHz, FMIN=150MHz Min Typ. Max Unit 4.5 5.0 5.5 V -- 7 15 mA 4.0 5.0 5.5 V -- 0.8 1.5 mA -- 120 240 µA 3.6 ~ 10.8 MHz 30 ~ 130 MHz Stand-by mode Crystal Oscillation Frequency Supply Voltage PLL OFF VDD2 (Operating crystal oscillation) Operating Power Supply Current IDD2 Operating Power Supply Current IDD3 VDD=5.0V, XT =10.8MHz PLL OFF VDD=5.0V, XT stop, PLL OFF Operating frequency range Connect crystal resonator to XT- XT terminal Crystal Oscillation Frequency fXT FMIN (FMH, FML) fFM FMIN (FML) fFML FML mode, VIN=0.3Vp-p 30 ~ 150 MHz AMIN (HF) fHF HF mode, VIN=0.2Vp-p 1 ~ 40 MHz AMIN (LF) fLF LF mode, VIN=0.2Vp-p 0.5 ~ 20 MHz IFIN1, IFIN2 fIF VIN=0.2Vp-p 0.1 ~ 15 MHz -- ~ 100 kHz 0.2 ~ VDD-0.5 Vp-p SCIN fSC FMH, FML mode, VIN=0.2Vp-p VIH=0.7VDD, VIL=0.3VDD, square wave input. Operating input amplitude range FMIN (FMH, FML) VFM FMH, FML mode, fIN=30~130MHz FMIN (FML) VFML FML mode, fIN=30~150MHz 0.3 ~ VDD-0.5 Vp-p AMIN (HF) VHF HF mode, fIN=1~40MHz 0.2 ~ VDD-0.5 Vp-p AMIN (LF) VLF LF mode, fIN=0.5~20MHz 0.2 ~ VDD-0.5 Vp-p IFIN1, IFIN2 VIF FIN=0.1~15MHz 0.2 ~ VDD-0.5 Vp-p IOL1 VOL=1.0V 5.0 10.0 -- mA IOEF VOFF=12V -- --- 2.0 µA OT1~OT4 N-ch open drain Output Current OFF-leak Current “L” level (To be continued) HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 3 2002.01.30. Silan Semiconductors SC9256 (Continued) Characteristic Symbol Test Condition/Pin Min Typ. Max Unit I/O-5~I/O-9, SCIN Input Voltage Input Current Output Current “H” level VIH1 0.7VDD ~ VDD “L” level VIL1 0 ~ 0.3VDD “H” level IIH VIH=5V -- -- 2.0 “L” level IIL VIL=0V -- -- -2.0 “H” level IOH4 VOH=4.0V (expect SCIN) -2.0 -4.0 -- “L” level IOL4 VOL=1.0V (expect SCIN) 2.0 4.0 -- V µA mA PERIOD, CLOCK, DATA Input Voltage Input Current Output Current “H” level VIH2 0.8VDD ~ VDD “L” level VIL2 0 ~ 0.2VDD “H” level IIH VIH=5V -- -- 2.0 “L” level IIL VIL=0V -- -- -2.0 “H” level IOH5 VOH=4.0V (DATA) -1.0 -3.0 -- “L” level IOL5 VOL=1.0V (DATA) 1.0 3.0 -- “H” level IOH3 VOH=4.0V -2.0 -4.0 -- “L” level IOL3 VOL=1.0V 2.0 4.0 -- -- -- ±1.0 V µA mA DO1, DO2 Input Current Tri-State Lead Current ITL VTLH=5V, VTLL=0V mA µA XT Output Current “H” level IOH2 VOH=4.0V -0.1 -0.3 -- “L” level IOL2 VOL=1.0V 0.1 0.3 -- 350 700 1400 500 1000 4000 mA Input feedback resistance Input Feedback “H” level Resistance “L” level Rf1 Rf2 FMIN, AMIN, IFIN (Ta=25°C) XT- XT (Ta=25°C) kΩ PIN DESCRIPTION Pin No. Symbol 1 XT 2 XT Pin name Description Circuit diagram Connects 3.6MHz, 4.5MHz, 7.2MHz Crystal oscillator or 10.8MHz crystal oscillator to pins supply reference frequency and internal clock VDD XT XT (To be continued) HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 4 2002.01.30. Silan Semiconductors SC9256 (Continued) Pin No. Symbol 3 PERIOD Period signal input Serial I/O ports. These pins transfer 4 CLOCK Clock signal input 5 6 DATA Pin name OT-2 8 OT-3 10 AMIN FMIN VDD data to and from the controller to set Schmitt input control the general-purpose counter input/output Schmitt input CLOCK,PERIOD DATA and general-purpose I/O ports. N channel open drain port pins, for General-purpose such uses as control signal output. output ports These pins are set to the OFF state N-channel open drain when power is turned on. These pins input FM and AM band Programmable 11 Circuit diagram divisions and dividing modes, and to Serial data OT-1 7 Description counter input VDD local oscillator signals by capacitor coupling. FMIN and AMIN operate at low amplitude. General-purpose I/O port input /output pins. Can be switched for use as input pins to measure general 13 I/O6/IFIN2 General-purpose I/O ports/Generalpurpose counter frequency measurement input 14 purpose counter frequencies. The VDD frequency measurement function has such uses as measuring inter- mediate frequencies (IF). These pins feature built-in amps. Data are input by capacitor coupling. FMIN and AMIN operate at low I/O-5 amplitude. /IFIN1 (note) Pins are set for input when power is turned on. 15 DO1 Phase comparator output 16 DO2/OT-4 purpose ports) 12 GND 9 VDD (Generaloutput VDD These pins are for phase comparator tri-state output. DO1 and DO2 are output in parallel. Power supply pins Applies 5.0V±10% HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 5 2002.01.30. Silan Semiconductors SC9256 FUNCTION DESCRIPTION Serial I/O ports As the block diagram shows, the functions are controlled by setting data in the 48 bits contained in each of the 2 sets of 24 bit registers. Each bit of data in these register is transferred through the serial ports between the controller and the DATA, CLOCK and PERIOD pins. Each serial transfer consists of a total of 32 bits, with 8 address bits and 24 data bits. Since all functions are controlled in units of registers, the explanation in this manual focuses on the 8 bit address and functions of each register. These registers consist of 24 bits and are selected by an 8 bit address. A list of the address assignment for each register is given below under register assignments. Register Input register 1 Address D0H Contents of 24 bits No. of bit PLL divisor setting 16 Reference frequency setting 4 PLL input and mode setting 2 Crystal oscillator selection 2 total 24 General=purpose counter control (including lock detection bit 4 control) Input register 2 D2H I/O port and general-purpose counter switching bits 3 I/O-5/CLK pin switching bit 1 DO pin control 1 Test bit 1 I/O port control (also used as general-purpose counter input 5 selection bits) Output data 9 total 24 Output register 1 Output register 2 General-purpose counter numeric data D1H 22 Not used 2 total 24 D3H Lock detection data 5 I/O port control data 5 Output data 4 Input data (undefined during output port selection) 5 Not used 5 total 24 When the PERIOD signal falls, the input data are latched in register 1 or register 2 and the function is performed. When the CLOCK signal falls for 9 time, the output data are latched in parallel in the output registers. The data are subsequently output serially from the data pin. HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 6 2002.01.30. Silan Semiconductors SC9256 REGISTER ASSIGMENTS Address=D0H LSB LSB P1 P2 P3 P4 Input registers P0 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 R0 R1 R2 R3 Reference frequency code data Programmable counter data FM MODE OSC1 OSC2 Crystal oscillator selection bits Programmable counter mode Address=D2H (*2) G0 G1 -- IF1 IF2 O4C DOHZ RESET START TEST XT -- TEST RESET CLK Gate I/O port bit bit time and general-purpose bit START select counter switching bits DOHZ bit bit -- M5 M6 O1 O2 O3 O4 -- -- -- O5 O6 f19 OVER BUSY "0" "0" Output port output data Also used as general-purpose counter input selection bits I/O port control Address=D1H LSB Input registers f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 Not used General-purpose counter data Address=D3H ENA- UN PE1 BLE LOCK PE2 PE3 "0" "0" Lock detection data "0" "0" "0" 0 Not used 0 0 M5 M6 O1 I/O port control data O2 O3 O4 0 0 Output data 0 I5 I6 Input data When power is turned on, the input registers are set as shown below. Address=D0H MSB Input registers LSB (*1) (*1) (*1) (*1) (*1) (*1) (*1) (*1) (*1) (*1) (*1) (*1) (*1) (*1) (*1) (*1) 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address=D2H 0 0 Note: 1. Data are undefined. 2. Set data to “0” for test bit. HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 7 2002.01.30. Silan Semiconductors SC9256 Serial transfer format The serial transfer format consists of 8 address bits and 24 data bits (Fig. 1). Addresses D0H~D3H are used. Start PERIOD End t4 t3 t5 t6 t7 t1 t2 9 clock signal fall CLOCK t8 (*) (*) DATA 0 0 1 0 1 LSB 1 MSB 8 address bits MSB LSB 24 data bits (24bit register) Fig.1 • Serial data transfer serial data are transferred in sync with the clock signal. In the idle state, the PERIOD, CLOCK and DATA pin lines are all set to “H” level. When the period signal is at “L” level, the falling of the clock signal initiates serial data transfer. Data transfer ceases when the period signal is set to “L” level when the clock signal is at “H” level. Once serial data transfer has begun, however, no more than 8 falls of the clock signal can occur during the time the period signal is at “L” level. Since the receiving side receives the serial data as valid data when the clock signal rises, it is effective for the sending side to produce output in sync with the clock signal fall. To receive serial data from the output registers (D1H, D3H), set the serial data output to high impedance after the 8 bit address is output but before the next clock signal falls. Data reception subsequently continues until the period signal becomes “L” level; data transfer ends just before the period signal rises. Therefore, the data pin must have an open-drain or tristate interface. Note: 1. when power is turned on, some internal circuit have undefined states. To set internal circuit states, execute a dummy data transfer before performing regular data transfer. 2. times t1~t8 have the following value: t1≥1.0µs t2≥1.0µs t3≥0.3µs t4≥0.3µs t5≥0.3µs t6≥1.0µs t7≥1.0µs t8≥0.3µs 3. Asterisks represent numbers taken from addresses, as in D*H. HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 8 2002.01.30. Silan Semiconductors SC9256 Crystal oscillator pins (XT, XT ) As fig.2 shows, the clock necessary for internal operation is produced by connecting a crystal oscillator between capacitors. Use the crystal oscillator selection bit to select an oscillating frequency of 3.6MHz, 4.5MHz, 7.2MHz or 10.8MHz which matches that of the crystal oscillator used. LSB MSB OSC1 OSC2 Address D0H OSC1 OSC2 OSCILLATOR FREQUENCY 0 0 3.6MHz 1 0 4.5MHz 0 1 7.2MHz 1 1 10.8MHz Divider XT C XT C X'tal C=30pF Typ. Fig.2 Note: set to 3.6MHz (OSC1=”0” and OSC2=”0”) when power is turned on. The crystal is not oscillating at this time because the system is in standby mode. Reference counter (Reference frequency divider) The reference counter section consists of a crystal oscillator and a counter. A crystal oscillator frequency of 3.6MHZ, 7.2MHZ or 10.8MHZ can be selected .A maximum of 15 reference frequencies can be generated. 1. Setting reference frequency The reference frequency is set using bits R0~R3. LSB MSB R0 R1 R2 R3 Address D0H R0 R1 R2 R3 REFERENCE FREQUENCY R0 R1 R2 R3 REFERENCE FREQUENCY *7.8125 KHz 0 0 0 0 0.5 KHz 0 0 0 1 1 0 0 0 1 KHz 1 0 0 1 9 KHz 0 1 0 0 2.5 KHz 0 1 0 1 10 KHz 1 1 0 0 3 KHz 1 1 0 1 12.5 KHz 0 0 1 0 3.125 KHz 0 0 1 1 25 KHz 1 0 1 0 *3.90654 KHz 1 0 1 1 0 1 1 1 1 1 0 0 5 KHz 6.25 KHz 0 1 1 1 1 1 1 1 50 KHz 100 KHz Standby mode (*1) HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 9 2002.01.30. Silan Semiconductors SC9256 Note: 1. Reference frequencies marked with an asterisk “*”can only be generated with a 4.5MHZ crystal oscillator. 2. (*1)Standby mode Standby mode occurs when bits R0,R1,R2,and R3 are all set to “1”.In standby mode, the programmable counter stops, and FM, AM and IFIN(when selected IFIN) are set to “amp off” state (pins at “L” level). This saves current consumption when the radio is turned off. The DO pins become high impedance during standby mode. During standby mode, the I/O ports (I/O-5~I/O-6) and output ports (OT1~OT4) can be controlled and the crystal oscillator can be turned on and off. 3.The system is set to standby mode when power is turned on. At this time, the crystal oscillator is not oscillating and the I/O ports are set to input mode. Programmable counter The programmable counter section consists of a 1/2 prescaler, a 2 modulus prescaler and a 4bit +12bit programmable binary counter. 1. Setting programmable counter 16 bits of divisor data and 2 bits, which indicate the dividing mode, are set in the programmable counter. (1) Setting dividing mode The FM and MODE bits are used to select the input pin and the dividing mode (pulses wallow mode or direct dividing mode). There are 4 possible choices, shown in the table below .Select one based on the frequency band used. LSB MSB FM MODE Address D0H INPUT FREQUENCY TYPICAL RANGE RECEIVING BAND MODE FM MODE DIVIDING MODE LF (2) HF 0 0 0 1 FML 1 0 FMH 1 1 Direct dividing mode LW,MW,SWL SWH Pulse swallow mode 1/2 + pulse swallow mode 0.5 ~ 20MHz 1 ~ 40MHz FM 30 ~ 130MHz 30 ~ 150MHz FM 30 ~ 130MHz INPUT FREQUENCY PIN AMIN n FMIN 2n Setting divisor The divisor for the programmable counter is set as binary data in bits P0~P15. • Pulse swallow mode (16 bits) LSB Address D0H P0 MSB P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 20 215 Divisor setting range (pulse swallow mode):n=210H~FFFH (528~65535) (Note) With the 1/2+pulse swallow mode, the actual divisor is twice the programmed value. HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 10 2002.01.30. Silan Semiconductors SC9256 • Direct dividing mode (12 bits) LSB MSB P0 Address D0H P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 20 211 Don't care Divisor setting range (direct dividing mode):n=10H~FFFH(16~4095) With the direct dividing mode, data p0~p3 are don’t-care and bit p4 is the LSB. 2. Prescaler and programmable counter circuit configuration (1) Pulse swallow mode circuit configuration PSC P0-P3 4bit swallow counter FMH 1/2 FMIN 2 modulus prescaler FML Preset To phase comparator 12bit programmable counter HF AMIN FM,MODE P4-P15 Prescaler section Fig.3 This circuit consists of a 2 modulus prescaler, a 4 bit swallow counter and a 12bit programmable counter. During FMIN(FMIN mode),a 1/2 prescaler is added to the preceding step. (2) Direct dividing method circuit configuration Preset Amp AMIN 12bit program counter To phase comparator P4-P15 Fig.4 With the direct dividing mode, the prescaler section is bypassed and the 12bit programmable counter is used. (3) Both FMIN and AMIN have built-in amps. Data are input by capacitor coupling. FMIN and AMIN operate at low amplitude. General-purpose counter The general-purpose counter is a 20bit counter. It has such uses as counting AM/FM band intermediate frequencies (IF) and detecting auto-stop signals during auto-search tuning. General-purpose counter pins can also be used as I/O ports. 1. General-purpose counter control bits (1) Bits G0 and G1 … Used for selecting the general-purpose counter gate time. HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 11 2002.01.30. Silan Semiconductors SC9256 LSB Address D2H G0 G1 MSB CYCLE MEASUREMENT PULSE 50 KHz G0 G1 GATE TIME 0 0 1 0 1ms 4ms 0 1 1 1 16ms 64ms 150 KHz 900 KHz Crystal oscillator frequency (2) Bits SC,IF1 and IF2 …I/O port and general-purpose counter switching bits. (*) The functions of the following pins are switched by data. LSB MSB IF1 IF2 Address D2H IF1 1 0 I/O-5/IFIN1 IFIN1 I/O-5 IF2 I/O-6/IFIN2 1 0 IFIN2 I/O-6 (3) Bits M5 sets the state for pin I/O-5/IFIN1; M6, for pin I/O-6/IFIN2. These operations are valid when bits SC, IF1 and IF2 are all set to 1. LSB MSB M5 M6 Address D2H PIN STATES (When bits sc, IF1 and IF2 are all set to "1") M5 M6 0 0 (*) 1 1 0 INPUT enabled 0 0 INPUT pulled down IFIN1 INPUT pulled down IFIN2 INPUT pulled down INPUT enabled INPUT pulled down Note: Bits marked with an asterisk “(*)” are don’t care (4) Bits f0~f9…The general-purpose counter results can be read in binary from bits f0~f9 of the output register (D1H). LSB Address D1H f0 MSB f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 20 OVER BUSY "0" "0" 219 General-purpose counter data (5) OVER and BUSY bits…Detect the operating state of the general-purpose counter. HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 12 2002.01.30. Silan Semiconductors Address D1H OVER BUSY SC9256 MSB "0" "0" BIT DATA = "1" BIT DATA = "0" General-purpose counter option monitor bit General-purpose counter busy General-purpose counter overflow detection bit Counted value in generalpurpose counter 220 (Overflow state) General-purpose counter ended counting Counted value in generalpurpose counter 220 -1 Note: When using the general-purpose counter, before referring to the contents of the general-purpose counter result bit (f0~f9), confirm that the busy bit is “0” (counting is ended) and the OVER bit is “0” (general-purpose counter data are normal). (6) START bit…When the data are set to “1”, the general-purpose counter is reset then counting begins. LSB MSB start Address D2H 2. 0 Counting continues uninterrupted. 1 Counting begins after general - purpose counter is reset. General-purpose counter circuit configuration The general-purpose counter section consists of input amps, a gate time control circuit and a 20 bit binary counter. f0-f19 Amp OVER IFIN1 20bit binary counter Overflow detection IFIN2 SCIN (CMOS input) Gate Cycle measurement pulse SC IF1 IF2 Gate time control circuit START G0 fXT G1 BUSY Fig.5 3. General-purpose counter measurement timing HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 13 2002.01.30. Silan Semiconductors SC9256 End PERIOD T1 START bit set to "1" IFIN1 OR IFIN2 BUSY bit T2 Gate Binary counter input Clock pulse to be measured Frequency measurement timing chart 0<T1≤0.25(µs), 0<T2 ≤1 (ms) Note: 1. IFIN1 and IFIN2 input have built-in amps. Data are input by capacitor coupling. FMIN and AMIN operate at low amplitude. General-purpose I/O ports These LSIs feature general-purpose output and I/O ports which are controlled through the serial ports. Input/output form port Input/output configuration Output port Dedicated: 4 ports N channel open-drain output I/O ports Dedicated: 1 port, CMOS input/output Maximum: 5 ports 1. General-purpose output ports (OT-1~OT-4) Pins OT-1~OT-4 are general-purpose dedicated output ports. They have such uses as control signal output. They are configured for N channel open-drain output and have an off withstanding voltage of 12V. The data set in bits O1~O4 of the input register (D2H) are output in parallel from their correspond dedicated output port pins OT-1~OT-4. SC9256 do not have dedicated output port OT-4, but setting the input register (D2H) CLK (O4C) bit to “1” converts pin DO2 into output port OT-4 (configured for CMOS output). The data set in bits O1~O4 of the input register (D2H) can also be read from the DATA pins as output register (D3H) serial data O1~O4. HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 14 2002.01.30. Silan Semiconductors SC9256 (1) SC9256 LSB MSB O1 O2 O3 O4 O4C Address D2H PIN OUTPUT STATE O4C DO2/OT-4PIN O1~O4 0 DO2 (Phase comparator output) 0 High impedance (N channel open drain output =off) "L" Level (*1) 1 OT-4 (General-purpose output port) 1 "L" level (N channel open drain output =on) "H" Level (*1) OT-1~OT-3 OT-4 (*1) (2)output register … The data set in bits O1~O4 of the input register can read as serial data O1~O4 from the output register (D3H). LSB MSB O1 O2 O3 O4 Address D2H Input register LSB MSB O1 O2 O3 O4 Address D3H Output register 2. General-purpose I/O ports (I/O-5~I/O-6) Pins I/O-5~ I/O-6 are general-purpose I/O ports used for control signal input and output. They are configured for CMOS input and output. These I/O ports are set for input or output using bits M5~M6 of the input register (D2H). Setting M5~M6 to “0” sets these ports for input. Data which are input in parallel from I/O-5~I/O-6 are latched in the internal register on the ninth fall of the serial clock signal. These data can then be read as serial data I5~I6 from the DATA pins. Data which are set in bits O5~O6 of the input register (D2H) are output in parallel from their corresponding general-purpose I/O port pin I/O-5~I/O6. These operations are valid when bits SC, IF1, IF2 and CLK are all set to “0”. HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 15 2002.01.30. Silan Semiconductors SC9256 (1) SC9256 LSB MSB IF1 "0" Address D2H IF2 "0" M5 M6 PIN INPUT /OUTPUT STATE (When IF1 and IF2 are "0") M5, M6 I/O -5, I/O -6 0 "L" Level 1 "H" Level • Setting data for output ports LSB Address D2H MSB IF1 "0" IF2 "0" CLK "0" M5 "1" M6 "1" O5 O6 PIN OUTPUT STATE (When IF1 and IF2 are "0") O5, O6 I/O -5, I/O -6 0 "L"level 1 "H"level (2)OUTPUT register…data which are set in bits M5~M6 of the input register (D2H) can be read as serial data M5~M6 from the output register (D3H). LSB MSB XT -- Address D2H -- M5 M6 LSB Address D3H Input register MSB 0 0 0 M5 M6 Output register HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 16 2002.01.30. Silan Semiconductors SC9256 LSB MSB 0 Address D3H 0 0 Input register I5 I6 I/O-5 I/O-6 Input data INPUT PORTS (I/O-5 ~ I/O-6) BIT DATA (I5-I6) "L" level 0 "H" level 1 Note: 1. 2. When pins I/O-5~I/O-6 are used for output, the data in I5~I6 of the output register(D3H) are undefined.. When power is turned on, input register (D2H) I/O port control bits M5~M6 and output data bits O5~O6 are set to “0”. General-purpose I/O ports are set as input ports. Pins which are used both as general-purpose I/O ports and for general-purpose counter input are set for I/O port input. The output state of general-purpose output ports is set to high impedance (N channel open drain output =off). 3. Pin I/O-5 and I/O-6 also serve as general-purpose counter input pins. Therefore, bits IF1 and IF2 of input register 2 must be set to “0” when these pins are used as I/O ports. Phase comparator The phase comparator outputs the phase error after comparing the phase difference of the reference frequency signal supplied by the reference counter and the divided output from the programmable counter. The frequencies and phase differences of these two signals are then equalized by passing them through low-pass filters. These signals then control the VCO. The filter constants can be customized for FM and AM bands since the signals are output in parallel from the phase comparator then pass through the two tristate buffer pins, DO1 and DO2. Reference frequency signal Programmable counter output R S VDD DO1 phase comparator FM VCO L.P.F VDD DO2 AM VCO L.P.F Fig.7 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 17 2002.01.30. Silan Semiconductors SC9256 VCC R R2 C RL To VCO varactor diode R1 S DO DO floating Tr1 Standard Tr1:2SC1815 Tr2:2SK246 High level Low level Tr2 R3 Typical low-pass filter constants (FM band reference values) C=0.33 F R1=10K R2=8.2K R3=330 RL=10K ¡ ¡ ¡ ¡ DO Output Timing Chart Typical Active Low-Pass Filter Circuit Fig.8 Fig.9 The figures above show the DO output timing chart and a typical active low-pass filter circuit featuring a Darlington connection between the FET and transistor. The filter circuit shown above is just one example. Actual circuits should be designed based on the band composition and the properties desired from the system. Pin DO2 can be switched for use as pin OT-4. Lock detection bits The lock detection bits detect locked states in the PLL system. These systems have an unlock detection bit (unlock bit) which is used to detect, using the reference frequency cycle, the phase difference between the reference frequency and divided output of programmable counter. These systems also have phase error detection bits ( bits PE1~PE3), which are capable of more precise detection (±0.55µs~±7.15µs). 1. Unlock detection bit (UNLOCK) This bit detects, using the reference frequency cycle, the phase difference between the reference frequency and the divided output of the programmable counter. When there is no lock, that is, when the reference frequency and the divided output of the programmable counter are not the same, unlock F/F is set. Unlock F/F is reset every time the input register (D2H) unlock reset bit (RESET) is set to “1”. After unlock F/F has been reset in this way, locked state can detected by checking the unlock detection bit (UNLOCK) of the output register (D3H). After unlock F/F has been reset, the unlock detection bit must be checked after a time interval exceeding that of the reference frequency cycle has elapsed. This is because the reference frequency cycle inputs the lock detection strobe to unlock F/F. If the time interval is short, the correct locked state cannot be detected. Therefore, the output register (D3H) has a lock enable bit (ENABLE). This bit is reset every time the input register (D2H) reset bit is set to “1”, and set to “1” through the lock detection timing. That is, the locked state is correctly detected when the lock enable bit (ENABLE) is “1”. HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 18 2002.01.30. Silan Semiconductors SC9256 Reference frequency Programmable counter output "H" level High impedance DO output "L" level Phase comparator Lock detection strobe Unlock is reset (RESET) Unlock F/F (UNLOCK) Lock enable (ENABLE) Phase error detection Counts phase difference. Fig.10 LSB MSB RESET Address D2H Input register Setting data to "1" resets unlock detection bit and lock enable bit. LSB Address D3H MSB ENABLE 1 0 UN LOCK Output register PLL lock detection enabled PLL lock detection in waiting state 1 PLL in unlocked state(*) 0 PLL in locked state Note: The asterisk (*) indicates an error state of over 180° phase difference relative to the reference frequency 2. Phase error detection bits (PE1~PE3) The unlock bit detects, using the reference frequency cycle, the phase difference between the reference frequency and the divided output of the programmable counter. The phase error detection bits (bits PE1~PE3) are capable of precise phase error detection of ±0.55µs~±7.15µs using the reference frequency cycle.( If the UNLOCK bit is set to “1” and the phase difference relative to the reference frequency is over 180°, bits PE1~PE3 cannot correctly detect the phase error. Therefore, bits PE1~PE3 are normally used when the UNLOCK bit is set to “0”.) Bits PE1~PE3 detect phase error normally when the phase difference is -180°~180° relative to the reference frequency cycle. HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 19 2002.01.30. Silan Semiconductors SC9256 LSB Address D3H MSB PE1 PE2 PE3 PE1 PE2 PE3 0 0 0 0 0 1 0 1 0 0 1 1 1 1 0 0 0 1 1 1 0 1 1 1 PHASE ERROR (PE) PE<0.55s 0.55sPE<1.65s 1.65s PE<2.75s 2.75sPE<3.85s 3.85sPE<4.95s 4.95sPE<6.05s 6.05sPE<7.15s 7.15sPE The phase error data can be read from the output register (D3H) as serial data PE1~PE3. Following is a typical lock detection operation. It shows the operation flow from locked state to frequency change with a phase error greater than ±6.05µs. Frequency change WAIT Phase error detection start Reset bit 1 WAIT Time interval exceeding that of reference frequcncy cycle ENABLE=1? NO YES UNLOCK bit =0? NO (UNLOCK) YES (Lock) Check phase error detection bits PE1,PE2 and PE3 NO PE1=1,PE2=0,PE3=1? YES s Phase error=greater than 4.95 and less than 6.05 s Fig.11 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 20 2002.01.30. Silan Semiconductors SC9256 Other Control Bits 1. CLK and C5 bits…Control bits which switch the function for the OT-4/DO2 pin. The O4C bit controls switching of the DO2 pin and OT-4 pin. When bits R0~R3 of the input register (D0H) are set to “1” (standby mode). LSB MSB O4C Address D2H O4C XT 0 0 0 1 1 0 1 1 XT DO2/OT-4 PIN STATE DO2 output OT-4 output CRYSTAL OSCILLATOR CIRCUIT STATE Oscillator circuit off Oscillator circuit on Oscillator circuit off Oscillator circuit on When one of bit R0~R3 of the input register (D0H) is set to “0” (not standby mode) LSB MSB O4C Address D2H O4C 2. XT 0 0 0 1 1 0 1 1 XT DO2/OT-4 PIN STATE CRYSTAL OSCILLATOR CIRCUIT STATE DO2 output Oscillator circuit on OT-4 output DOHZ bit…controls the DO2 pin output state. LSB 3. MSB DOHZ Address D2H 0 phase comparison error output 1 DO2 output fixed at high impedance TEST bit… Data should normally be set to “0”. LSB Address D2H MSB TEST "0" HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 21 2002.01.30. Silan Semiconductors SC9256 ELECTRICAL CHARACTERISTICS CURVE AMIN(LF) Frequency Characteristics FMIN(LF) Frequency Characteristics 1414 1000 INPUT LEVEL (mVrms) INPUT LEVEL (mVrms) 1414 1000 500 200 106 71 50 20 10 5 2 1 0.1 500 200 106 71 50 20 10 5 2 0.2 0.5 1 2 5 10 20 1 0 50 100 20 INPUT FREQUENCY (MHz) AMIN(HF) Frequency Characteristics INPUT LEVEL (mVrms) INPUT LEVEL (mVrms) 80 100 120 140 160 180 200 1414 1000 500 200 106 71 50 20 10 5 2 500 200 106 71 50 20 10 5 2 1 1 0.2 0.5 1 2 5 10 20 40 50 100 0.05 0.1 0.2 INPUT FREQUENCY (MHz) (Note) 60 IFIN(LF) Frequency Characteristics 1414 1000 0.1 40 INPUT FREQUENCY (MHz) Operating Guarantee Range VDD=4.5~5.5v,Ta = -40 ~ 85) Standard Characteristics(VDD = 5V,Ta =25) 0.5 1 2 5 10 15 20 50 INPUT FREQUENCY (MHz) (Note) FMIN:FMH + FMIN:FML Operating Guarantee Range (VDD=4.5~5.5v,Ta = -40 ~ 85) Standard Characteristics(VDD = 5V,Ta =25) HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 22 2002.01.30. Silan Semiconductors SC9256 APPLICATION CIRCUIT VCC 5Vtyp. Varator Diode C C 16 2 15 AM VCO X'tal PERIOD 3 CLOCK 4 DATA 5 SC9256 MicroController 1 0.01 F 14 0.01 F 13 AM VCO F 0.01F 12 AMIF signal FMIF signal 0.001 6 11 7 10 8 9 4.7 F 0.1 3 F Output Port HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 23 2002.01.30. Silan Semiconductors SC9256 PACKAGE OUTLINE DIP-16-300-2.54 UNIT: mm 0.25 B 7.62(300) 0.25 0.05 2.54 6.35 B 1.52 B 15 degree 4.36MAX 19.55 0.3 3.00MIN 0.5MIN B0.1 1.27MAX 0.5 SOP-16-300-1.27 UNIT:mm B0.10 0.45 0.30 5.30 B 1.27 B0.25 B 7.62(300) 0.40 7.80 2.25MAX +0.05 0.15 -0.02 10.15 8.89 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 24 2002.01.30.