Silan Semiconductors SC9257 PLL FOR DTS DESCRIPTION The SC9257 is phase-locked loop (PLL) LSIs for digital tuning systems (DTS) with built in 2 modulus prescalers. All functions ate controlled through 3 serial bus lines. These LSIs DIP-20-300-2.54 are used to configure high-performance digital tuning system. FEATURES * Optimal for configuring digital tuning systems in high-fi tuners and car stereos. * built-in prescalers. Operate at input frequency ranging from SOP-20-300-1.27 30~150 MHz during FMIN input (with 2 modulus prescaler) and at 0.5~40MHz during AMIN input (with 2 modulus prescaler or direct dividing). * 16 bit programmable counter, dual parallel output phase comparator, crystal oscillator and reference counter. * 4 N-channel open-drain output ports (OFF withstanding voltage:12V) for such * 3.6MHz, 4.5MHz, 7.2MHz or 10.8MHz crystal oscillators can be used. uses as control signal output. * Standby mode function (turns off FM, AM * 15 possible reference frequencies. ( When using 4.5MHz crystal) and * Built-in 20 bit general-purpose counter for such uses as consumption. measuring intermediate frequencies (IFIN1 and IFIN2) and lowfrequency pilot signal cycles (SCIN). IF amps) to save current * All functions controlled through 3 serial bus lines. * High-precision (±0.55~±7.15µs) PLL phase error detection. * Numerous general-purpose I/O pins for such uses as peripheral * CMOS structure with operating power supply range of VDD=5.0±0.5V. circuit control. PIN CONFIGURATION 1 20 DO2 XT 2 19 DO1 PERIOD 3 18 I/O-7/SCIN CLOCK 4 17 I/O - 8/IFIN1 DATA 5 OT-1 6 OT-2 7 14 FMIN OT-3 8 13 AMIN OT-4 9 12 VDD SC9257 XT I/O - 5/CLK 10 16 I/O - 9/IFIN2 15 GND 11 I/O-6 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 1 2001.10.18 Silan Semiconductors SC9257 BLOCK DIAGRAM VDD AMP 1/2 2 MODULUS PERSCALER 4bit SWALLOW COUNTER FMH HF AMIN OSC CIRCUIT XT 12bit PROGRAMMABLE COUNTER LF MODE FM XT POWER ON RESET 4 12 REFERENCE COUNTER MAX 15 1ms OSC 4 24bit REGISTER RESET PHASE COMPARATOR FM IN GND PSC FML UNLOCK TRI-STATE BUFFER DO1 TRI-STATE BUFFER DO2 OT4 I/O-5/CLK DATA I/O PORT 5 24bit SHIFT REGISTER CLOCK 8 TEST ADDRESS DECODER 5 24 I/O-6 22 PERIOD 10 24bit REGISTER 4 4 OUTPUT PORT OT-4 I/O-9/IFIN2 AMP 20bit BINARY COUNTER UNIVERSAL COUNTER CONTROL I/O-8/IFIN1 GATE AMP I/O-7/SCIN 1ms XT OT-1 OT-3 OT-2 OT-4 ABSOLUTE MAXIMUM RATINGS (Ta=25°C) Characteristic Symbol Value Unit Supply Voltage VCC -0.3~6.0 V Input Voltage VIN -0.3~VDD+0.3 V VOFF 13 V PD 300(200) mW N-ch Open-Drain Off withstanding Voltage Power Dissipation Operating Temperature TOPR -40~85 °C Storage Temperature TSTG -65~150 °C HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 2 2001.10.18 Silan Semiconductors SC9257 ELECTRICAL CHARACTERISTICS (unless otherwise specified, Ta= -40~85°C, VDD=4.5~5.58V.) Characteristic Symbol Operating Power Supply Voltage VDD1 Operating Power Supply Current IDD1 Test Condition/Pin PLL operation (normal operating) VDD=5.0V, XT=10.8MHz, FMIN=150MHz Min Typ. Max Unit 4.5 5.0 5.5 V -- 7 15 mA 4.0 5.0 5.5 V -- 0.8 1.5 mA -- 120 240 µA 3.6 ~ 10.8 MHz 30 ~ 130 MHz 30 ~ 150 MHz Stand-by mode Crystal Oscillation Frequency Supply Voltage PLL OFF VDD2 (Operating crystal oscillation) Operating Power Supply Current IDD2 Operating Power Supply Current IDD3 VDD=5.0V, XT =10.8MHz PLL OFF VDD=5.0V, XT stop, PLL OFF Operating frequency range Connect crystal resonator Crystal Oscillation Frequency fXT FMIN (FMH, FML) fFM FMIN (FML) fFML AMIN (HF) fHF HF mode, VIN=0.2Vp-p 1 ~ 40 MHz AMIN (LF) fLF LF mode, VIN=0.2Vp-p 0.5 ~ 20 MHz IFIN1, IFIN2 fIF VIN=0.2Vp-p 0.1 ~ 15 MHz -- ~ 100 kHz 0.2 ~ VDD-0.5 Vp-p SCIN fSC to XT- XT terminal FMH, FML mode, VIN=0.2Vp-p FML mode, VIN=0.3Vp-p VIH=0.7VDD, VIL=0.3VDD, square wave input. Operating input amplitude range FMIN (FMH, FML) VFM FMH, FML mode, fIN=30~130MHz FMIN (FML) VFML FML mode, fIN=30~150MHz 0.3 ~ VDD-0.5 Vp-p AMIN (HF) VHF HF mode, fIN=1~40MHz 0.2 ~ VDD-0.5 Vp-p AMIN (LF) VLF LF mode, fIN=0.5~20MHz 0.2 ~ VDD-0.5 Vp-p IFIN1, IFIN2 VIF FIN=0.1~15MHz 0.2 ~ VDD-0.5 Vp-p IOL1 VOL=1.0V 5.0 10.0 -- mA IOEF VOFF=12V -- --- 2.0 µA OT1~OT4 N-ch open drain Output Current OFF-leak Current “L” level (To be continued) HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 3 2001.10.18 Silan Semiconductors SC9257 (Continued) Characteristic Symbol Test Condition/Pin Min Typ. Max Unit I/O-5~I/O-9, SCIN Input Voltage Input Current Output Current “H” level VIH1 0.7VDD ~ VDD “L” level VIL1 0 ~ 0.3VDD “H” level IIH VIH=5V -- -- 2.0 “L” level IIL VIL=0V -- -- -2.0 “H” level IOH4 VOH=4.0V (expect SCIN) -2.0 -4.0 -- “L” level IOL4 VOL=1.0V (expect SCIN) 2.0 4.0 -- V µA mA PERIOD, CLOCK, DATA Input Voltage Input Current Output Current “H” level VIH2 0.8VDD ~ VDD “L” level VIL2 0 ~ 0.2VDD “H” level IIH VIH=5V -- -- 2.0 “L” level IIL VIL=0V -- -- -2.0 “H” level IOH5 VOH=4.0V (DATA) -1.0 -3.0 -- “L” level IOL5 VOL=1.0V (DATA) 1.0 3.0 -- “H” level IOH3 VOH=4.0V -2.0 -4.0 -- “L” level IOL3 VOL=1.0V 2.0 4.0 -- -- -- ±1.0 V µA mA DO1, DO2 Input Current Tri-State Lead Current ITL VTLH=5V, VTLL=0V mA µA XT Output Current “H” level IOH2 VOH=4.0V -0.1 -0.3 -- “L” level IOL2 VOL=1.0V 0.1 0.3 -- 350 700 1400 500 1000 4000 mA Input feedback resistance Input Feedback “H” level Resistance “L” level Rf1 Rf2 FMIN, AMIN, IFIN (Ta=25°C) XT- XT (Ta=25°C) kΩ HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 4 2001.10.18 Silan Semiconductors SC9257 PIN DESCRIPTION Pin No. Symbol 1 XT Pin name Crystal oscillator pins 2 XT 3 PERIOD Description Circuit diagram VDD Connects 3.6MHz, 4.5MHz, 7.2MHz or 10.8MHz crystal oscillator to supply reference frequency and internal clock Period signal input Serial I/O ports. These pins transfer XT XT VDD data to and from the controller to set Clock signal input Schmitt input divisions and dividing modes, and to 4 CLOCK 5 DATA 6 OT-1 7 OT-2 General-purpose such uses as control signal output. 8 OT-3 output ports These pins are set to the OFF state 9 OT-4 10 I/O-5/CLK Schmitt input control the general-purpose counter Serial data DATA and general-purpose I/O ports. input/output N channel open drain port pins, for N-channel open drain when power is turned on. VDD CMOS structure allows free use of General-purpose I/O ports 11 CLOCK,PERIOD these ports for input or output. Ports are set for input when the power is turned on , I/O-5 can be switched for I/O-6 use as a system clock output pin. 13 14 VDD These pin input FM and AM band local AMIN Programmable oscillator counter input coupling. FMIN and AMIN operate at FMIN signals by capacitor low amplitude. General-purpose I/O port input/output pins. Can be switched for use as input 16 I/O9/IFIN2 pins to measure general-purpose General-purpose counter frequencies. The frequency V DD I/O ports/General- measurement function has such uses purpose 17 I/O8/IFIN1 counter as measuring intermediate frequency frequencies (IF). measurement These pins feature built-in amps. Data input are input by capacitor coupling. FMIN and AMIN operate at low amplitude. (note) Pins are set for input when power is turned on. (To be continued) HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 5 2001.10.18 Silan Semiconductors SC9257 (Continued) Pin No. Symbol Pin name General-purpose I/O 18 I/O7/SCIN input DO1 DO2/OT-4 purpose ports) 15 GND 12 VDD input pin to measure low-frequency (note) This pin is set for input when power is turned on. Phase comparator output 20 VDD cycle signal cycles. measurement 19 Circuit diagram General-purpose I/O port input/output ports/ pin. Can be switched for use as signal General-purpose counter Description (Generaloutput These pins are for phase comparator VDD tri-state output. DO1 and DO2 are output in parallel. Power supply pins Applies 5.0V±10% HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 6 2001.10.18 Silan Semiconductors SC9257 FUNCTION DESCRIPTION Serial I/O ports As the block diagram shows, the functions are controlled by setting data in the 48 bits contained in each of the 2 sets of 24 bit registers. Each bit of data in these register is transferred through the serial ports between the controller and the DATA, CLOCK and PERIOD pins. Each serial transfer consists of a total of 32 bits, with 8 address bits and 24 data bits. Since all functions are controlled in units of registers, the explanation in this manual focuses on the 8 bit address and functions of each register. These registers consist of 24 bits and are selected by an 8 bit address. A list of the address assignment for each register is given below under register assignments. Register Input register 1 Address D0H Contents of 24 bits No. of bit PLL divisor setting 16 Reference frequency setting 4 PLL input and mode setting 2 Crystal oscillator selection 2 total 24 General=purpose counter control (including lock detection bit 4 control) Input register 2 D2H I/O port and general-purpose counter switching bits 3 I/O-5/CLK pin switching bit 1 DO pin control 1 Test bit 1 I/O port control (also used as general-purpose counter input 5 selection bits) Output data 9 total 24 Output register 1 Output register 2 General-purpose counter numeric data D1H 22 Not used 2 total 24 D3H Lock detection data 5 I/O port control data 5 Output data 4 Input data (undefined during output port selection) 5 Not used 5 total 24 When the PERIOD signal falls, the input data are latched in register 1 or register 2 and the function is performed. When the CLOCK signal falls for 9 time, the output data are latched in parallel in the output registers. The data are subsequently output serially from the data pin. HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 7 2001.10.18 Silan Semiconductors SC9257 REGISTER ASSIGMENTS Address=D0H LSB LSB P1 P2 P3 P4 P5 Input registers P0 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 R0 R1 R2 R3 Reference frequency code data Programmable counter data FM MODE OSC1 OSC2 Crystal oscillator selection bits Programmable counter mode Address=D2H (*2) G0 G1 Gate time select SC IF1 IF2 I/O port and general-purpose counter switching bits CLK DOHZ RESET START TEST C5 CLK bit RESET bit DOHZ bit C6 TEST bit M7 M8 M9 O1 O2 O3 Also used as generalpurpose counter input selection bits START bit O4 O5 O6 O7 O8 O9 f19 OVER BUSY "0" "0" Output port output data I/O port control Address=D1H LSB f1 f2 f3 f4 f5 f6 f7 f8 Input registers f0 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 General-purpose counter data Not used Address=D3H ENA- UN PE1 BLE LOCK PE2 PE3 "0" "0" Lock detection data "0" "0" "0" C5 Not used C6 M7 M8 M9 O1 I/O port control data O2 O3 O4 I5 I6 Output data I7 I8 I9 Input data When power is turned on, the input registers are set as shown below. Address=D0H MSB LSB (*1) (*1) (*1) (*1) (*1) (*1) (*1) (*1) (*1) (*1) (*1) (*1) (*1) (*1) (*1) 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Input registers (*1) Address=D2H 0 Note: 0 1. Data are undefined. 2. Set data to “0” for test bit. HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 8 2001.10.18 Silan Semiconductors SC9257 Serial transfer format The serial transfer format consists of 8 address bits and 24 data bits (Fig. 1). Addresses D0H~D3H are used. Start End PERIOD t4 t3 t5 t6 t7 t1 t2 9 clock signal fall CLOCK t8 (*) (*) DATA 0 0 1 0 1 LSB 1 MSB 8 address bits MSB LSB 24 data bits (24bit register) Fig.1 • Serial data transfer serial data are transferred in sync with the clock signal. In the idlestate, the PERIOD, CLOCK and DATA pin lines are all set to “H” level. When the period signal is at “L” level, the falling of the clock signal initiates serial data transfer. Data transfer ceases when the period signal is set to “L” level when the clock signal is at “H” level. Once serial data transfer has begun, however, no more than 8 falls of the clock signal can occur during the time the period signal is at “L” level. Since the receiving side receives the serial data as valid data when the clock signal rises, it is effective for the sending side to produce output in sync with the clock signal fall. To receive serial data from the output registers (D1H, D3H), set the serial data output to high impedance after the 8 bit address is output but before the next clock signal falls. Data reception subsequently continues until the period signal becomes “L” level; data transfer ends just before the period signal rises. Therefore, the data pin must have an open-drain or tristate interface. Note: 1. when power is turned on, some internal circuit have undefined states. To set internal circuit states, execute a dummy data transfer before performing regular data transfer. 2. times t1~t8 have the following value: t1≥1.0µs t2≥1.0µs t3≥0.3µs t4≥0.3µs t5≥0.3µs t6≥1.0µs t7≥1.0µs t8≥0.3µs 3. Asterisks represent numbers taken from addresses, as in D*H. HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 9 2001.10.18 Silan Semiconductors SC9257 Crystal oscillator pins (XT, XT ) As fig.2 shows, the clock necessary for internal operation is produced by connecting a crystal oscillator between capacitors. Use the crystal oscillator selection bit to select an oscillating frequency of 3.6MHz, 4.5MHz, 7.2MHz or 10.8MHz which matches that of the crystal oscillator used. LSB MSB OSC1 OSC2 Address D0H OSC2 OSCILLATOR FREQUENCY 0 0 3.6MHz 1 0 4.5MHz 0 1 7.2MHz 1 1 10.8MHz OSC1 Divider XT C XT C X'tal C=30pF Typ. Fig.2 Note: set to 3.6MHz (OSC1=”0” and OSC2=”0”) when power is turned on. The crystal is not oscillating at this time because the system is in standby mode. HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 10 2001.10.18 Silan Semiconductors SC9257 Reference counter (Reference frequency divider) The reference counter section consists of a crystal oscillator and a counter. A crystal oscillator frequency of 3.6MHZ, 7.2MHZ or 10.8MHZ can be selected .A maximum of 15 reference frequencies can be generated. 1. Setting reference frequency The reference frequency is set using bits R0~R3. LSB MSB R0 R1 R2 R3 Address D0H R0 R1 R2 R3 REFERENCE FREQUENCY R0 R1 R2 R3 REFERENCE FREQUENCY 0 1 0 0 0 0 0 0 0.5 KHz 1 KHz 0 1 0 0 0 0 1 1 0 1 0 0 2.5 KHz 0 1 0 1 10 KHz 1 1 0 0 3 KHz 1 1 0 1 12.5 KHz 0 0 1 0 3.125 KHz 0 0 1 1 25 KHz 1 0 0 1 1 1 0 0 *3.90654 KHz 5 KHz 1 0 0 1 1 1 1 1 50 KHz 100 KHz 1 1 1 0 6.25 KHz 1 1 1 1 *7.8125 KHz 9 KHz Standby mode (*1) (Note 1) Reference frequencies marked with an asterisk “*”can only be generated with a 4.5MHZ crystal oscillator. (Note 2) (*1)Standby mode Standby mode occurs when bits R0,R1,R2,and R3 are all set to “1”.In standby mode, the programmable counter stops, and FM, AM and IFIN(when selected IFIN) are set to “amp off” state (pins at “L” level). This saves current consumption when the radio is turned off. The DO pins become high impedance during standby mode. During standby mode, the I/O ports (I/O-5~I/O-9) and output ports (OT1~OT4) can be controlled and the crystal oscillator can be turned on and off. (Note 3) The system is set to standby mode when power is turned on. At this time, the crystal oscillator is not oscillating and the I/O ports are set to input mode. Programmable counter The programmable counter section consists of a 1/2 prescaler, a 2 modulus prescaler and a 4bit +12bit programmable binary counter. 1. Setting programmable counter 16 bits of divisor data and 2 bits, which indicate the dividing mode, are set in the programmable counter. HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 11 2001.10.18 Silan Semiconductors SC9257 (1) Setting dividing mode The FM and MODE bits are used to select the input pin and the dividing mode (pulses wallow mode or direct dividing mode). There are 4 possible choices, shown in the table below .Select one based on the frequency band used. LSB MSB FM MODE Address D0H INPUT FREQUENCY TYPICAL RANGE RECEIVING BAND MODE FM MODE DIVIDING MODE LF HF 0 0 0 1 FML 1 0 FM H 1 1 Direct dividing mode LW,MW,SWL SWH 0.5 ~ 20MHz 1 ~ 40MHz FM 30 ~ 130MHz 30 ~ 150MHz FM 30 ~ 130MHz Pulse swallow mode 1/2 + pulse swallow mode INPUT FREQUENCY PIN AMIN n FM IN 2n (2) Setting divisor The divisor for the programmable counter is set as binary data in bits P0~P15. • Pulse swallow mode (16 bits) LSB Address D0H MSB P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 20 215 Divisor setting range (pulse swallow mode):n=210H~FFFH (528~65535) (Note) With the 1/2+pulse swallow mode, the actual divisor is twice the programmed value. • Direct dividing mode (12 bits) LSB Address D0H P0 MSB P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 20 211 Don't care Divisor setting range (direct dividing mode):n=10H~FFFH(16~4095) With the direct dividing mode, data p0~p3 are don’t-care and bit p4 is the LSB. HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 12 2001.10.18 Silan Semiconductors 2. SC9257 Prescaler and programmable counter circuit configuration (1) Pulse swallow mode circuit configuration PSC P0-P3 4bit swallow counter FM IN FM H 1/2 2 modulus prescaler FM L Preset To phase comparator 12bit programmable counter HF AMIN FM,MODE P4-P15 Prescaler section Fig.3 This circuit consists of a 2 modulus prescaler, a 4 bit swallow counter and a 12bit programmable counter. During FMIN(FMIN mode),a 1/2 prescaler is added to the preceding step. (2) Direct dividing method circuit configuration Amp AMIN Preset 12bit program counter To phase comparator P4-P15 Fig.4 With the direct dividing mode, the prescaler section is bypassed and the 12bit programmable counter is used. (3) Both FMIN and AMIN have built-in amps. Data are input by capacitor coupling. FMIN and AMIN operate at low amplitude. General-purpose counter The general-purpose counter is a 20bit counter. It has such uses as counting AM/FM band intermediate frequencies (IF) and detecting auto-stop signals during auto-search tuning. It also features a cycle measurement function for such uses as measuring low-frequency pilot signal cycles. 1. General-purpose counter control bits (1) Bits G0 and G1 … Used for selecting the general-purpose counter gate time. HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 13 2001.10.18 Silan Semiconductors SC9257 LSB Address D2H G0 G1 MSB CYCLE MEASUREMENT PULSE 50 KHz G0 G1 GATE TIME 0 0 1 0 1ms 4ms 0 1 1 1 16ms 64ms 150 KHz 900 KHz Crystal oscillator frequency (2) Bits SC,IF1 and IF2 …I/O port and general-purpose counter switching bits. (*) The functions of the following pins are switched by data. LSB Address D2H MSB sc IF1 IF2 SC I/O-7/SCIN IF1 1 0 SCIN 1 0 I/O-7 I/O-8/IFIN1 SCIN I/O-8 IF2 I/O-9/IFIN2 1 0 IFIN2 I/O-9 (3) Bits M7, M8 and M9 … M7 sets the state for pin I/O-7/SCIN, M8 sets the state for pin I/O-8/IFIN1; M9, for pin I/O-9/IFIN2. These operations are valid when bits SC, IF1 and IF2 are all set to 1. LSB MSB M7 M8 M9 Address D2H M7 M8 M9 0 0 0 (*) (*) 1 (*) 1 0 1 0 0 PIN STATES (When bits sc, IF1 and IF2 are all set to "1") SCIN INPUT disabled IFIN1 INPUT pulled down INPUT enabled INPUT enabled INPUT pulled down IFIN2 INPUT pulled down INPUT enabled INPUT pulled down Note: Bits marked with an asterisk “(*)” are don’t care HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 14 2001.10.18 Silan Semiconductors SC9257 (4) Bits f0~f9…The general-purpose counter results can be read in binary from bits f0~f9 of the output register (D1H). LSB Address D1H f0 MSB f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 20 OVER BUSY "0" "0" 219 General-purpose counter data (5) OVER and BUSY bits…Detect the operating state of the general-purpose counter. Address D1H MSB OVER BUSY "0" "0" BIT DATA = "1" BIT DATA = "0" General-purpose counter option monitor bit General-purpose counter busy General-purpose counter ended counting General-purpose counter overflow detection bit Counted value in generalpurpose counter220 (Overflow state) Counted value in generalpurpose counter220 -1 Note: When using the general-purpose counter, before referring to the contents of the general-purpose counter result bit (f0~f9), confirm that the busy bit is “0” (counting is ended) and the OVER bit is “0” (general-purpose counter data are normal). (6) START bit…When the data are set to “1”, the general-purpose counter is reset then counting begins. LSB MSB start Address D2H 0 Counting continues uninterrupted. 1 Counting begins after general - purpose counter is reset. HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 15 2001.10.18 2. Silan Semiconductors SC9257 General-purpose counter circuit configuration The general-purpose counter section consists of input amps, a gate time control circuit and a 20 bit binary counter. f0-f19 Amp OVER IFIN1 20bit binary counter Overflow detection IFIN2 Gate Cycle measurement pulse SCIN (CMOS input) SC IF1 IF2 fXT Gate time control circuit START G0 G1 BUSY Fig.5 3. General-purpose counter measurement timing End PERIOD End PERIOD T1 T1 START bit set to "1" START bit set to "1" IFIN1 OR IFIN2 SCIN BUSY bit BUSY bit T2 Gate Gate Binary counter input Binary counter input Clock pulse to be measured Reference clock pulse Frequency measurement timing chart Cycle measurement timing chart 0<T1≤0.25(µs), 0<T2 ≤1 (ms) Note: 1. IFIN1 and IFIN2 input have built-in amps. Data are input by capacitor coupling. FMIN and AMIN operate at low amplitude. 2. SCIN is configured for CMOS input, so input signals should be logic level. HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 16 2001.10.18 Silan Semiconductors SC9257 General-purpose I/O ports These LSIs feature general-purpose output and I/O ports which are controlled through the serial ports. Input/output form port Output port Dedicated: 4 ports Input/output configuration N channel open-drain output I/O ports Dedicated: 1 port, CMOS input/output Maximum: 5 ports 1. General-purpose output ports (OT-1~OT-4) Pins OT-1~OT-4 are general-purpose dedicated output ports. They have such uses as control signal output. They are configured for N channel open-drain output and have an off withstanding voltage of 12V. The data set in bits O1~O4 of the input register (D2H) are output in parallel from their correspond dedicated output port pins OT-1~OT-4. The data set in bits O1~O4 of the input register (D2H) can also be read from the DATA pins as output register (D3H) serial data O1~O4. (1) SC9257 LSB MSB O1 O2 O3 O4 Address D2H PIN OUTPUT STATE O1~O4 OT-1~OT-4 0 High impedance (N channel open drain output =off) 1 "L" level (N channel open drain output =on) (2)output register … The data set in bits O1~O4 of the input register can read as serial data O1~O4 from the output register (D3H). LSB MSB O1 O2 O3 O4 Address D2H Input register LSB MSB O1 O2 O3 O4 Address D3H Output register HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 17 2001.10.18 Silan Semiconductors SC9257 2. General-purpose I/O ports (I/O-5~I/O-9) Pins I/O-5~ I/O-9 are general-purpose I/O ports used for control signal input and output. They are configured for CMOS input and output. These I/O ports are set for input or output using bits C5, C6 and M7~M9 of the input register (D2H). Setting bits C5, C6 and M7~M9 to “0” sets these ports for input. Data which are input in parallel from I/O5~I/O-9 are latched in the internal register on the ninth fall of the serial clock signal. These data can then be read as serial data I5~I9 from the DATA pins. Setting bit C5, C6 and M7~M9 to “1” sets these ports for output. Data which are set in bits O5~O9 of the input register (D2H) are output in parallel from their corresponding general-purpose I/O port pin I/O-5~I/O9. These operations are valid when bits SC, IF1, IF2 and CLK are all set to “0”. (1) SC9257 LSB MSB SC "0" Address D2H IF1 "0" IF2 "0" CLK "0" C5 C6 M7 M8 M9 PIN INPUT /OUTPUT STATE (When SC,IF1 and IF2 are "0") C5,C6 M7~M9 I/O -5~I/O -9 0 Input port 1 Output port • Setting data for output ports LSB Address D2H MSB SC "0" IF1 "0" IF2 "0" O5~O9 CLK "0" C5 "1" C6 "1" M7 "1" M8 "1" M9 "1" O5 O6 O7 O8 O9 PIN OUTPUT STATE (When SC,IF1 and IF2 are "0") I/O -5~I/O -9 0 "L"level 1 "H"level Note: On the SC9257, pins I/O-7~I/O-9 also serve as general-purpose counter input pins. Therefore, bits SC, IF1 and IF2 of the input register (D2H) must be set to “0” when pins I/O-7~ I/O-9 are used for I/O ports. Since pin I/O-5 also serves as the CLK pin, the CLK bit of the input register (D2H) must be set to “0” when pin I/O5 is used as an I/O port. HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 18 2001.10.18 Silan Semiconductors SC9257 (2) Output register… Data which ate set in bits C5, C6 and M7~M9 of the input register (D2H) can be read as serial data C5, C6 and M7~M9 from the output register (D3H). LSB MSB C5 C6 M7 M8 M9 Address D2H Input register LSB MSB Output register C5 C6 M7 M8 M9 Address D3H Data which are input in parallel from pins I/O –5~I/O-9 can be read as serial data I5~I9 from the output register (D3H) LSB MSB I5 I6 I7 I8 I9 Address D3H I/O-5 I/O-6 I/O-7 Input register I/O-8 I/O-9 Input data INPUT PORTS (I/O-5 ~ I/O-9) BIT DATA (15-19) "L" level 0 "H" level 1 Note: 1. When pins I/O-5~I/O-9 are used for output, the data in I5~I9 of the output register(D3H) are undefined.. 2.When power is turned on, input register (D2H) I/O port control bits C5, C6 and M7~M9 and output data bits O5~O9 are set to “0”. General-purpose I/O ports are set as input ports. Pins which are used both as general-purpose I/O ports and for general-purpose counter input are set for I/O port input. The output state of general-purpose output ports is set to high impedance (N channel open drain output =off). A typical example of data setting for general-purpose counter and I/O port use is shown below. LSB Address D2H SC IF1 IF2 "0" "1" "1" PIN NAME I/O-7/SCIN Pin function I/O-7 Pin input/ output state MSB M7 M8 M9 "1" "1" "0" I/O-8/IFIN1 IFIN1 Output port Input enable I/O-9/IFIN2 IFIN2 Input pulled down As shown above, the pins can be switched as necessary to enable use as an I/O port or general-purpose counter. HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 19 2001.10.18 Silan Semiconductors SC9257 Phase comparator The phase comparator outputs the phase error after comparing the phase difference of the reference frequency signal supplied by the reference counter and the divided output from the programmable counter. The frequencies and phase differences of these two signals are then equalized by passing them through low-pass filters. These signals then control the VCO. The filter constants can be customized for FM and AM bands since the signals are output in parallel from the phase comparator then pass through the two tristate buffer pins, DO1 and DO2. Reference frequency signal Programmable counter output R S VDD DO1 phase comparator FM VCO L.P.F VDD DO2 AM VCO L.P.F Fig.7 VCC R R2 C RL To VCO varactor diode R1 S DO Tr1 DO floating High level Standard Tr1:2SC1815 Tr2:2SK246 Low level DO Output Timing Chart Tr2 R3 Typical low-pass filter constants (FM band reference values) C=0.33F R1=10K R2=8.2K R3=330 RL=10K Typical Active Low-Pass Filter Circuit Fig.8 Fig.9 The figures above show the DO output timing chart and a typical active low-pass filter circuit featuring a Darlington connection between the FET and transistor. The filter circuit shown above is just one example. Actual circuits should be designed based on the band composition and the properties desired from the system. HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 20 2001.10.18 Silan Semiconductors SC9257 Lock detection bits The lock detection bits detect locked states in the PLL system. These systems have an unlock detection bit (unlock bit) which is used to detect, using the reference frequency cycle, the phase difference between the reference frequency and divided output of programmable counter. These systems also have phase error detection bits ( bits PE1~PE3), which are capable of more precise detection (±0.55µs~±7.15µs). 1. Unlock detection bit (UNLOCK) This bit detects, using the reference frequency cycle, the phase difference between the reference frequency and the divided output of the programmable counter. When there is no lock, that is, when the reference frequency and the divided output of the programmable counter are not the same, unlock F/F is set. Unlock F/F is reset every time the input register (D2H) unlock reset bit (RESET) is set to “1”. After unlock F/F has been reset in this way, locked state can detected by checking the unlock detection bit (UNLOCK) of the output register (D3H). After unlock F/F has been reset, the unlock detection bit must be checked after a time interval exceeding that of the reference frequency cycle has elapsed. This is because the reference frequency cycle inputs the lock detection strobe to unlock F/F. If the time interval is short, the correct locked state cannot be detected. Therefore, the output register (D3H) has a lock enable bit (ENABLE). This bit is reset every time the input register (D2H) reset bit is set to “1”, and set to “1” through the lock detection timing. That is, the locked state is correctly detected when the lock enable bit (ENABLE) is “1”. Reference frequency Programmable counter output "H" level High impedance DO output "L" level Phase comparator Lock detection strobe Unlock is reset (RESET) Unlock F/F (UNLOCK) Lock enable (ENABLE) Phase error detection Counts phase difference. Fig.10 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 21 2001.10.18 Silan Semiconductors SC9257 LSB MSB RESET Address D2H Input register Setting data to "1" resets unlock detection bit and lock enable bit. LSB Address D3H MSB ENABLE UN LOCK 1 Output register PLL lock detection enabled PLL lock detection in waiting state 0 1 PLL in unlocked state(*) 0 PLL in locked state Note: The asterisk (*) indicates an error state of over 180° phase difference relative to the reference frequency 2. Phase error detection bits (PE1~PE3) The unlock bit detects, using the reference frequency cycle, the phase difference between the reference frequency and the divided output of the programmable counter. The phase error detection bits (bits PE1~PE3) are capable of precise phase error detection of ±0.55µs~±7.15µs using the reference frequency cycle.( If the UNLOCK bit is set to “1” and the phase difference relative to the reference frequency is over 180°, bits PE1~PE3 cannot correctly detect the phase error. Therefore, bits PE1~PE3 are normally used when the UNLOCK bit is set to “0”.) Bits PE1~PE3 detect phase error normally when the phase difference is -180°~180° relative to the reference frequency cycle. LSB Address D3H MSB PE1 PE2 PE3 PE1 PE2 PE3 0 0 0 PE<0.55s 0 0 0 0 1 1 1 0 1 0.55sPE<1.65s 1.65s PE<2.75s 2.75sPE<3.85s 1 1 1 0 0 1 0 1 0 3.85sPE<4.95s 4.95sPE<6.05s 6.05sPE<7.15s 1 1 1 7.15sPE PHASE ERROR (PE) The phase error data can be read from the output register (D3H) as serial data PE1~PE3. HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 22 2001.10.18 Silan Semiconductors SC9257 Following is a typical lock detection operation. It shows the operation flow from locked state to frequency change with a phase error greater than ±6.05µs. Frequency change WAIT Phase error detection start Reset bit 1 WAIT Time interval exceeding that of reference frequcncy cycle ENABLE=1? NO YES UNLOCK bit =0? NO (UNLOCK) YES (Lock) Check phase error detection bits PE1,PE2 and PE3 NO PE1=1,PE2=0,PE3=1? YES Phase error=greater than 4.95s and less than6.05s Fig.11 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 23 2001.10.18 Silan Semiconductors SC9257 Other control bits 1. CLK and C5 bits…Control bits which switch the function for the I/O-5/CLK pin. (1) The CLK bit controls switching of the I/O-5/CLK pin and CLK pin. When bits R0~R3 of the input register (D0H) are all set to “1” (standby mode) LSB MSB CLK Address D2H CLK C5 C5 0 0 0 1 1 0 Input port I/O port Oscillator circuit off Output port System clock off (CLK at "L" level) CLK output 1 CRYSTAL OSCILLATOR CIRCUIT STATE I/O-5/ CLK PIN STATE 1 Oscillator circuit on System clock output(*) When one of bit R0~R3 of the input register (D0H) is set to “0” (not standby mode) LSB MSB CLK Address D2H CLK C5 C5 0 0 0 1 1 0 1 1 CRYSTAL OSCILLATOR CIRCUIT STATE I/O-5/ CLK PIN STATE Input port I/O port Output port CLK output Oscillator circuit on System clock output(*) Note: The system clock output marked with an asterisk “(*)” refers to output of the crystal oscillator frequencies listed below. Crystal oscillator (MHz) System clock (kHz) Duty (%) 10.8 7.2 600 50 3.6 4.2 750 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 24 2001.10.18 2. Silan Semiconductors SC9257 DOHZ bit…controls the DO2 pin output state. LSB MSB DOHZ Address D2H 0 1 3. DO2 output in normal operation (phase comparison error output) DO2 output fixed at high impedance TEST bit… Data should normally be set to “0”. LSB Address D2H MSB TEST "0" HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 25 2001.10.18 Silan Semiconductors SC9257 ELECTRICAL CHARACTERISTICS CURVE AMIN(LF) Frequency Characteristics FMIN(LF) Frequency Characteristics 1414 1000 INPUT LEVEL (mVrms) INPUT LEVEL (mVrms) 1414 1000 500 200 106 71 50 20 10 5 2 1 0.1 500 200 106 71 50 20 10 5 2 0.2 0.5 1 2 5 10 20 1 0 50 100 20 INPUT FREQUENCY (MHz) INPUT LEVEL (mVrms) INPUT LEVEL (mVrms) 1414 1000 500 200 106 71 50 20 10 5 2 500 200 106 71 50 20 10 5 2 0.2 0.5 1 2 5 10 1 20 40 50 100 0.05 0.1 0.2 INPUT FREQUENCY (MHz) (Note) 80 100 120 140 160 180 200 IFIN(LF) Frequency Characteristics 1414 1000 1 60 INPUT FREQUENCY (MHz) AMIN(HF) Frequency Characteristics 0.1 40 Operating Guarantee Range VDD=4.5~5.5v,Ta = -40 ~ 85) Standard Characteristics(VDD = 5V,Ta =25) 0.5 1 2 5 10 15 20 50 INPUT FREQUENCY (MHz) (Note) FMIN:FMH + FMIN:FML Operating Guarantee Range (VDD=4.5~5.5v,Ta = -40 ~ 85) Standard Characteristics(VDD = 5V,Ta =25) HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 26 2001.10.18 Silan Semiconductors SC9257 APPLICATION CIRCUIT VCC 5Vtyp. Varator Diode C MicroController C 1 20 AM VCO X'tal 19 3 18 CLOCK 4 DATA 5 0.01F 17 0.01F 16 6 SC9257 2 PERIOD AM VCO SCIN signal AMIF signal FMIF signal 15 0.001F 7 14 8 13 9 12 10 11 0.01F 4.7F 0.1F 2 4 I/O Port 12V max. Output Port HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 27 2001.10.18 Silan Semiconductors SC9257 PACKAGE OUTLINE DIP20-P-300-2.54 UNIT: mm 6.40B0.2 7.62 0.25 +0.1 -0.05 2.54 15 o 1.40B0.1 3.30B0.3 3.5B0.2 4.15B0.3 25.1 24.6B0.2 B 1.27 7.62 5.3B0.2 UNIT: mm 7.62 (300mil) SOP20-P-300-1.27 0.43B0.1 13.3 1.5B0.2 12.8B0.2 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 28 2001.10.18