UCC2626 UCC3626 application INFO available Brushless DC Motor Controller PRELIMINARY FEATURES DESCRIPTION • Two Quadrant and Four Quadrant Operation The UCC3626 motor controller IC combines many of the functions required to design a high performance, two or four quadrant, 3-phase, brushless DC motor controller into one package. Rotor position inputs are decoded to provide six outputs that control an external power stage. A precision triangle oscillator and latched comparator provide PWM motor control in either voltage or current mode configurations. The oscillator is easily synchronized to an external master clock source via the SYNCH input. Additionally, a QUAD select input configures the chip to modulate either the low side switches only, or both upper and lower switches, allowing the user to minimize switching losses in less demanding two quadrant applications. • Integrated Absolute Value Current Amplifier • Pulse-by-Pulse and Average Current Sensing • Accurate, Variable Duty Cycle Tachometer Output • Trimmed Precision Reference • Precision Oscillator The chip includes a differential current sense amplifier and absolute value circuit which provide an accurate reconstruction of motor current, useful for pulse by pulse over current protection as well as closing a current control loop. A precision tachometer is also provided for implementing closed loop speed control. The TACH_OUT signal is a variable duty cycle, frequency output which can be used directly for digital control or filtered to provide an analog feedback signal. Other features include COAST, BRAKE, and DIR_IN commands along with a direction output, DIR_OUT. • Direction Output BLOCK DIAGRAM QUAD 20 BRAKE 19 COAST 18 DIR_IN 21 HALLA 15 HALLB 16 5 VOLT REFERENCE 28 VDD 2 VREF 27 AHI 25 BHI 23 CHI 26 ALOW 24 BLOW 22 CLOW 1.75V DIRECTION SELECT HALL DECODER HALLC 17 DIR_OUT 8 PWM_NI 14 PWM_I 13 SYNCH 7 DIRECTION DETECTOR EDGE DETECTOR PWM COMPARATOR OSCILLATOR R•C S Q R Q 3 CT 6 OC_REF 12 IOUT 11 SNS_NI 9 SNS_I 10 OVER-CURRENT COMPARATOR S Q R Q ONE SHOT TACH_OUT 5 C_TACH 4 R_TACH 1 GND PWM LOGIC SENSE AMPLIFIER X5 UDG-97173 04/99 UCC2626 UCC3626 ABSOLUTE MAXIMUM RATINGS CONNECTION DIAGRAMS Supply Voltage VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15V Inputs Pins 20, 19, 18, 21, 15, 16, 17, 7, 12, 9, 10 . . . . –0.3V to VDD Pins 13, 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to 8.0V Output Current Pins 22, 23, 24, 25, 26, 27 . . . . . . . . . . . . . . . . . . . . . ±200mA Pins 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20mA Pins 3. 8, 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . –55°C to +150°C Lead Temperature (Soldering 10 Seconds). . . . . . . . . . +300°C DIL-28, SOIC-28, TSSOP-28 (Top View) N Package, DW Package, PW Package Note: Unless otherwise indicated, voltages are referenced to ground. Currents are positive into, negative out of specified terminal. Consult packaging section of Databook for thermal limitations and considerations of package. ORDERING INFORMATION UCC 626 PACKAGE TEMPERATURE RANGE TEMPERATURE RANGE UCC2626N UCC2626DW UCC2626PW UCC3626N UCC3626DW UCC3626PW –40° C to +85° C 0° C to +70° C PACKAGE DIL SOIC TSSOP DIL SOIC TSSOP GND 1 28 VDD VREF 2 27 AHI TACH_OUT 3 26 ALO R_TACH 4 25 BHI C_TACH 5 24 BLOW CT 6 23 CHI SYNCH 7 22 CLOW DIR_OUT 8 21 DIR_IN SNS_NI 9 20 QUAD SNS_I 10 19 BRAKE IOUT 11 18 COAST OC_REF 12 17 HALLC PWM_I 13 16 HALLB PWM_NI 14 15 HALLA ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for VCC = 12V; CT = 1nF, RTACH = 250K, CTACH = 100pF, TA = TJ, TA = –40°C to +85°C for the UCC2626, and 0°C to +70°C for the UCC3626. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Overall Supply Current 3 10 mA Under-Voltage Lockout Start Threshold 10.5 V UVLO Hysteresis 0.5 V 5.0 V Reference Output Voltage IVREF = –2mA Line Regulation 11V < VCC < 14.5V Load Regulation –1 > IVREF > –5mA 4.9 Short Circuit Current 5 5.1 V 10 mV 30 40 mV 120 mA Threshold 1.75 V Hysteresis 0.1 V Input Bias Current 0.1 µA Coast Input Comparator 2 UCC2626 UCC3626 ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for VCC = 12V; CT = 1nF, RTACH = 250K, CTACH = 100pF, TA = TJ, TA = –40°C to +85°C for the UCC2626, and 0°C to +70°C for the UCC3626. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Current Sense Amplifier Input Offset Voltage VCM = 0V 5 mV 5.1 V/V µA Input Bias Current VCM = 0V Gain VCM = 0V CMRR –0.3V < VCM < 0.5 60 dB PSRR 11V < VCC <14.5V 60 dB Output High Voltage IIOUT= –100µA Output Low Voltage IIOUT = 100µA Output Source Current VIOUT = 2V 10 4.9 5 5 V 50 mV µA 500 PWM Comparator Input Common Mode Range 2.0 Propogation Delay 8.0 75 V nS Over-Current Comparator Input Common Mode Range 0.0 Propogation Delay 5.0 175 V nS Logic Inputs Logic High QUAD, BRAKE, DIR Logic Low QUAD, BRAKE, DIR Input Current QUAD, BRAKE, DIR 3.5 1.5 V V 0.1 µA Hall Buffer Inputs VIL HALLA, HALLB, HALLC 1 V VIH HALLA, HALLB, HALLC 1.9 V Input Current 0V < VIN < 5V –25 µA Frequency RTACH = 250k, CT = 1nF 10 Frequency Change With Voltage 12V < VCC < 14.5V Oscillator KHz 5 % CT Peak Voltage 7.5 V CT Valley Voltage 2.5 V CT Peak-to-Valley Voltage 5.0 V SYNCH Pin Minimum Pulse Width –500 ns Tachometer VOH/VREF IOUT = –10µA 99 100 % Vol IOUT = 10µA 0 20 mV RON High IOUT = –100µA 1 kΩ RON Low IOUT = 100µA 1 kΩ Ramp Threshold, Lo 20 mV Ramp Threshold, Hi 2.52 V µA CTACH Charge Current RTACH = 49.9kΩ T-on Accuracy Note 1 –3 50 3 % DIR OUT High Level IOUT = –100µA 3.5 5.1 V DIR OUT Low Level IOUT = 100µA 0 1 V Direction Output 3 UCC2626 UCC3626 ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for VCC = 12V; CT = 1nF, RTACH = 250K, CTACH = 100pF, TA = TJ, TA = –40°C to +85°C for the UCC2626, and 0°C to +70°C for the UCC3626. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Output Section Maximum Duty Cycle Output Low Voltage IOUT = 10mA Output High Voltage IOUT = –10mA Output Low Voltage IOUT = 1mA Output High Voltage IOUT = –1mA Rise/Fall Time CI = 100pF 100 % 4.0 5.1 V 1 V 4.0 5.1 V 0.4 100 V nS Note 1: T(on) is calculated using the formula: T(on) = CTACH (VHI –VLO)/ICHARGE. This number is compared to the formula T(on) = RTACH CTACH. PIN DESCRIPTIONS AHI, BHI, CHI: Digital outputs used to control the high side switches in a three phase inverter. For specific decoding information reference Table I. DIR_OUT: DIR_OUT represents the actual direction of the rotor as decoded from the HALLA, B & C inputs. For any valid combination of HALLA, B &C inputs there are two valid transitions, one which translates to a clockwise rotation and another which translates to a counterclockwise rotation. The polarity of DIR_OUT is the same as DIR_IN while motoring, i.e. sequencing from top to bottom in Table 1. ALOW, BLOW, CLOW: Digital outputs used to control the low side switches in a three phase inverter. For specific decoding information reference Table I. BRAKE: BRAKE is a digital input which causes the device to enter brake mode. In brake mode all three high side outputs are turned off, AHI, BHI & CHI, while all three lowside outputs are turned on, ALOW, BLOW, CLOW. During brake mode the tachometer output remains operational. The only conditions which can inhibit the low side commands during brake are UVLO, exceeding peak current, the output of the PWM comparator, or the COAST command. GND: GND is the reference ground for all functions of the part. Bypass and timing capacitors should be terminated as close to this point as possible. HALLA, HALLB, HALLC: These three inputs are designed to accept rotor position information positioned 120° apart. For specific decode information reference Table I. These inputs should be externally pulled-up to VREF or another appropriate external supply. COAST: The COAST input consists of a hysteretic comparator which disables the outputs. The input is useful in implementing an overvoltage bus clamp in four quadrant applications. The outputs will be disabled when the input is above 1.75V. IOUT: IOUT represents the output of the current sense and absolute value amplifiers. The output signal appearing is a representation of the following expression: IOUT = ABS (ISENS _ I − ISENS _ NI ) • 5 CT: This pin is used in conjunction with the R_TACH pin to set the frequency of the oscillator. A timing capacitor is normally connected between this point and ground and is alternately charged and discharged between 2.5V and 7.5V. This output can be used to close a current control loop as well as provide additional filtering of the current sense signal. OC_REF: OC_REF is an analog input which sets the trip voltage of the overcurrent comparator. The sense input of the comparator is internally connected to the output of the current sense amplifier and absolute value circuit. C_TACH: A timing capacitor is connected between this pin and ground to set the width of the TACH_OUT pulse. The capacitor is charged with a current set by the resistor on pin RT. PWM_NI: PWM_NI is the noninverting input to the PWM comparator. DIR_IN: DIR_IN is a digital input which determines the order in which the HALLA,B & C inputs are decoded. For specific decode information reference Table I. PWM_I: PWM_I is the inverting input to the PWM comparator. 4 UCC2626 UCC3626 PIN DESCRIPTIONS (cont.) QUAD: The QUAD input selects between “two” QUAD = 0 and “four” QUAD = 1 quadrant operation. When in “two-quadrant” mode only the low side devices are effected by the output of the PWM comparator. In “four-quadrant” mode both high and low side devices are controlled by the PWM comparator. TACH_OUT: TACH_OUT is the output of a monostable triggered by a change in the commutation state, thus providing a variable duty cycle, frequency output. The on-time of the monostable is set by the timing capacitor connected to C_TACH. The monostable is capable of being retriggered if a commutation occurs during it's on-time. SYNCH: The SYNCH input is used to synchronize the PWM oscillator with an external digital clock. When using the SYNCH feature, a resistor equal to RTACH must be placed in parallel with CT. When not used, ground SYNCH. R_TACH: A resistor connected between R_TACH and ground programs the current for both the oscillator and tachometer. VDD: VDD is the input supply connection for this device. Undervoltage lockout keeps the outputs off for inputs below 10.5V. The input should be bypassed with a 0.1µF ceramic capacitor, minimum. SNS_NI, SNS_I: These inputs are the noninverting and inverting inputs to the current sense amplifier, respectively. The integrated amplifier is configured for a gain of five. An absolute value function is also incorporated into the output in order to provide a representation of actual motor current when operating in four quadrant mode. VREF: VREF is a 5V, 2% trimmed reference output with 5mA of maximum available output current. This pin should be bypassed to ground with a 0.1µF ceramic capacitor, minimum. APPLICATION INFORMATION Table 1 provides the decode logic for the six outputs, AHI, BHI, CHI, ALOW, BLOW, and CLOW as a function of the BRAKE, COAST, DIR_IN, HALLA, HALLB, and HALLC inputs. signals are never simultaneously high or low. Motor's whose sensors provide 60° encoding can be converted to 120° using the circuit shown in Fig. 1. In order to prevent noise from commanding improper commutation states, some form of low pass filtering on HALLA, HALLB, and HALLC is recommended. Passive The UCC3626 is designed to operate with 120° position sensor encoding. In this format, the three position sensor Table 1. Commutation truth table. B R A K E 0 0 0 0 0 0 0 0 0 0 0 0 X 1 0 0 C O A S T 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 D I R _ IN 1 1 1 1 1 1 0 0 0 0 0 0 X X X X HALL INPUTS HIGH SIDE OUTPUTS VREF LOW SIDE OUTPUTS 1kΩ 499Ω A B C A B C A B C 1 1 1 0 0 0 1 0 0 0 1 1 X X 1 0 0 0 1 1 1 0 0 0 1 1 1 0 X X 1 0 1 0 0 0 1 1 1 1 1 0 0 0 X X 1 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 1 0 0 HALLB HALLA VREF 2.2nF 1kΩ 1kΩ HALLA 2N2222A HALLB 2.2nF VREF 1kΩ 499Ω HALLC HALLC 2.2nF Figure 1. Circuit to convert 60° hall code to 120° code. 5 UCC2626 UCC3626 APPLICATION INFORMATION (cont.) VREF 1kΩ 499Ω SYNCH HALLA HALLA 2.2nF WITHOUT SYNCH VREF 1kΩ 499Ω CT HALLB HALLB WITH SYNCH 2.2nF VREF Figure 3. Synchronized and unsynchronized oscillator waveforms. 1kΩ 499Ω HALLC HALLC 1.E+06 2.2nF PWM FREQUENCY (Hz) R_TACH = 25k Figure 2. Passive hall filtering technique. RC networks generally work well and should be located as close to the IC as possible. Fig. 2 illustrates these techniques. R_TACH = 100k 1.E+05 R_TACH = 250k 1.E+04 Configuring the Oscillator R_TACH = 500k The UCC3626 oscillator is designed to operate at frequencies up to 250kHz and provide a triangle waveform on CT with a peak to peak amplitude of 5V for improved noise immunity. The current used to program CT is derived off of the R_TACH resistor according to the following equation: IOSC = 1.E+03 1.E-10 1.E-09 1.E-08 1.E-07 CT (F) Figure 4. PWM oscillator frequency vs. CT and R_TACH. 25 Amps R _ TACH switching current spikes in the local ground from causing jitter in the oscillator. Synchronizing the Oscillator Oscillator frequency is set by R_TACH and CT according to the following relationship: A common system specification is for all oscillators in a design to be synchronized to a master clock. The UCC3626 provides a SYNCH input for exactly this purpose. The SYNCH input is designed to interface with a digital clock pulse generated by the master oscillator. A positive going edge on this input causes the UCC3626 oscillator to begin discharging. In order for the slave oscillator to function properly it must be programmed for a frequency slightly lower than that of the master. Also, a resistor equal to RTACH must be placed in parallel with CT. Fig. 3 illustrates the waveforms for a slave oscillator programmed to 20kHz with a master frequency of 30kHz. The SYNCH pin should be grounded when not used. 2 .5 Frequency = Hz (R _ TACH • CT ) Timing resistor values should be between 25kΩ and 500kΩ while capacitor values should fall between 100pF and 1µF. Fig. 4 provides a graph of oscillator frequency for various combinations of timing components. As with any high frequency oscillator, timing components should be located as close to the IC pins as possible when laying out the printed circuit board. It is also important to reference the timing capacitor directly to the ground pin on the UCC3626 rather than daisy chaining it to another trace or the ground plane. This technique prevents 6 UCC2626 UCC3626 APPLICATION INFORMATION (cont.) Programming the Tachometer 1.E+00 The UCC3626 tachometer consists of a precision, 5V monostable, triggered by either a rising or falling edge on any of the three Hall inputs, HALLA, HALLB, HALLC. The resulting TACH_OUT waveform is a variable dutycycle square wave whose frequency is proportional to motor speed, as given by: 1.E-01 R_TACH = 250k 1.E-02 R_TACH = 500k Ton (sec) (V • P ) TACH _ OUT = Hz 20 where P is the number of motor pole pairs and V is motor velocity in RPM. R_TACH = 100k 1.E-04 The on-time of the monostable is programmed via timing resistor R_TACH and capacitor C_TACH according to the following equation: R_TACH = 25k 1.E-05 On − Time = R _ TACH • C _ TACH sec 1.E-06 Fig. 5 provides a graph of On-Time for various combinations of R_TACH and C_TACH. On-Time is typically set to a value less than the minimum TACH-OUT period as given by: T _ Period MIN = 1.E-03 1.E-10 1.E-09 1.E-08 Ctach (F) 1.E-07 1.E-06 Figure 5. Tachometer on-time vs. C_TACH and R_TACH. 20 sec VMAX • P The TACH_OUT signal can be used to close a digital velocity loop using a microcontroller, as shown in Fig. 6, or directly low pass filtered in an analog implementation, Fig. 7. where P is the number of motor pole pairs and V is motor velocity in RPM. UCC3626 MC68HC11 PB0 – PB7 PC0 AD558 DB0 – DB7 VCE VCS VOUT 4 R_TACH 5 C_TACH 6 CT 14 PWM_NI 13 PWM_I 3 TACH_OUT VOUTSENSE VOUTSELECT IC1 UDG-97188 Figure 6. Digital velocity loop implementation using MC68HC11. 7 UCC2626 UCC3626 APPLICATION INFORMATION (cont.) When configured for two quadrant operation, (QUAD=0), the UCC3626 will only modulate the low side devices of the output power stage. The current paths within the output stage during the PWM on and off times are illustrated in Fig. 9. During the 'on' interval, both switches are on and current flows through the load down to ground. During the 'off' time, the lower switch is shut off and the motor current circulates through the upper half bridge via the flyback diode. The motor is assumed to be operating in either quadrant I or III. Two Quadrant vs Four Quadrant Control Fig. 8 illustrates the four possible quadrants of operation for a motor. Two quadrant control refers to a system whose operation is limited to quadrants I and III where torque and velocity are in the same direction. With a two quadrant brushless DC amplifier, there are no provisions other than friction to decelerate the load, limiting the approach to less demanding applications. Four quadrant controllers, on the other hand, provide controlled operation in all quadrants, including II and IV, where torque and rotation are of opposite direction. VMOT S3 S1 S5 IOFF IPHASE UCC3626 2 VREF 4 R_TACH 5 C_TACH 6 CT 14 PWM_NI 13 PWM_I 3 TACH_OUT + BEMF ION – + S4 S2 S6 Figure 9. Two quadrant chopping. UDG-97189 VMOT Figure 7. Simple analog velocity loop. S3 S1 S5 IOFF VELOCITY CW IPHASE + BEMF - II I TORQUE CW CCW III ION S2 IV S4 CCW Figure 8. Four quadrants of operation. Figure 10. Two quadrant reversal. 8 S6 UCC2626 UCC3626 APPLICATION INFORMATION (cont.) waveforms for both two and four quadrant operation are illustrated in Fig. 12. VMOT Power Stage Design Considerations S3 S1 S5 The flexible architecture of the UCC3626 requires the user to pay close attention to the design of the power output stage. Two and Four Quadrant applications that do not require the brake function are able to utilize the power stage approach illustrated in Fig. 13A. In many cases the body diode of the MOSFET can be utilized to reduce parts count and cost. If efficiency is a key requirement, Schottky diodes can be used in parallel with the switches. IPHASE + BEMF IOFF ION S2 S4 S6 If the system requires a braking function, diodes must be added in series with the lower power devices and the lower flyback diodes returned to ground, as pictured in Fig. 13B,C. This requirement prevents brake currents from circulating in the lower half bridge and bypassing the sense resistor. In addition, the combination of braking and four quadrant control necessitates an additional resistor in the diode path to sense current during the PWM 'off' time as illustrated in Fig. 13C. Figure 11. Four quadrant reversal. If one attempts to operate in quadrants II or IV by changing the DIR bit and reversing the torque, switches 1 and 4 are turned off and switches 2 and 3 turned on. Under this condition motor current will very quickly decay, reverse direction and increase until the control threshold is reached. At this point switch 2 will turn off and current will once again circulate in the upper half bridge, however, in this case the motor's BEMF is in phase with the current, i.e. the motor's direction of rotation has not yet changed. Fig. 10 illustrates the current paths when operating in this mode. Under these conditions there is nothing to limit the current other than motor and drive impedance. These high circulating currents can result in damage to the power devices in addition to high, uncontrolled torque. Current Sensing The UCC3626 includes a differential current sense amplifier with a fixed gain of five, along with an absolute value circuit. The current sense signal should be low pass filtered to eliminate leading edge spikes. In order to maximize performance, the input impedance of the amplifier should be balanced. If the sense voltage must be trimmed for accuracy reasons, a low value input divider or a differential divider should be used to maintain impedance matching, as shown in Fig. 14. With four quadrant chopping motor current always flows through the sense resistor. However, during the flyback period the polarity across the sense resistor is reversed. The absolute value amplifier cancels the polarity reversal by inverting the negative sense signal during the flyback time, see Fig. 15. Therefore, the output of the absolute value amplifier is a reconstructed analog of the motor current, suitable for protection as well as feedback loop closure. By pulse width modulating both the upper and lower power devices (QUAD=1), motor current will always decay during the PWM “off” time, eliminating any uncontrolled circulating currents. In addition, current will always flow through the current sense resistor, thus providing a suitable feedback signal. Fig. 11 illustrates the current paths during a four quadrant torque reversal. Motor drive 9 UCC2626 UCC3626 APPLICATION INFORMATION (cont.) ROTOR POSITION IN ELECTRICAL DEGREES 0 60 120 180 240 300 360 420 480 540 600 660 720 H1 SENSOR INPUTS H2 H3 Code 101 100 110 010 011 001 101 100 110 010 011 001 AHI HIGH SIDE OUTPUTS QUAD=0 BHI CHI ALO LOW SIDE OUTPUTS QUAD=0 BLO CLO + A 0 + MOTOR PHASE CURRENTS B QUAD=0 0 + C 0 AHI HIGH SIDE OUTPUTS QUAD=1 BHI CHI ALO LOW SIDE OUTPUTS QUAD=1 BLO CLO + A 0 - MOTOR PHASE CURRENTS B QUAD=1 + 0 + C 0 100% Duty Cycle PWM 50% Duty Cycle PWM UDG-97190 Figure 12. Motor drive and current waveforms for 2 quadrant (QUAD=0) and 4 quadrant (QUAD=1) operation. 10 UCC2626 UCC3626 TYPICAL APPLICATIONS VMOT VMOT VMOT TO MOTOR CURRENT SENSE TO MOTOR CURRENT SENSE CURRENT SENSE (a) (a) (b) (c) TO MOTOR (b) (c) TWO QUADRANT FOUR QUADRANT SAFE BRAKING POWER REVERSAL Yes Yes Yes Yes No Yes No Yes Yes In 4-Quad Only No In 4-Quad Only CURRENT SENSE PULSE BY AVERAGE PULSE Yes Yes Yes No Yes Yes Figure 13. Power stage topologies. Fig. 16 illustrates a simple 175V, 2A two quadrant velocity controller using the UCC3626. The power stage is designed to operate with a rectified off-line supply using IR2210s to provide the interface between the low voltage control signals and the power MOSFETs. The power topology illustrated in Fig. 13C is implemented in order to provide braking capability. The controller's speed command is set by potentiometer R30 while the speed feedback signal is obtained by low pass filtering and buffering the TACH-OUT signal using R11 and C9. Small signal compensation of the velocity control loop is provided by amplifier U5A, whose output is used to control the PWM duty cycle. The integrating capacitor, C8, places a pole at 0Hz and a zero in conjunction with R10. This zero can be used to cancel the low frequency motor pole and cross the loop over with a –20dB gain response. 11 Four quadrant applications require the control of motor current. Fig. 17 illustrates a sign/magnitude current control loop within an outer bipolar velocity loop using the UCC3626. U1 serves as the velocity loop error amplifier and accepts a +/-5V command signal. Velocity feedback is provided by low pass filtering and scaling the TACH_OUT signal using U2. The direction output, DIR_OUT, switch and U3 set the polarity of the tachometer gain according to the direction of rotation. The output of the velocity error amplifier, U1, is then converted to sign/magnitude form using U5 and U6. The sign portion is used to drive the DIR input while the magnitude commands the current error amplifier, U8. Current feedback is provided by the internal current sense amplifier via the IOUT pin. UCC2626 UCC3626 TYPICAL APPLICATION (cont.) RF RADJ Rs RF SNS_NI SNS_NI RF RADJ Rs CF CF RF RF SNS_I SNS_I RADJ << RF (a) (b) Figure 14. (a) Differential divider and (b) low value divider. VMOT Ip S3 S1 Is S5 IPHASE Ip If + BEMF - IOFF 5*Ip ION S2 S4 S6 Im Is X5 Im If Figure 15. Current sense amplifier waveform. 12 Figure 16. Two quadrant velocity controller. 13 VREF R30 10K FROM HALL SENSORS R10 R29 C7 C5 2200pF R5 499 R2 1k Speed Set R6 499 R1 1k U5A 1/2 LM358 C8 R7 10k C2 0.1µF VREF U5B 1/2 LM358 C6 100pF R9 10k C3 2200pF C1 0.1µF R8 10k VREF C4 2200pF R4 499 R3 1k VREF 13 PWM_I 14 PWM_NI C9 0.1µF R14 15k R13 35k VREF R12 250k TACH_OUT RTACH 3 4 C10 3900pF CT 6 5 OC_REF 12 CTACH DIR_OUT SYNCH 8 7 IOUT 11 18 COAST SNS_I 10 19 BRAKE 9 CLOW 22 SNS_NI 21 DIR_IN 20 QUAD 17 HALLC BLOW 24 16 HALLB CHI 23 BHI 25 AHI 27 ALOW 26 GND 1 UCC3626 U1 15 HALLA VREF 2 28 VDD R11 160k +12V C17 0.1µF C23 0.01µF VREF C14 0.1µF VREF C11 0.1µF VREF R31 2k R30 2k 13 VSS COM LO VCC 11 SD 14 NC NC 12 LIN 10 HIN VS HO 8 NC IR2110 VDD VB COM LO 9 U4 13 VSS 14 NC VCC 11 SD VS NC HO NC 8 10 HIN 12 LIN IR2110 VB VDD 9 U3 COM LO 14 NC 13 VSS VCC 11 SD NC VS 10 HIN 12 LIN HO IR2110 VDD VB NC 8 9 U2 2 1 3 4 5 7 6 2 1 3 4 5 7 6 2 1 3 4 5 7 6 C19 0.1µF C18 0.1µF C16 0.1µF C15 0.1µF C13 0.1µF C12 0.1µF R25 10 D3 1N5818 R26 47 D6 1N5818 R24 47 D5 1N5818 R22 47 D4 1N5818 R20 47 D18 11DF4 +12V R23 10 R21 10 D2 1N4148 R18 47 D17 11DF4 +12V R19 10 R17 10 D1 1N4148 R16 47 D16 11DF4 +12V R15 10 R27 0.1 Q6 IRF730 D13 1N5821 Q5 IRF730 VMOT Q4 IRF730 D10 1N5821 Q3 IRF730 VMOT Q2 IRF730 D7 1N5821 Q1 IRF730 VMOT R28 0.1 D15 1N5418 MOTOR PHASE A C20 10µF D11 1N5418 MOTOR PHASE A C21 10µF D8 1N5418 MOTOR PHASE A C22 10µF TYPICAL APPLICATIONS (cont.) UCC2626 UCC3626 UDG-97184 UCC2626 UCC3626 TYPICAL APPLICATIONS (cont.) SIGN/MAGNITUDE CONVERTER 10k VELOCITY COMMAND +/– 5V 10k – U1 + 10k 11 IOUT 13 PWM_I 21 DIR 3 TACH_OUT 8 DIR_OUT 10k – U5 + – U6 + 10k – U8 + CURRENT MAGNITUDE CURRENT ERROR AMPLIFIER U7 CURRENT SIGN BIPOLAR 10k TACH GAIN 10k – + U3 4.99k 4.99k – U2 + TACHOMETER FILTER 2N7002 UDG-99061 Figure 17. Four quadrant control loop. UNITRODE CORPORATION 7 CONTINENTAL BLVD. • MERRIMACK, NH 03054 TEL. (603) 424-2410 • FAX (603) 424-3460 14 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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