® SP3249E Intelligent +3.0V to +5.5V RS-232 Transceivers ■ Meets true EIA/TIA-232-F Standards from a +3.0V to +5.5V power supply ■ Interoperable with EIA/TIA-232 and adheres to EIA/TIA-562 down to a +2.7V power source ■ Minimum 250Kbps data rate under load ■ Regulated Charge Pump Yields Stable RS-232 Outputs Regardless of VCC Variations ■ Enhanced ESD Specifications: +15KV Human Body Model +15KV IEC1000-4-2 Air Discharge +8KV IEC1000-4-2 Contact Discharge DESCRIPTION The SP3249E device is an RS-232 transceiver solution intended for portable or hand-held applications such as notebook and palmtop computers. The SP3249E uses an internal high-efficiency, charge-pump power supply that requires only 0.1µF capacitors in 3.3V operation. This charge pump and Sipex's driver architecture allow the SP3249E device to deliver compliant RS-232 performance from a single power supply ranging from +3.0V to +5.0V. The SP3249E is a 5-driver/3-receiver device, ideal for laptop/notebook computer and PDA applications. SELECTION TABLE Part Number Power Supplies RS-232 Drivers RS-232 Receivers External Components AUTO ON-LINE™ Circuitry TTL 3-State Number of Pins SP3223E +3.0V to +5.5V 2 2 4 capacitors YES YES 20 SP3243E +3.0V to +5.5V 3 5 4 capacitors YES YES 28 SP3238E +3.0V to +5.5V 5 3 4 capacitors YES YES 28 SP3239E +3.0V to +5.5V 5 3 4 capacitors NO YES 28 SP3249E +3.0V to +5.5V 5 3 4 capacitors NO NO 24 Applicable U.S. Patents - 5,306,954; and other patents pending. Rev.4/08/02 SP3249E Intelligent +3.0V to +5.5V RS-232 Transceivers 1 © Copyright 2002 Sipex Corporation ABSOLUTE MAXIMUM RATINGS Input Voltages TxIN ...................................................-0.3V to +6.0V RxIN...................................................................+25V Output Voltages TxOUT.............................................................+13.2V RxOUT,......................................-0.3V to (VCC + 0.3V) Short-Circuit Duration TxOUT.....................................................Continuous Storage Temperature......................-65°C to +150°C These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability and cause permanent damage to the device. VCC.......................................................-0.3V to +6.0V V+ (NOTE 1).......................................-0.3V to +7.0V V- (NOTE 1)........................................+0.3V to -7.0V V+ + |V-| (NOTE 1)...........................................+13V ICC (DC VCC or GND current).........................+100mA Note 1: V+ and V- can have maximum magnitudes of 7V, but their absolute difference cannot exceed 13V. SPECIFICATIONS VCC = +3.0 to +5.5, C1 -C4 = 0.1µF (tested at 3.3V + 5%), C1-C4 = 0.22µF (tested at 3.3V + 10%), C1 = 0.047µF, and C2-C4 = 0.33µF (tested at 5.0V + 10%), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER MIN. Supply Current TYP. MAX. UNITS CONDITIONS 0.3 1.0 mA 0.8 V V VCC = +3.3V or +5.0V, TxIN VCC = +3.3V or +5.0V, TxIN ±1.0 µA TxIN, TA = 25°C 0.4 VCC, no load LOGIC INPUTS AND RECEIVER OUTPUTS Input Logic Threshold LOW HIGH 2.4 ±0.01 Input Leakage Current Output Voltage LOW V IOUT = 1.6mA VCC - 0.6 VCC - 0.1 V IOUT = -1.0mA Output Voltage Swing ±5.0 ±5.4 V All driver outputs loaded with 3KΩ to GND Output Resistance 300 Ω VCC = V+ = V- = 0V, VOUT = ±2V Output Voltage HIGH DRIVER OUTPUTS ±35 Output Short-Circuit Current ±60 mA 25 V VOUT = GND RECEIVER INPUTS Input Voltage Range -25 Input Threshold LOW 0.6 Input Threshold LOW 0.8 1.2 V V VCC = 5.0V Input Threshold HIGH 1.5 2.4 V VCC = 3.3V Input Threshold HIGH 1.8 2.4 V VCC = 5.0V 7 kΩ Input Hysteresis Input Resistance Rev.4/08/02 1.5 VCC = 3.3V 0.5 3 V 5 SP3249E Intelligent +3.0V to +5.5V RS-232 Transceivers 2 © Copyright 2002 Sipex Corporation SPECIFICATIONS VCC = +3.0 to +5.5, C1 -C4 = 0.1µF (tested at 3.3V + 5%), C1-C4 = 0.22µF (tested at 3.3V + 10%), C1 = 0.047µF, and C2-C4 = 0.33µF (tested at 5.0V + 10%), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER MIN. TYP. MAX. UNITS CONDITIONS TIMING CHARACTERISTICS Maximum Data Rate 250 kbps RL = 3kΩ, CL = 1000pF, one driver switching Receiver Propagation Delay tPHL 0.15 µs tPLH 0.15 µs Receiver input to receiver output, CL = 150pF Receiver input to receiver output, CL = 150pF Receiver Output Enable Time 200 ns Normal operation Receiver Output Disable Time 200 ns Normal operation Driver Skew 100 ns I tPLH - tPLH I,TA = 25°C Receiver Skew 50 ns Transition-Region Slew Rate 30 I tPLH - tPLH I V/µs VCC = 3.3V, RL = 3kΩ, TAMB =25°C, measurements taken from -3.0V to +3.0V or +3.0V to -3.0V TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise noted, the following performance characteristics apply for VCC = +3.3V, 250kbps data rate, all drivers loaded with 3kΩ, 0.1µF charge pump capacitors, and TAMB = +25°C. SLEW RATE vs. LOAD CAPACITANCE TRANSMITTER OUTPUT vs. LOAD CAPACITANCE 6 25 4 20 2 15 VOH VOL 0 -2 0 1000 2000 3000 4000 5000 POS. SR NEG SR 10 5 -4 0 0 -6 1000 2000 3000 4000 5000 pF pF Figure 2. Slew Rate vs. Load Capacitance Figure 1. Transmitter Output vs. Load Capacitance SUPPLY CURRENT vs LOAD CAPACITANCE 60 50 40 250Kbps 120Kbps 20Kbps 30 20 10 0 0 1000 2000 3000 4000 5000 pF Figure 3. Supply Current vs. Load Capacitance when Transmitting Data Rev.4/08/02 SP3249E Intelligent +3.0V to +5.5V RS-232 Transceivers 3 © Copyright 2002 Sipex Corporation PIN DESCRIPTION NAME FUNCTION PIN NO. C2+ Positive terminal of the inverting charge-pump capacitor. 1 GND Ground. 2 C2- Negative terminal of the inverting charge-pump capacitor. 3 V- Regulated -5.5V output generated by the charge pump. 4 T1OUT RS-232 driver output. 5 T2OUT RS-232 driver output. 6 T3OUT RS-232 driver output. 7 R1IN RS-232 receiver input. 8 R2IN RS-232 receiver input. 9 T4OUT RS-232 driver output. 10 R3IN RS-232 receiver input. 11 T5OUT RS-232 driver output. 12 TTL/CMOS driver input. 13 TTL/CMOS receiver output. 14 TTL/CMOS driver input. 15 R2OUT TTL/CMOS receiver output. 16 R1OUT TTL/CMOS receiver output. 17 T3IN TTL/CMOS driver input. 18 T2IN TTL/CMOS driver input. 19 T1IN TTL/CMOS driver input. 20 C1- Negative terminal of the voltage doubler charge-pump capacitor. 21 VCC +3.0V to +5.5V supply voltage. 22 V+ Regulated +5.5V output generated by the charge pump. 23 C1+ Positive terminal of the voltage doubler charge-pump capacitor. 24 T5IN R3OUT T4IN Table 1. Device Pin Description Rev.4/08/02 SP3249E Intelligent +3.0V to +5.5V RS-232 Transceivers 4 © Copyright 2002 Sipex Corporation C2+ 1 24 C1+ GND 2 23 V+ C2- 3 22 VCC V- 4 21 C1- T1OUT 5 T2OUT 6 20 T1IN SP3249E 19 T2IN T3OUT 7 18 T3IN R1IN 8 17 R2IN 9 16 R2OUT T4OUT 10 R1OUT 15 T4IN R3IN 11 14 T5OUT 12 R3OUT 13 T5IN Figure 4. SP3249E Pinout Configuration C5 C1 + + VCC 22 0.1µF VCC 24 C1+ V+ 23 0.1µF C3 + 0.1µF 21 C11 C2+ C2 TTL/CMOS INPUTS + SP3249E 4 C4 0.1µF 3 C220 T1IN T1OUT 5 19 T2IN T2OUT 6 18 T3IN T3OUT 7 15 T4IN T4OUT 10 13 T5IN T5OUT 12 17 R1OUT TTL/CMOS OUTPUTS V- R1IN 8 R2IN 9 R3IN 11 + 0.1µF RS-232 OUTPUTS 5kΩ 16 R2OUT 5kΩ 14 R3OUT RS-232 INPUTS 5kΩ GND 2 Figure 5. SP3249E Typical Operating Circuit Rev.4/08/02 SP3249E Intelligent +3.0V to +5.5V RS-232 Transceivers 5 © Copyright 2002 Sipex Corporation DESCRIPTION output voltage swing is +5.4V with no load and +5V minimum fully loaded. The driver outputs are protected against infinite short-circuits to ground without degradation in reliability. These drivers comply with the EIA-TIA-232F and all previous RS-232 versions. Unused driver inputs should be connected to GND or VCC. The SP3249E device meets the EIA/TIA-232 and ITU-T V.28/V.24 communication protocols and can be implemented in battery-powered, portable, or hand-held applications such as notebook or palmtop computers. The SP3249E device features Sipex's proprietary and patented (U.S. #5,306,954) on-board charge pump circuitry that generates ±5.5V RS-232 voltage levels from a single +3.0V to +5.5V power supply. The SP3249E device can operate at a data rate of 250kbps fully loaded. The drivers can guarantee a data rate of 250kbps fully loaded with 3kΩ in parallel with 1000pF, ensuring compatibility with PC-to-PC communication software. The slew rate of the driver output is internally limited to a maximum of 30V/µs in order to meet the EIA standards (EIA RS-232D 2.1.7, Paragraph 5). The transition of the loaded output from HIGH to LOW also meets the monotonicity requirements of the standard. The SP3249E is a 5-driver/3-receiver device, ideal for portable or hand-held applications. The SP3249E device is an ideal choice for power sensitive designs. THEORY OF OPERATION The SP3249E device is made up of three basic circuit blocks: 1. Drivers, 2. Receivers, and 3. the Sipex proprietary charge pump. Figure 7 shows a loopback test circuit used to test the RS-232 Drivers. Figure 8 shows the test results of the loopback circuit with all five drivers active at 120kbps with typical RS-232 loads in parallel with 1000pF capacitors. Figure 6 shows the test results where one driver was active at 250kbps and all five drivers loaded with an RS232 receiver in parallel with a 1000pF capacitor. A solid RS-232 data transmission rate of 120kbps provides compatibility with many designs in personal computer peripherals and LAN applications. Drivers The drivers are inverting level transmitters that convert TTL or CMOS logic levels to 5.0V EIA/ TIA-232 levels with an inverted sense relative to the input logic levels. Typically, the RS-232 VCC C5 C1 + + 22 0.1µF VCC 24 C1+ 0.1µF 1 C2+ C2 UART or Serial µC + 0.1µF V+ 23 C3 21 C1- SP3249E 0.1µF Receivers V- 4 C4 3 C2- RxD 20 T1IN T1OUT 5 CTS 19 T2IN T2OUT 6 DSR 18 T3IN T3OUT 7 DCD 15 T4IN T4OUT 10 RI 13 T5IN T5OUT 12 TxD + + 0.1µF The receivers convert ±5.0V EIA/TIA-232 levels to TTL or CMOS logic output levels. RS-232 OUTPUTS Since receiver input is usually from a transmission line where long cable lengths and system interference can degrade the signal, the inputs have a typical hysteresis margin of 500mV. This ensures that the receiver is virtually immune to noisy transmission lines. Should an input be left unconnected, an internal 5kΩ pulldown resistor to ground will commit the output of the receiver to a HIGH state. R1IN 8 17 R1OUT 5kΩ RTS 16 R2OUT DTR 14 R3OUT R2IN 9 5kΩ RS-232 INPUTS R3IN 11 5kΩ GND 2 Figure 6. Interface Circuitry Controlled by Microprocessor Supervisory Circuit Rev.4/08/02 SP3249E Intelligent +3.0V to +5.5V RS-232 Transceivers 6 © Copyright 2002 Sipex Corporation Charge Pump VCC The charge pump is a Sipex–patented design (U.S. #5,306,954) and uses a unique approach compared to older less–efficient designs. The charge pump still requires four external capacitors, but uses a four–phase voltage shifting technique to attain symmetrical 5.5V power supplies. The internal power supply consists of a regulated dual charge pump that provides output voltages 5.5V regardless of the input voltage (VCC) over the +3.0V to +5.5V range. This is important to maintain compliant RS-232 levels regardless of power supply fluctuations. C5 C1 + + 0.1µF VCC C1+ V+ 0.1µF C3 + 0.1µF C1C2+ C2 + SP3249E VC4 0.1µF C2- LOGIC INPUTS LOGIC OUTPUTS + 0.1µF TxOUT TxIN RxOUT RxIN 1000pF 5kΩ GND The charge pump operates in a discontinuous mode using an internal oscillator. If the output voltages are less than a magnitude of 5.5V, the charge pump is enabled. If the output voltages exceed a magnitude of 5.5V, the charge pump is disabled. This oscillator controls the four phases of the voltage shifting (Figure 13). A description of each phase follows. Figure 7. Loopback Test Circuit for RS-232 Driver Data Transmission Rates Phase 2 (Figure 12) — VSS transfer — Phase two of the clock connects the negative terminal of C2 to the VSS storage capacitor and the positive terminal of C2 to GND. This transfers a negative generated voltage to C 3 . This generated voltage is regulated to a minimum voltage of -5.5V. Simultaneous with the transfer of the voltage to C3, the positive side of capacitor C1 is switched to VCC and the negative side is connected to GND. Phase 1 (Figure 11) — VSS charge storage — During this phase of the clock cycle, the positive side of capacitors C1 and C2 are initially charged to VCC. Cl+ is then switched to GND and the charge in C1– is transferred to C2–. Since C2+ is connected to VCC, the voltage potential across capacitor C2 is now 2 times VCC. Phase 3 (Figure 14) Figure 8. Loopback Test Circuit Result at 120kbps (All Drivers Fully Loaded) Rev.4/08/02 Figure 9. Loopback Test Circuit result at 250kbps (All Drivers Fully Loaded) SP3249E Intelligent +3.0V to +5.5V RS-232 Transceivers 7 © Copyright 2002 Sipex Corporation allowing the charge pump cycle to begin again. The charge pump cycle will continue as long as the operational conditions for the internal oscillator are present. — VDD charge storage — The third phase of the clock is identical to the first phase — the charge transferred in C1 produces –VCC in the negative terminal of C1, which is applied to the negative side of capacitor C2. Since C2+ is at VCC, the voltage potential across C2 is 2 times VCC. Since both V+ and V– are separately generated from VCC, in a no–load condition V+ and V– will be symmetrical. Older charge pump approaches that generate V– from V+ will show a decrease in the magnitude of V– compared to V+ due to the inherent inefficiencies in the design. Phase 4 (Figure 15) — VDD transfer — The fourth phase of the clock connects the negative terminal of C2 to GND, and transfers this positive generated voltage across C2 to C4, the VDD storage capacitor. This voltage is regulated to +5.5V. At this voltage, the internal oscillator is disabled. Simultaneous with the transfer of the voltage to C4, the positive side of capacitor C1 is switched to VCC and the negative side is connected to GND, The clock rate for the charge pump typically operates at 500kHz. The external capacitors can be as low as 0.1µF with a 16V breakdown voltage rating. VCC = +5V C4 +5V C1 + – C2 –5V + – – + VDD Storage Capacitor + – VSS Storage Capacitor C3 –5V Figure 10. Charge Pump — Phase 1 VCC = +5V C4 C1 + C2 – + – – + + – VDD Storage Capacitor VSS Storage Capacitor C3 –10V Figure 11. Charge Pump — Phase 2 [ T ] +6V a) C2+ 1 2 T 2 0V 0V b) C2T -6V Ch1 2.00V Ch2 2.00V M 1.00µs Ch1 1.96V Figure 12. Charge Pump Waveforms Rev.4/08/02 SP3249E Intelligent +3.0V to +5.5V RS-232 Transceivers 8 © Copyright 2002 Sipex Corporation VCC = +5V C4 +5V + C1 C2 – –5V + – – + + – VDD Storage Capacitor VSS Storage Capacitor C3 –5V Figure 13. Charge Pump — Phase 3 VCC = +5V C4 +10V C1 + C2 – + – – + VDD Storage Capacitor + – VSS Storage Capacitor C3 Figure 14. Charge Pump — Phase 4 VCC C5 + 22 VCC 0.1µF 24 C1 + C1+ 0.1µF 21 C11 + C2 C2+ V+ C3 SP3249E 0.1µF 3 23 V- C2- + 4 0.1µF C4 R1IN 8 R2IN 9 R3IN 11 20 T1IN T1OUT 5 19 T2IN T2OUT 6 18 T3IN T3OUT 7 15 T4IN T4OUT 10 13 T5IN T5OUT 12 17 R1OUT 0.1µF + 5kΩ 16 R2OUT 5kΩ 14 R3OUT 5kΩ 6 7 8 9 GND 2 DB-9 Connector Pins: 1. Received Line Signal Detector 2. Received Data 3. Transmitted Data 4. Data Terminal Ready 5. Signal Ground (Common) DB-9 Connector 6. 7. 8. 9. 1 2 3 4 5 DCE Ready Request to Send Clear to Send Ring Indicator Figure 15. Circuit for the connectivity of the SP3249E with a DB-9 connector Rev.4/08/02 SP3249E Intelligent +3.0V to +5.5V RS-232 Transceivers 9 © Copyright 2002 Sipex Corporation normal usage. The transceiver IC receives most of the ESD current when the ESD source is applied to the connector pins. The test circuit for IEC1000-4-2 is shown on Figure 20. There are two methods within IEC1000-4-2, the Air Discharge method and the Contact Discharge method. ESD TOLERANCE The SP3249E device incorporates ruggedized ESD cells on all driver output and receiver input pins. The ESD structure is improved over our previous family for more rugged applications and environments sensitive to electrostatic discharges and associated transients. The improved ESD tolerance is at least +15kV without damage nor latch-up. With the Air Discharge Method, an ESD voltage is applied to the equipment under test (EUT) through air. This simulates an electrically charged person ready to connect a cable onto the rear of the system only to find an unpleasant zap just before the person touches the back panel. The high energy potential on the person discharges through an arcing path to the rear panel of the system before he or she even touches the system. This energy, whether discharged directly or through air, is predominantly a function of the discharge current rather than the discharge voltage. Variables with an air discharge such as approach speed of the object carrying the ESD potential to the system and humidity will tend to change the discharge current. For example, the rise time of the discharge current varies with the approach speed. There are different methods of ESD testing applied: a) MIL-STD-883, Method 3015.7 b) IEC1000-4-2 Air-Discharge c) IEC1000-4-2 Direct Contact The Human Body Model has been the generally accepted ESD testing method for semiconductors. This method is also specified in MIL-STD-883, Method 3015.7 for ESD testing. The premise of this ESD test is to simulate the human body’s potential to store electro-static energy and discharge it to an integrated circuit. The simulation is performed by using a test model as shown in Figure 16. This method will test the IC’s capability to withstand an ESD transient during normal handling such as in manufacturing areas where the ICs tend to be handled frequently. The Contact Discharge Method applies the ESD current directly to the EUT. This method was devised to reduce the unpredictability of the ESD arc. The discharge current rise time is constant since the energy is directly transferred without the air-gap arc. In situations such as hand held systems, the ESD charge can be directly discharged to the equipment from a person already holding the equipment. The current is transferred on to the keypad or the serial port of the equipment directly and then travels through the PCB and finally to the IC. The IEC-1000-4-2, formerly IEC801-2, is generally used for testing ESD on equipment and systems. For system manufacturers, they must guarantee a certain amount of ESD protection since the system itself is exposed to the outside environment and human presence. The premise with IEC1000-4-2 is that the system is required to withstand an amount of static electricity when ESD is applied to points and surfaces of the equipment that are accessible to personnel during RSS RC C SW2 SW2 SW1 SW1 CSS DC Power Source Device Under Test Figure 16. ESD Test Circuit for Human Body Model Rev.4/08/02 SP3249E Intelligent +3.0V to +5.5V RS-232 Transceivers 10 © Copyright 2002 Sipex Corporation Contact-Discharge Module RSS RC C RV SW2 SW1 Device Under Test CSS DC Power Source RS and RV add up to 330Ω for IEC1000-4-2. Figure 17. ESD Test Circuit for IEC1000-4-2 i➙ The circuit model in Figures 16 and 17 represent the typical ESD testing circuit used for all three methods. The CS is initially charged with the DC power supply when the first switch (SW1) is on. Now that the capacitor is charged, the second switch (SW2) is on while SW1 switches off. The voltage stored in the capacitor is then applied through RS, the current limiting resistor, onto the device under test (DUT). In ESD tests, the SW2 switch is pulsed so that the device under test receives a duration of voltage. 30A 15A 0A For the Human Body Model, the current limiting resistor (RS) and the source capacitor (CS) are 1.5kW an 100pF, respectively. For IEC-1000-42, the current limiting resistor (RS) and the source capacitor (CS) are 330W an 150pF, respectively. t=0ns t=30ns t➙ Figure 18. ESD Test Waveform for IEC1000-4-2 The higher CS value and lower RS value in the IEC1000-4-2 model are more stringent than the Human Body Model. The larger storage capacitor injects a higher voltage to the test point when SW2 is switched on. The lower current limiting resistor increases the current charge onto the test point. DEVICE PIN TESTED HUMAN BODY MODEL Air Discharge Driver Outputs Receiver Inputs ±15kV ±15kV ±15kV ±15kV IEC1000-4-2 Direct Contact ±8kV ±8kV Level 4 4 Table 2. Transceiver ESD Tolerance Levels Rev.4/08/02 SP3249E Intelligent +3.0V to +5.5V RS-232 Transceivers 11 © Copyright 2002 Sipex Corporation PACKAGE: PLASTIC SHRINK SMALL OUTLINE (SSOP) E H D A Ø e B A1 L DIMENSIONS (Inches) Minimum/Maximum (mm) Rev.4/08/02 24–PIN A 0.068/0.078 (1.73/1.99) A1 0.002/0.008 (0.05/0.21) B 0.010/0.015 (0.25/0.38) D 0.317/0.328 (8.07/8.33) E 0.205/0.212 (5.20/5.38) e 0.0256 BSC (0.65 BSC) H 0.301/0.311 (7.65/7.90) L 0.022/0.037 (0.55/0.95) Ø 0°/8° (0°/8°) SP3249E Intelligent +3.0V to +5.5V RS-232 Transceivers 12 © Copyright 2002 Sipex Corporation PACKAGE: PLASTIC THIN SMALL OUTLINE (TSSOP) e DIMENSIONS in inches (mm) Minimum/Maximum 0.126 BSC (3.2 BSC) 0.252 BSC (6.4 BSC) 1.0 OIA 0.169 (4.30) 0.177 (4.50) 0.039 (1.0) Symbol D 24 Lead 0.303/0.311 (7.70/7.90) e 0.026 BSC (0.65 BSC) 0’-8’ 12’REF e/2 0.039 (1.0) 0.043 (1.10) Max D 0.033 (0.85) 0.037 (0.95) 0.007 (0.19) 0.012 (0.30) 0.002 (0.05) 0.006 (0.15) (θ2) 0.008 (0.20) 0.004 (0.09) Min 0.004 (0.09) Min Gage Plane (θ3) 0.010 (0.25) 0.020 (0.50) 0.026 (0.75) (θ1) 1.0 REF Rev.4/08/02 SP3249E Intelligent +3.0V to +5.5V RS-232 Transceivers 13 © Copyright 2002 Sipex Corporation ORDERING INFORMATION Model SP3249ECA SP3249ECY SP3249EEA SP3249EEY ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ Temperature Range 0°C to +70°C 0°C to +70°C ○ ○ ○ ○ ○ ○ -40°C to +85°C -40°C to +85°C ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ Package Types 24-pin SSOP 24-pin TSSOP ○ ○ ○ ○ ○ 24-pin SSOP 24 -pin TSSOP ○ ○ Please consult the factory for pricing and availability on a Tape-On-Reel option. Corporation SIGNAL PROCESSING EXCELLENCE Sipex Corporation Headquarters and Sales Office 22 Linnell Circle Billerica, MA 01821 TEL: (978) 667-8700 FAX: (978) 670-9001 e-mail: [email protected] Sales Office 233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600 Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Rev.4/08/02 SP3249E Intelligent +3.0V to +5.5V RS-232 Transceivers 14 © Copyright 2002 Sipex Corporation