® SP3223E/3243E Intelligent +3.0V to +5.5V RS-232 Transceivers ■ Meets true EIA/TIA-232-F Standards from a +3.0V to +5.5V power supply ■ Interoperable with EIA/TIA-232 and adheres to EIA/TIA-562 down to a +2.7V power source ■ AUTO ON-LINE® circuitry automatically wakes up from a 1µA shutdown ■ Minimum 120Kbps data rate under load ■ Regulated Charge Pump Yields Stable RS-232 Outputs Regardless of VCC Variations ■ Enhanced ESD Specifications: +15KV Human Body Model +15KV IEC1000-4-2 Air Discharge +8KV IEC1000-4-2 Contact Discharge DESCRIPTION The SP3223E and 3243E products are RS-232 transceiver solutions intended for portable or hand-held applications such as notebook and palmtop computers. The SP3223E and 3243E use an internal high-efficiency, charge-pump power supply that requires only 0.1µF capacitors in 3.3V operation. This charge pump and Sipex's driver architecture allow the SP3223E/ 3243E series to deliver compliant RS-232 performance from a single power supply ranging from +3.3V to +5.0V. The SP3223E is a 2-driver/2-receiver device, and the SP3243E is a 3-driver/5-receiver device ideal for laptop/notebook computer and PDA applications. The SP3243E includes one complementary receiver that remains alert to monitor an external device's Ring Indicate signal while the device is shutdown. The AUTO ON-LINE® feature allows the device to automatically "wake-up" during a shutdown state when an RS-232 cable is connected and a connected peripheral is turned on. Otherwise, the device automatically shuts itself down drawing less than 1µA. SELECTION TABLE Device Power Supplies RS-232 Drivers RS-232 Receivers External Components AUTO ON-LINE® TTL 3-State No. of Pins Circuitry SP3223E +3.0V to +5.5V 2 2 4 capacitors YES YES 20 SP3243E +3.0V to +5.5V 3 5 4 capacitors YES YES 28 Applicable U.S. Patents - 5,306,954; and other patents pending. Rev. 11/14/02 SP3223E +3.0V to +5.5V RS-232 Transceivers 1 © Copyright 2002 Sipex Corporation Power Dissipation per package ABSOLUTE MAXIMUM RATINGS 28-pin PDIP (derate 16.0mW/oC above+70oC).....1300mW 20-pin SSOP (derate 9.25mW/oC above +70oC)....750mW 20-pin TSSOP (derate 11.1mW/oC above +70oC)..900mW 28-pin SOIC (derate 12.7mW/oC above +70oC)...1000mW 28-pin SSOP (derate 11.2mW/oC above +70oC)....900mW These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability and cause permanent damage to the device. VCC.......................................................-0.3V to +6.0V V+ (NOTE 1).......................................-0.3V to +7.0V V- (NOTE 1)........................................+0.3V to -7.0V V+ + |V-| (NOTE 1)...........................................+13V ICC (DC VCC or GND current).........................+100mA Input Voltages TxIN, ONLINE, SHUTDOWN, EN (SP3223E).................-0.3V to +6.0V RxIN...................................................................+15V Output Voltages TxOUT...............................................................+15V RxOUT, STATUS.......................-0.3V to (VCC + 0.3V) Short-Circuit Duration TxOUT.....................................................Continuous Storage Temperature......................-65°C to +150°C NOTE 1: V+ and V- can have maximum magnitudes of 7V, but their absolute difference cannot exceed 13V. SPECIFICATIONS Unless otherwise noted, the following specifications apply for VCC = +3.0V to +5.5V with TAMB = TMIN to TMAX. Typical values apply at VCC = +3.3V or +5.0V and TAMB = 25°C. PARAMETER MIN. TYP. MAX. UNITS CONDITIONS Supply Current, AUTO ON-LINE® 1.0 10 µA All RxIN open, ONLINE = GND, SHUTDOWN = VCC, TxIN=VCC or GND,VCC = +3.3V, TAMB = +25° C Supply Current, Shutdown 1.0 10 µA SHUTDOWN = GND, TxIN=VCC or GND, VCC = +3.3V, TAMB = +25° C Supply Current, AUTO ON-LINE® Disabled 0.3 1.0 mA ONLINE = SHUTDOWN = VCC, no load, VCC = +3.3V, TAMB = +25° C 0.8 V DC CHARACTERISTICS LOGIC INPUTS AND RECEIVER OUTPUTS Input Logic Threshold LOW HIGH 2.0 VCC = +3.3V or +5.0V, TxIN, EN (SP3223E), ONLINE, SHUTDOWN Input Leakage Current ±0.01 ±1.0 µA TxIN, EN, ONLINE, SHUTDOWN, TAMB = +25° C Output Leakage Current ±0.05 ±10 µA Receivers disabled 0.4 V IOUT = 1.6mA V IOUT = -1.0mA Output Voltage LOW Output Voltage HIGH Rev. 11/14/02 VCC - 0.6 VCC - 0.1 SP3223E +3.0V to +5.5V RS-232 Transceivers 2 © Copyright 2002 Sipex Corporation SPECIFICATIONS (continued) Unless otherwise noted, the following specifications apply for VCC = +3.0V to +5.5V with TAMB = TMIN to TMAX. Typical values apply at VCC = +3.3V or +5.0V and TAMB = 25°C. PARAMETER MIN. TYP. Output Voltage Swing ±5.0 ±5.4 Output Resistance 300 MAX. UNITS CONDITIONS DRIVER OUTPUTS Output Short-Circuit Current ±35 ±70 Output Leakage Current V All driver outputs loaded with 3KΩ to GND, TAMB = +25° C Ω VCC = V+ = V- = 0V, VOUT = ±2V ±60 ±100 mA ±25 µA 15 V VOUT = 0V VOUT = ±15V VCC = 0V or 3.0V to 5.5V, VOUT = ±12V, Drivers disabled RECEIVER INPUTS Input Voltage Range -15 Input Threshold LOW 0.6 1.2 V VCC = 3.3V Input Threshold LOW 0.8 1.5 V VCC = 5.0V Input Threshold HIGH 1.5 2.4 V VCC = 3.3V Input Threshold HIGH 1.8 2.4 V VCC = 5.0V Input Hysteresis 0.3 Input Resistance 3 V 5 7 kΩ AUTO ON-LINE® CIRCUITRY CHARACTERISTICS (ONLINE = GND, SHUTDOWN = VCC) STATUS Output Voltage LOW STATUS Output Voltage HIGH 0.4 VCC - 0.6 V IOUT = 1.6mA V IOUT = -1.0mA Receiver Threshold to Drivers Enabled (tONLINE) 200 µS Figure 15 Receiver Positive or Negative Threshold to STATUS HIGH (tSTSH) 0.5 µS Figure 15 Receiver Positive or Negative Threshold to STATUS LOW (tSTSL) 20 µS Figure 15 Rev. 11/14/02 SP3223E +3.0V to +5.5V RS-232 Transceivers 3 © Copyright 2002 Sipex Corporation SPECIFICATIONS (continued) Unless otherwise noted, the following specifications apply for VCC = +3.0V to +5.5V with TAMB = TMIN to TMAX. Typical values apply at VCC = +3.3V or +5.0V and TAMB = 25°C. PARAMETER MIN. TYP. MAX. UNITS CONDITIONS 120 235 kbps Receiver Propagation Delay tPHL tPLH 0.3 0.3 µs Receiver input to Receiver output, CL = 150pF Receiver Output Enable Time 200 ns Normal operation Receiver Output Disable Time 200 ns Normal operation Driver Skew 100 500 ns | tPHL - tPLH |, TAMB = 25oC Receiver Skew 200 1000 ns | tPHL - tPLH | 30 V/µs TIMING CHARACTERISTICS Maximum Data Rate Transition-Region Slew Rate RL = 3KΩ, CL = 1000pF, one driver active VCC= 3.3V, RL = 3KΩ, TAMB = 25oC, measurements taken from -3.0V to +3.0V or +3.0V to -3.0V TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise noted, the following performance characteristics apply for VCC = +3.3V, 120Kbps data rate, all drivers loaded with 3KΩ, 0.1µF charge pump capacitors, and TAMB = +25°C. 14 12 4 10 Slew Rate [V/µs] Transmitter Output Voltage [V] 6 Vout+ Vout- 2 0 0 500 1000 1500 -2 6 +Slew -Slew 4 -4 2 -6 0 Load Capacitance [pF] 0 500 1000 1500 Load Capacitance [pF] 2000 Figure 2. Slew Rate VS. Load Capacitance for the SP3223E Figure 1. Transmitter Output Voltage VS. Load Capacitance for the SP3223E Rev. 11/14/02 8 SP3223E +3.0V to +5.5V RS-232 Transceivers 4 © Copyright 2002 Sipex Corporation TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise noted, the following performance characteristics apply for VCC = +3.3V, 120Kbps data rate, all drivers loaded with 3KΩ, 0.1µF charge pump capacitors, and TAMB = +25°C. 40 118KHz 60KHz 10KHz 6 Transmitter Output Voltage [V] Supply Current [mA] 35 30 25 20 15 10 4 Vout+ Vout- 2 0 0 500 1000 2000 1500 2500 -2 -4 5 -6 Load Capacitance [pF] 0 0 500 1000 1500 Load Capacitance [pF] 2000 Figure 4. Transmitter Output Voltage VS. Load Capacitance for the SP3243E 16 80 14 70 12 60 Supply Current [mA] Slew Rate [V/µs] Figure 3. Supply Current VS. Load Capacitance when Transmitting Data for the SP3223E 10 8 6 + Slew - Slew 4 118KHz 60KHz 10KHz 50 40 30 20 10 2 0 0 0 500 1000 1500 2000 2500 0 3000 500 1500 2000 2500 3000 Figure 6. Supply Current VS. Load Capacitance when Transmitting Data for the SP3243E Figure 5. Slew Rate VS. Load Capacitance for the SP3243E Rev. 11/14/02 1000 Load Capacitance [pF] Load Capacitance [pF] SP3223E +3.0V to +5.5V RS-232 Transceivers 5 © Copyright 2002 Sipex Corporation PIN NUMBER NAME FUNCTION SP3223E SP3243E EN Receiver Enable. Apply logic LOW for normal operation. Apply logic HIGH to disable the receiver outputs (high-Z state). 1 - C1+ Positive terminal of the voltage doubler charge-pump capacitor. 2 28 V+ Regulated +5.5V output generated by the charge pump. 3 27 C1- Negative terminal of the voltage doubler charge-pump capacitor. 4 24 C2+ Positive terminal of the inverting charge-pump capacitor. 5 1 C2- Negative terminal of the inverting charge-pump capacitor. 6 2 V- Regulated -5.5V output generated by the charge pump. 7 3 R1IN RS-232 receiver input. 16 4 R2IN RS-232 receiver input. 9 5 R3IN RS-232 receiver input. - 6 R4IN RS-232 receiver input. - 7 R5IN RS-232 receiver input. - 8 R1OUT TTL/CMOS receiver output. 15 19 R2OUT TTL/CMOS receiver output. 10 18 R2OUT Non-inverting receiver-2 output, active in shutdown. - 20 R3OUT TTL/CMOS receiver output. - 17 R4OUT TTL/CMOS receiver output. - 16 R5OUT TTL/CMOS receiver output. - 15 TTL/CMOS Output indicating online and shutdown status. 11 21 T1IN TTL/CMOS driver input. 13 14 T2IN TTL/CMOS driver input. 12 13 T3IN TTL/CMOS driver input. - 12 Apply logic HIGH to override AUTO ON-LINE circuitry keeping drivers active (SHUTDOWN must also be logic HIGH, refer to Table 2). 14 23 T1OUT RS-232 driver output. 17 9 T2OUT RS-232 driver output. 8 10 T3OUT RS-232 driver output. - 11 Ground. 18 25 +3.0V to +5.5V supply voltage. 19 26 Apply logic LOW to shut down drivers and charge pump. This overrides all AUTO ON-LINE® circuitry and ONLINE (refer to Table 2). 20 22 STATUS ONLINE GND VCC SHUTDOWN Table 1. Device Pin Description Rev. 11/14/02 SP3223E +3.0V to +5.5V RS-232 Transceivers 6 © Copyright 2002 Sipex Corporation EN 20 SHUTDOWN 1 C1+ 2 19 VCC V+ 3 18 GND C1- 4 17 T1OUT C2+ 5 16 R1IN C2- 6 15 R1OUT V- 7 14 T2OUT 8 13 T1IN R2IN 9 12 T2IN SP3223E R2OUT 10 11 ONLINE STATUS Figure 7. SP3223E Pinout Configuration C2+ 1 28 C1+ C2- 2 27 V+ V- 3 26 VCC R1IN 4 25 GND R2IN 5 24 C1- R3IN 6 R4IN 7 SP3243E 23 ONLINE 22 SHUTDOWN 21 STATUS R5IN 8 T1OUT 9 20 R2OUT T2OUT 10 19 R1OUT T3OUT 11 18 R2OUT T3IN 12 17 R3OUT T2IN 13 16 R4OUT T1IN 14 15 R5OUT Figure 8. SP3243E Pinout Configuration Rev. 11/14/02 SP3223E +3.0V to +5.5V RS-232 Transceivers 7 © Copyright 2002 Sipex Corporation +3V to +5V C5 C1 + + 19 0.1µF VCC 2 C1+ V+ 3 0.1µF C3 + 0.1µF 4 C15 C2+ C2 + 0.1µF TTL/CMOS INPUTS SP3223E V- 7 C4 6 C213 T1IN T1OUT 17 12 T2IN T2OUT R1IN 15 R1OUT 8 RS-232 OUTPUTS RS-232 INPUTS R2IN 10 R2OUT 0.1µF 16 5KΩ TTL/CMOS OUTPUTS + 9 5KΩ VCC 1 EN 20 14 To µP Supervisor Circuit 11 SHUTDOWN ONLINE STATUS GND 18 Figure 9. SP3223E Typical Operating Circuit Rev. 11/14/02 SP3223E +3.0V to +5.5V RS-232 Transceivers 8 © Copyright 2002 Sipex Corporation C5 C1 + + VCC 26 VCC 0.1µF 28 C1+ V+ 27 0.1µF C3 + 0.1µF 24 C11 C2+ C2 + 0.1µF TTL/CMOS INPUTS SP3243E V- 3 C4 2 C214 T1IN T1OUT 13 T2IN T2OUT 10 12 T3IN T3OUT 11 + 0.1µF 9 RS-232 OUTPUTS 20 R2OUT 19 R1OUT R1IN 4 R2IN 5 R3IN 6 R4IN 7 R5IN 8 5KΩ 18 R2OUT 5KΩ TTL/CMOS OUTPUTS 17 R3OUT 5KΩ 16 R4OUT RS-232 INPUTS 5KΩ 15 R5OUT VCC 22 23 To µP Supervisor Circuit 5KΩ SHUTDOWN ONLINE 21 STATUS GND 25 Figure 10. SP3243E Typical Operating Circuit Rev. 11/14/02 SP3223E +3.0V to +5.5V RS-232 Transceivers 9 © Copyright 2002 Sipex Corporation DESCRIPTION The SP3223E and SP3243E transceivers meet the EIA/TIA-232 and ITU-T V.28/V.24 communication protocols and can be implemented in battery-powered, portable, or hand-held applications such as notebook or palmtop computers. The SP3223E and SP3243E devices feature Sipex's proprietary and patented (U.S.-5,306,954) on-board charge pump circuitry that generates ±5.5V RS-232 voltage levels from a single +3.0V to +5.5V power supply. The SP3223E and SP3243E devices can operate at a typical data rate of 235kbps fully loaded. The SP3223E and SP3243E series is an ideal choice for power sensitive designs. The SP3223E and SP3243E devices feature AUTO ON-LINE® circuitry which reduces the power supply drain to a 1µA supply current. In many portable or hand-held applications, an RS-232 cable can be disconnected or a connected peripheral can be turned off. Under these conditions, the internal charge pump and the drivers will be shut down. Otherwise, the system automatically comes online. This feature allows design engineers to address power saving concerns without major design changes. The SP3223E is a 2-driver/2-receiver device, and the SP3243E is a 3-driver/5-receiver device ideal for portable or hand-held applications. The SP3243E includes one complementary always-active receiver that can monitor an external device (such as a modem) in shutdown. This aids in protecting the UART or serial controller IC by preventing forward biasing of the protection diodes where VCC may be disconnected. THEORY OF OPERATION The SP3223E and SP3243E series is made up of four basic circuit blocks: 1. Drivers, 2. Receivers, 3. the Sipex proprietary charge pump, and 4. AUTO ON-LINE® circuitry. Drivers The drivers are inverting level transmitters that convert TTL or CMOS logic levels to 5.0V EIA/ TIA-232 levels with an inverted sense relative to the input logic levels. Typically, the RS-232 output voltage swing is +5.4V with no load and +5V minimum fully loaded. The driver outputs are protected against infinite short-circuits to ground without degradation in reliability. These drivers comply with the EIA-TIA-232F and all previous RS-232 versions. Unused driver inputs should be connected to GND or VCC. VCC + C5 + C1 26 VCC 0.1µF 28 C1+ V+ 27 0.1µF C3 + 0.1µF 24 C11 C2+ C2 + 0.1µF SP3243E V- 3 C4 2 C214 T1IN T1OUT RTS 13 T2IN T2OUT 10 DTR 12 T3IN T3OUT 11 RxD 19 R1OUT CTS 18 R2OUT DSR 17 R3OUT DCD 16 R4OUT RI 15 R5OUT TxD + 0.1µF 9 RS-232 OUTPUTS 20 R2OUT UART or Serial µC R1IN 4 5KΩ R2IN 5 5KΩ R3IN 6 R4IN 7 R5IN 8 5KΩ RS-232 INPUTS The drivers can guarantee a data rate of 120Kbps fully loaded with 3KΩ in parallel with 1000pF, ensuring compatibility with PC-to-PC communication software. 5KΩ VCC 22 23 5KΩ SHUTDOWN ONLINE 21 STATUS GND 25 RESET µP Supervisor IC The slew rate of the driver output is internally limited to a maximum of 30V/µs in order to meet the EIA standards (EIA RS-232D 2.1.7, Paragraph 5). The transition of the loaded output from HIGH to LOW also meets the monotonicity requirements of the standard. VIN Figure 11. Interface Circuitry Controlled by Microprocessor Supervisory Circuit Rev. 11/14/02 SP3223E +3.0V to +5.5V RS-232 Transceivers 10 © Copyright 2002 Sipex Corporation DEVICE: SP3223E SHUTDOWN +3V to +5V EN TXOUT C5 RXOUT C1 0 0 High Z 1 High Z + 2 C1+ Active Active 1 1 Active High Z + 0.1µF SP3223E SP3243E V- C4 T1IN T1OUT TXIN TXOUT R2OUT 0 High Z High Z Active 1 Active Active Active + 0.1µF R1IN R1OUT 5KΩ RXIN RXOUT RXOUT 0.1µF TTL/CMOS INPUTS DEVICE: SP3243E TXOUT + 7 6 C2- TTL/CMOS OUTPUTS SHUTDOWN 3 C3 5 C2+ High Z 0 V+ 0.1µF Active 1 19 VCC 0.1µF 4 C1- C2 0 + 1 VCC 20 14 To µP Supervisor Circuit 11 5KΩ 1000pF EN 1000pF SHUTDOWN ONLINE STATUS GND 18 Table 2. SHUTDOWN and EN Truth Tables Note: In AUTO ON-LINE® Mode where ONLINE = GND and SHUTDOWN = VCC, the device will shut down if there is no activity present at the Receiver inputs. Figure 12. Loopback Test Circuit for RS-232 Driver Data Transmission Rates Figure 12 shows a loopback test circuit used to test the RS-232 Drivers. Figure 13 shows the test results of the loopback circuit with all three drivers active (SP3243E) at 120Kbps with typical RS-232 loads in parallel with 1000pF capacitors. Figure 14 shows the test results where one driver was active at 235Kbps and all three drivers loaded with an RS-232 receiver in parallel with a 1000pF capacitor. A solid RS-232 data trans- mission rate of 120Kbps provides compatibility with many designs in personal computer peripherals and LAN applications. Receivers The receivers convert ±5.0V EIA/TIA-232 levels to TTL or CMOS logic output levels. Receivers have an inverting output that can be disabled by using the EN pin. T1 IN T1 IN T1 OUT T1 OUT R1 OUT R1 OUT Figure 13. Loopback Test Circuit Result at 120Kbps (All Drivers Fully Loaded) Rev. 11/14/02 Figure 14. Loopback Test Circuit result at 235Kbps (All Drivers Fully Loaded) SP3223E +3.0V to +5.5V RS-232 Transceivers 11 © Copyright 2002 Sipex Corporation The charge pump operates in a discontinuous mode using an internal oscillator. If the output voltages are less than a magnitude of 5.5V, the charge pump is enabled. If the output voltages exceed a magnitude of 5.5V, the charge pump is disabled. This oscillator controls the four phases of the voltage shifting. A description of each phase follows. Receivers are active when the AUTO ON-LINE® circuitry is enabled or when in shutdown. During the shutdown, the receivers will continue to be active. If there is no activity present at the receivers for a period longer than 100µs or when SHUTDOWN is enabled, the device goes into a standby mode where the circuit draws 1µA. Driving EN to a logic HIGH forces the outputs of the receivers into high-impedance. The truth table logic of the SP3223E and SP3243E driver and receiver outputs can be found in Table 2. Phase 1 — VSS charge storage — During this phase of the clock cycle, the positive side of capacitors C1 and C2 are initially charged to VCC. Cl+ is then switched to GND and the charge in C1– is transferred to C2–. Since C2+ is connected to VCC, the voltage potential across capacitor C2 is now 2 times VCC. The SP3243E includes an additional non-inverting receiver with an output R2OUT. R2OUT is an extra output that remains active and monitors activity while the other receiver outputs are forced into high impedance. This allows Ring Indicator (RI) from a peripheral to be monitored without forward biasing the TTL/CMOS inputs of the other devices connected to the receiver outputs. Phase 2 — VSS transfer — Phase two of the clock connects the negative terminal of C2 to the VSS storage capacitor and the positive terminal of C2 to GND. This transfers a negative generated voltage to C 3. This generated voltage is regulated to a minimum voltage of -5.5V. Simultaneous with the transfer of the voltage to C3, the positive side of capacitor C1 is switched to VCC and the negative side is connected to GND. Since receiver input is usually from a transmission line where long cable lengths and system interference can degrade the signal, the inputs have a typical hysteresis margin of 300mV. This ensures that the receiver is virtually immune to noisy transmission lines. Should an input be left unconnected, an internal 5KΩ pulldown resistor to ground will commit the output of the receiver to a HIGH state. Phase 3 — VDD charge storage — The third phase of the clock is identical to the first phase — the charge transferred in C1 produces –VCC in the negative terminal of C1, which is applied to the negative side of capacitor C2. Since C2+ is at VCC, the voltage potential across C2 is 2 times VCC. Charge Pump The charge pump is a Sipex–patented design (U.S. 5,306,954) and uses a unique approach compared to older less–efficient designs. The charge pump still requires four external capacitors, but uses a four–phase voltage shifting technique to attain symmetrical 5.5V power supplies. The internal power supply consists of a regulated dual charge pump that provides output voltages 5.5V regardless of the input voltage (VCC) over the +3.0V to +5.5V range. This is important to maintain compliant RS-232 levels regardless of power supply fluctuations. Rev. 11/14/02 Phase 4 — VDD transfer — The fourth phase of the clock connects the negative terminal of C2 to GND, and transfers this positive generated voltage across C2 to C4, the VDD storage capacitor. This voltage is regulated to +5.5V. At this voltage, the internal oscillator is disabled. Simultaneous with the transfer of the voltage to C4, the positive side of capacitor C1 is switched to VCC and the negative side is connected to GND, allowing the charge pump cycle to begin again. The charge pump cycle will continue as long as the operational conditions for the internal oscillator are present. SP3223E +3.0V to +5.5V RS-232 Transceivers 12 © Copyright 2002 Sipex Corporation Since both V+ and V– are separately generated from VCC, in a no–load condition V+ and V– will be symmetrical. Older charge pump approaches that generate V– from V+ will show a decrease in the magnitude of V– compared to V+ due to the inherent inefficiencies in the design. The clock rate for the charge pump typically operates at 250kHz. The external capacitors can be as low as 0.1µF with a 16V breakdown voltage rating. S H U T RECEIVER +2.7V 0V RS-232 INPUT VOLTAGES -2.7V D O W N VCC STATUS 0V tSTSL tSTSH tONLINE +5V DRIVER RS-232 OUTPUT VOLTAGES 0V -5V Figure 15. AUTO ON-LINE® Timing Waveforms Rev. 11/14/02 SP3223E +3.0V to +5.5V RS-232 Transceivers 13 © Copyright 2002 Sipex Corporation VCC = +5V C4 +5V C1 + C2 – –5V + – – + VDD Storage Capacitor + – VSS Storage Capacitor C3 –5V Figure 16. Charge Pump — Phase 1 VCC = +5V C4 C1 + C2 – + – – + + – VDD Storage Capacitor VSS Storage Capacitor C3 –10V Figure 17. Charge Pump — Phase 2 [ T ] +6V a) C2+ T 1 0V 2 2 0V b) C2T -6V Ch1 2.00V Ch2 2.00V M 1.00µs Ch1 1.96V Figure 18. Charge Pump Waveforms VCC = +5V C4 +5V + C1 + C2 – –5V – + – – + VDD Storage Capacitor VSS Storage Capacitor C3 –5V Figure 19. Charge Pump — Phase 3 VCC = +5V +10V C1 + – C2 C4 + – – + + – VDD Storage Capacitor VSS Storage Capacitor C3 Figure 20. Charge Pump — Phase 4 Rev. 11/14/02 SP3223E +3.0V to +5.5V RS-232 Transceivers 14 © Copyright 2002 Sipex Corporation 4 -2 8.6 4.93 2.67 1.82 1.57 1.38 1.23 1.12 1.02 0.939 0.62 0 3.46 Vout+ Vout- 2 0.869 Transmitter Output Voltage [V] 6 -4 -6 Load Current Per Transmitter [mA] Figure 21. SP3243E Driver Output Voltages vs. Load Current per Transmitter C5 C1 + + VCC 26 0.1µF VCC 28 C1+ V+ 27 0.1µF C3 + 0.1µF 24 C11 C2+ C2 + 0.1µF SP3243E V- 3 C4 2 C214 T1IN T1OUT 13 T2IN T2OUT 10 12 T3IN T3OUT 11 + 0.1µF 9 20 R2OUT R1IN 4 19 R1OUT 5KΩ R2IN 5 18 R2OUT 5KΩ R3IN 17 R3OUT 6 5KΩ R4IN 7 16 R4OUT 5KΩ 15 R5OUT VCC 22 23 To µP Supervisor Circuit R5IN 8 5KΩ DB-9 Connector SHUTDOWN ONLINE 21 STATUS 6 7 8 9 GND 25 DB-9 Connector Pins: 1. Received Line Signal Detector 2. Received Data 3. Transmitted Data 4. Data Terminal Ready 5. Signal Ground (Common) 6. 7. 8. 9. 1 2 3 4 5 DCE Ready Request to Send Clear to Send Ring Indicator Figure 22. Circuit for the connectivity of the SP3243E with a DB-9 connector Rev. 11/14/02 SP3223E +3.0V to +5.5V RS-232 Transceivers 15 © Copyright 2002 Sipex Corporation RS-232 SIGNAL AT RECEIVER INPUT SHUTDOWN INPUT ONLINE INPUT STATUS OUTPUT TRANSCEIVER STATUS YES HIGH LOW HIGH Normal Operation (AUTO ON-LINE® ) NO HIGH HIGH LOW Normal Operation NO HIGH LOW LOW Shutdown (AUTO ON-LINE® ) YES LOW HIGH/LOW HIGH Shutdown NO LOW HIGH/LOW LOW Shutdown Table 3. AUTO ON-LINE® Logic RXINACT Inactive Detection Block RS-232 Receiver Block RXIN RXOUT Figure 23. Stage I of AUTO ON-LINE® Circuitry Delay Stage Delay Stage Delay Stage Delay Stage Delay Stage STATUS R1INACT R2INACT R4INACT R3INACT R5INACT SHUTDOWN Figure 24. Stage II of AUTO ON-LINE® Circuitry Rev. 11/14/02 SP3223E +3.0V to +5.5V RS-232 Transceivers 16 © Copyright 2002 Sipex Corporation AUTO ON-LINE® Circuitry The second stage of the AUTO ON-LINE® circuitry, shown in Figure 24, processes all the receiver's RXINACT signals with an accumulated delay that disables the device to a 1µA supply current. The STATUS pin goes to a logic LOW when the cable is disconnected, the external transmitters are disabled, or the SHUTDOWN pin is invoked. The typical accumulated delay is around 20µs. The SP3223E and SP3243E devices have a patent pending AUTO ON-LINE® circuitry on board that saves power in applications such as laptop computers, palmtop (PDA) computers, and other portable systems. The SP3223E and SP3243E devices incorporate an AUTO ON-LINE® circuit that automatically enables itself when the external transmitters are enabled and the cable is connected. Conversely, the AUTO ON-LINE® circuit also disables most of the internal circuitry when the device is not being used and goes into a standby mode where the device typically draws 1µA. This function can also be externally controlled by the ONLINE pin. When this pin is tied to a logic LOW, the AUTO ON-LINE® function is active. Once active, the device is enabled until there is no activity on the receiver inputs. The receiver input typically sees at least ±3V, which are generated from the transmitters at the other end of the cable with a ±5V minimum. When the external transmitters are disabled or the cable is disconnected, the receiver inputs will be pulled down by their internal 5kΩ resistors to ground. When this occurs over a period of time, the internal transmitters will be disabled and the device goes into a shutdown or standy mode. When ONLINE is HIGH, the AUTO ON-LINE® mode is disabled. When the SP3223E and SP3243E drivers or internal charge pump are disabled, the supply current is reduced to 1µA. This can commonly occur in hand-held or portable applications where the RS-232 cable is disconnected or the RS-232 drivers of the connected peripheral are turned off. The AUTO ON-LINE® mode can be disabled by the SHUTDOWN pin. If this pin is a logic LOW,the AUTO ON-LINE® function will not operate regardless of the logic state of the ONLINE pin. Table 3 summarizes the logic of the AUTO ON-LINE® operating modes. The truth table logic of the SP3223E and SP3243E driver and receiver outputs can be found in Table 2. The STATUS pin outputs a logic LOW signal if the device is shutdown. This pin goes to a logic HIGH when the external transmitters are enabled and the cable is connected. The AUTO ON-LINE® circuit has two stages: 1) Inactive Detection 2) Accumulated Delay When the SP3223E and SP3243E devices are shut down, the charge pumps are turned off. V+ charge pump output decays to VCC, the V- output decays to GND. The decay time will depend on the size of capacitors used for the charge pump. Once in shutdown, the time required to exit the shut down state and have valid V+ and V- levels is typically 200µs. The first stage, shown in Figure 23, detects an inactive input. A logic HIGH is asserted on RXINACT if the cable is disconnected or the external transmitters are disabled. Otherwise, RXINACT will be at a logic LOW. This circuit is duplicated for each of the other receivers. Rev. 11/14/02 For easy programming, the STATUS can be used to indicate DTR or a Ring Indicator signal. Tying ONLINE and SHUTDOWN together will bypass the AUTO ON-LINE® circuitry so this connection acts like a shutdown input pin. SP3223E +3.0V to +5.5V RS-232 Transceivers 17 © Copyright 2002 Sipex Corporation normal usage. The transceiver IC receives most of the ESD current when the ESD source is applied to the connector pins. The test circuit for IEC1000-4-2 is shown on Figure 26. There are two methods within IEC1000-4-2, the Air Discharge method and the Contact Discharge method. ESD TOLERANCE The SP3223E/3243E series incorporates ruggedized ESD cells on all driver output and receiver input pins. The ESD structure is improved over our previous family for more rugged applications and environments sensitive to electro-static discharges and associated transients. The improved ESD tolerance is at least +15kV without damage nor latch-up. With the Air Discharge Method, an ESD voltage is applied to the equipment under test (EUT) through air. This simulates an electrically charged person ready to connect a cable onto the rear of the system only to find an unpleasant zap just before the person touches the back panel. The high energy potential on the person discharges through an arcing path to the rear panel of the system before he or she even touches the system. This energy, whether discharged directly or through air, is predominantly a function of the discharge current rather than the discharge voltage. Variables with an air discharge such as approach speed of the object carrying the ESD potential to the system and humidity will tend to change the discharge current. For example, the rise time of the discharge current varies with the approach speed. There are different methods of ESD testing applied: a) MIL-STD-883, Method 3015.7 b) IEC1000-4-2 Air-Discharge c) IEC1000-4-2 Direct Contact The Human Body Model has been the generally accepted ESD testing method for semiconductors. This method is also specified in MIL-STD-883, Method 3015.7 for ESD testing. The premise of this ESD test is to simulate the human body’s potential to store electro-static energy and discharge it to an integrated circuit. The simulation is performed by using a test model as shown in Figure 25. This method will test the IC’s capability to withstand an ESD transient during normal handling such as in manufacturing areas where the ICs tend to be handled frequently. The Contact Discharge Method applies the ESD current directly to the EUT. This method was devised to reduce the unpredictability of the ESD arc. The discharge current rise time is constant since the energy is directly transferred without the air-gap arc. In situations such as hand held systems, the ESD charge can be directly discharged to the equipment from a person already holding the equipment. The current is transferred on to the keypad or the serial port of the equipment directly and then travels through the PCB and finally to the IC. The IEC-1000-4-2, formerly IEC801-2, is generally used for testing ESD on equipment and systems. For system manufacturers, they must guarantee a certain amount of ESD protection since the system itself is exposed to the outside environment and human presence. The premise with IEC1000-4-2 is that the system is required to withstand an amount of static electricity when ESD is applied to points and surfaces of the equipment that are accessible to personnel during R RSS R RC C SW2 SW2 SW1 SW1 C CSS DC Power Source Device Under Test Figure 25. ESD Test Circuit for Human Body Model Rev. 11/14/02 SP3223E +3.0V to +5.5V RS-232 Transceivers 18 © Copyright 2002 Sipex Corporation Contact-Discharge Module R RSS R RC C RV SW2 SW1 Device Under Test CSS DC Power Source RS and RV add up to 330Ω for IEC1000-4-2. Figure 26. ESD Test Circuit for IEC1000-4-2 i➙ The circuit model in Figures 25 and 26 represent the typical ESD testing circuit used for all three methods. The CS is initially charged with the DC power supply when the first switch (SW1) is on. Now that the capacitor is charged, the second switch (SW2) is on while SW1 switches off. The voltage stored in the capacitor is then applied through RS, the current limiting resistor, onto the device under test (DUT). In ESD tests, the SW2 switch is pulsed so that the device under test receives a duration of voltage. 30A 15A 0A For the Human Body Model, the current limiting resistor (RS) and the source capacitor (CS) are 1.5kΩ an 100pF, respectively. For IEC-1000-42, the current limiting resistor (RS) and the source capacitor (CS) are 330Ω an 150pF, respectively. t=0ns t=30ns t➙ Figure 27. ESD Test Waveform for IEC1000-4-2 The higher CS value and lower RS value in the IEC1000-4-2 model are more stringent than the Human Body Model. The larger storage capacitor injects a higher voltage to the test point when SW2 is switched on. The lower current limiting resistor increases the current charge onto the test point. DEVICE PIN TESTED HUMAN BODY MODEL Air Discharge Driver Outputs Receiver Inputs ±15kV ±15kV ±15kV ±15kV IEC1000-4-2 Direct Contact ±8kV ±8kV Level 4 4 Table 4. Transceiver ESD Tolerance Levels Rev. 11/14/02 SP3223E +3.0V to +5.5V RS-232 Transceivers 19 © Copyright 2002 Sipex Corporation PACKAGE: PLASTIC DUAL–IN–LINE (NARROW) E1 E D1 = 0.005" min. (0.127 min.) A1 = 0.015" min. (0.381min.) D A = 0.210" max. (5.334 max). C A2 B1 B e = 0.100 BSC (2.540 BSC) Ø L eA = 0.300 BSC (7.620 BSC) ALTERNATE END PINS (BOTH ENDS) DIMENSIONS (Inches) Minimum/Maximum (mm) 16–PIN 20–PIN 28–PIN A2 0.115/0.195 (2.921/4.953) 0.115/0.195 (2.921/4.953) 0.068/0.078 (1.73/1.99) B 0.014/0.022 (0.356/0.559) 0.014/0.022 (0.356/0.559) 0.002/0.008 (0.05/0.21) B1 0.045/0.070 (1.143/1.778) 0.045/0.070 (1.143/1.778) 0.010/0.015 (0.25/0.38) C 0.008/0.014 (0.203/0.356) 0.008/0.014 (0.203/0.356) 0.397/0.407 (10.07/10.33) D Rev. 11/14/02 0.980/1.060 0.780/0.800 (19.812/20.320) (24.892/26.924) 0.205/0.212 (5.20/5.38) E 0.300/0.325 (7.620/8.255) 0.300/0.325 (7.620/8.255) 0.0256 BSC (0.65 BSC) E1 0.240/0.280 (6.096/7.112) 0.240/0.280 (6.096/7.112) 0.301/0.311 (7.65/7.90) L 0.115/0.150 (2.921/3.810) 0.115/0.150 (2.921/3.810) 0.022/0.037 (0.55/0.95) Ø 0°/ 15° (0°/15°) 0°/ 15° (0°/15°) 0°/8° (0°/8°) SP3223E +3.0V to +5.5V RS-232 Transceivers 20 © Copyright 2002 Sipex Corporation PACKAGE: PLASTIC SHRINK SMALL OUTLINE (SSOP) E H D A Ø e A1 B DIMENSIONS (Inches) Minimum/Maximum (mm) Rev. 11/14/02 L 16–PIN 20–PIN 24–PIN 28–PIN A 0.068/0.078 (1.73/1.99) 0.068/0.078 (1.73/1.99) 0.068/0.078 (1.73/1.99) 0.068/0.078 (1.73/1.99) A1 0.002/0.008 (0.05/0.21) 0.002/0.008 (0.05/0.21) 0.002/0.008 (0.05/0.21) 0.002/0.008 (0.05/0.21) B 0.010/0.015 (0.25/0.38) 0.010/0.015 (0.25/0.38) 0.010/0.015 (0.25/0.38) 0.010/0.015 (0.25/0.38) D 0.239/0.249 (6.07/6.33) 0.278/0.289 (7.07/7.33) 0.317/0.328 (8.07/8.33) 0.397/0.407 (10.07/10.33) E 0.205/0.212 (5.20/5.38) 0.205/0.212 (5.20/5.38) 0.205/0.212 (5.20/5.38) 0.205/0.212 (5.20/5.38) e 0.0256 BSC (0.65 BSC) 0.0256 BSC (0.65 BSC) 0.0256 BSC (0.65 BSC) 0.0256 BSC (0.65 BSC) H 0.301/0.311 (7.65/7.90) 0.301/0.311 (7.65/7.90) 0.301/0.311 (7.65/7.90) 0.301/0.311 (7.65/7.90) L 0.022/0.037 (0.55/0.95) 0.022/0.037 (0.55/0.95) 0.022/0.037 (0.55/0.95) 0.022/0.037 (0.55/0.95) Ø 0°/8° (0°/8°) 0°/8° (0°/8°) 0°/8° (0°/8°) 0°/8° (0°/8°) SP3223E +3.0V to +5.5V RS-232 Transceivers 21 © Copyright 2002 Sipex Corporation PACKAGE: PLASTIC SMALL OUTLINE (SOIC) (WIDE) E H D A Ø e B A1 L DIMENSIONS (Inches) Minimum/Maximum (mm) Rev. 11/14/02 28–PIN A 0.093/0.104 (2.352/2.649) A1 0.004/0.012 (0.102/0.300) B 0.013/0.020 (0.330/0.508) D 0.697/0.713 (17.70/18.09) E 0.291/0.299 (7.402/7.600) e 0.050 BSC (1.270 BSC) H 0.394/0.419 (10.00/10.64) L 0.016/0.050 (0.406/1.270) Ø 0°/8° (0°/8°) SP3223E +3.0V to +5.5V RS-232 Transceivers 22 © Copyright 2002 Sipex Corporation PACKAGE: PLASTIC THIN SMALL OUTLINE (TSSOP) E2 E D A Ø e B A1 L DIMENSIONS in inches (mm) Minimum/Maximum Rev. 11/14/02 20–PIN A - /0.043 (- /1.10) A1 0.002/0.006 (0.05/0.15) B 0.007/0.012 (0.19/0.30) D 0.252/0.260 (6.40/6.60) E 0.169/0.177 (4.30/4.50) e 0.026 BSC (0.65 BSC) E2 0.126 BSC (3.20 BSC) L 0.020/0.030 (0.50/0.75) Ø 0°/8° SP3223E +3.0V to +5.5V RS-232 Transceivers 23 © Copyright 2002 Sipex Corporation ORDERING INFORMATION Model SP3223ECP SP3223ECA SP3223ECY SP3223EEP SP3223EEA SP3223EEY SP3243ECT SP3243ECA SP3243EET SP3243EEA ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ Temperature Range 0°C to +70°C 0°C to +70°C 0ºC to +70ºC -40°C to +85°C -40°C to +85°C -40°C to +85°C ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ 0°C to +70°C 0°C to +70°C -40°C to +85°C -40°C to +85°C ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ 28-pin Wide SOIC 28-pin SSOP 28-pin Wide SOIC 28-pin SSOP ○ ○ Package Types 20-pin PDIP 20-pin SSOP 20-pin TSSOP 20-pin PDIP 20-pin SSOP 20-pin TSSOP ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ Please consult the factory for pricing and availability on a Tape-On-Reel option. Corporation SIGNAL PROCESSING EXCELLENCE Sipex Corporation Headquarters and Sales Office 233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600 Sales Office 22 Linnell Circle Billerica, MA 01821 TEL: (978) 667-8700 FAX: (978) 670-9001 e-mail: [email protected] Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others. Rev. 11/14/02 SP3223E +3.0V to +5.5V RS-232 Transceivers 24 © Copyright 2002 Sipex Corporation