74AC11286
9-BIT PARITY GENERATOR/CHECKER
WITH BUS DRIVER PARITY I/O PORTS
SCAS068A – AUGUST 1988 – REVISED APRIL 1993
•
•
•
•
•
•
•
•
D OR N PACKAGE
(TOP VIEW)
Generates Either Odd or Even Parity for
Nine Data Lines
Cascadable for n-Bits Parity
Direct Bus Connection for Parity
Generation or for Checking by Using the
Parity I/O Port
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
EPIC (Enhanced-Performance Implanted
CMOS) 1-mm Process
500-mA Typical Latch-Up Immunity
at 125°C
Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
B
A
PARITY I/O
GND
PARITY ERROR
XMIT
I
1
14
2
13
3
12
4
11
5
10
6
9
7
8
C
D
E
VCC
F
G
H
t
description
The 74AC11286 universal 9-bit parity generator/checker features a local output for parity checking and a
bus-driving parity I/O port for parity generation/checking. The word-length capability is easily expanded by
cascading.
The XMIT control input is implemented specifically to accommodate cascading. When the XMIT is low, the parity
tree is disabled and the PARITY ERROR output will remain at a high logic level regardless of the input levels.
When XMIT is high, the parity tree is enabled. The PARITY ERROR output will indicate a parity error when either
an even number of inputs (A through I) are high and PARITY I/O is forced to a low logic level, or when an odd
number of inputs are high and PARITY I/O is forced to a high logic level.
The I/O control circuitry was designed so that the I/O port will remain in the high-impedance state during power
up or power down to prevent bus glitches.
The 74AC11286 is characterized for operation from – 40°C to 85°C.
FUNCTION TABLE
NUMBER OF INPUTS
(A THRU I) THAT
ARE HIGH
XMIT
INPUT
PARITY
I/O
PARITY
ERROR
OUTPUT
0, 2, 4, 6, 8
l
H
H
1, 3, 5, 7, 9
l
L
H
h
h
H
h
l
L
h
h
L
h
l
H
0 2,
0,
2 4,
4 6,
6 8
1 3,
1,
3 5,
5 7,
7 9
h — high input level
H — high output level
l — low input level
L — low output level
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1993, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–1
74AC11286
9-BIT PARITY GENERATOR/CHECKER
WITH BUS DRIVER PARITY I/O PORTS
SCAS068A – AUGUST 1988 – REVISED APRIL 1993
logic symbol†
A
B
C
D
E
F
G
H
I
XMIT
2
2k
1
14
13
1
12
3
PARITY I/O
N2
10
9
8
2, 1
7
6
5
PARITY ERROR
EN 1
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
A
B
C
D
E
F
G
H
I
PARITY
I/O
XMIT
2
1
14
13
12
10
5 PARITY
ERROR
9
8
7
3
6
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 100 mA
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2–2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
74AC11286
9-BIT PARITY GENERATOR/CHECKER
WITH BUS DRIVER PARITY I/O PORTS
SCAS068A – AUGUST 1988 – REVISED APRIL 1993
recommended operating conditions
MIN
VCC
Supply voltage
VIH
High-level input voltage
NOM
3
VCC = 3 V
VCC = 4.5 V
5.5
V
0.9
Low-level input voltage
VI
VO
Input voltage
0
Output voltage
0
IOH
High-level output current
VCC = 4.5 V
VCC = 5.5 V
1.35
Input transition rise or fall rate
TA
Operating free-air temperature
V
1.65
VCC
VCC
VCC = 3 V
VCC = 4.5 V
Dt /Dv
V
3.85
VIL
Low-level output current
UNIT
2.1
3.15
VCC = 5.5 V
VCC = 3 V
IOL
MAX
V
V
–4
– 24
VCC = 5.5 V
VCC = 3 V
– 24
VCC = 4.5 V
VCC = 5.5 V
24
mA
12
mA
24
0
10
ns/ V
– 40
85
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = – 50 mA
VOH
IOH = – 4 mA
IOH = – 24 mA
VOL
VCC
TA = 25°C
MIN
TYP
MAX
MIN
3V
2.9
2.9
4.5 V
4.4
4.4
5.5 V
5.4
5.4
3V
2.58
2.48
4.5 V
3.94
3.8
5.5 V
4.94
MAX
V
4.8
IOH = – 75 mA{
5.5 V
3V
0.1
0.1
IOL = 50 mA
4.5 V
0.1
0.1
5.5 V
0.1
0.1
IOL = 12 mA
IOL = 24 mA
IOL = 75 mA{
IOZ
II
VO = VCC or GND
VI = VCC or GND
ICC
Ci
VI = VCC or GND,
VI = VCC or GND
3.85
3V
0.36
0.44
4.5 V
0.36
0.44
5.5 V
0.36
0.44
5.5 V
IO = 0
± 0.5
±5
5.5 V
± 0.1
±1
5.5 V
8
80
3.5
Co
VO = VCC or GND
5V
8.5
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
V
1.65
5.5 V
5V
UNIT
mA
mA
mA
pF
pF
2–3
74AC11286
9-BIT PARITY GENERATOR/CHECKER
WITH BUS DRIVER PARITY I/O PORTS
SCAS068A – AUGUST 1988 – REVISED APRIL 1993
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V, (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
Any A thru I
PARITY I/O
tPLH
tPHL
Any A thru I
PARITY ERROR
tPLH
tPHL
PARITY I/O
PARITY ERROR
tPZH
tPZL
XMIT
PARITY I/O
tPHZ
tPLZ
XMIT
PARITY I/O
MIN
TA = 25°C
TYP
MAX
MIN
MAX
2.6
10
11.7
2.6
13.1
3.8
11.6
14.5
3.8
16.1
3
8.5
13.1
3
14.7
4
10.9
16
4
17.8
2.2
5.9
7.6
2.2
8.4
3.4
7.9
10.2
3.4
11.1
1.8
4.9
6.4
1.8
7
3.5
9.7
12.8
3.5
13.6
3.2
5.4
6.6
3.2
7
3.2
5.4
6.7
3.2
7.2
UNIT
ns
ns
ns
ns
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V, (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
Any A thru I
PARITY I/O
tPLH
tPHL
Any A thru I
PARITY ERROR
tPLH
tPHL
PARITY I/O
PARITY ERROR
tPZH
tPZL
XMIT
PARITY I/O
tPHZ
tPLZ
XMIT
PARITY I/O
MIN
TA = 25°C
TYP
MAX
MIN
MAX
2
5.5
8
2
9
3.1
6.9
9.1
3.1
10.7
2.5
5.2
8.9
2.5
10
3.3
6.5
10.7
3.3
12
1.9
3.9
5.6
1.9
6.2
2.9
5
7.2
2.9
7.9
1.4
3.3
4.9
1.4
5.3
3
5.4
8.3
3
8.9
3.1
4.8
6.1
3.1
6.5
3
4.6
6
3
6.3
UNIT
ns
ns
ns
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
d
2–4
Power dissipation capacitance
TEST CONDITIONS
Outputs enabled
Outputs disabled
POST OFFICE BOX 655303
CL = 50 pF,
pF
• DALLAS, TEXAS 75265
f = 1 MHz
TYP
53
46
UNIT
pF
74AC11286
9-BIT PARITY GENERATOR/CHECKER
WITH BUS DRIVER PARITY I/O PORTS
SCAS068A – AUGUST 1988 – REVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
LOAD CIRCUIT
Output
Control
(low-level
enabling)
VCC
50%
50%
0V
tPHL
tPLH
VOH
Output
S1
Open
2 × VCC
GND
50%
50%
500 Ω
CL = 50 pF
(see Note A)
Input
(see Note B)
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
50% VCC
50% VCC
VOL
VCC
0V
tPZL
Output
Waveform 2
S1 at GND
(see Note C)
[ VCC
tPLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note C)
50% VCC
VOL
tPHZ
tPZH
VOLTAGE WAVEFORMS
20% VCC
50% VCC
80% VCC
VOH
[0V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–5
74AC11286
9-BIT PARITY GENERATOR/CHECKER
WITH BUS DRIVER PARITY I/O PORTS
SCAS068A – AUGUST 1988 – REVISED APRIL 1993
2–6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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