TIL306, TIL307 NUMERIC DISPLAYS WITH LOGIC SLBS001 – D1034, JUNE 1982 – REVISED SEPTEMBER 1992 SOLID-STATE DISPLAYS WITH INTEGRAL TTL MSI CIRCUIT CHIP FOR USE IN ALL SYSTEMS WHERE THE DATA TO BE DISPLAYED IS THE PULSE COUNT • • • • • • • 6,9-mm (0.270-Inch) Character Height High Luminous Intensity TIL306 Has Left Decimal TIL307 Has Right Decimal Easy System Interface • Wide Viewing Angle Internal TTL MSI Chip and Counter, Latch, Decoder, and Driver Constant-Current Drive for Light-Emitting Diodes mechanical data These assemblies consist of display chips and a TTL MSI chip mounted on a header with a red molded plastic body. Multiple displays may be mounted on 11,43-mm (0.450-inch) centers. PIN ASSIGNMENTS Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 QB QC QD QA LS RBI MAX-COUNT GND Pin 9 Pin 10 Pin 11 Pin 12 Pin 13 Pin 14 Pin 15 Pin16 PCEI SCEI RBO CLR DP BI CLK VCC 3,56 (0.140) 2,79 (0.110) Seating Plane (see Note A) 4,32 (0.170) MIN CL of Pin 1 4,42 (0.174) 3,81 (0.150) 0,56 (0.022) 0,46 (0.018) DIA All Pins 7,87 (0.310) 7,62 (0.300) 1,52 (0.060) 1,02 (0.040) Decimal Point TIL307 CL of Pin 1 1 2,54 (0.100) 4,45 (0.175) 3,94 (0.155) 4 Places 6,45 (0.254) 10° 0,66 (0.026) 0,66 (0.026) 3,81 (0.150) 3,81 (0.150) 26,67 (1.050) 25,65 (1.010) 2,54 (0.100) T.P. 14 Places (see Note C) Logic Chip Decimal Point TIL306 TIL306 TIL307 A F TOP VIEW G E D.P. A B C D F G E B C D D.P. 10,67 (0.420) 9,65 (0.380) ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES NOTES: A. Lead dimensions are not controlled above the seating plane. B. Centerlines of character segments and decimal points are shown as dashed lines. Associated dimensions are nominal. C. The true-position pin spacing is 2,54 mm (0.100 inch) between centerlines. Each centerline is located with 0,26 mm (0.010 inch) of its true longitudinal position relative to pins 1 and 16. Copyright 1992, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 MAX-COUNT QA Count Enable Inputs QC QB QD VCC To Logic Chip SCEI PCEI QA T QA CLK POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 QB T QB a f QC T QC b g e c d QD T QD dp CLR DP BI LS Synchronous BCD counter, 4-bit latch, decoder/driver, seven-segment LED display with decimal point RBI RBO TL306 has left decimal. TL307 has right decimal. TL306, TL307 NUMERIC DISPLAYS WITH LOGIC Latch Outputs SLBS001–D1034, JUNE 1982–REVISED SEPTEMBER 1992 2 logic diagram TIL306, TIL307 NUMERIC DISPLAYS WITH LOGIC SLBS001 – D1034, JUNE 1982 – REVISED SEPTEMBER 1992 description These internally-driven seven-segment light-emitting-diode (LED) displays contain a BCD counter, a four-bit latch, and a decoder/LED driver in a single 16-pin package. A description of the functions of the inputs and outputs of these devices are in the terminal function table. The TTL MSI circuits contain the equivalent of 86 gates on a single chip. Logic inputs and outputs are completely TTL/DTL compatible. The buffered inputs are implemented with relatively large resistors in series with the bases of the input transistors to lower drive-current requirements to one-half of that required for a standard Series 54/74 TTL input. The serial-carry input, actually two internal loads, is rated as one standard series 54/74 load. The logic outputs, except RBO, are active pullup, and the latch outputs QA, QB, QC, and QD are each capable of driving three standard Series 54/74 loads at a low logic level or six loads at a high logic level while the maximum-count output is capable of driving five Series 54/74 loads at a low logic level or ten loads at a high logic level. The RBO node with passive pull-up serves as a ripple-blanking output with the capability to drive three Series 54/74 loads. The LED driver outputs are designed specifically to maintain a relatively constant on-level current of approximately 7 mA through each LED segment and decimal point. All inputs are diode clamped to minimize transmission-line effects, thereby simplifying system design. Maximum clock frequency is typically 18 MHz and power dissipation is typically 600 mW with all segments on. The display format is as follows: The displays may be interconnected to produce an n-digit display with the following features: • • • • • • • • • Ripple-blanking input and output for blanking leading or trailing zeroes Floating-decimal-point logic capability Overriding blanking for suppressing entire display or pulse modulation of LED brightness Dual count-enable inputs for parallel lookahead and serial ripple logic to build high-speed fully synchronous, multidigit counter systems with no external logic, minimizing total propagation delay from the clock to the last latch output Provision for ripple-count cascading between packages Positive-edge-triggered synchronous BCD counter Parallel BCD data outputs available to drive logic processors or remote slaved displays simultaneously with data being displayed Latch strobe input allows counter to operate while a previous data point is displayed Reset-to-zero capability with clear input. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TIL306, TIL307 NUMERIC DISPLAYS WITH LOGIC SLBS001 – D1034, JUNE 1982 – REVISED SEPTEMBER 1992 Terminal Functions PIN DESCRIPTION NAME NO. BLANKING Input (BI) 14 When high, will blank (turn off) the entire display and force RBO low. Must be low for normal display. May be pulsed to implement intensity control of the display. CLEAR Input (CLR) 12 When low, resets and holds counter at 0. Must be high for normal counting. CLOCK Input (CLK) 15 Each positive-going transition will increment the counter provided that the circuit is in the normal counting mode (serial and parallel count enable inputs low, clear input high). DECIMAL POINT Input (DP) 13 Must be high to display decimal point. The decimal point is not displayed when this input is low or when the display is blanked. 4, 1, 2, 3 The BCD data that drives the decoder can be stored in the 4-bit latch and is available at these outputs for driving other logic and/or processors. The binary weights of the outputs are: QA = 1, QB = 2, QC = 4, QD = 8. LATCH Outputs (QA, QB, QC, QD) LATCH STROBE Input (LS) 5 When low, data in latches follow the data in the counter. When high, the data in the latches are held constant, and the counter may be operated independently. MAX-COUNT Output 7 Will go low when the counter is at 9 and serial count enable input is low. Will return high when the counter changes to 0 and will remain high during counts 1 through 8. Will remain high (inhibited) as long as serial count enable input is high. PARALLEL Count Enable Input (PCEI) 9 Must be low for normal counting mode. When high, counter will be inhibited. Logic level must not be changed when the clock is low. RIPPLE-BLANKING Input (RBI) 6 When the data in the latches is BCD 0, a low input will blank the entire display and force the RBO low. This input has no effect if the data in the latches is other than 0. RIPPLE-BLANKING Output (RBO) 11 Supplies ripple-blanking information for the ripple-blanking input of the next decade. Provides a low if BI is high, or if RBI is low and the data in the latches is BCD 0; otherwise, this output is high. This pin has a resistive pullup circuit suitable for performing a wire-AND function with any open-collector output. Whenever this pin is low, the entire display will be blanked; therefore, this pin may be used as an active-low blanking input. SERIAL Count Enable Input (SCEI) 10 Must be low for normal counting mode, also must be low to enable maximum count output to go low. When high, counter will be inhibited and maximum count output will be driven high. Logic level must not be changed when the clock is low. absolute maximum ratings over operating case temperature range (unless otherwise noted) Supply voltage, VCC (see Note 1): Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Nonrepetitive peak, tw ≤ 100 ms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating case temperature range, TC (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 85°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 25°C to 85°C NOTES: 1. Voltage values are with respect to network ground terminal. 2. Case temperature is the surface temperature of the plastic measured directly over the integrated circuit. Forced-air cooling may be required to maintain this temperature. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TIL306, TIL307 NUMERIC DISPLAYS WITH LOGIC SLBS001 – D1034, JUNE 1982 – REVISED SEPTEMBER 1992 recommended operating conditions Supply voltage, VCC Low logic level Normalilzed N lil d fan-out f t from f each h output, t t N (to Series 54/74 integrated circuits) High logic level MIN NOM MAX UNIT 4.75 5 5.25 V QA, QB, QC, QD, RBO 3 MAX-COUNT Output 5 RBO 3 QA, QB, QC, QD 6 MAX-COUNT Output Clock pulse duration, duration tw(clock) ( l k) High logic level 25 Low logic level 55 Clear pulse duration, tw(clear) Latch strobe pulse duration, tw(latch strobe) Setup time, time tsu 10 25 ns 45 ns PCEI/SCEI↑ before CLOCK↑ 30 CLEAR↑ before CLOCK↑ 60 Operating case temperature, TC ns ns 0 70 °C electrical characteristics at 25°C case temperature PARAMETER VIH VIL High-level input voltage VIK Input clamp voltage TEST CONDITIONS MIN TYP† RBO VCC = 4.75 V, VCC = 4.75 V, II = – 12 mA IOH = – 120 µA High-level output voltage QA, QB, QC, QD MAX-COUNT Output VCC = 4.75 V, VCC = 4.75 V, IOH = – 240 µA IOH = – 400 µA VOL Low-level output voltage g (see Note 3) QA, QB, QC, QD, RBO VCC = 4.75 V, VCC = 4.75 V, IOL = 4.8 mA IOL = 8 mA II Input current at maximum input voltage VCC = 5.25 V, VI = 5.5 V MAX-COUNT Output RBO node VCC = 5.25 V, VI = 2.4 V – 0.12 Short circuit output current Short-circuit ICC Supply current Iv Luminous intensity y (see Note 5) λp Wavelength at peak emission V 1 mA 40 µA – 0.5 mA 20 µA – 1.6 RBO node VCC = 5.25 V, VI = 0.4 V – 1.5 Other inputs IOS V 04 0.4 SCEI Low-level input current V V Other inputs IIL 0.8 – 1.5 2.4 SCEI High-level input current UNIT V Low-level input voltage VOH IIH MAX 2 QA, QB, QC, QD MAX-COUNT Output 5 25 V VCC = 5.25 VCC = 5 V, –9 – 27.5 – 15 – 55 See Note 4 VCC = 5 V DP Input mA – 0.8 VCC = 5.25 V, Figure – 2.4 See Note 4 120 200 mA mA 700 1200 µcd 40 70 µcd 660 nm ∆λ Spectral bandwidth VCC = 5 V, See Note 4 20 nm † All typical values are at VCC = 5 V. NOTES: 3. This parameter is measured with the display blanked (BI = 5 V). 4. These parameters are measured with all LED segments and the decimal point on. 5. Luminous intensity is measured with a light sensor and filter combination that approximates the CIE (International Commission on Illumination) eye-response curve. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TIL306, TIL307 NUMERIC DISPLAYS WITH LOGIC SLBS001 – D1034, JUNE 1982 – REVISED SEPTEMBER 1992 switching characteristics, VCC = 5 V, TC = 25°C PARAMETER† fmax tPLH tPHL tPLH tPHL tPLH tPHL tPHL FROM (INPUT) TO (OUTPUT) SERIAL lookahead TEST CONDITIONS CL = 15 pF,, See Figure 1 MAX COUNT Output MAX-COUNT CLK Input QA, QB, QC, QD RL = 560 Ω,, 23 28 F CL = 15 pF, See Figure 1 1 2 kΩ, kΩ RL = 1.2 38 57 VCC RL From Output Under Test CL = 15 pF NOTES: A. CL includes probe and jig capacitance. B. All diodes are 1N3064. Figure 1. Load Circuit POST OFFICE BOX 655303 18 29 PARAMETER MEASUREMENT INFORMATION 6 12 26 CLR Input QA, QB, QC, QD † fmax ≡ Maximum clock frequency tPLH ≡ Propagation delay time, low-to-high-level output tPHL ≡ Propagation delay time, high-to-low-level output Output TYP 12 MAX COUNT Output MAX-COUNT CLK Input MIN • DALLAS, TEXAS 75265 MAX UNIT MHz ns ns ns ns TIL306, TIL307 NUMERIC DISPLAYS WITH LOGIC SLBS001 – D1034, JUNE 1982 – REVISED SEPTEMBER 1992 TYPICAL CHARACTERISTICS RELATIVE LUMINOUS INTENSITY vs CASE TEMPERATURE RELATIVE SPECTRAL CHARACTERISTICS 0.9 Luminous Intensity Relative to Value at TC = 25 °C 1 VCC = 5 V TC = 25°C Relative Luminous Intensity 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 600 620 640 660 680 700 4 VCC = 5 V 2 1 0.7 0.4 0.2 0.1 0 10 20 30 40 50 60 70 TC – Case Temperature – °C λ – Wavelength – nm Figure 2 Figure 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 PACKAGE OPTION ADDENDUM www.ti.com 23-Apr-2005 PACKAGING INFORMATION Orderable Device Status (1) TIL306 OBSOLETE 16 TBD Call TI Call TI TIL307 OBSOLETE 16 TBD Call TI Call TI TIL307 OBSOLETE 16 TBD Call TI Call TI TIL307 OBSOLETE 16 TBD Call TI Call TI Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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