TI TSL214

× SOES002E − JUNE 1991 − REVISED MARCH 1994
•
•
•
•
•
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(TOP VIEW)
On-Board 64-Bit Static Shift Register
Extendable Data I/O for Expanding the
Number of Sensors
VDD
SI
CLK
AO
GND
SO
VDD
Analog Buffer With Sample and Hold for
Analog Output Over Full Clock Period
Single-Supply Operation
500-kHz Shift Clock
14-Pin Clear Plastic Package
•1
14
2
13
3
12
4
11
5
10
6
9
7
8
NC
NC
GND
NC
NC
NC
NC
NC −No internal connection
Advanced LinCMOS Technology
description
The TSL214 integrated opto sensor consists of 64 charge-mode pixels arranged in a 64 × 1 linear array. Each
pixel measures 120 µm × 70 µm, with 125-µm center-to-center spacing. Operation is simplified by internal logic
requiring only clock and start-integration-pulse signals.
The TSL214 is intended for use in a wide variety of applications including linear and rotary encoding, bar-code
reading, edge detection and positioning, and contact imaging.
The TSL214 is supplied in a 14-pin dual-in-line clear plastic package.
Caution. These devices have limited built-in gate protection. The leads should be shorted together or the device placed in conductive
foam during storage or handling to prevent electrostatic damage to the MOS gates.
Advanced LinCMOS is a trademark of Texas Instruments Incorporated.
Copyright  1994, Texas Instruments Incorporated
! "#$ %!&
% "! "! '! ! !( !
%% )*& % "!+ %! !!$* $%!
!+ $$ "!!&
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77251−1443
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× SOES002E − JUNE 1991 − REVISED MARCH 1994
functional block diagram
VDD
1, 7
1
2
3
64 Pixels
Sense
Node
Dark Pixel
Reference
Generator
Pixel Selector Switch
S1
S2
S3
Pixel
Buffer
Differential
Amplifier
Pixel
Buffer
Sample
and
Hold
Output
Buffer
RL
(external load)
S64
Nonoverlapping
Clock Generator
Reset
Q1
CLK 3
Q2
Q3
64-Bit Shift Register
SI 2
6 SO
Q64
Clock
Generator
Terminal Functions
TERMINAL
NAME
DESCRIPTION
NO.
AO
4
Analog output
CLK
3
Clock input. CLK controls charge transfer, pixel output, and reset.
GND
5, 12
Ground (substrate). All voltages are referenced to the substrate.
NC
8 −11,
13, 14
No internal connection
SI
2
Serial input. SI defines the end of the integration period and initiates the pixel output sequence.
6
Serial output. SO provides a signal to drive the SI input of another TSL214 sensor for cascading.
SO
VDD
2
4 AO
1, 7
Supply voltage. VDD supplies power to the analog and digital circuits.
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× SOES002E − JUNE 1991 − REVISED MARCH 1994
detailed description
sensor elements
The line of sensor elements, called pixels, consists of 64 discrete photosensing areas. Light energy striking a
pixel generates electron-hole pairs in the region under the pixel. The field generated by the bias on the pixel
causes the electrons to collect in the element while the holes are swept into the substrate. The amount of charge
accumulated in each element is directly proportional to the amount of incident light and the integration time.
device operation
Operation of the 64 × 1 array sensor consists of two time periods: an integration period during which charge is
accumulated in the pixels and an output period during which signals are transferred to the output. The integration
period is defined by the interval between serial-input (SI) pulses and includes the output period (see Figure 1).
The required length of the integration period depends upon the amount of incident light and the desired output
signal level.
sense node
On completion of the integration period, the charge contained in each pixel is transferred in turn to the sense
node under the control of the clock (CLK) and SI signals. The signal voltage generated at this node is directly
proportional to the amount of charge and inversely proportional to the capacitance of the sense node.
reset
An internal reset signal is generated by the nonoverlapping clock generator (NOCG) and occurs every clock
cycle. Reset establishes a known voltage on the sense node in preparation for the next charge transfer. This
voltage is used as a reference level for the differential signal amplifier.
shift register
The 64-bit shift register controls the transfer of charge from the pixels to the output stages and provides timing
signals for the NOCG. The SI signal provides the input to the shift register and is shifted under direct control
of the clock. The input is shifted out to the serial output (SO) on the 64th clock cycle. This SO pulse can then
be used as the SI pulse for another device for multiple-unit operation.
The output period is initiated by the presence of the SI pulse coincident with a rising edge of the clock
(Figures 1 and 2). The output voltage corresponds to the level of the first pixel after settling time (ts) and remains
constant for a valid time (tv). A voltage corresponding to each succeeding pixel is available at each rising edge
of the clock. The output period ends on the rising edge of the 65th clock cycle, at which time the output assumes
a high-impedance state. The 65th clock cycle terminates the output of the last pixel and clears the shift register
in preparation for the next SI pulse. To achieve minimum integration time, the SI pulse may be present on the
66th rising edge of the clock to immediately reinitiate the output phase. Once the output period is initiated by
an SI pulse, the clock must be allowed to complete 65 positive-going transitions in order to reset the internal
logic to a known state.
sample-and-hold
The sample-and-hold signal generated by the NOCG is used to hold analog output voltage of each pixel constant
until the next pixel is clocked out. The signal is sampled while the clock is high and held constant while the clock
is low.
nonoverlapping clock generators
The NOCG circuitry provides internal control signals for the sensor, including reset and pixel-charge sensing.
The signals are synchronous and are controlled by the outputs of the shift register.
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× SOES002E − JUNE 1991 − REVISED MARCH 1994
initialization
Initialization of the sensor elements may be necessary on power up or during operation after any period of clock
or SI inactivity exceeding the integration time. The initialization phase consists of 12 to 15 consecutively
performed output cycles and clears the pixels of any charge that may have accumulated during the inactive
period.
multiple unit operation
Multiple sensor devices may be connected together in a serial or parallel configuration. The serial connection
is accomplished by connecting analog outputs (AO) together and connecting the SO terminal of each sensor
device to the SI terminal of the next device. The SI signal is applied to the first device only, with each succeeding
device receiving its SI from the SO of the preceding device. For n cascaded devices, the SI pulse is applied to
the first device after every n•64 positive-going clock transitions. A common clock signal is applied to all the
devices simultaneously. Parallel operation of multiple devices is accomplished by supplying clock and SI signals
to all the devices simultaneously. The output of each device is then separately used for processing.
output enable
The internally generated output-enable signal enables the output stage of the sensor during the output period
(64 clock cycles). During the remainder of the integration period, the output stage is in the high-impedance state,
which allows output interconnections of multiple devices without interference.
CLK
64 Cycles
Clock Continues or Remains Low After 65th Cycle
64 Cycles
tint
SI
SO
AO
4
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
Analog
Output Period
Figure 1. Timing Waveforms
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ÇÇÇÇ
ÇÇÇÇ
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× SOES002E − JUNE 1991 − REVISED MARCH 1994
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
(see Note 1)†
Supply voltage range, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Digital output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VDD +0.5 V
Digital output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 mA
Digital input current range, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA to 20 mA
Operating case temperature range, TC (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −10°C to 85°C
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −25°C to 85°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Voltage values are with respect to GND.
2. Case temperature is the surface temperature of the plastic measured directly over the integrated circuit.
recommended operating conditions
MIN
Supply voltage, VDD
Input voltage, VI
NOM
Low-level input voltage, VIL
V
0
VDD
VDD
V
Wavelength of light source, λ
VDD × 0.3
750
Clock input frequency, fclock
10
Pulse duration, CLK low, tw(CLKL)
UNIT
5.5
VDD × 0.7
0
High-level input voltage, VIH
MAX
4.5
500
50
Hold time, SI after CLK↑, th(SI)
50
External resistive load, AO, RL
ms
ns
ns
Ω
330
Total number of TSL214 outputs connected together
kHz
µs
5
Setup time, SI before CLK↑, tsu(SI)
V
nm
1
Sensor integration time, tint (see Figures 1 and 2)
V
10
Operating free-air temperature, TA
0
•
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70
°C
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× SOES002E − JUNE 1991 − REVISED MARCH 1994
electrical characteristics at VDD = 5 V, TA = 25°C, fclock = 180 kHz, λp = 565 nm, RL = 330 Ω,
CL = 330 pF, tint = 5 ms, Ee = 20 µW/cm2 (unless otherwise noted) (see Note 3)
PARAMETER
TEST CONDITIONS
MIN
TYP
Low-level output voltage
MAX
0.1
High-level output voltage
IO = 0
Analog output voltage saturation level
Ee = 60 µW/cm2
Analog output voltage (white, average over 64 pixels)
4.4
Output voltage (white) change with change in VDD
Ee = 0
VDD = 5 V ± 5%
Dispersion of analog output voltage
See Note 4
Linearity of analog output voltage
See Note 5
Pixel recovery time
See Note 6
Supply current
High-level input current
IDD (average)
VI = VDD
Low-level input current
VI = 0
V
V
3
3.4
1.75
Analog output voltage (dark, each pixel)
UNIT
V
2.2
0.25
V
0.4
V
±2%
±7.5%
0.85
1.15
Input capacitance
25
40
ms
4
9
mA
0.5
µA
0.5
µA
5
pF
NOTES: 3. The input irradiance (Ee) is supplied by an LED array with λp = 565 nm.
4. Dispersion of analog-output voltage is the maximum difference between the voltage from any single pixel and the average output
voltage from all pixels of the device under test.
5. Linearity of analog-output voltage is calculated by averaging over 64 pixels and measuring the maximum deviation of the voltage
at 2 ms and 3.5 ms from a line drawn between the voltage at 2.5 ms and the voltage at 5 ms.
6. Pixel recovery time is the time required for a pixel to go from the analog-output voltage (white, average over 64 pixels) level to
analog-output voltage (dark, each pixel) level or vice versa after a step change in light input.
operating characteristics, VDD = 5 V, TA = 25°C, fclock = 500 kHz, RL = 330 Ω, CL = 330 pF,
tint = 5 ms, Ee = 20 µW/cm2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tr(SO)
tf(SO)
Rise time, SO
25
ns
Fall time, SO
25
ns
tpd(SO)
ts
Propagation delay time, SO
See Figure 2 and Note 7
Settling time
ns
1
tv
Valid time
NOTE 7: Clock duty cycle is assumed to be 50%.
6
70
1/2 fclock
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77251−1443
µs
µs
× SOES002E − JUNE 1991 − REVISED MARCH 1994
PARAMETER MEASUREMENT INFORMATION
VDD
0.1 µF†
1
VDD
2
SI
3
CLK
7
VDD
SI
AO
4
AO
RL = 330 Ω
CLK
CL = 330 pF
TSL214
SO
GND
5
6
SO
GND
12
† Supply bypass capacitor with short leads should be placed as close to the device as possible.
TEST CIRCUIT
tw(CLKL)
1
2
64
65
5V
2.5 V
CLK
0V
tsu(SI)
5V
50 %
SI
0V
th(SI)
tpd(SO)
50 %
SO
ts
ts
AO
tpd(SO)
90 %
Pixel 1
90 %
50 %
10 %
tr(SO)
10 %
90 %
tf(SO)
90 %
Pixel 64
tv
OPERATIONAL WAVEFORMS
Figure 2. Test Circuit and Operational Waveforms
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× SOES002E − JUNE 1991 − REVISED MARCH 1994
TYPICAL CHARACTERISTICS
INTEGRATION TIME
vs
IRRADIANCE, FOR CONSTANT
AVERAGE ANALOG OUTPUT VOLTAGE
NORMALIZED RESPONSIVITY
vs
WAVELENGTH OF INCIDENT LIGHT
10
1
VDD = 5 V
λ = 565 nm
Analog Output Voltage (white,
average over (64 pixels) = 2.2 V
TA = 25°C
0.4
f int − Integration Time − ms
Normalized Responsivity
9
0.1
0.04
VDD = 5 V
TA = 25° C
tint = 3 ms
0.01
400
8
7
6
5
4
3
2
500
600
700
800
900
1000 1100
λ − Incident Wavelength − nm
0
5
10
15 20 25 30 35 40
Ee − Irradiance − µW/cm2
Figure 3
OUTPUT VOLTAGE
vs
INTEGRATION TIME
300
1
VDD = 5 V
TA = 25°C
0.9
250
Output Voltage Normalized to 2.2 V
Analog Output Voltage (dark) − mV
50
Figure 4
ANALOG OUTPUT VOLTAGE (DARK)
vs
INTEGRATION TIME
200
150
100
VDD = 5 V
Ee = 0
TA = 25°C
50
1
2
Ee = 20 µW/cm2
0.8
0.7
Ee = 10 µW/cm2
0.6
0.5
0.4
0.3
Ee = 2 µW/cm2
0.2
0.1
0
4
7 10
40
20
0
70 100
2
3
tint − Integration Time − ms
Figure 5
8
45
4
5
6
7
8
tint − Integration Time − ms
Figure 6
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10
× SOES002E − JUNE 1991 − REVISED MARCH 1994
MECHANICAL DATA
This assembly consists of a sensor chip mounted on a printed circuit board in a clear molded plastic package. The
distance between the top surface of the package and the surface of the sensor is nominally 1,0 mm (0.040 inch).
No. 1 Sensor
Element
Designation per JEDEC Std. 30:
PDIP-T14
1,91 (0.075) MAX
Both Rows
10,67 (0.420)
9,65 (0.380)
CL
Bottom View
3,6 (0.142) NOM
(first pixel
location)
19,30 (0.760)
18,29 (0.720)
14
1
13
2
12
3
11
4
10
5
9
6
8
7
2,16 (0.085) MAX
4 Places
2,54 (0.100) T.P.
12 Places
(see Note A)
Sensor Center Line
7,87 (0.310)
7,37 (0.290)
3,43 (0.135)
2,79 (0.110)
3,94 (0.155)
3,68 (0.145)
CL
CL
Seating Plane
4,6 (0.180) MIN
0,508 (0.020)
0,406 (0.016)
Dia All Pins
ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTE A: The true-position spacing is 2,54 mm (0.100 inch) between lead centerlines. Each pin centerline is located within 0,25 mm (0.010 inch)
of its true longitudinal positions.
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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77251−1443
9
× SOES002E − JUNE 1991 − REVISED MARCH 1994
10
•
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS
77251−1443
× SOES002E − JUNE 1991 − REVISED MARCH 1994
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77251−1443
11
PACKAGE OPTION ADDENDUM
www.ti.com
2-Mar-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
TSL214
OBSOLETE
XCEPT
COB
Pins Package Eco Plan (2)
Qty
14
TBD
Lead/Ball Finish
Call TI
MSL Peak Temp (3)
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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