SLS SL74LV14D

TECHNICAL DATA
SL74LV14
Hex Schmitt-Trigger Inverter
The 74LV14 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT14.
The 74LV14 provides six inverting buffers with Schmitt-trigger action.
•
•
•
•
Wide Operating Voltage: 1.0 to 5.5 V
Optimized for Low Voltage applications: 1.0 to 3.6 V
Accepts TTL input levels between VCC =2.7 V and VCC =3.6 V
Low input current
ORDERING INFORMATION
SL74LV14N Plastic
SL74LV14D SOIC
SL74LV14
Chip
TA = -40° ÷ 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
FUNCTION TABLE
Input
Output
A
Y= A
L
H
H
L
PIN 14 =VCC
PIN 7 = GND
SLS
System Logic
Semiconductor
1
SL74LV14
MAXIMUM RATINGS *
Symbol
Parameter
VCC
DC supply voltage (Referenced to GND)
IIK* 1
Value
Unit
-0.5 ~ +7.0
V
DC input diode current
±20
mA
2
DC output diode current
±50
mA
3
DC output source or sink current
-bus driver outputs
±25
mA
DC GND current for types with
- bus driver outputs
±50
mA
ICC
DC VCC current for types with
- bus driver outputs
±50
mA
PD
Power dissipation per paskade, plastic DIP+
SOIC package+
750
500
mW
-65 ~ +150
°C
260
°C
IOK*
Io*
IGND
Tstg
Storage temperature
TL
Lead temperature, 1.5 mm from Case for 10 seconds
(Plastic DIP ), 0.3 mm (SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C
SOIC Package: : - 8 mW/°C from 70° to 125°C
* 1: VI < -0.5V or VI > VCC+0.5V
* 2: Vo < -0.5V or Vo > VCC+0.5V
* 3: -0.5V < Vo < VCC+0.5V
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VIN, VOUT
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, t f
Input Rise and Fall Time
1.0 V≤VCC <2.0 V
2.0 V≤VCC <2.7 V
2.7 V≤VCC <3.6 V
3.6 V≤VCC ≤5.5 V
Min
Max
Unit
1.0
5.5
V
0
VCC
V
-40
+125
°C
0
0
0
0
500
200
100
50
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range
GND≤(VIN or VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.
SLS
System Logic
Semiconductor
2
SL74LV14
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbol
Parameter
Test
Conditions
VCC
Guaranteed Limit
Unit
min
max
-40°C ÷ 85°C
min
max
VIT+
Positive-Going
Input Threshold
Voltage
VO ≥ VOH
1.2
2.0
2.7
3.0
3.6
4.5
5.5
0.45
0.85
1.05
1.25
1.55
1.75
2.15
0.95
1.35
1.95
2.15
2.35
3.10
3.80
0.4
0.8
1.0
1.2
1.5
1.7
2.1
1.0
1.4
2.0
2.2
2.4
3.15
3.85
0.4
0.8
1.0
1.2
1.5
1.7
2.1
1.0
1.4
2.0
2.2
2.4
3.15
3.85
V
VIT-
Negative-Going
Input Threshold
Voltage
VO ≤ VOL
1.2
2.0
2.7
3.0
3.6
4.5
5.5
0.2
0.35
0.45
0.65
0.85
0.95
1.15
0.65
0.85
1.35
1.45
1.75
1.95
1.15
0.15
0.3
0.4
0.6
0.8
0.9
1.1
0.7
0.9
1.4
1.5
1.8
2.0
2.26
0.15
0.3
0.4
0.6
0.8
0.9
1.1
0.7
0.9
1.4
1.5
1.8
2.0
2.26
V
VH
Hysteresis
Voltage
VO ≥ VOH
1.2
2.0
2.7
3.0
3.6
4.5
5.5
0.2
0.25
0.35
0.45
0.45
0.45
0.65
0.65
0.75
1.05
1.15
1.15
1.35
1.45
0.15
0.3
0.4
0.6
0.8
0.9
1.1
0.7
0.9
1.4
1.5
1.8
2.0
2.6
0.15
0.3
0.4
0.6
0.8
0.9
1.1
0.7
0.9
1.4
1.5
1.8
2.0
2.6
V
High-Level
Output Voltage
VI = VIH –or
VIL
1.2
2.0
2.7
3.0
3.6
4.5
5.5
1.05
1.85
2.55
2.85
3.45
4.35
5.35
-
1.0
1.8
2.5
2.8
3.4
4.3
5.3
-
1.0
1.8
2.5
2.8
3.4
4.3
5.3
-
V
3.0
2.48
-
2.40
-
2.20
-
V
4.5
3.70
-
3.60
-
3.50
-
1.2
2.0
2.7
3.0
3.6
4.5
5.5
-
0.15
0.15
0.15
0.15
0.15
0.15
0.15
-
0.2
0.2
0.2
0.2
0.2
0.2
0.2
-
0.2
0.2
0.2
0.2
0.2
0.2
0.2
VOH
VO ≤ VOL
IO = -100
µA
VOH
High-Level
Output Voltage
VI = VIH –or
VIL
V
25°C
-40°C ÷ 125°C
min
max
IO = -6.0
mA
VI = VIH –or
VIL
IO = -12.0
mA
VOL
Low-Level
Output Voltage
VI = VIH –or
VIL
IO = 100 µA
SLS
System Logic
Semiconductor
V
3
SL74LV14
DC ELECTRICAL CHARACTERISTICS (continuation)
Symbol
VOL
Parameter
Low-Level
Output Voltage
Test
Conditions
Guaranteed Limit
VCC
V
25°C
min
max
-40°C ÷ 85°C
min
max
Unit
-40°C ÷ 125°C
min
max
VI = VIH –or
IO = 6.0 mA
3.0
-
0.33
-
0.40
-
0.50
VI = VIH –or
VIL
4.5
-
0.40
-
0.55
-
0.65
V
IO = 12.0
mA
µA
IIL
Low-Level Input
Leakage Current
VI=0 V
5.5
-
-0.1
-
-1.0
-
-1.0
IIH
High-Level
Input Leakage
Current
VI= VÑÑ
5.5
-
0.1
-
1.0
-
1.0
ICC
Quiescent
Supply Current
(per Package)
VI=0 Â or
VÑÑ
5.5
-
4.0
-
20
-
40
µA
Additional
Quiescent
Supply Current
on input
VI = VÑÑ 0.6V
2.7
3.6
-
0.2
-
0.5
-
0.85
mA
ICC1
IO = 0 µA
IO = 0 µA
.
SLS
System Logic
Semiconductor
4
SL74LV14
AC ELECTRICAL CHARACTERISTICS (CL=50 pF, t LH =t HL = 2.5 ns, RL=1 kÙ)
Symbol
tPLH, t PHL
CI
Parameter
Propagation
Delay, Input A
to Output Y
(Figure 1 )
VCC
1.2
2.0
2.7
3.0
4.5
min
-
max
VI=0 V or
V1
tLH = tHL
=2.5 ns
Ñ L = 50 pF
RL = 1 kÙ
5.5
-
7.0
-
7.0
-
7.0
pF
5.5
-
30
-
30
-
30
pF
25°C
V
Input
Capacitance
CPD
Guaranteed Limit
Test
Conditions
VI=0 V or
VÑÑ
tH L
ns
V1
0.9
VX
0.1
Unit
-40°C ÷ 125°C
min
max
200
48
35
28
23
tL H
0.9
Input À
150
28
22
17
14
-40°C ÷ 85°C
min
max
170
37
28
22
18
VX
0.1
tP H L
GND
tP L H
V OH
Output Y
VY
VY
VO L
VX=0.5 VCC
Figure 1. Switching Waveforms
VC C
VI
VO
PULSE
GENERATOR
RT
DEVICE
UNDER
TEST
Termination resistance RT – should
be equal to ZOUT of pulse
generators
CL
RL
Figure 2. Test Circuit
SLS
System Logic
Semiconductor
5
SL74LV14
CHIP PAD DIAGRAM SL74LV14
1.33 ±0.03
1.42 ±0.03
13
12
11
10
09
08
14
07
01
02
03
04
05
06
Chip marking
IN74LV14
(x=0.130; y=0.130)
Pad size 0.108 x 0.108 mm (Pad size is given as per metallization layer)
Thickness of chip 0.46 ± 0,02 mm
PAD LOCATION
Pad No
01
02
03
04
05
06
07
08
09
10
11
12
13
14
SLS
System Logic
Semiconductor
Symbol
A1
Y1
A2
Y2
A3
Y3
GND
Y4
A4
Y5
A5
Y6
A6
VCC
X
0.130
0.130
0.381
0.616
0.881
1.116
1.115
1.115
1.115
0.804
0.569
0.378
0.143
0.130
Y
0.463
0.230
0.126
0.126
0.126
0.126
0.631
0.846
1.181
1.194
1.194
1.194
1.194
0.813
6