TECHNICAL DATA IN74LV00 Quad 2-Input NAND Gate The IN74LV00 is low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT00A. The IN74LV00 provides the 2-Input NAND function. • • • Optimized for Low Voltage applications: 1.2 to 3.6 V Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V Low Input Current ORDERING INFORMATION IN74LV00N Plastic IN74LV00D SOIC IZ74LV00 Chip TA = -40° ? 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM 01 1A 02 1B 04 2A 05 2B 09 3A 10 3B 12 4A 13 4B 1Y 2Y 3Y 03 06 08 FUNCTION TABLE PIN 14 =VCC PIN 7 = GND 4Y 11 Input Output A B Y =A *B L L H L H H H L H H H L H - high level L - low level INTEGRAL 1 IN74LV00 MAXIMUM RATINGS * Symbol VCC IIK * DC supply voltage (Referenced to GND) Value Unit -0.5 ÷ +5.0 V 1 DC input diode current ±20 mA 2 DC output diode current ±50 mA DC output source or sink current -bus driver outputs ±25 mA DC VCC current for types with - bus driver outputs ±50 mA DC GND current for types with - bus driver outputs ±50 mA Power dissipation per package, plastic DIP+ SOIC package+ 750 500 mW -65 ÷ +150 °C 260 °C IOK * IO * Parameter 3 ICC IGND PD Tstg TL Storage temperature Lead temperature, 1.5 mm from Case for 10 seconds (Plastic DIP ), 0.3 mm (SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C SOIC Package: : - 8 mW/°C from 70° to 125°C * 1: VI < -0.5 or VI > VCC+0.5V * 2: Vo < -0.5 or Vo > VCC+0.5V * 3: -0.5V < Vo < VCC+0.5V RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, t f Input Rise and Fall Time VCC =1.2 V VCC =2.0 V VCC =3.0 V VCC =3.6 V Min Max Unit 1.2 3.6 V 0 VCC V -40 +125 °C 0 0 0 0 1000 700 500 400 ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. INTEGRAL 2 IN74LV00 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Symbol Parameter Test Conditions Guaranteed Limit VCC, V -40°C ÷ 85°C 25°C Unit -40°C ÷ 125°C min max min max min max VIH High-Level Input Voltage 1.2 2.0 3.0 3.6 0.9 1.4 2.1 2.5 - 0.9 1.4 2.1 2.5 - 0.9 1.4 2.1 2.5 - V VIL Low -Level Input Voltage 1.2 2.0 3.0 3.6 - 0.3 0.6 0.9 1.1 - 0.3 0.6 0.9 1.1 - 0.3 0.6 0.9 1.1 V VOH High-Level Output VI = VIL or VIH Voltage IO = -50 µÀ 1.2 2.0 3.0 3.6 1.1 1.92 2.92 3.52 - 1.0 1.9 2.9 3.5 - 1.0 1.9 2.9 3.5 - V VI = VIL or VIH IO = -6.0 mÀ 3.0 2.48 - 2.34 - 2.20 - V Low-Level Output VI = VIL or VIH Voltage IO = 50 µÀ 1.2 2.0 3.0 3.6 - 0.09 0.09 0.09 0.09 - 0.1 0.1 0.1 0.1 - 0.1 0.1 0.1 0.1 V VI = VIL or VIH IO = 6.0 mÀ 3.0 - 0.33 - 0.4 - 0.5 V VOL IIL Low-Level Input Leakage Current VI = 0 V 3.6 - -0.1 - -1.0 - -1.0 µA IIÍ High-Level Input VI = VCC Leakage Current 3.6 - 0.1 - 1.0 - 1.0 µA IÑÑ Quiescent Supply VI = 0  or VCC Current IO = 0 µÀ (per Package) 3.6 - 2.0 - 20 - 40 µA INTEGRAL 3 IN74LV00 AC ELECTRICAL CHARACTERISTICS (CL=50 pF, t LH = t HL = 6.0 ns, VIL=0V, VIH=VCC) Symbol Parameter Guaranteed Limit VCC V 25°C Unit -40°C ? 85°C -40°C ? 125°C min max min max min max tTHL, (t TLH) Output Transition Time, Any Output (Figure 1) 1.2 2.0 * - 60 16 10 - 75 20 13 - 90 24 15 tPHL, (t PLH) Propagation Delay, Input A to Output Y (Figure 1) 1.2 2.0 * - 135 23 14 - 405 28 18 - 405 34 21 Input Capacitance 3.0 - 7.0 - - - - CI CPD Power Dissipation Capacitance (Per Inverter) ns pF ÒÀ=25°Ñ, VI=0V?VCC pF 44 * - VCC= (3.3±0.3) V Used to determine the no-load dynamic power consumption: PD = CPDVCC2fI+ ?(C LVCC2fo), fI-input frequency, fo- output frequency (MHz) ?(C LVCC2fo) – sum of the outputs t HL tLH 0.9 Input À, B V CC 0.9 V1 V1 0.1 0.1 tP LH GND t PHL 0.9 Output Y VCC 0.9 V1 V1 0.1 0.1 GND tTHL t TLH V1 = 0.5 V CC Figure 1. Switching Waveforms VCC VI VO PULSE GENERATOR RT DEVICE UNDER TEST CL RL Termination resistance RT should be equal to ZOUT pulse generators Figure 2. Test Circuit INTEGRAL 4 IN74LV00 CHIP PAD DIAGRAM IZ74LV00 12 10 11 08 13 1.20 ±0.03 09 Chip marking 25LV00 (x=1.009; y=0.727) 14 07 01 02 06 04 03 05 1.23 ±0.03 Pad size 0.108 x 0.108 mm (Pad size is given as per metallization layer) Thickness of chip 0.46 ± 0,02 mm PAD LOCATION Pad No Symbol X Y 01 02 03 04 05 06 07 08 09 10 11 12 13 14 A1 B1 Y1 A2 B2 Y2 GND Y3 A3 B3 Y4 A4 B4 Vcc 0.111 0.111 0.504 0.672 1.009 1.009 1.009 1.009 1.009 0.672 0.504 0.336 0.111 0.111 0.287 0.119 0.111 0.111 0.111 0.277 0.447 0.806 0.974 0.974 0.974 0.974 0.772 0.618 INTEGRAL 5