CXA1645P/M RGB Encoder For the availability of this product, please contact the sales office. Description The CXA1645P/M is an encoder IC that converts analog RGB signals to a composite video signal. This IC has various pulse generators necessary for encoding. Composite video outputs and Y/C outputs for the S terminal are obtained just by inputting composite sync, subcarrier and analog RGB signals. It is best suited to image processing of personal computers and video games. 24 pin SOP (Plastic) 24 pin DIP (Plastic) Features • Single 5V power supply • Compatible with both NTSC and PAL systems • Built-in 75Ω drivers (RGB output, composite video output, Y output, C output) • Both sine wave and pulse can be input as a subcarrier. • Built-in band pass filter for the C signal and delay line for the Y signal • Built-in R-Y and B-Y modulator circuits • Built-in PAL alternate circuit • Burst flag generator circuit • Half H killer circuit Structure Bipolar silicon monolithic IC Absolute Maximum Ratings 14 V • Supply voltage VCC • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –65 to +150 °C • Allowable power PD CXA1645P 1250 mW dissipation CXA1645M 780 mW Recommended Operating Condition Supply voltage VCC1, 2 5.0 ± 0.25 V Applications Image processing of video games and personal computers Block Diagram and Pin Configuration GND2 ROUT GOUT BOUT CVOUT VCC2 FO YTRAP YOUT COUT VREF IREF 24 23 22 21 20 19 18 17 16 15 14 13 75 DRIVER 75 DRIVER VIDEO OUT R-OUT G-OUT Y/C MIX B-OUT REGULATOR DELAY SYNC ADD MATRIX CLAMP BPF R-Y Modulator B-Y Modulator CLAMP CLAMP SIN-PULSE CLAMP PHASE SHIFTER PULSE GEN 1 2 3 4 5 6 7 8 9 10 11 12 GND1 RIN GIN BIN NC SCIN NPIN BFOUT YCLPC SYNCIN NC VCC1 Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E93411A41-ST CXA1645P/M ∗ Externally applied voltage Pin Description Pin No. 1 Symbol GND1 Pin voltage Equivalent circuit Description Ground for all circuits other than RGB, composite video and Y/C output circuits. The leads to GND2 should be as short and wide as possible. 0V∗ VCC1 2 3 4 100µ Black level when clamped 2.0V 180µ RIN GIN BIN 100µ 2 3 4 Analog RGB signal inputs. Input 100%, = 1Vp-p (max.). To minimize clamp error, input at as low impedance as possible. ICLP turns ON only in the burst flag period. GND1 ICLP 5 NC NO CONNECTION VCC1 6 SCIN — Subcarrier input. Input 0.4 to 0.5Vp-p sine wave or pulse. 20P 20k 6 129 Refer to Notes on Operation, Nos. 3 and 5. 20k 100µ 2.5V GND1 VCC1 80k 68k 7 NPIN 1.7V Pin for switching between NTSC and PAL modes NTSC: VCC, PAL: GND 7 3k 32k GND1 VCC1 8 BFOUT H : 3.6V L : 3.2V BF pulse monitoring output. Incapable of driving a 75Ω load. 8 129 25µ 25µ GND1 –2– CXA1645P/M Pin No. Symbol Pin voltage Equivalent circuit Description VCC1 129 9 YCLPC 2.5V Pin to determine the Y signal clamp time constant. Connect to GND via a 0.1µF capacitor. 9 1.6V 5µ GND1 VCC1 40k 10 SYNC IN 2.2V Composite sync signal input. Input TTLlevel voltages. L ( ≤ 0.8V): SYNC period H ( ≥ 2.0V) 10 4k 2.2V GND1 12 VCC1 Power supply for all circuits other than RGB, composite video and Y/C output circuits. Refer to Notes on Operation. Nos. 4 and 10. 5.0V∗ VCC1 13 IREF Pin to determine the internal reference current. Connect to GND via a 47kΩ resistor. 2.0V 13 129 50µ GND1 VCC1 14 VREF 4.0V Internal reference voltage. Connect a decoupling capacitor of approximately 10µF. 14 Refer to Notes on Operation, Nos. 4 and 7. GND1 –3– CXA1645P/M Pin No. Symbol Pin voltage Equivalent circuit Description VCC2 VCC1 600µ 15 COUT 2.2V Chroma signal output. Capable of driving a 75Ω load. 15 10k 20k Refer to Notes on Operation, Nos. 6 and 9. GND2 VCC2 VCC1 600µ 16 YOUT Black level 1.3V Y signal output. Capable of driving a 75Ω load. 16 10k 20k Refer to Notes on Operation, Nos. 6 and 9. GND2 VCC1 17 YTRAP Black level 1.6V 8.5k 17 1.5k 0.5P GND1 Input resistance 1.5kΩ Pin for reducing cross color caused by the subcarrier frequency component of the Y signal. When the CVOUT pin is in use, connect a capacitor or a capacitor and an inductor in series between YTRAP and GND. Decide capacitance and inductance, giving consideration to cross color and the required resolution. No influence on the YOUT pin. Refer to Notes on Operation, No. 8. VCC1 18 FO Internal filter fo adjustment pin. Connect to GND via the following resistor according to the NTSC or PAL mode. NTSC: 20kΩ (±1%) PAL : 16kΩ (±1%) 2.0V 18 129 50µ GND1 –4– CXA1645P/M Pin No. 19 Symbol VCC2 Equivalent circuit Pin voltage Description Power supply for RGB, composite video and Y/C output circuits. Decouple this pin with a large capacitor of 10µF or above as a high current flows. 5.0V∗ Refer to Notes on Operation, Nos. 4 and 10. VCC2 VCC1 600µ CVOUT Composite video signal output. Capable of driving a 75Ω load. 20 20k 10k 20 Black level 1.2V Refer to Notes on Operation, Nos. 6 and 9. GND2 500µ 21 22 23 BOUT GOUT ROUT Black level 1.7V VCC2 VCC1 Analog RGB signal outputs. Capable of driving a 75Ω load. 21 22 23 5.5k Refer to Notes on Operation, Nos. 6 and 9. 200µ GND1 GND2 24 GND2 Ground for RGB, composite video and Y/C output circuits. The leads to GND1 should be as short and wide as possible. 0V∗ –5– CXA1645P/M Electrical Characteristics (Ta = 25°C, VCC = 5V, See the Electrical Characteristics Measurement Circuit.) S1 Item Current consumption 1 Symbol S2 S3 S4 S5 Measu RIN rement SYNC GIN SCIN NPIN FO point IN BIN ICC1 ICC1 2V SG4 5V SG5 20k Current consumption 2 ICC2 ICC2 Measurement Conditions Min. No input signal, SG5: CSYNC TTL level, SG4: SIN wave 3.58MHz 0.5Vp-p Fig. 1 Typ. Max. Unit 31 mA 12 (R, G, BOUT) RGB output voltage RGB output frequency characteristics D VO (R) SG1 VO (G) SG2 VO (B) SG3 F fC (R) SG1 D fC (G) SG2 fC (B) SG3 E 2V 2V E F SG1 to SG3: DC direct coupling 2.5VDC, 1.0Vp-p f = 200kHz Pin 9 = Clamp voltage Fig. 2 0.64 SG1 to SG3: DC direct coupling 2.5VDC, 1.0Vp-p f = 200kHz/5MHz Pin 9 = Clamp voltage Fig. 3 –3.0 0.71 0.78 Vp-p dB (YOUT & CVOUT) Output sync level VO (YS1/2) R100%: Y level VO (YR1/2) B100%: Y level SG1 0V VO (YG1/2) to SG3 VO (YB1/2) White 100%: Y level VO (YW1/2) G100%: Y level Output frequency characteristics fC (Y1/2) 5V SG5 20k B/C SG1 to 0V SG3 5V 2V 20k SG1 to SG3: 100% color bar input, 1.0Vp-p (Max.) SG5: CSYNC TTL level Fig. 4 SG1 to SG3: DC direct coupling 2.5VDC, 1.0Vp-p f = 200kHz/5MHz Pin 9 = Clamp voltage Fig. 3 ∗ Clamp voltage: voltage appearing at Pin 9 when CSYNC is input. –6– 0.26 0.29 0.33 Vp-p 0.17 0.21 0.26 V 0.35 0.42 0.49 V 0.065 0.08 0.095 V 0.6 0.71 0.82 V –3.0 dB CXA1645P/M S1 Item Symbol S2 S3 S4 S5 Measu RIN rement SYNC GIN SCIN NPIN FO point IN BIN Measurement Conditions Min. Typ. Max. Unit 0.2 0.25 0.3 Vp-p 2.84 3.16 3.48 94 104 114 2.65 2.95 3.25 231 241 251 2.01 2.24 2.47 337 347 357 deg 2.5 2.75 3.2 µs 0.4 0.6 0.75 µs 20 mVp-p (COUT & CVOUT) Burst level R chroma ratio R phase G chroma ratio G phase B chroma ratio B phase VO (BN1/2) R/BN1/2 SG1 to SG3: 100% color bar input, 1.0Vp-p (Max.) SG4: SIN wave, 3.58MHz 0.5Vp-p SG5: CSYNC TTL level Fig. 5 θR1/2 G/BN1/2 θG1/2 B/BN1/2 SG1 to SG4 SG3 5V SG5 20k θB1/2 Burst width tW (B) 1/2 Burst position tD (B) 1/2 A/C Carrier leak PAL burst level ratio VL1/2 SG1 to SG4 SG3 5V SG5 20k K (BP1/2) θPAL1/2 PAL burst phase SG1 to SG4 GND SG5 16k SG3 θPAL1/2 SG1 to SG3: No signal, SG4: SIN wave, 3.58MHz 0.5Vp-p SG5: CSYNC TTL level 3.58MHz component measured. Fig. 6 SG1 to SG3: No signal, SG4: SIN wave, 4.43MHz 0.5Vp-p SG5: CSYNC TTL level Fig. 6 ∗ Clamp voltage: voltage appearing at Pin 9 when CSYNC is input. –7– 0.9 1.0 1.1 125 135 145 215 225 235 deg deg deg 1 24 –8– 2V 2 0.1µ SG2 S1 21 4 S1 75 20 5 NC 6 PAL ICC2 A 16k S2 SG4 SIN 0.5Vp-p PAL 7 17 NC 8 5V S3 NTSC NC 75 B 9 2V 0.1µ 75 A 10 S4 BPF 75 DRIVER 15 75 220µ PULSE GEN B-Y Modulator R-Y Modulator 75 DRIVER 16 75 220µ SYNC ADD PHASE SHIFTER Y/C MIX CLAMP 18 20k NTSC S5 SIN-PULSE DELAY 47µ 5V 19 VIDEO OUT 0.01µ 75 C 220µ 0.1µ SG3 CLAMP B-OUT 75 220µ 75 D SG1 to SG3 100% color bar (1Vp-p max.) 0.1µ SG1 S1 3 CLAMP G-OUT R-OUT CLAMP 22 75 75 23 220µ 75 E 220µ 75 F MATRIX Electrical Characteristics Measurement Circuit SG5 CSYNC NC 11 0.1µ 5V 0.01µ 12 13 ICC1 A REGULATOR 14 10µ 47k 47µ CXA1645P/M CXA1645P/M Measuring Signals and Output Waveforms SG5 SG4 SYNC IN 0.5Vp-p SCIN f = 3.58MHz 2.0V SG5 SYNC IN 64µs 2.0V 64µs 0.8V 0.8V 4.5µs 10µs SG1 RIN 1.0Vp-p SG2 GIN 1.0Vp-p 4.5µs Fig. 1 SG3 1.0Vp-p BIN SG1 to 3 RIN 2.5V GIN BIN 1.0Vp-p BC point YOUT CVOUT f = 200kHz Vo (YB) Vo (YW) Vo (YG) Vo (YS) Vo (YR) DEF point Fig. 4 ROUT VO GOUT BOUT Fig. 2 SG4 0.5Vp-p SCIN f = 3.58MHz SG1 to 3 SG5 RIN 2.5V GIN BIN 1.0Vp-p SYNC IN f = 200kHz/5MHz DEF BC point ROUT GOUT BOUT YOUT CVOUT 2.0V 64µs 0.8V 4.5µs 10µs VO Fig. 3 fc = 20log SG1 RIN 1.0Vp-p SG2 GIN 1.0Vp-p Vo (5MHz) Vo (200kHz) SG3 BIN 1.0Vp-p SG4 C point CVOUT 0.5Vp-p SCIN f = 3.58MHz/ 4.43MHz VO (BN) VO (CG) VO (CB) VO (CR) tD (B) 64µs 0.8V A point 4.5µs Vo (BN) VO (BN) Vo (BN) C point tW (B) CVOUT K (BP) = Vo (BN) B/BN = COUT VL VL G/BN = tW (B) 2.0V SG4 SYNC IN R/BN = Vo (BN) Vo (BN) Vo (BN) A point COUT Fig. 6 –9– VO (CB) VO (CG) VO (CR) Fig. 5 VO (CR) VO (BN) VO (CG) VO (BN) VO (CB) VO (BN) CXA1645P/M Application Circuit (NTSC mode) R OUT 220µ G OUT 220µ B OUT VCC CV OUT 220µ C OUT 220µ 220µ 75 75 23 24 75 21 22 20k 75 19 20 1% G-OUT 75 NC 18 VIDEO OUT R-OUT 10µ 47k 220µ 0.1µ ∗ 47µ 0.01µ +5V Y OUT 16 15 75 DRIVER 75 DRIVER 17 Y/C MIX 75 B-OUT 13 14 REGULATOR DELAY SYNC ADD MATRIX CLAMP BPF R-Y Modulator B-Y Modulator CLAMP CLAMP CLAMP 2 3 4 1 6 5 9 8 7 NC 0.1µ PULSE GEN PHASE SHIFTER SIN-PULSE NC 10 0.1µ 0.1µ 0.01µ G IN 47µ SYNC IN SCIN R IN 12 11 NC 0.1µ B IN ∗ Metal film resistor ±1% Application Circuit (PAL mode) R OUT 220µ G OUT 220µ B OUT VCC CV OUT 220µ C OUT 220µ 0.01µ 75 24 75 23 75 16k 75 21 22 ∗ 1% 47µ 20 19 18 R-OUT G-OUT 10µ 47k 220µ 75 75 17 Y/C MIX VIDEO OUT Y OUT 220µ NC +5V 16 15 75 DRIVER 75 DRIVER B-OUT 0.1µ 13 14 REGULATOR SYNC ADD CLAMP MATRIX DELAY BPF R-Y Modulator B-Y Modulator 1 CLAMP CLAMP CLAMP 2 3 4 SIN-PULSE 5 6 7 NC 0.1µ PULSE GEN 9 10 12 11 NC 0.1µ 0.1µ 0.1µ G IN 8 NC SYNC IN SCIN R IN PHASE SHIFTER B IN 0.01µ 47µ ∗ Metal film resistor ±1% Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 10 – CXA1645P/M Description of Operation Analog RGB signals input from Pins 2, 3 and 4 are clamped in the clamping circuit and output from Pins 23, 22 and 21, respectively. The matrix circuit performs operations on each input signal, generating luminance signal Y and color difference signals R-Y and B-Y. The Y signal enters the delay line to adjust delay time with the color signal C. Then, after addition of the CSYNC signal input from Pin 10, the Y signal is output from Pin 16. A subcarrier input from Pin 6 is input to the phase shifter, where its phase is sfited 90°. Then, the subcarrier is input to the modulators and modulated by the R-Y signal and the B-Y signal. Modulated subcarriers are mixed, sent to the band pass filter to eliminate higher harmonic components and finally output from Pin 15 as the C signal. At the same time, Y and C signals are mixed and output from Pin 20 as the composite video signal. Burst Signal The CXA1645P/M generates burst signals at the timing shown below according to the composite sync signal input. H synchronization SYNC IN (TTL level) tD (B) tW (B) C VIDEO OUT Burst signal COUT tD (B) tW (B) V synchronization ODD SYNC IN EVEN ODD C VIDEO OUT EVEN Burst signal Synchronizing signal – 11 – CXA1645P/M Notes on Operation Be careful of the following when using the CXA1645P/M. 1. This IC is designed for image processing of personal computers and video games. When using the IC in other video devices, make thorough investigations on image quality. 2. Be sure that analog RGB signals are input at 1.0Vp-p maximum and have low enough impedance. High impedance may affect color saturation, hue, etc. Inputting RGB signals in excess of 1.3Vp-p may disable the clamp operation. 3. The SC input (Pin 6) can be either a sine wave or a pulse in the range from 0.4 to 5.0Vp-p. However, when a pulse is input, its phase may be shifted several degrees from that of the sine wave input. In the IC, the SC input is biased to 1/2 VCC. Accordingly, when a 5.0Vp-p pulse is input and the duty factor deviates from 50%, High- and Low-level pulse voltages may exceed VCC and GND in the IC, which causes subcarrier distortion. In such a case, be very careful that the duty factor keeps to 50%. 4. When designing a printed circuit board pattern, pay careful attention to the routing of the VCC and GND leads. To decouple the VCC and VREF pins, use tantalum, ceramic or other capacitors with good frequency characteristics. Ground the capacitors by connections shown below as closely to each IC pin as possible. Try to design the leads as short and wide as possible. VCC1, VREF VCC2 ... GND1 ... GND2 Design the pattern so that VCC (or VREF) is connected to GND via a capacitor at the shortest distance. 5. SC and SYNC input pulses Attach a resistor and a capacitor to eliminate high-frequency components of SC (Figure A) and SYNC (Figure B) before input. Fig. A 2.2k Fig. B 2.2k 5P 47P Be careful not to input pulses containing high-frequency components. Otherwise, high-frequency components may flow into VCC, GND and peripheral parts, resulting in malfunctions. 6. Connecting an external resistor to the 75Ω driver output pin A capacitance of several dozen picofarads at each pin may start oscillation. To prevent oscillation, design the pattern so that a 75Ω resistor is mounted near the pin (see Figure C). Fig. C ∗ ∗ 75 ∗ Make these leads short. When any of the 75Ω driver output pins is not in use, leave it unconnected and design the pattern so that no parasitic capacitance is generated on the printed circuit board. – 12 – CXA1645P/M 7. VREF pin (Pin 14) Do not connect this pin to an external load that might cause AC signals to flow, which will cause IC malfunctions. When connecting a DC load, make sure that the current flowing from this pin is kept below 2mA. 8. YTRAP pin (Pin 17) There are the following two means of reducing cross color generated by subcarrier frequency components contained in the Y signal. (1) Install a capacitor of 30 to 68pF between YTRAP and GND. Decide the capacitance by conducting image evaluation, etc., giving consideration to both cross color and resolution. Relations between capacitance and image quality are as follows: (2) Capacitance 30pF ←→ 68pF Cross color Resolution Large ←→ Small High ←→ Low 17 C Connect a capacitor C and an inductor L in series between YTRAP and GND. When the subcarrier 1 frequency is fo, the values C and L are determined by the equation fo = . Decide the values in 2π √LC image evaluation, etc., giving consideration to both cross color and resolution. Relations between inductor values and image quality are as follows: Inductor value Small ←→ Large Cross color Resolution Large ←→ Small High ←→ Low 17 C L For instance, L = 68µH and C = 28pF are recommended for NTSC. It is necessary to select an inductor L with a sufficiently small DC resistance. Method (2) is more useful for achieving a higher resoluation than method (1). When an even higher resolution is necessary, use of the S terminal (YOUT and COUT) is recommended. 9. Driving COUT (Pin 15), YOUT (Pin 16), CVOUT (Pin 20), and B.G.R OUT (Pins 21, 22 and 23) outputs In Pin Description, "Capable of driving a 75Ω load" means that the pin can drive a capacitor +75Ω +75Ω load shown in the figure below. In other words, the pin is capable of driving a 150Ω load in AC. 75Ω 220µF PIN 75Ω Keep in mind that the pin is incapable of driving a 150Ω load in DC load in DC direct coupling. 10. This IC employs a number of 75Ω driver pins, so oscillation is likely to occur when measures described in Nos. 4 and 6 are not taken thoroughly. Be very careful of oscillation in printed circuit board design and carry out thorough investigations in the actual driving condition. – 13 – CXA1645P/M Package Outline Unit: mm CXA1645P + 0.1 05 0.25 – 0. 24PIN DIP (PLASTIC) 400mil + 0.4 30.2 – 0.1 10.16 13 1 + 0.3 8.5 – 0.1 24 0° to 15° 12 + 0.4 3.7 – 0.1 3.0 MIN 0.5 MIN 2.54 0.5 ± 0.1 1.2 ± 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE DIP-24P-01 LEAD TREATMENT SOLDER PLATING EIAJ CODE ∗DIP024-P-0400-A LEAD MATERIAL COPPER / 42 ALLOY PACKAGE WEIGHT 2.0g JEDEC CODE CXA1645M 24PIN SOP (PLASTIC) + 0.4 15.0 – 0.1 24 + 0.4 1.85 – 0.15 13 6.9 + 0.2 0.1 – 0.05 12 0.45 ± 0.1 1.27 + 0.1 0.2 – 0.05 0.5 ± 0.2 1 7.9 ± 0.4 + 0.3 5.3 – 0.1 0.15 ± 0.12 M PACKAGE STRUCTURE SONY CODE SOP-24P-L01 EIAJ CODE ∗SOP024-P-0300-A JEDEC CODE MOLDING COMPOUND EPOXY/PHENOL RESIN LEAD TREATMENT SOLDER PLATING LEAD MATERIAL COPPER ALLOY / 42ALLOY PACKAGE WEIGHT 0.3g – 14 –