CXA2060BS Y/C/RGB/D for PAL/NTSC/SECAM Color TVs For the availability of this product, please contact the sales office. Description The CXA2060BS is a bipolar IC which integrates the luminance signal processing, chroma signal processing, RGB signal processing, and sync and deflection signal processing functions for PAL/ NTSC/SECAM system color TVs onto a single chip. This IC includes deflection processing functions for wide-screen TVs. With a SECAM decoder and 1H delay line built in for PAL/SECAM, this IC can be used in configuring multi-color system TV set. 48 pin SDIP (Plastic) Features • Supports the I2C bus • 1H delay line and SECAM decoder • Supports NTSC/PAL-N/PAL-M systems with three crystal pins • Deflection compensation circuit for support of various wide modes • Count down system eliminates need for V oscillation frequency adjustment • Automatic identification of 50/60Hz vertical frequency (forced control possible) • Supports non-interlace display (even/odd selectable) • Automatic identification of PAL, NTSC and SECAM color systems (forced control possible) • Automatic identification of 4.43MHz/3.58MHz for crystal (forced control possible) • No adjustment of Y/C filter required • Three CV inputs, two Y/C inputs (Y/C input shared with CV input), one Y/C input supporting external comb filter, two RGB inputs • Dynamic picture/dynamic color circuit • AKB and gamma correction circuits • YS1 can be forcibly turned OFF • FSC output (shared with PAL-N crystal pin) Applications Color TVs (4:3, 16:9) Structure Bipolar silicon monolithic IC Absolute Maximum Ratings (Ta = 25°C, GND1, 2 = 0V) V • Supply voltage VCC1, 2 –0.3 to +12 • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –65 to +150 °C • Allowable power dissipation PD 1.5 W (When mounted on a 50mm × 50mm board) • Voltage at each pin –0.3 to VCC1, 2 + 0.3 V Operating Conditions Supply voltage VCC1, 2 9 ± 0.5 V Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E98631-PS 2 VIDEO SW <VIDEO SEL> <S SEL> MONITOR SW MON OUT 6 7 COMB C IN Y SW COMB Y IN 9 4 CVBS1/Y1 IN CVBS2/Y2 IN 41 C1 IN CHROMA Y ACC AMP CHROMA SW ACC AMP LIM AMP H SYNC SEP <HSS> <HMASK> <<RFLEVEL>> AKB <<IKR>> I2C BUS DECODER STATUS I/F DRIVE AMP <R/G/B DRIVE> 33 16 10 12 REG 19 IREF EW PARABOLA FUNC. <H SIZE> <TRAPEZIUM> <PIN AMP> <EW DC> <CORNERPIN> <S CORRECTION> <V LINEARITY> <EHT COMP> DAC SW VD SAW FUNC. <VON> <V SIZE> <V POSITION> 18 HD GEN. <HD W> PHASE DET. <H POSITION> <AFC BOW> <AFC ANGLE> HPROT <<HNG>> <ASPECT> <SCROLL> <UPPER VLIN> <LOWER VLIN> <V ZOOM> <V UNDER SCAN> WIDE SAW FUNC. ABL/PEAK LIM <ABL MODE> <ABL VTH> 29 31 30 32 5 H TIM GEN. <H BLK> <LEFT HBLK> <RIGHT HBLK> VSAW GEN. (50/60) VTIM SHARPNESS DL SHARPNESS AMP <SHARPNESS> <SHP F0> <PRE/OVER> VPROT <<VNG>> VM AMP (OFF YS/YM) 25 26 CLAMP RGB 1/2 27 17 <HOSC> HSAW GEN. <<FIELD ID>> LINE COUNTER V TIM GEN. <V UNDER SCAN> <Y DELAY> SECAM DL PAL/NTSC CLAMP DC TRAN <DC TRAN> Y/C MIX RGB CLAMP COLOR AMP <COLOR> <C OFF> AXIS <AXIS PAL> <AXIS NTSC> EYUV CLAMP YUV SW <Y SEL> YUV OUT <YUV OUT> 28 39 38 37 36 20 AFC <AFC GAIN> <FH HIGH> <<HLOCK>> <<HCENT>> <FIELD FREQ> <CD MODE> <INTERLACE> COUNT DOWN <TRAP OFF> V SYNC SEP <VSS> ATT SECAM VCO CAL. by 4.43MHz FILTER ALIGNMENT CAL. by fsc PLL SECAM FM DEMOD. TRAP PAL: 4.43MHz NTSC: 3.58MHz SECAM: 4.2 + 4.43MHz ACC DET. <BELL F0> BELL FILTER DPIC <DPIC> <AGING> 1H DELAYLINE (PAL/SECAM) SW NTSC/ PAL, SECAM KILLER <KILLER OFF> 15 VM OUT/V PROT AFC FIL BPF PAL: 4.43MHz NTSC: 3.58MHz <C BPF> LINE BLK DEEMPHASIS SECAM APED 1 ER-Y IN SCP CHROMA AMP 8 GND2 PAL/NTSC Y CLAMP 40 EB-Y IN YUV SW V TIM TV/C2 IN 43 APC FIL COLOR SYSTEM DISCRIMINATOR <XTAL> <ID LEVEL> <COL SYSTEM> <<APC LOCK>> <COL LOOP> <<PAL>> <NO COLOR> <<SECAM>> <ID STOP> <<XTAL ID>> <ID START> PAL/NTSC DEMOD. 44 X'TAL 3 46 EY IN R1 IN HP/PROTECT ACC DET. X'TAL 2 47 YS1 HD APC <HUE> X'TAL 1 48 VCC2 C VCO 4.433619MHz 3.579545MHz 3.575611MHz 3.582056MHz G1 IN YS1 SW <RGB SEL> G2 IN (R-YOUT) R2 IN (YOUT) PICTURE AMP <PICTURE> 45 BRIGHT CONT. <BRIGHT> B1 IN YM SW YS2 SW DYNAMIC COLOR <DYNAMIC C> YS2/YM I REF GND1 CUTOFF CONT. <R/G/B CUTOFF> B2 IN (B-YOUT) GAMMA AMP <GAMMA> CLAMP REG –2– VCC1 R/G/B BLK <PON> <R/G/B ON> Block Diagram ABL IN 11 EW 13 VD+ 14 VD– 34 SCL 35 SDA 22 R OUT 23 G OUT 24 B OUT 21 IK IN 3 42 ABL FIL CXA2060BS CXA2060BS Pin Configuration APED 1 48 X'TAL 1 C1 IN 2 47 X'TAL 2 ABL IN 3 46 X'TAL 3 CVBS1/Y1 IN 4 45 APC FIL V TIM 5 44 Vcc2 MON OUT 6 43 TV/C2 IN COMB C IN 7 42 ABL FIL Y CLAMP 8 41 COMB Y IN 9 40 GND2 GND1 10 39 CVBS2/Y2 IN EB-Y IN 38 ER-Y IN EW 11 I REF 12 37 EY IN VD+ 13 36 YUV SW VD– 14 35 SDA VM OUT/V PROT 15 34 SCL REG 16 33 Vcc1 SCP 17 32 R2 IN HP/PROTECT 18 31 G2 IN HD 19 30 B2 IN AFC FIL 20 29 YS2/YM IK IN 21 28 R1 IN R OUT 22 27 G1 IN G OUT 23 26 B1 IN B OUT 24 25 YS1 –3– CXA2060BS Pin Description Pin No. Symbol Equivalent circuit 1.93k 1k 1 APED Description Connects a capacitor for black peak hold of the dynamic picture feature (black extension). The 4.7µF capacitor is connected to GND. 1 94k 7.8k 8k 147 Chroma signal input. Input a chroma signal having a burst level of 300mVp-p via a 0.01µF capacitor. Normally the S pin signal is input. 2 2 C1 IN 50k 5.4V 130k 3 ABL IN 147 3 86k CVBS signal/luminance signal input. Input a 1Vp-p (100% white including sync) CVBS signal via a 1µF capacitor. Input the Y signal when a separated Y/C signal is input. 147 4 4 CVBS1/Y1 IN This pin is for both ABL control signal input and VD high-voltage correction signal input. High-voltage correction has linear control characteristics when this pin's voltage is in the approximate range of 1V and 8V. Control characteristics can be varied using the EHT_COMP control of the bus. ABL functions as a PIC/BRT-ABL (average value type). The threshold voltage at which ABL activates can be switched to either 3V or 1V depending on the bus. 50k 5.4V –4– CXA2060BS Pin No. Symbol Equivalent circuit Description 100µA V timing pulse output. This is a 0/5V negative polarity pulse. HSS/VSS can be monitored using the V TIM SEL register. 147 5 V TIM 5 25k 100µA 147 6 MON OUT 6 100µA 147 10p 25k 7 7 Output of the signal input from TV, CVBS1 or CVBS2 as selected by VIDEO SEL and S SEL of the bus. In the case of S pin input, a luminance signal and chroma signal are mixed and output. Output level is 2Vp-p including sync. COMB C IN 25k Chroma signal input from a comb filter. The input chroma signal is a 0.6Vp-p burst signal. 5.4V 4k 1.5k 8 8 Y CLAMP Connects a capacitor for luminance signal clamp. The 0.1µF capacitor is connected to GND. 4k 147 25k 9 9 COMB Y IN 25k 5.4V –5– Luminance signal input from a comb filter. The signal is input via a 1µF capacitor and has a level of 2Vp-p. (100% white including sync) CXA2060BS Pin No. 10 Symbol Equivalent circuit Description GND for 1HDL and deflection system circuit. GND1 1.2k 11 EW 11 V parabola wave output. 147 12 I REF 12 7.2k This pin is used to set the reference current within the IC. A 10kΩ resistor (metallic film resistor) having an error less than 1% is connected to GND. 2k 13 VD+ 13 V sawtooth wave output. The polarity of Pin 13 output and Pin 14 output are reversed. 2k 14 VD– 14 –6– CXA2060BS Pin No. Symbol Equivalent circuit Description Output of luminance signal differential waveform for VM (Velocity Modulation). The phase of VM output is synchronized to the phase of RGB output. It is approximately 250ns ahead of RGB output. This pin is also used for V protect signal input. When the large current (4mA) is forcibly drawn through this pin, all RGB output is blanked, and 1 is output to the status register VNG. 1k 15 147 VM OUT/ V PROT 15 1k 500 16 REG Decoupling capacitance for the regulator within the IC. The 47µF capacitor is connected to GND. 16 4.4k 50µA Sand castle pulse output. The sand castle pulse is a waveform superimposed with the burst gate pulse on the composite blanking pulse. 147 17 SCP 17 25k 147 10k 60k 18 18 HP/PROTECT 96k 50µA 100µA –7– H deflection pulse input for H AFC. The 5Vp-p pulse is input via a capacitor. Since this pin is also used to input an XRAY protect signal, a hold down function activates if this pin's voltage goes above a "7V cycle" and below 1V. If this occurs, HD output goes high impedance, RGB output is blanked, and 1 is output to the status register HNG. It is necessary to turn the IC's power OFF then ON again to cancel this status. CXA2060BS Pin No. Symbol Equivalent circuit Description 147 19 19 HD 20k H drive signal output. This is open collector output for the NPN transistor. 20k 147 20 1k 100k 20 Connects an AFC lag lead filter. CR is connected to GND. AFC FIL 100k 30k 147 21 IK IN 4k 21 3k CRT beam current input (cathode current IK). This current is converted into voltage within the IC. In order to eliminate any adverse effects exercised by CRT leak current (max. 100µA) for AKB operation, it is clamped at the V blanking interval. The AKB loop is activated by comparing the reference pulse component of this signal to the reference voltage within the IC. The RGB output cutoff can be varied using CUTOFF of the bus. The IK reference signal current can be controlled ±50% around a 13µA center. Since the beam current of the video section is large, be sure to attach a zener diode of about 4V to the pin to protect the IC. 200 22 23 24 R OUT G OUT B OUT 22 12k 23 24 2mA –8– RGB signal output. Outputs 3.0Vp-p during 100% white input. PICTURE: 3Fh DRIVE: 3Fh BRIGHT: 1Fh CXA2060BS Pin No. Symbol Equivalent circuit Description YS1 switch control pin. Selects RGB1 input. YS1 Vth: 0.7V This pin is also used as the slave address modification switch. If the voltage at this pin goes over 7V, the slave address is changed from 88h to 8Ah. SLAVE ADDRESS Vth: 7V 147 25 25 YS1 30k 26 26 27 28 B1 IN G1 IN R1 IN RGB1 signal input. A 0.7Vp-p (no-sync 100 IRE) signal is input via a 0.01µF capacitor. The input signal is clamped at the SCP burst timing. 27 28 1.2k 60k YS2/YM switch control pin. Selects RGB2 input. When operating at High level (YM Vth: 0.7V) as a YM switch the output signal undergoes 10dB attenuation. YS2 Vth: 2V 147 29 29 YS2/YM 13k 7k 30 30 31 32 B2 IN G2 IN R2 IN 31 32 100 1.2k 60k 33 RGB2 signal input. A 0.7Vp-p (no-sync 100 IRE) signal is input via a 0.01µF capacitor. The input signal is clamped at the SCP burst timing just as RGB1 IN. This pin becomes the YUV output pin based on the YUV OUT register. Be sure to pull up this pin by 10kΩ when used for YUV output. Power pin for the signal block and deflection block. Vcc1 –9– CXA2060BS Pin No. Symbol Equivalent circuit Description 34 34 4k SCL I2C bus standard SCL (Serial Clock) input. 10k 4k 35 35 SDA I2C bus standard SDA (Serial Data) input/output. 7.5k 7.5k 147 36 36 YUV SW 20k YUV SW control pin. Selects external YUV input. Vth: 0.7V This switch includes a function for forcibly turning OFF external Y input only using Y SEL of the bus. 37 37 EY IN 1.5k 40k 38 39 ER-Y IN EB-Y IN External Y/R-Y/B-Y signal input. Input is via a 0.01µF capacitor. EY IN: 0.7Vp-p (no sync) ER-Y IN: 0.735Vp-p (75% color bar) EB-Y IN: 0.931Vp-p (75% color bar) 38 39 1.5k 65k 40 GND pin for signal block circuits. GND2 – 10 – CXA2060BS Pin No. Symbol Equivalent circuit 147 41 41 CVBS2/Y2 IN 50k 5.4V Description CVBS signal/luminance signal input. A 1Vp-p signal (including sync) is input via a 1µF capacitor. Input the Y signal when a separated Y/C signal is input. 200k 20k 42 Connects the capacitor (4.7µF) forming the ABL control signal LPF to GND. 42 ABL FIL 1.2k 147 43 43 TV/C2 IN 50k 5.4V 44 Input of CVBS signal from a TV tuner or chroma signal. A 1Vp-p (including sync) CVBS signal or 300mVp-p burst chroma signal is input via a 1µF capacitor. Power pin for the signal block. Vcc2 4.6V 1k 45 APC FIL 1k 45 – 11 – Connects a chroma APC lag lead filter. CR is connected to GND. CXA2060BS Pin No. 46 Symbol X'tal 3 Equivalent circuit 46 2k 1.33k 47 X'tal 2 Description 47 2k Connects an APC crystal. The crystals should be connected as follows. X'tal 3: PAL-N crystal (3.58205625MHz) X'tal 2: NTSC crystal (3.579545MHz) X'tal 1: PAL/SECAM crystal (4.43361875MHz) or PAL-M crystal (3.57561149MHz) 1.33k Pin 46 can be switched for use as FSC output using the FSCSW register. 2V DC, 0.7Vp-p signal is output. 1k 48 X'tal 1 48 2k 1.33k – 12 – Current consumption 1 fHHIFR Horizontal free-running frequency 2 HD pulse width 3 4 – 13 – HBLKph = SCP (HBLKrise) – Hsync (cent) HBLKph HBLKw BGPph BGPw HP phase H BLK phase H BLK pulse width BGP phase BGP pulse width 6 7 8 9 10 BGPph = SCP (BGPrise) – Hsync (cent) HPph = HP (cent) – Hsync (cent) HPph HD pulse width 2 HDW = 1 tstr (HP) = 7.5µs, tHP = 12µs HDW = 0 FH HIGH = 0 HOSC = 7 (no input signal) FH HIGH = 1 VCC1, VCC2 = 9V Bus data: initial setting values Measurement conditions 5 HDw HDw fHFR Horizontal free-running frequency ICC Symbol 2 Sync deflection block items Item No. 17 18 19 33, 44 Measurement pin Set I2C bus registers to I2C Bus Register Initial Setting Values and measure them. Electrical Characteristics Measurement Conditions SCP Hsync HD 7.5µs HP Hsync HD HBLKph HDW HDW BGPph HPph H drive output frequency HBLKw BGPw 12µs Measure the current flowing into the pin. Measurement contents 2.8 3.4 9 –2.5 3.0 19 22.5 16.2 15.5 80 Min. 3.0 3.9 10 –1.75 3.7 20 24 16.7 15.7 125 Typ. 3.2 4.4 11 –1 4.4 21 25.5 17.2 15.9 170 Max. µs µs µs µs µs µs µs kHz kHz mA Unit Ta = 25°C, VCC1, VCC2 = 9V, GND1, GND2 = 0V CXA2060BS – 14 – VEWdc1 50Hz 50Hz VEWp-p VEWp-p = VEWdc1 – VEWdc0 EW drive output center voltage (50Hz) EW drive output amplitude (50Hz) 17 18 60Hz/50Hz ∆VSp-p = VSp-p2/VSp-p1 × 100 ∆VSp-p 16 60Hz – 50Hz ∆VSdc = VSdc2 – VSdc1 50Hz V drive output amplitude (60Hz) 14 ∆VSdc VSp-p1 V drive output amplitude (50Hz) 50Hz V drive output center voltage (60Hz) VSdc1 V drive output center voltage (50Hz) 13 C/D non-standard mode VTIMph = VTIM (fall) – Vsync (fall) Measurement conditions 15 VTIMw VTIM pulse width 12 VTIMph Symbol VTIM phase Item 11 No. 11 13 13 5 Measurement pin EW Vsync VD+ Vsync VD+ Vsync 1.5ms VTIM Vsync VEWdc0 10.6ms VSdc2 8.78ms VSdc1 10.6ms VTIMph VTIMw VEWdc1 Measurement contents VSp-p2 VSp-p1 450 3.9 99 –10 1.2 3.4 45 10 Min. 560 4.1 100 0 1.35 3.6 60 20 Typ. 670 4.3 101 10 1.5 3.8 75 30 Max. mV V % mV V V µs µs Unit CXA2060BS 23 VGBLK VBBLK G BLK voltage B BLK voltage 22 23 – 15 – 32 YUV OUT = 1 Vy = V1 – V0 Vy Luminance (Y) output 26 21 ∆IIK IK current (Min.) R CUTOFF = 0h G CUTOFF = 0h B CUTOFF = 0h IIKmin/IIKmax 25 21 IIK IK current (Max.) 24 R CUTOFF = Fh G CUTOFF = Fh B CUTOFF = Fh IIK = (Vrrf – V0)/4k 24 22 VRBLK R BLK voltage 11 Measurement pin 21 P ON = 0 20 Signal block items 60Hz/50Hz ∆VEWp-p ∆VEWp-p = (VEWdc2 – VEWdc20)/ VEWp-p × 100 EW DRIVE output amplitude (60Hz) 60Hz – 50Hz ∆VEWdc = VEWdc2 – VEWdc1 Measurement conditions ∆VEWdc Symbol EW DRIVE output center voltage (60Hz) Item 19 No. 1.5ms VEWdc20 VEWdc2 8.78ms V0 V0 V0 V1 Vrrf Vgrf Vbrf Vrrf Vgrf Vbrf 0.7V 22H 23H 24H 25H 26H 27H R2IN (YOUT) TV/C2IN IKIN (Min.) IKIN (Max.) TV/C2IN Measure the pin voltage. EW Vsync Measurement contents 610 27 15 0 0 0 97 –10 Min. 670 32 22 0.15 0.15 0.15 100 0 Typ. 730 37 29 0.3 0.3 0.3 103 10 Max. mV % µA V V V % mV Unit CXA2060BS – 16 – Vbrt Vr-y Vb-y SECAM color difference (R-Y) output SECAM color difference (B-Y) output 29 30 ∆G Symbol RGB BRIGHT voltage RGB amplitude ratio Item 28 27 No. ROUT TV/C2IN BOUT GOUT ROUT TV/C2IN 31 30 SECAM signal (75%) Vb-y = Vb1 – Vb0 VB1 VG1 VR1 0.7V Vgrf Vbrf Vbb Vgb Vrb Vb1 B2IN (B-YOUT) Vb0 Vr1 Vr0 R-YID RED CYAN R-Y AAA AAAA B-Y Vrrf 22H 23H 24H 25H 26H 27H VB0 VG0 VR0 Measurement contents B-YID BLUE YELLOW G2IN (R-YOUT) TV/C2IN BOUT 22, 23, 24 GOUT 22, 23, 24 Measurement pin SECAM signal (75%) Vr-y = Vr1 – Vr0 Black level – Ref. P. level Rch: Vbrtr = Vrb – Vrrf Gch: Vbrtg = Vgb – Vgrf Bch: Vbrtb = Vbb – Vbrf ∆GR = 20 × log ((VR1 – VR0)/Vy) ∆GG = 20 × log ((VG1 – VG0)/Vy) ∆GB = 20 × log ((VB1 – VB0)/Vy) Measurement conditions 880 690 –450 12 Min. 1040 800 –400 13.5 Typ. 1200 910 –350 15 Max. mV mV mV dB Unit CXA2060BS – 17 – VM output FSC output 34 35 Vfsc Vvm FSC SW = 1 3.58MHz 700mVp-p 46 15 30, 31 YUV OUT = 1, NTSC signal φoffset = tan–1 (4/7 × ((Vb1 – Vb0)/ (Vb2 – Vb0))) φoffset HUE center offset 33 30 PAL color difference (B-Y) output 32 PAL signal Vb-y = Vb1 – Vb0 Vr-y Vb-y Measurement pin 31 Measurement conditions PAL signal Vr-y = Vr1 – Vr0 Symbol PAL color difference (R-Y) output Item 31 No. FSCOUT VMOUT/VPROT TV/C2IN B2IN (B-YOUT) TV/C2IN B2IN (B-YOUT) Vb0 700mVp-p 90deg 700mVp-p ±90deg Vvm Vfsc 700mVp-p 3.58MHz AA AA AA AA Vb2 Vb1 AAA A AA Vb1 400mVp-p 0deg Vb0 Vr0 Vr1 AA A AAA 400mVp-p 0deg G2IN (R-YOUT) TV/C2IN Measurement contents 500 1.8 –6 430 900 Min. 900 2.3 0 500 1000 Typ. 1300 2.8 6 570 1100 Max. mV V Deg mV mV Unit CXA2060BS – 18 – HP HD Signal sources HP GEN H PROT 7µs delay 1µ 1µ Pseudo CRT 2.2k SCP OUT VM OUT 100 V PROT 100 51k E/W COMB Y IN 51k VD OUT 100 5 4 47µ 10k 4700p 12k 1k 1µ X'TAL 3 46 APC FIL 45 ABL IN CVBS1/Y1 IN R2 IN 32 17 SCP R1 IN 28 G1 IN 27 B1 IN 26 YS1 25 22 R OUT 23 G OUT 24 B OUT YS2/YM 29 B2 IN 30 21 IK IN 20 AFC FIL 19 HD G2 IN 31 Vcc1 33 16 REG 18 HP/PROTECT SCL 34 SDA 35 YUV SW 36 EY IN 37 ER-Y IN 38 EB-Y IN 39 GND2 40 15 VM OUT/V PROT 14 VD– 13 VD+ 12 I REF 11 EW 10 GND1 COMB Y IN Y CLAMP 8 9 ABL FIL 42 COMB C IN 7 CVBS2/Y2 IN 41 TV/C2 IN 43 Vcc2 44 X'TAL 2 47 C1 IN V TIM X'TAL 1 48 APED MON OUT COMB C IN 0.1µ 1µ 3 2 6 100 9V 0.01µ 1 MON OUT V TIM OUT CVBS1/Y1 IN ABL IN C1 IN 4.7µ 100 100 100 0.01µ 0.01µ 100 0.01µ 0.01µ 0.01µ 100 0.01µ 0.01µ 0.1µ 47µ 47µ 0.22µ PAL-N X'TAL NTSC X'TAL YS 1 RGB 1 IN YS2/YM RGB 2 IN Vcc + 9V SCL SDA YUV SW EXT YUV IN CVBS2/Y2 IN TV/C2 IN PAL/SECAM or PAL-M X'TAL 0.1µ 4.7µ 0.01µ 0.01µ 1µ 1µ 220p 10k 18p 18p 18p are all GND unless otherwise specified in the measurement column for Electrical Characteristics. Electrical Characteristics Measurement Circuit CXA2060BS from HDOUT 1k 1k 9V 5V 47µ 10k 2000p 2 1 16 VDD 3 1A 4 7 6 1B 5 TC4538BP 9 10 11 12 13 14 15 2T1 2000p 10k 2T2 HD OUT HP/PROTECT HP/PROTECT 2CD 1T1 2A 1T2 2B 1CD 2Q 8 VSS 2Q 1Q – 19 – 1Q HP GEN Circuit width 12µs delay 7µs CXA2060BS CXA2060BS Electrical Characteristics Measurement Conditions (I2C Bus Register Initial Settings) Register name Number of Initial setting value bits Description P ON 1 1 RGB output ON HD W 1 0 HD pulse width normal AXIS PAL 1 0 PAL axis forced OFF V ON 1 1 VD ON FH HIGH 1 1 fH normal YUV OUT 1 0 RGB2 IN input mode AGING 1 0 AGING OFF VIDEO SEL 2 0 Selects TV input S SEL 2 0 Selects TV/CVBS/BLK R ON 1 1 R output ON G ON 1 1 G output ON B ON 1 1 B output ON Y SEL 1 0 Enables YUVSW switching X'TAL 2 3 Automatically identified COL SYSTEM 2 3 Automatically identified COL LOOP 2 1 Automatically identified at 4STD C BPF 1 1 BPF ON C TRAP OFF 1 0 TRAP ON PICTURE 6 3Fh Max. value NO COLOR 1 0 No signal = NTSC FSC SW 1 0 FSC OFF COLOR 6 1Fh Center value C OFF 1 0 C signal ON KILLER OFF 1 0 Cancels KILLER OFF forced OFF mode HUE 6 1Fh SHP F0 1 0 F0 AXIS NTSC 1 0 NTSC JAPAN axis BRIGHT 6 1Fh DC TRAN 1 0 100% PRE/OVER 1 0 1:1 SHARPNESS 4 7h Center value R CUTOFF 4 7h Center value G CUTOFF 4 7h Center value B CUTOFF 4 7h Center value Center value 2.5MHz Center value – 20 – CXA2060BS Register name Number of Initial setting value bits Description Max. value R DRIVE 6 3Fh ABL MODE 1 1 PICTURE/BRIGHT shared mode ABL VTH 1 0 VTH = 3V G DRIVE 6 3Fh Max. value DY COL 1 0 Dynamic color OFF RGB SEL 1 0 Enables YS1 SW switching B DRIVE 6 3Fh GAMMA 2 0 Gamma correction OFF H OSC 4 7h Center value Y DELAY 4 7h Center value FIELD FREQ 2 0 Automatically identified (free-running 50Hz) CD MODE 2 0 Standard mode INTERLACE 2 0 Interlace mode H SS 1 0 1/3 from sync tip V SS 1 0 1/3 from sync tip V SIZE 6 1Fh H MASK 1 0 V POSITION 6 1Fh Center value AFC GAIN 2 1 Gain medium SCORRECTION 4 0 No correction V LINEARITY 4 7h 100% H SIZE 6 1Fh EW DC 1 0 H POSITION 6 1Fh Center value PIN AMP 6 1Fh Center value CORNER PIN 6 1Fh Center value TRAPEZIUM 4 7h Center value EHT COMP 4 Fh Max. correction level AFC BOW 4 7h Center value AFC ANGLE 4 7h Center value LEFT HBLK 4 7h Center value RIGHT HBLK 4 7h Center value ASPECT 6 2Fh Center value H BLK 1 0 H BLK width variability OFF VUNDERSCAN 1 0 OFF Max. value Center value Macrovision countermeasure OFF Center value DC level standard mode – 21 – CXA2060BS Register name Number of Initial setting value bits Description SCROLL 6 1Fh Center value V ZOOM 1 0 Zoom OFF UPPER VLIN 4 0 Linearity 100% LOWER VLIN 4 0 Linearity 100% V TIM SEL 2 0 V timing pulse output ID STOP 2 1 Center value ID START 2 2 Center value BELL F0 6 1Fh Center value ID LEVEL 2 1 Center value – 22 – – 23 – 51k 1µ 2.2k 51k 100 100 100 100 10k 0.1µ 100 47µ 100 100 1µ 4700p 1µ 12k 1k 100 100 COMB 1µ 10k 0.1µ 0.01µ 4.7µ COMB Y IN 24 B OUT 23 G OUT 22 R OUT 21 IK IN 20 AFC FIL 19 HD 18 HP/PROTECT YS1 25 B1 IN 26 G1 IN 27 R1 IN 28 YS2/YM 29 B2 IN 30 G2 IN 31 R2 IN 32 Vcc1 33 16 REG 17 SCP SCL 34 SDA 35 YUV SW 36 EY IN 37 ER-Y IN 38 EB-Y IN 39 GND2 40 15 VM OUT/V PROT 14 VD– 13 VD+ 12 I REF 11 EW 10 GND1 9 CVBS2/Y2 IN 41 ABL FIL 42 7 COMB C IN 8 Y CLAMP TV/C2 IN 43 Vcc2 44 APC FIL 45 X'TAL 3 46 MON OUT 6 5 V TIM 4 CVBS1/Y1 IN ABL IN X'TAL 2 47 2 C1 IN 3 X'TAL 1 48 1 APED 100 100 100 0.01µ 0.01µ 100 0.01µ 0.01µ 0.01µ 100 0.01µ 0.01µ 0.1µ 47µ 47µ 0.22µ PAL-N X'TAL NTSC X'TAL PAL/SECAM or PAL-M X'TAL 0.1µ 4.7µ 0.01µ 0.01µ 1µ 1µ 220p 10k 18p 18p 18p External RGB input 1 External RGB input 2 Vcc + 9V I 2C External YUV input CVBS/S input 2 Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. RGB output IK input X-ray protection signal input H drive output H deflection pulse input Sand castle pulse output VM output V sawtooth wave output V protect signal input V parabola wave output ABL/high voltage correction signal input MON output V timing pulse output CVBS/S input Application Circuit 30 31 32 10k 10k 10k Vcc During C DEC mode CXA2060BS CXA2060BS Register Table Sleve Address Slave ADD pin = GND Slave ADD pin = VCC 88H: Slave Receiver 89H: Slave Transmitter 8AH: Slave Receiver 8BH: Slave Transmitter Control Register (Sub Address 00000 results in Power-On-Reset) Sub Address Bit7 Bit6 Bit5 Bit4 xxx00000 P ON HD W AXIS PAL V ON xxx00001 VIDEO SEL S SEL xxx00010 X'TAL COL SYSTEM Bit3 Bit2 FH HIGH YUV OUT R ON G ON COL LOOP Bit1 Bit0 AGING 0 B ON Y SEL C BPF C TRAP OFF xxx00011 PICTURE NO COLOR FSCSW xxx00100 COLOR C OFF KILLER OFF xxx00101 HUE SHP F0 AXIS NTSC xxx00110 BRIGHT DC TRAN PRE/OVER xxx00111 SHARPNESS R CUTOFF xxx01000 G CUTOFF B CUTOFF xxx01001 R DRIVE ABL MODE ABL VTH xxx01010 G DRIVE DY COL RGB SEL xxx01011 B DRIVE GAMMA xxx01100 xxx01101 H OSC Y DELAY CD MODE FIELD FREQ xxx01110 V SIZE xxx01111 V POSITION xxx10000 INTERLACE H SS V SS ∗ H MASK AFC GAIN V LINEARITY S CORRECTION xxx10001 H SIZE ∗ EW DC xxx10010 H POSITION ∗ ∗ xxx10011 PIN AMP ∗ ∗ xxx10100 CORNER PIN ∗ ∗ xxx10101 TRAPEZIUM EHT COMP xxx10110 AFC BOW AFC ANGLE xxx10111 LEFT HBLK RIGHT HBLK xxx11000 ASPECT H BLK V UNDER SCAN xxx11001 SCROLL V ZOOM ∗ xxx11010 xxx11011 LOWER VLIN UPPER VLIN 0 0 VTIM SEL ID START ID STOP ID LEVEL BELL F0 xxx11100 Status Register 1st BYTE H LOCK 2nd BYTE H CENT IKR V NG X'TAL ID H NG NO VSYNC – 24 – APC LOCK PAL RF LEVEL SECAM FIELD ID 0 1 CXA2060BS Description of Registers Register Name (Number of Bits) Description 1. Y Signal Block Registers VIDEOSEL (2) Switches the VIDEO switch to select various input signals. Enabled when S SEL = 0 or 3. 0 = Selects TV input signal 1 = Selects CVBS1 input signal 2 = Selects CVBS2 input signal 3 = Mute S SEL (2) Selects Y/C input signals. Set VIDEO SEL to 3 (Mute) when S SEL is set to 1 or 2. 0 = Selects one of TV, CVBS1 or CVBS2 input, or Mute 1 = Selects Y1/C1 input 2 = Selects Y2/C2 input 3 = Selects Y/C input from comb filter (In this case, select one of TV, CVBS1 or CVBS2 input, or Mute for MON OUT.) C TRAP OFF (1) ON/OFF switch for Y block chroma trap filter Set the chroma trap filter to OFF (= 1) using microcomputer control as necessary when APC LOCK and SECAM status are 0. 0 = Trap filter ON 1 = Trap filter OFF SHP F0 (1) Switches sharpness f0 0 = 2.5MHz 1 = 3.0MHz SHARPNESS (4) Sharpness gain control 0h = –12dB 7h = +3.5dB Fh = +9dB DC TRAN (1) Switches the DC transmission rate 0 = 100% 1 = 85% PRE/OVER (1) Sharpness preshoot/overshoot control 0 = 1:1 1 = 2:1 – 25 – CXA2060BS Y DELAY (4) Y signal delay control 0h = MIN Fh = MAX Y SEL (1) Internal Y signal fixed mode ON/OFF switch 0 = YUV SW (Pin 36) standard operation (When Pin 36 = high, selects EY IN, ER-Y IN, EB-Y IN input) 1 = EY IN (Pin 37) input only disabled (When Pin 36 = high, selects internal Y, ER-Y IN, EB-Y IN input) AGING (1) White output aging mode ON/OFF switch (set to 0 at power ON) 0 = Aging mode OFF 1 = Aging mode ON (The Y block outputs a 60 IRE flat signal when there is no input signal.) 2. Chroma Signal Block Registers COLOR SYSTEM (2) Color system setting 0 = Forced PAL 1 = Forced SECAM 2 = Forced NTSC 3 = Automatic identification mode X'TAL (2) Crystal setting 0 = Forced X'TAL1 (PAL/SECAM or PAL-M crystal) 1 = Forced X'TAL2 (NTSC crystal) 2 = Forced X'TAL3 (PAL-N crystal) 3 = Automatic identification mode COLOR LOOP (2) Identification loop setting in color system automatic identification mode 0 = Automatically identifies the three systems PAL, SECAM and NTSC 4.43 (one crystal: 4.43 MHz) 1 = Automatically identifies the four systems PAL, SECAM, NTSC and NTSC 4.43 (two crystals: 4.43 and 3.58 MHz) 2 = Automatically identifies the three systems PAL-M, PAL-N, and NTSC (three crystals) 3 = Do not use HUE (6) Hue control (Phase control for the chroma demodulation axis. Enabled for NTSC only.) 0h = –35° 3Fh = +35° – 26 – CXA2060BS COLOR (6) Color gain control 0h = –30dB or less 1Fh = 0dB 3Fh = +6dB C OFF (1) Chroma signal ON/OFF switch 0 = Chroma signal ON 1 = Chroma signal OFF FSC SW (1) FSC signal ON/OFF switch 0 = FSC OFF: used as crystal pin 1 = FSC ON: outputs 700mVp-p FSC C BPF (1) Chroma band pass filter ON/OFF switch 0 = Band pass filter OFF 1 = Band pass filter ON AXIS NTSC (1) In NTSC mode, this switch selects Japan axis or US axis color detection axis. This is valid when AXIS PAL = 0. (This is automatically switched to PAL/SECAM detection axis in PAL/SECAM mode.) 0 = Set to Japan axis B-Y: 0°/1, R-Y: 95°/0.78, G-Y: 236°/0.33 1 = Set to US axis B-Y: 0°/1, R-Y: 102°/0.78, G-Y: 236°/0.3 AXIS PAL (1) Switch for forcing the color detection axis to an orthogonal axis (PAL axis) 0 = Forced OFF 1 = Orthogonal axis forced ON B-Y: 0°/1, R-Y: 90°/0.57, G-Y: 227°/0.34 NO COLOR (1) This switch switches the no signal definition for the chroma signal in the PAL (/NTSC) status register. 0 = PAL status register is 1 when there is no signal 1 = PAL status register is 0 when there is no signal YUV OUT (1) This switch switches the R2 IN, G2 IN and B2 IN input pins (Pins 32, 31 and 30) to the Y and color difference signal output pins. 0 = R2 IN, G2 IN and B2 IN signal input mode 1 = Pin 30: B-Y output Pin 31: R-Y output Pin 32: Y output (At this time, connect each pin to Vcc via a 10kΩ resistor.) KILLER OFF (1) Color killer ON/OFF switch 0 = Color killer standard mode 1 = Color killer forced OFF mode – 27 – CXA2060BS ID START (2) The position at which the SECAM identification pulse starts can be changed. (0.2µs/STEP) 0 = Delayed 0.4µs to center position. 2 = Center 3 = Advanced 0.2µs to center position. ID STOP (2) The position at which the SECAM identification pulse stops can be changed. (0.2µs/STEP) 0 = Delayed 0.2µs to center position. 1 = Center 3 = Advanced 0.4µs to center position. SECAM identification performance can be optimized by adjusting these together with the ID LEVEL register. Color is more easily applied when the identification pulse width is wide and less easily applied when it is narrow. BELL F0 (6) BELL Filter f0 adjustment (0.7%/STEP) 0h = f0 – 16% 1Fh = f0 center 3Fh = f0 + 16% ID LEVEL (2) SECAM identification level setting SECAM identification performance can be optimized by adjusting this together with ID START/STOP registers. 0 = Color is less easily applied 3 = Color is easily applied 3. RGB Signal Block Registers PICTURE (6) Picture gain control 0h = –15dB 3Fh = 0dB (During 0.7Vp-p input: RGB output 3.0Vp-p, gamma OFF, DRIVE MAX) BRIGHT (6) Brightness control (RGB DC bias control) 0h = –30 IRE to center 1Fh = –12 IRE to reference pulse 3Fh = +30 IRE to center (100 IRE = 2.4Vp-p) R DRIVE (6) R output drive control 0h = 1.5Vp-p 3Fh = 3.0Vp-p (PICTURE: MAX) G DRIVE (6) G output drive control 0h = 1.5Vp-p 3Fh = 3.0Vp-p (PICTURE: MAX) – 28 – CXA2060BS B DRIVE (6) B output drive control 0h = 1.5Vp-p 3Fh = 3.0Vp-p (PICTURE: MAX) R CUTOFF G CUTOFF B CUTOFF (4) RGB output cutoff control (4) (Input current of reference pulse excluding leak component) (4) 0h = 6.5µA 7h = 13µA Fh = 19µA GAMMA (2) RGB output gamma correction control 0 = Gamma correction OFF 3 = +12 IRE correction to 40 IRE input (PICTURE: MAX) ABL MODE (1) Switches ABL mode 0 = Mode in which only picture ABL functions 1 = Mode for both picture ABL and bright ABL ABL VTH (1) Switch for switching ABL control signal detection level (VTH) 0 = VTH: 3V 1 = VTH: 1V DYNAMIC C (1) Dynamic color function ON/OFF switch 0 = Dynamic color OFF 1 = Dynamic color ON RGB SEL (1) Disables switching of the YS1 switch and disallows input of external signals from RGB1. 0 = YS1 standard mode 1 = YS1 forced OFF mode P ON (1) Switch for blanking all RGB output signals including the AKB reference pulse (set to 0 at power ON) 0 = RGB output blanking (AKB reference pulse is also not output) 1 = RGB output ON R ON (1) Switch for blanking the R output signal not including the AKB reference pulse 0 = R output blanking 1 = R output ON G ON (1) Switch for blanking the G output signal not including the AKB reference pulse 0 = G output blanking 1 = G output ON – 29 – CXA2060BS B ON (1) Switch for blanking the B output signal not including the AKB reference pulse 0 = B output blanking 1 = B output ON 4. Deflection Block Registers H OSC (4) H VCO oscillation frequency adjustment (40Hz/STEP) 0h = Low Fh = High V SS (1) Switches the slice level for vertical sync signal separation 0 = 1/3 (from sync tip) 1 = 1/4 (from sync tip) H MASK (1) Macrovision countermeasure ON/OFF 0 = OFF 1 = ON H SS (1) Switches the slice level for horizontal sync signal separation 0 = 1/3 (from sync tip) 1 = 1/4 (from sync tip) VTIM SEL (2) Selects the signal output on the VTIM pin (Pin 5). 0 = V retrace timing pulse 1 = Horizontal sync signal 2 = Vertical sync separation signal 3 = Do not use CD MODE (2) V countdown system mode switching 0 = Standard mode (used during RF signal input) 1 = Mode where time constant used during countdown mode switching has been lowered from standard mode (used during VCR signal input) 2 = Fixed wide window mode This setting is recommended when shortening the lock time. 3 = Do not use FIELD FREQ (2) Sets the V frequency mode 0 = Automatic identification mode (selects 50Hz when there is no signal) 1 = Automatic identification mode (selects 60Hz when there is no signal) 2 = Forced 50Hz 3 = Forced 60Hz – 30 – CXA2060BS INTERLACE (2) Switches interlace/non-interlace mode 0, 1 = Interlace mode 2 = Non-interlace mode (even fields are shifted +1/2H) 3 = Non-interlace mode (odd fields are shifted +1/2H) AFC GAIN (2) AFC loop gain control (PLL for H sync and H VCO) 0 = Gain high 1 = Gain medium 2 = Gain low 3 = Gain minimum H POSITION (6) Horizontal picture position adjustment (HAFC phase control) 0h = 2µs delay (right picture position: picture delayed to HD) 3Fh = 2µs advance (left picture position: picture advanced to HD) AFC BOW (4) Vertical line bow compensation amount adjustment (phase control using HAFC parabola wave) 0h = Top and bottom of picture delayed 380ns to picture center 7h = Center Fh = Top and bottom of picture advanced 380ns to picture center AFC ANGLE (4) Vertical line slope compensation amount adjustment (phase control using HAFC VSAW) 0h = Top of picture delayed 320ns and bottom of picture advanced 320ns to picture center 7h = Center Fh = Top of picture advanced 320ns and bottom of picture delayed 320ns to picture center LEFT HBLK (4) Controls the BLK width on the left side of the picture when HBLK = 1 0h = +1.2µs: HBLK max. width 7h = Center Fh = –1.2µs: HBLK min. width RIGHT HBLK (4) Controls the BLK width on the right side of the picture when HBLK = 1 0h = +1.2µs: HBLK max. width 7h = Center Fh = –1.2µs: HBLK min. width HBLK (1) HBLK width control switch when a 16:9 CRT is in 4:3 soft normal mode 0 = Control OFF 1 = Control ON – 31 – CXA2060BS FH HI (1) Increases the free-running frequency of the H oscillation frequency 1kHz. (ON mode set at power ON) 0 = Max. frequency mode ON 1 = Max. frequency mode OFF (standard free-running frequency) HD W (1) HD pulse width switch (set to 0 at power ON) 0 = Standard mode (25µs pulse width) 1 = Narrow pulse width mode (use this mode when the time between the HD rising edge and FBP rising edge is short) V SIZE (6) Vertical picture size adjustment (VD output gain control) 0h = –15% (min. size) 1Fh = 0% 3Fh = +15% (max. size) V POSITION (6) Vertical picture position adjustment (DC bias control for VD output) 0h = –0.1V (lowers picture position) 1Fh = 0V (center 3V DC) 3Fh = +0.1V (raises picture position) S CORRECTION (4) Vertical S distortion correction amount adjustment (gain control for secondary component of VD) 0h = Secondary component amplitude added to the VD signal is 0mVp-p Fh = Secondary component amplitude added to the VD signal is 100mVp-p V LINEALITY (4) Vertical linearity adjustment (gain control for secondary component of VD) 0h = 85% (picture bottom/picture top) picture top enlarged 1Fh = 100% (picture bottom/picture top) 3Fh = 115% (picture bottom/picture top) picture top compressed EHT COMP (4) High-voltage fluctuation compensation setting for vertical picture size (gain control for VD output) 0h = 0% Fh = –5% (max. compensation) V ON (1) VD output ON/OFF switch (set to 0 at power ON) 0 = DC voltage 1 = Sawtooth wave H SIZE (6) Horizontal picture size adjustment (DC bias control for EW output) 0Fh = –0.5V (small horizontal picture size) 1Fh = 0V (center 4V DC) 3Fh = +0.5V (large horizontal picture size) – 32 – CXA2060BS PIN AMP (6) Horizontal pin distortion compensation amount adjustment (gain control for V parabola wave) 0h = 0.15Vp-p (large horizontal size at picture top and bottom: min. compensation) 1Fh = 0.7Vp-p 3Fh = 1.3Vp-p (small horizontal size at picture top and bottom: max. compensation) CORNER PIN (6) Picture top and bottom pin distortion compensation amount adjustment (top/bottom gain control for V parabola wave) 0h = –0.4V (small horizontal size at picture top and bottom: max. compensation) 3Fh = +0.4V (large horizontal size at picture top and bottom: min. compensation) TRAPEZIUM (4) Horizontal trapezium distortion amount compensation (phase control for parabola wave) 0h = 1.5ms advance (large horizontal size at picture top: small horizontal size at bottom) Fh = 1.5ms delay (small horizontal size at picture top: large horizontal size at bottom) ASPECT (6) Aspect ratio control (gain control for sawtooth wave) 0h = 75% 16:9 CRT Full 2Fh = 100% 4:3 CRT Full 3Fh = 110% SCROLL (6) Vertical picture scroll control when a 16:9 CRT is in zoom mode 0h = Scrolls 32H toward picture bottom and zooms picture bottom 1Fh = Center 3Fh = Scrolls 32H toward picture top and zooms picture top UPPER VLIN (4) Adjusts vertical linearity of picture top. 0h = 100% (picture top/picture bottom) 1Fh = 85% (picture top/picture bottom, picture top size is compressed) LOWER VLIN (4) Adjusts vertical linearity of picture bottom. 0h = 100% (picture bottom/picture top) 1Fh = 75% (picture bottom/picture top, picture bottom size is compressed) V UNDER SCAN (1) This mode is for compressing the vertical sawtooth wave. 0 = OFF 1 = ON Compressed to 50% when ASPECT = 0h Compressed to 75% when ASPECT = 3Fh RGB vertical blanking is increased by 10H at both top and bottom at this time. V ZOOM (1) Zoom mode ON/OFF switch for 16:9 CRTs 0 = Zoom OFF 1 = Zoom ON (Top and bottom of picture are together cut 25% when ASPECT = 2Fh. RGB output also undergoes blanking during this interval.) – 33 – CXA2060BS EW DC (1) This mode lowers the DC level of the V parabola wave when 4:3 deflection is used for a 16:9 CRT. 0 = OFF 1 = ON (DC level lowered) It is necessary at this time to readjust for pin distortion when EWDC = 0 is used for the picture distortion compensation. 5. Status Registers H LOCK (1) Lock status for H Sync and H VCO 0 = Free-running status 1 = H Sync and H VCO are locked IKR (1) AKB operation status 0 = AKB loop not stable 1 = AKB loop stable V NG (1) V protect status 0 = V protect OFF (IC normal operation status) 1 = V protect ON (RGB output undergoes complete blanking at this time) H NG (1) X-ray protect status 0 = H drive output ON 1 = H drive output OFF (HD output is high impedance at this time and RGB output undergoes blanking. It is necessary to turn the IC's power OFF then ON again to cancel this status.) APC LOCK (1) Lock status for input chroma signal and APC for PAL/NTSC 0 = APC not locked (Color killer when APC LOCK = 0 and SECAM = 0) 1 = APC locked PAL (1) PAL identification status When NO COLOR = 0 0 = NTSC 1 = PAL or NO SIG (KILLER ID ON) When NO COLOR = 1 0 = NTSC or NO SIG (KILLER ID ON) 1 = PAL SECAM (1) SECAM identification status 0 = Identified as not SECAM (Color killer when APC LOCK = 0 and SECAM = 0) 1 = Identified as SECAM – 34 – CXA2060BS FIELD ID (1) V drive oscillation frequency 0 = 60Hz mode 1 = 50Hz mode H CENT (1) H VCO status 0 = The H VCO oscillation frequency is higher than the horizontal frequency of the input signal selected by the VIDEO SW 1 = The H VCO oscillation frequency is lower than the horizontal frequency of the input signal selected by the VIDEO SW X'TAL ID (2) Crystal selection status 0 = Identified as X'TAL1 (Pin 48 crystal) 1 = Identified as X'TAL2 (Pin 47 crystal) 2 = Identified as X'TAL3 (Pin 46 crystal) NO VSYNC (1) VSS presence status Weak electromagnetic field detection can be performed according to RF LEVEL status. 0 = VSS present 1 = VSS not present RF LEVEL (2) RF weak electromagnetic field level 0 = Strong electromagnetic field 1 = Medium electromagnetic field 2 = Weak electromagnetic field 3 = Very weak electromagnetic field – 35 – CXA2060BS I2C Bus Power-On Initial Settings The initial settings listed here for power-on when V drive starts to oscillate are reference values; the actual settings may be determined as needed according to the conditions under which the set is to be used. Register Table "∗": Undefined Control Registers Sub Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 x x x 0 0 0 0 0 00 h 0 0 0 1 1 0 0 0 x x x 0 0 0 0 1 01 h 0 0 0 0 0 0 0 0 x x x 0 0 0 1 0 02 h 1 1 1 1 0 1 1 0 x x x 0 0 0 1 1 03 h 1 1 1 1 1 1 0 0 x x x 0 0 1 0 0 04 h 0 1 1 1 1 1 0 0 x x x 0 0 1 0 1 05 h 0 1 1 1 1 1 0 0 x x x 0 0 1 1 0 06 h 0 1 1 1 1 1 0 0 x x x 0 0 1 1 1 07 h 0 1 1 1 0 1 1 1 x x x 0 1 0 0 0 08 h 0 1 1 1 0 1 1 1 x x x 0 1 0 0 1 09 h 0 1 1 1 1 1 1 0 x x x 0 1 0 1 0 0A h 0 1 1 1 1 1 0 0 x x x 0 1 0 1 1 0B h 0 1 1 1 1 1 0 0 x x x 0 1 1 0 0 0C h 0 1 1 1 0 1 1 1 x x x 0 1 1 0 1 0D h 0 0 0 0 0 0 0 0 x x x 0 1 1 1 0 0E h 0 1 1 1 1 1 ∗ 0 x x x 0 1 1 1 1 0F h 0 1 1 1 1 1 0 1 x x x 1 0 0 0 0 10 h 0 1 1 1 0 1 1 1 x x x 1 0 0 0 1 11 h 0 1 1 1 1 1 ∗ 0 x x x 1 0 0 1 0 12 h 0 1 1 1 1 1 ∗ ∗ x x x 1 0 0 1 1 13 h 0 1 1 1 1 1 ∗ ∗ x x x 1 0 1 0 0 14 h 0 1 1 1 1 1 ∗ ∗ x x x 1 0 1 0 1 15 h 0 1 1 1 0 1 1 1 x x x 1 0 1 1 0 16 h 0 1 1 1 0 1 1 1 x x x 1 0 1 1 1 17 h 0 1 1 1 0 1 1 1 x x x 1 1 0 0 0 18 h 1 0 1 1 1 1 0 0 x x x 1 1 0 0 1 19 h 0 1 1 1 1 1 0 ∗ x x x 1 1 0 1 0 1A h 0 0 0 0 0 0 0 0 x x x 1 1 0 1 1 1B h 0 0 0 0 0 1 1 0 x x x 1 1 1 0 0 1C h 0 1 1 1 1 1 0 1 – 36 – CXA2060BS Description of Operation 1. Power-On Sequence The CXA2060BS does not have an internal power-on sequence. Therefore, all power-on sequences are controlled by the set microcomputer (I2C bus controller). (1) Power-on The IC is reset and the RGB outputs are all blanked. H drive starts to oscillate, but oscillation is at the maximum frequency (16kHz or more) and is not synchronized with the input signal in order to prevent FBT (flyback transformer for generating high voltage) H squealing. Output of vertical signal V TIM starts, but V drive is DC output. Bus registers which are set by power-on reset are as follows. P ON = 0: RGB all blanked ON HD W = 0: Normal mode V ON = 0: V output stopped mode FH HIGH = 0: H oscillator maximum frequency mode AGING = 0: All white output aging mode OFF YUV OUT = 0 (2) Bus register data transfer The register setting sequence differs according to the set sequence. Register settings for the following sequence are shown as an example. Set sequence Power-on ↓ Degauss ↓ V drive oscillation ↓ AKB operation start ↓ AKB loop stable ↓ Video output CXA2060BS register settings Reset status in (1) above. ↓ Reset status in (1) above. The CRT is degaussed in a completely darkened condition. ↓ The IC is set to the power-on initial settings. (See the following page.) A sawtooth wave is output to V drive and the IC waits for the vertical deflection to stabilize. The H drive oscillator frequency goes to the standard frequency. ↓ R ON, G ON and B ON are set to 0. P ON is set to 1 and a reference pulse is output from RGBOUT. Then, the IC waits for the cathode to warm up and the beam current to start flowing. ↓ Status register IKR is monitored. IKR = 0: Unstable IKR = 1: Stable Note that the time until IKR = 1 is returned differs according to the initial status of the cathode. Also note that the time until IKR = 1 results may differ from the actual time until the cathode current stabilizes. It is recommended that video output start after IKR = 1 has been established for 1 or 2 seconds. ↓ R ON, G ON and B ON are set to 1 and the video signal is output from RGBOUT. – 37 – CXA2060BS (3) Power-on initial settings The initial settings listed here for power-on when V drive starts to oscillate are reference values; the actual settings may be determined as needed according to the conditions under which the set is to be used. P ON =0 RGB all blanked HD W =0 Normal AXIS PAL =0 PAL axis forced OFF V ON =1 V drive oscillation FH HIGH =1 H oscillation frequency standard YUV OUT =0 R2 IN/G2 IN/B2 IN signal input mode AGING =0 Aging Mode OFF VIDEO SEL =0 TV signal input (User) S SEL =0 TV/CVBS1/CVBS2 input or Mute selection (User) R ON =0 Rch video output blanked G ON =0 Gch video output blanked B ON =0 Bch video output blanked Y SEL =0 YUV SW standard operation X'TAL =3 AUTO COL SYSTEM = 3 AUTO COL LOOP =1 Automatic identification for PAL/SECAM/NTSC/NTSC4.43 C BPF =1 C BPF ON C TRAP OFF =0 C TRAP ON PICTURE = 3Fh MAX (User Control) NO COLOR =0 PAL identification output to status (when there is no signal) FSC SW =0 FSC OFF COLOR = 1Fh Center (User Control) C OFF =0 Chroma signal ON KILLER OFF =0 Color killer normal mode HUE = 1Fh Center (User Control) SHP F0 =0 2.5MHz AXIS NTSC =0 Japan axis BRIGHT = 1Fh Center (User Control) DC TRAN =0 100% PRE/OVER =0 Sharpness Pre/Over ratio 1:1 SHARPNESS = 7h Center (User Control) R CUTOFF = 7h Center (Adjust) G CUTOFF = 7h Center (Adjust) B CUTOFF = 7h Center (Adjust) R DRIVE = 1Fh Center (Adjust) ABL MODE =1 Picture ABL/Bright ABL combination mode ABL VTH =0 Vth = 3V G DRIVE = 1Fh Center (Adjust) DY COL =0 Dynamic Color OFF RGB SEL =0 YS1 SW normal mode B DRIVE = 1Fh Center (Adjust) GAMMA =0 Gamma OFF H OSC = 7h Center (Adjust) Y DELAY = 7h Center (Adjust) FIELD FREQ =0 AUTO CD MODE =0 Normal – 38 – CXA2060BS (Power-on initial settings continued) INTERLACE =0 H SS =0 V SS =0 V SIZE = 1Fh H MASK =0 V POSITION = 1Fh AFC GAIN =1 S CORRECTION = 7h V LINEALITY = 7h H SIZE = 1Fh EW DC =0 H POSITION = 1Fh PIN AMP = 1Fh CORNER PIN = 1Fh TRAPEZIUM = 7h EHT COMP = 7h AFC BOW = 7h AFC ANGLE = 7h LEFT HBLK = 7h RIGHT HBLK = 7h ASPECT = 2Fh HBLK =0 V UNDER SCAN = 0 SCROLL = 1Fh V ZOOM =0 UPPER VLIN = 0h LOWER VLIN = 0h VTIM SEL =0 ID STOP =1 ID START =2 BELL F0 = 1Fh ID LEVEL =1 Interlace Mode Slice level 1/3 (from sync tip) Slice level 1/3 (from sync tip) Center (Adjust) Macrovision countermeasure OFF Center (Adjust) Gain medium Center (Adjust) Center (Adjust) Center (Adjust) OFF Center (Adjust) Center (Adjust) Center (Adjust) Center (Adjust) Center (Adjust) Center (Adjust) Center (Adjust) HBLK width min. HBLK width min. 100% Control OFF OFF Center (User Control) Zoom OFF 100% (No compression) 100% (No compression) V retrace pulse timing pulse Center Center Center Center 2. Various Mode Settings The CXA2060BS contains bus registers for deflection compensation which can be set for various wide modes. Wide mode setting registers can be used separately from registers for normal picture distortion adjustment, and once picture distortion adjustment has been performed in full mode, wide mode settings can be made simply by changing the corresponding register. • Vertical picture distortion adjustment registers V SIZE, V POSITION, S CORRECTION, V LINEARITY • Horizontal picture distortion adjustment registers H SIZE, EW DC, PIN AMP, CORNER PIN, TRAPEZIUM, AFC BOW, AFC ANGLE, H POSITION • Wide mode setting registers LEFT HBLK, RIGHT HBLK, ASPECT, HBLK, V UNDER SCAN, SCROLL, V ZOOM, UPPER VLIN, LOWER VLIN – 39 – CXA2060BS Various mode settings I2C bus register CRT size Soft size Mode name 1)-1 16:9 16:9 Full Standard value for 16:9 CRTs 1)-2 16:9 4:3 Wide full Standard value for 16:9 CRTs Setting 2) 3) 4) 16:9 16:9 16:9 4:3 16:9 4:3 4:3 (16:9 + subtitles) ASPECT = HBLK = LEFT HBLK = RIGHT HBLK = PIN AMP = EW DC = Normal Zoom ASPECT V ZOOM SCROLL = 2Fh: V size 100% = 1: Zoom ON (V size limited to 75%) = 0h: Zoom bottom of picture 1Fh: Zoom center of picture 3Fh: Zoom top of picture ASPECT UP VLIN = 2Fh: V size 100% = Adjustment: Top of picture slightly compressed = Adjustment: Bottom of picture greatly compressed = 1: V size limited to 75% = Adjustment LO VLIN Subtitle-in V ZOOM SCROLL 5) 16:9 4:3 Split screen mode 0h: V size 75% 1: HBLK width adjustment ON Adjustment Adjustment Adjustment 1 V UNDER SCAN = 1: Compressed 6) 16:9 4:3 Wide zoom ASPECT UP VLIN LO VLIN (S CORR = = = = Adjustment: V size 90% Adjustment Top and bottom of Adjustment picture compressed Adjustment) 7) 4:3 4:3 4:3 normal Standard value for 4:3 CRTs 8) 4:3 16:9 V compression ASPECT = Adjustment V UNDER SCAN = 1: V size 80% (Compressed to a total of 75%) ∗ Since the amount of compensation for distortion in the vertical position of a CRT does not change due to the above modes, it is possible to use initial values for all screen distortion registers. – 40 – CXA2060BS Mode examples are given below. The 570 actual number of scanning lines displayed under PAL (480 lines for NTSC) will be used in the description. Data stored in the wide mode setting registers is also given. Note that actual adjustment values may differ slightly due to variations among different ICs. Standard setting data differs for 16:9 CRTs and 4:3 CRTs. (Standard value) Register ASPECT SCROLL V ZOOM UPPER VLIN LOWER VLIN V UNDER SCAN HBLK LEFT HBLK RIGHT HBLK 16:9 CRT 4:3 CRT 0h 1Fh 1 0h 0h 0 0 7h 7h 2Fh 1Fh 0 0h 0h 0 0 7h 7h 1) Full mode This mode reproduces the full 570 (NTSC: 480) lines on a 16:9 CRT. Normal 4:3 images are compressed vertically, but in the case of a squeezed video source which compresses 16:9 images to 4:3 images, 16:9 images are reproduced in their original 16:9 aspect ratio. The register settings are the 16:9 CRT standard values. 2) Normal mode In this mode, 4:3 images are reproduced without modification on a 16:9 CRT. A black border appears at the left and right of the picture. In this mode, the H deflection size must be compressed by 25% compared to full mode. The CXA2060BS performs compression with a register (EW DC) that compresses the H size. Because excessive current flows to the horizontal deflection circuit in this case, adequate consideration must be given to the allowable power dissipation, etc., of the horizontal deflection coil in the design of the set. In addition, this concern can also be addressed through measures taken external to the IC, such as switching the horizontal deflection coil. Full mode should be used when performing memory processing to add a black border to the video signal. H blanking of the image normally uses the flyback pulse input from HP/PROTECT (Pin 18). However, the blanking width can be varied according to the control register setting when blanking is insufficient for the right and left black borders. Change the following three settings with respect to the 16:9 CRT standard values for the register settings. HBLK =1 LEFT HBLK = Adjustment value RIGHT HBLK = Adjustment value The H angle of deflection decreases, causing it to differ from the PIN compensation amount during H size full status. Therefore, in addition to the wide mode registers, PIN AMP must also be readjusted only for this mode. – 41 – CXA2060BS 3) Zoom mode In this mode, 4:3 images are reproduced on a 16:9 CRT by enlarging the picture without other modification. The top and bottom of normal 4:3 images are lost, but almost the entire picture can be reproduced for vista size video software, etc. which already has black borders at the top and bottom. Setting the ASPECT register to 2Fh (100%) allows zooming to be performed for 4:3 images without distortion. In this case, the number of scanning lines is reduced to 430 lines compared to 570 lines for full mode. The zooming position can be shifted vertically by the SCROLL register. V blanking of the image normally begins from V sync and continues for 2H after the AKB reference pulse, but the top and bottom parts which are lost are also blanked during this mode. Adjust the following two registers with respect to the 16:9 CRT standard values for the register settings. ASPECT = 2Fh SCROLL = 1Fh or user control 4) Subtitle-in mode When Cinema Scope images which have black borders at the top and bottom of the picture are merely enlarged with the zoom mode in 3) above, the subtitles present in the black borders may be lost. Therefore, this mode is used to super-compress only the subtitle part and reproduce it on the display. Add the LOWER VLIN adjustment to the zoom mode settings for the register settings. ASPECT = 2Fh SCROLL = 1Fh or user control LOWER VLIN = Adjustment value LOWER VLIN causes the linearity at the bottom of the picture to deteriorate. Therefore, UPPER VLIN should also be adjusted if the top and bottom of the picture are to be made symmetrical. Since the picture is compressed vertically, the number of scanning lines exceeds 430 lines. 5) Two-picture mode This mode is used to reproduce two 4:3 video displays on a 16:9 CRT such as for P and P. To achieve this, the V size must be further compressed from the condition where ASPECT = 0 (V size 75%: full mode). This IC performs this compression with V UNDER SCAN. 16:9 CRT standard values are used with only V UNDER SCAN changed to 1 for the register settings. V UNDER SCAN = 1 6) Wide zoom mode This mode reproduces 4:3 video software naturally on wide displays by enlarging 4:3 images without other modification and compressing the parts of the image which protrude from the picture into the top and bottom parts of the picture. The display enlargement ratio is controlled by ASPECT, and the compression ratios at the top and bottom of the picture are controlled by UPPER VLIN and LOWER VLIN. Adjust the following three registers with respect to the 16:9 CRT standard values for the register settings. ASPECT = Adjustment value UPPER VLIN = Adjustment value LOWER VLIN = Adjustment value 7) 4:3 CRT normal mode This is the standard mode for 4:3 CRTs. The register settings are the 4:3 CRT standard values. – 42 – CXA2060BS 8) V compression mode This mode is used to reproduce M-N converter output consisting of 16:9 images expanded to 4:3 aspect ratio and other squeezed signals without distortion on a 4:3 CRT. In this case, the V size must be compressed to 75%. This is done using V UNDER SCAN in 5) above. Setting V UNDER SCAN to ON compresses the V size to 75%. Fine adjustment of the V size is possible by adding the ASPECT adjustment. 4:3 CRT standard values are used with the ASPECT and V UNDER SCAN settings changed for the register settings. ASPECT = Adjustment V UNDER SCAN = 1 – 43 – CXA2060BS VIDEO SW INPUT: 1.0Vp-p SELECTOR TV/C2-IN VIDEO SELECTOR Y1/CVBS1-IN +6dB MON-OUT 2Vp-p MIX Y2/CVBS2-IN C1-IN –11dB SELECTOR INPUT: 2.0Vp-p +12dB –6dB TO-Y Sig 200mVp-p (without sync) TO-SSEP Sig 4Vp-p (with sync) COMBY-IN COMBC-IN –6dB TO-C Burst: 250mVp-p SELECTOR 2 to 3 A 2 to 4 B C I2C: VIDEO SEL D I2C: S SEL A B C D TO-Y TO-C MON-OUT 0 0 0 0 TV TV TV 0 1 0 0 CVBS1 CVBS1 CVBS1 1 0 0 0 CVBS2 CVBS2 CVBS2 1 1 0 0 NOSIG NOSIG NOSIG 1 1 0 1 Y1 C1 Y1 + C1 1 1 1 0 Y2 C2 Y2 + C2 0 0 1 1 COMBY COMBC TV 0 1 1 1 COMBY COMBC CVBS1 1 0 1 1 COMBY COMBC CVBS2 1 1 1 1 NOSIG NOSIG NOSIG – 44 – CXA2060BS [Color Status] APC LOCK PAL SECAM X'TAL ID FIELD ID 3.58 NTSC 1 0 0 01 0 4.43 NTSC 1 0 0 00 0 PAL 1 1 0 00 1 PAL60 1 1 0 00 0 SECAM 0 0 1 00 1 PAL-M 1 1 0 00 0 PAL-N 1 1 0 10 1 No color signal 0 0 0 ∗∗ ∗ Input – 45 – CXA2060BS 3. Signal Processing The CXA2060BS consists of separate blocks for sync signal processing, H deflection signal processing, V deflection signal processing and Y/C and RGB signal processing, all controlled by an I2C bus. 1) Sync signal processing The Y signal selected by the video switch is sync separated by a horizontal/vertical sync separation circuit. A phase comparison between the horizontal sync split signal obtained and the H VCO output signal is conducted and an AFC loop is configured, and an H pulse synchronized to H sync is created within the IC. When AFC is locked to H sync, 1 is output to the status register (H LOCK). This can be used to detect the presence of a video signal. The vertical sync split signal is sent to the V countdown block and V deflection timing is obtained by the appropriate window processing. V cycle timing such as the AKB reference pulse is generated using this V timing pulse. The V retrace timing pulse and sync split signal are output on V TIM (Pin 5) according to the V TIMSEL register setting. 2) H deflection signal processing A phase comparison is conducted between the H pulse obtained from sync processing and the H deflection pulse input on Pin 18 (HP/PROTECT) and the horizontal position of the picture displayed on the CRT is controlled by controlling the phase of H drive output. The compensation signal created using the vertical sawtooth wave is superimposed and vertical picture distortion compensation is also performed. The H deflection pulse is used for H blanking of the video signal. If the width of the H deflection pulse is narrow, a pulse created by the IC can be added and the result used as the H blanking pulse (HBLK). Although Pin 18 is for normal pulse input, the pin is kept lowered to near GND level, H drive output is stopped and 1 is output to the status register (H NG). It is necessary to turn the IC's power OFF and ON again in order to cancel this status. 3) V deflection signal processing The vertical sawtooth wave oscillates in sync with the V timing pulse cycle output by the countdown. After wide deflection processing is added to this sawtooth wave, it undergoes picture distortion adjustment by the function circuits V drive and EW drive, respectively, and the result is output as the V drive and EW drive signals. 4) Y signal processing The Y/CVBS signal selected by the video switch is sent to the Y signal processing circuit. The Y signal is sent to the RGB signal processing circuit via a trap filter for eliminating the chroma signal, a delay line, sharpness control, clamp, and black expansion circuits. In addition, the output of the Y signal processing circuit can be monitored using Pin 32 (R2 IN) by setting register YUV OUT to 1. (At this time, be sure to connect a 10kΩ resistor to Vcc as a load for Pin 32.) Also, a differential waveform of the Y signal synchronized with YOUT (RGB OUT) is output from Pin 15 as VM OUT. When the CVBS signal is selected, set the C TRAP OFF register to 0 (trap filter ON), and when the Y signal split from Y/C separation is selected, set this register to 1 (trap filter OFF). The internal filter f0 is adjusted automatically within the IC. Since the filter f0 does not settle down while the color killer is operating, be sure to set the trap filter to OFF if it is an obstacle. – 46 – CXA2060BS 5) C signal processing The TV, CVBS or chroma (PAL, NTSC) signals (specified input: burst level 300mVp-p) selected by the Video SW pass through an ACC, chroma band-pass filter, chroma amplifier, and demodulation circuit to form the color difference signals R-Y and B-Y. After being processed by 1HDL the signals are input to the RGB signal processing circuit. The output signals (color difference signals) of this C signal processing circuit can be monitored, just like Y output, using Pin 30 (B2 IN) and Pin 31 (G2 IN) by setting the register YUV OUT to 1. B-Y is output from Pin 30 (B2 IN) and R-Y is output from Pin 31 (G2 IN). (At this time, be sure to connect a 10kΩ resistor to Vcc as a load for Pins 30 and 31.) The color killer is activated when the burst level falls –36dB or more below the specified input. The SECAM signal (specified input: R-YID: 215mVp-p, B-YID: 167mVp-p) passes through an ACC, bell filter, limiter amplifier, demodulation circuit, line blanking circuit, and de-emphasis circuit to form the color difference signals R-Y and B-Y. After being processed by 1HDL the signals are input to the RGB signal processing circuit. In addition, the color system (PAL, NTSC or SECAM) and sub-carrier frequency (4.43MHz or 3.58MHz) are automatically identified according to the input chroma signal. Circuits such as the internal VCO, demodulation circuit and color axis circuit of the RGB signal processing block (described below) are automatically adjusted. The system is selected either automatically by the I2C bus (COL SYSTEM and X'TAL) or by forcible modes. The color system status selected using the status registers NTSC/PAL, SECAM and X'TAL ID is output (refer to the color status table). 6) RGB signal processing The Y and color difference signals obtained by the Y/C signal processing circuit are first input to the YUV SW, then selected and switched with the external Y and color difference signals. After the selected Y and color difference signals are used to form the G-Y signal in the next axis circuit (including color control), they are used for the RGB signals. Next, these signals pass through the external RGB signal SW circuits YS1 SW and YM SW (half-tone SW), external RGB signal SW circuit YS2 SW, dynamic color, picture control, gamma correction, clamp, brightness control, drive control, and cutoff control circuits, and are then output on Pin 22 (ROUT), Pin 23 (GOUT), and Pin 24 (BOUT). An external RGB signal (100 IRE 100% white: 0.7Vp-p) conforming to normal video signal specifications is input to Pins 26, 27 and 28 and Pins 30, 31 and 32. The voltage added to Pin 3 (ABL IN) is compared to the reference voltage within the IC and then integrated by the capacitor connected to Pin 42 (ABL FIL) to form a control signal used for picture control and brightness control. The ABL mode can be selected using the register ABL MODE for switching such that only picture control is performed or so that both picture control and brightness control are performed. There is a protective function such that brightness control is activated even when only picture control is being performed if beam current flows excessively. This IC includes two functions for performing white balance and black balance adjustments: drive control for performing gain adjustment between RGB outputs and cutoff control for performing DC level adjustments between RGB outputs. These can be independently controlled for three channels by the I2C bus. In addition to this, the cutoff control function also includes an auto-cutoff function (AKB) which performs automatic adjustment by forming a loop between the IC and CRT. This can compensate for temporal variations of the CRT. – 47 – CXA2060BS Auto-cutoff functions are as follows. • R, G, and B reference pulses for auto cutoff, shifted 1H each in the order mentioned, appear at the top of the picture (actually, in the overscan portion). The reference pulse uses 1H in the V blanking interval, and is output from each R, G and B output pin. • The RGB cathode current (IK) is input to Pin 21 (IK IN). • The cathode current input to Pin 21 (IK IN) is converted to a voltage within the IC. The reference pulse interval of this voltage is compared with the reference voltage within the IC, and a current generated by this voltage difference is used to charge a capacitor within the IC. This charge is held at times other than the reference pulse interval. • The DC level of the RGB output changes according to the voltage generated by the capacitor. A loop functions to make the voltage converted from the current input to Pin 21 (IK IN) match the reference voltage within the IC. The IC internal reference voltages for R, G and B undergo cutoff control by the I2C bus and can be independently adjusted. The cathode signal current flowing during the reference pulse interval should be about 13µA at the cutoff control center. The IC can also handle up to 100µA cathode leak current flowing during blanking. Large current flows during the video interval, and this leads to destruction around IK IN, be absolutely sure to connect a zener diode of about 4V to the IK IN pin. – 48 – CXA2060BS 4. Notes on Operation Because the R, G and B signals and deflection signals output from the CXA2060BS are DC direct connected, the pattern (set board) must be designed with consideration given to minimizing interference from around the power supply and GND. Do not separate the GND patterns for each pin; a solid earth is ideal. Locate the power supply side of the by-pass capacitor which is inserted between the power supply and GND as near to the pin as possible. Also, locate the crystal oscillator and IREF resistor as near to the pin as possible, and be sure that signal lines do not pass close to these pins. Drive the Y, external Y/color difference and external RGB signals at a sufficiently low impedance, as these signals are clamped when they are input using the capacitor connected to the input pin. Use a resistor (such as a meal film resistor) with an error of less than 1% for the IREF pin. Be sure that Vcc1 and Vcc2 have the same electric potential. Use crystals manufactured by Daishinku Corp. Properties of this IC are not guaranteed if used with crystals from another manufacturer. – 49 – CXA2060BS Curve Data I2C bus data conforms to the "I2C Bus Register Initial Settings" of the Electrical Characteristics Measurement Conditions. V_POSITION 4.5 4 4 V [V] V [V] V_SIZE 4.5 3.5 V_SIZE = 0 V_SIZE = 1F V_SIZE = 3F 3 2.5 0 5 10 Time [ms] 3.5 3 15 V_POSITION = 0 V_POSITION = 1F V_POSITION = 3F 2.5 20 0 5 4 4 V [V] V [V] 4.5 3.5 2.5 S_CORR = 0 S_CORR = 7 S_CORR = F 0 5 10 Time [ms] 3 15 2.5 20 0 5 4 V [V] V [V] 4 3.5 10 20 15 20 3.5 3 V_ASPECT = 0 V_ASPECT = 2F V_ASPECT = 3F 5 10 Time [ms] V_SCROLL 4.5 0 15 V_LINE = 0 V_LINE = 7 V_LINE = F V_ASPECT 2.5 20 3.5 4.5 3 15 V_LINE S_CORR 4.5 3 10 Time [ms] 15 2.5 20 Time [ms] – 50 – V_SCROLL = 0 V_SCROLL = 1F V_SCROLL = 3F 0 5 10 Time [ms] CXA2060BS LO_VLIN 4.5 4 4 V [V] V [V] UP_VLIN 4.5 3.5 UP_VLIN = 0 UP_VLIN = 7 UP_VLIN = F 3 2.5 0 5 10 Time [ms] 3.5 LO_VLIN = 0 LO_VLIN = 7 LO_VLIN = F 3 15 2.5 20 0 5 4.5 4 4 3.5 3 2.5 5 10 Time [ms] 20 15 15 20 15 20 3.5 3 PIN_AMP = 0 PIN_AMP = 1F PIN_AMP = 3F 0 15 TRAPEZIUM 4.5 V [V] V [V] PIN_AMP 10 Time [ms] 2.5 20 TRAPEZIUM = 0 TRAPEZIUM = 7 TRAPEZIUM = F 0 5 CO_PIN 10 Time [ms] H_SIZE 4.5 5 4.5 4 V [V] V [V] 4 3.5 3.5 3 2.5 CO_PIN = 0 CO_PIN = 1F CO_PIN = 3F 0 5 10 Time [ms] H_SIZE = 0 H_SIZE = 1F H_SIZE = 3F 3 15 2.5 20 – 51 – 0 5 10 Time [ms] CXA2060BS H_POSITION TRAP OFF 2.5 0 2 –10 1.5 0.5 Gain [dB] Time [µs] 1 0 –0.5 –20 –30 –1 –1.5 3.5MHz TRAPOFF = 0 TRAPOFF = 1 4.43MHz TRAPOFF = 0 –40 –2 –2.5 0 10 20 30 40 DATA 50 –50 60 0 1 2 Y_DELAY 4 3 DATA 5 6 SHARPNESS 1200 10 8 1100 6 Gain [dB] Time [ns] 1000 900 4 2 0 800 –2 700 600 0 10 5 SHP-f0 = 3.0MHz SHP-f0 = 2.5MHz –4 NTSC/PAL SECAM –6 15 0 5 DATA 10 15 DATA PICTURE COLOR 4 10 5 0 0 Gain [dB] Gain [dB] –4 –8 –5 –10 –15 –12 –20 –16 –20 –25 0 10 20 40 30 DATA 50 –30 60 – 52 – 0 10 20 30 40 DATA 50 60 BRIGHT R-DRIVE, G-DRIVE, B-DRIVE 4 0.4 0.2 2 0 Gain [dB] Potential Difference Between Gch Reference Pulse Level and Black Level [Vp-p] CXA2060BS –0.2 –0.4 –0.6 0 –2 –0.8 –1 0 10 20 30 40 DATA 50 –4 60 0 GAMMA 30 40 DATA 50 60 Input Current of Reference Pulse [mA] 20 4 Gch Output [V] 20 CUT_OFF (R, G, B) 4.5 3.5 3 2.5 GAMMA = 0 GAMMA = 1 GAMMA = 2 GAMMA = 3 2 1.5 10 0 20 60 80 40 CVIN Input Amplitude [IRE] 15 10 5 0 100 0 5 10 DATA – 53 – 15 CXA2060BS Package Outline Unit: mm + 0.1 5 0.0 0.25 – 48PIN SDIP (PLASTIC) + 0.4 43.2 – 0.1 25 15.24 + 0.3 13.0 – 0.1 48 1 0° to 15° 24 0.5 ± 0.1 0.9 ± 0.15 Two kinds of package surface: 1.All mat surface type. 2.Center part is mirror surface. + 0.4 4.6 – 0.1 3.0 MIN 0.5 MIN 1.778 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER/PALLADIUM PLATING SONY CODE SDIP-48P-02 LEAD TREATMENT EIAJ CODE SDIP048-P-0600 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 5.1g JEDEC CODE NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). – 54 –